drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { 0 }
  38 };
  39
  40 static void ath_detach(struct ath_softc *sc);
  41
  42 /* return bus cachesize in 4B word units */
  43
  44 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  45 {
  46         u8 u8tmp;
  47
  48         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  49         *csz = (int)u8tmp;
  50
  51         /*
  52          * This check was put in to avoid "unplesant" consequences if
  53          * the bootrom has not fully initialized all PCI devices.
  54          * Sometimes the cache line size register is not set
  55          */
  56
  57         if (*csz == 0)
  58                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  59 }
  60
  61 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  62 {
  63         if (!sc->sc_curaid)
  64                 sc->cur_rate_table = sc->hw_rate_table[mode];
  65         /*
  66          * All protection frames are transmited at 2Mb/s for
  67          * 11g, otherwise at 1Mb/s.
  68          * XXX select protection rate index from rate table.
  69          */
  70         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  71 }
  72
  73 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  74 {
  75         if (chan->chanmode == CHANNEL_A)
  76                 return ATH9K_MODE_11A;
  77         else if (chan->chanmode == CHANNEL_G)
  78                 return ATH9K_MODE_11G;
  79         else if (chan->chanmode == CHANNEL_B)
  80                 return ATH9K_MODE_11B;
  81         else if (chan->chanmode == CHANNEL_A_HT20)
  82                 return ATH9K_MODE_11NA_HT20;
  83         else if (chan->chanmode == CHANNEL_G_HT20)
  84                 return ATH9K_MODE_11NG_HT20;
  85         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  86                 return ATH9K_MODE_11NA_HT40PLUS;
  87         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  88                 return ATH9K_MODE_11NA_HT40MINUS;
  89         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  90                 return ATH9K_MODE_11NG_HT40PLUS;
  91         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  92                 return ATH9K_MODE_11NG_HT40MINUS;
  93
  94         WARN_ON(1); /* should not get here */
  95
  96         return ATH9K_MODE_11B;
  97 }
  98
  99 static void ath_update_txpow(struct ath_softc *sc)
 100 {
 101         struct ath_hal *ah = sc->sc_ah;
 102         u32 txpow;
 103
 104         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 105                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 106                 /* read back in case value is clamped */
 107                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 108                 sc->sc_curtxpow = txpow;
 109         }
 110 }
 111
 112 static u8 parse_mpdudensity(u8 mpdudensity)
 113 {
 114         /*
 115          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 116          *   0 for no restriction
 117          *   1 for 1/4 us
 118          *   2 for 1/2 us
 119          *   3 for 1 us
 120          *   4 for 2 us
 121          *   5 for 4 us
 122          *   6 for 8 us
 123          *   7 for 16 us
 124          */
 125         switch (mpdudensity) {
 126         case 0:
 127                 return 0;
 128         case 1:
 129         case 2:
 130         case 3:
 131                 /* Our lower layer calculations limit our precision to
 132                    1 microsecond */
 133                 return 1;
 134         case 4:
 135                 return 2;
 136         case 5:
 137                 return 4;
 138         case 6:
 139                 return 8;
 140         case 7:
 141                 return 16;
 142         default:
 143                 return 0;
 144         }
 145 }
 146
 147 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 148 {
 149         struct ath_rate_table *rate_table = NULL;
 150         struct ieee80211_supported_band *sband;
 151         struct ieee80211_rate *rate;
 152         int i, maxrates;
 153
 154         switch (band) {
 155         case IEEE80211_BAND_2GHZ:
 156                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 157                 break;
 158         case IEEE80211_BAND_5GHZ:
 159                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 160                 break;
 161         default:
 162                 break;
 163         }
 164
 165         if (rate_table == NULL)
 166                 return;
 167
 168         sband = &sc->sbands[band];
 169         rate = sc->rates[band];
 170
 171         if (rate_table->rate_cnt > ATH_RATE_MAX)
 172                 maxrates = ATH_RATE_MAX;
 173         else
 174                 maxrates = rate_table->rate_cnt;
 175
 176         for (i = 0; i < maxrates; i++) {
 177                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 178                 rate[i].hw_value = rate_table->info[i].ratecode;
 179                 sband->n_bitrates++;
 180                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 181                         rate[i].bitrate / 10, rate[i].hw_value);
 182         }
 183 }
 184
 185 static int ath_setup_channels(struct ath_softc *sc)
 186 {
 187         struct ath_hal *ah = sc->sc_ah;
 188         int nchan, i, a = 0, b = 0;
 189         u8 regclassids[ATH_REGCLASSIDS_MAX];
 190         u32 nregclass = 0;
 191         struct ieee80211_supported_band *band_2ghz;
 192         struct ieee80211_supported_band *band_5ghz;
 193         struct ieee80211_channel *chan_2ghz;
 194         struct ieee80211_channel *chan_5ghz;
 195         struct ath9k_channel *c;
 196
 197         /* Fill in ah->ah_channels */
 198         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 199                                       regclassids, ATH_REGCLASSIDS_MAX,
 200                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 201                 u32 rd = ah->ah_currentRD;
 202                 DPRINTF(sc, ATH_DBG_FATAL,
 203                         "Unable to collect channel list; "
 204                         "regdomain likely %u country code %u\n",
 205                         rd, CTRY_DEFAULT);
 206                 return -EINVAL;
 207         }
 208
 209         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 210         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 211         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 212         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 213
 214         for (i = 0; i < nchan; i++) {
 215                 c = &ah->ah_channels[i];
 216                 if (IS_CHAN_2GHZ(c)) {
 217                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 218                         chan_2ghz[a].center_freq = c->channel;
 219                         chan_2ghz[a].max_power = c->maxTxPower;
 220
 221                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 222                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 223                         if (c->channelFlags & CHANNEL_PASSIVE)
 224                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 225
 226                         band_2ghz->n_channels = ++a;
 227
 228                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 229                                 "channelFlags: 0x%x\n",
 230                                 c->channel, c->channelFlags);
 231                 } else if (IS_CHAN_5GHZ(c)) {
 232                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 233                         chan_5ghz[b].center_freq = c->channel;
 234                         chan_5ghz[b].max_power = c->maxTxPower;
 235
 236                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 237                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 238                         if (c->channelFlags & CHANNEL_PASSIVE)
 239                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 240
 241                         band_5ghz->n_channels = ++b;
 242
 243                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 244                                 "channelFlags: 0x%x\n",
 245                                 c->channel, c->channelFlags);
 246                 }
 247         }
 248
 249         return 0;
 250 }
 251
 252 /*
 253  * Set/change channels.  If the channel is really being changed, it's done
 254  * by reseting the chip.  To accomplish this we must first cleanup any pending
 255  * DMA, then restart stuff.
 256 */
 257 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 258 {
 259         struct ath_hal *ah = sc->sc_ah;
 260         bool fastcc = true, stopped;
 261
 262         if (sc->sc_flags & SC_OP_INVALID)
 263                 return -EIO;
 264
 265         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 266             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 267             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 268             (sc->sc_flags & SC_OP_FULL_RESET)) {
 269                 int status;
 270                 /*
 271                  * This is only performed if the channel settings have
 272                  * actually changed.
 273                  *
 274                  * To switch channels clear any pending DMA operations;
 275                  * wait long enough for the RX fifo to drain, reset the
 276                  * hardware at the new frequency, and then re-enable
 277                  * the relevant bits of the h/w.
 278                  */
 279                 ath9k_hw_set_interrupts(ah, 0);
 280                 ath_draintxq(sc, false);
 281                 stopped = ath_stoprecv(sc);
 282
 283                 /* XXX: do not flush receive queue here. We don't want
 284                  * to flush data frames already in queue because of
 285                  * changing channel. */
 286
 287                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 288                         fastcc = false;
 289
 290                 DPRINTF(sc, ATH_DBG_CONFIG,
 291                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 292                         sc->sc_ah->ah_curchan->channel,
 293                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 294
 295                 spin_lock_bh(&sc->sc_resetlock);
 296                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 297                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 298                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 299                         DPRINTF(sc, ATH_DBG_FATAL,
 300                                 "Unable to reset channel %u (%uMhz) "
 301                                 "flags 0x%x hal status %u\n",
 302                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 303                                                   hchan->channelFlags),
 304                                 hchan->channel, hchan->channelFlags, status);
 305                         spin_unlock_bh(&sc->sc_resetlock);
 306                         return -EIO;
 307                 }
 308                 spin_unlock_bh(&sc->sc_resetlock);
 309
 310                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 311                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 312
 313                 if (ath_startrecv(sc) != 0) {
 314                         DPRINTF(sc, ATH_DBG_FATAL,
 315                                 "Unable to restart recv logic\n");
 316                         return -EIO;
 317                 }
 318
 319                 ath_setcurmode(sc, ath_chan2mode(hchan));
 320                 ath_update_txpow(sc);
 321                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 322         }
 323         return 0;
 324 }
 325
 326 /*
 327  *  This routine performs the periodic noise floor calibration function
 328  *  that is used to adjust and optimize the chip performance.  This
 329  *  takes environmental changes (location, temperature) into account.
 330  *  When the task is complete, it reschedules itself depending on the
 331  *  appropriate interval that was calculated.
 332  */
 333 static void ath_ani_calibrate(unsigned long data)
 334 {
 335         struct ath_softc *sc;
 336         struct ath_hal *ah;
 337         bool longcal = false;
 338         bool shortcal = false;
 339         bool aniflag = false;
 340         unsigned int timestamp = jiffies_to_msecs(jiffies);
 341         u32 cal_interval;
 342
 343         sc = (struct ath_softc *)data;
 344         ah = sc->sc_ah;
 345
 346         /*
 347         * don't calibrate when we're scanning.
 348         * we are most likely not on our home channel.
 349         */
 350         if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
 351                 return;
 352
 353         /* Long calibration runs independently of short calibration. */
 354         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 355                 longcal = true;
 356                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 357                 sc->sc_ani.sc_longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while sc_caldone is false */
 361         if (!sc->sc_ani.sc_caldone) {
 362                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 363                     ATH_SHORT_CALINTERVAL) {
 364                         shortcal = true;
 365                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 366                         sc->sc_ani.sc_shortcal_timer = timestamp;
 367                         sc->sc_ani.sc_resetcal_timer = timestamp;
 368                 }
 369         } else {
 370                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 371                     ATH_RESTART_CALINTERVAL) {
 372                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 373                                                 &sc->sc_ani.sc_caldone);
 374                         if (sc->sc_ani.sc_caldone)
 375                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 376                 }
 377         }
 378
 379         /* Verify whether we must check ANI */
 380         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 381            ATH_ANI_POLLINTERVAL) {
 382                 aniflag = true;
 383                 sc->sc_ani.sc_checkani_timer = timestamp;
 384         }
 385
 386         /* Skip all processing if there's nothing to do. */
 387         if (longcal || shortcal || aniflag) {
 388                 /* Call ANI routine if necessary */
 389                 if (aniflag)
 390                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 391                                              ah->ah_curchan);
 392
 393                 /* Perform calibration if necessary */
 394                 if (longcal || shortcal) {
 395                         bool iscaldone = false;
 396
 397                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 398                                                sc->sc_rx_chainmask, longcal,
 399                                                &iscaldone)) {
 400                                 if (longcal)
 401                                         sc->sc_ani.sc_noise_floor =
 402                                                 ath9k_hw_getchan_noise(ah,
 403                                                                ah->ah_curchan);
 404
 405                                 DPRINTF(sc, ATH_DBG_ANI,
 406                                         "calibrate chan %u/%x nf: %d\n",
 407                                         ah->ah_curchan->channel,
 408                                         ah->ah_curchan->channelFlags,
 409                                         sc->sc_ani.sc_noise_floor);
 410                         } else {
 411                                 DPRINTF(sc, ATH_DBG_ANY,
 412                                         "calibrate chan %u/%x failed\n",
 413                                         ah->ah_curchan->channel,
 414                                         ah->ah_curchan->channelFlags);
 415                         }
 416                         sc->sc_ani.sc_caldone = iscaldone;
 417                 }
 418         }
 419
 420         /*
 421         * Set timer interval based on previous results.
 422         * The interval must be the shortest necessary to satisfy ANI,
 423         * short calibration and long calibration.
 424         */
 425         cal_interval = ATH_LONG_CALINTERVAL;
 426         if (sc->sc_ah->ah_config.enable_ani)
 427                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 428         if (!sc->sc_ani.sc_caldone)
 429                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 430
 431         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 432 }
 433
 434 /*
 435  * Update tx/rx chainmask. For legacy association,
 436  * hard code chainmask to 1x1, for 11n association, use
 437  * the chainmask configuration.
 438  */
 439 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 440 {
 441         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 442         if (is_ht) {
 443                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 444                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 445         } else {
 446                 sc->sc_tx_chainmask = 1;
 447                 sc->sc_rx_chainmask = 1;
 448         }
 449
 450         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 451                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 452 }
 453
 454 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 455 {
 456         struct ath_node *an;
 457
 458         an = (struct ath_node *)sta->drv_priv;
 459
 460         if (sc->sc_flags & SC_OP_TXAGGR)
 461                 ath_tx_node_init(sc, an);
 462
 463         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 464                              sta->ht_cap.ampdu_factor);
 465         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 466 }
 467
 468 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 469 {
 470         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 471
 472         if (sc->sc_flags & SC_OP_TXAGGR)
 473                 ath_tx_node_cleanup(sc, an);
 474 }
 475
 476 static void ath9k_tasklet(unsigned long data)
 477 {
 478         struct ath_softc *sc = (struct ath_softc *)data;
 479         u32 status = sc->sc_intrstatus;
 480
 481         if (status & ATH9K_INT_FATAL) {
 482                 /* need a chip reset */
 483                 ath_reset(sc, false);
 484                 return;
 485         } else {
 486
 487                 if (status &
 488                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 489                         spin_lock_bh(&sc->sc_rxflushlock);
 490                         ath_rx_tasklet(sc, 0);
 491                         spin_unlock_bh(&sc->sc_rxflushlock);
 492                 }
 493                 /* XXX: optimize this */
 494                 if (status & ATH9K_INT_TX)
 495                         ath_tx_tasklet(sc);
 496         }
 497
 498         /* re-enable hardware interrupt */
 499         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 500 }
 501
 502 static irqreturn_t ath_isr(int irq, void *dev)
 503 {
 504         struct ath_softc *sc = dev;
 505         struct ath_hal *ah = sc->sc_ah;
 506         enum ath9k_int status;
 507         bool sched = false;
 508
 509         do {
 510                 if (sc->sc_flags & SC_OP_INVALID) {
 511                         /*
 512                          * The hardware is not ready/present, don't
 513                          * touch anything. Note this can happen early
 514                          * on if the IRQ is shared.
 515                          */
 516                         return IRQ_NONE;
 517                 }
 518                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 519                         return IRQ_NONE;
 520                 }
 521
 522                 /*
 523                  * Figure out the reason(s) for the interrupt.  Note
 524                  * that the hal returns a pseudo-ISR that may include
 525                  * bits we haven't explicitly enabled so we mask the
 526                  * value to insure we only process bits we requested.
 527                  */
 528                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 529
 530                 status &= sc->sc_imask; /* discard unasked-for bits */
 531
 532                 /*
 533                  * If there are no status bits set, then this interrupt was not
 534                  * for me (should have been caught above).
 535                  */
 536                 if (!status)
 537                         return IRQ_NONE;
 538
 539                 sc->sc_intrstatus = status;
 540
 541                 if (status & ATH9K_INT_FATAL) {
 542                         /* need a chip reset */
 543                         sched = true;
 544                 } else if (status & ATH9K_INT_RXORN) {
 545                         /* need a chip reset */
 546                         sched = true;
 547                 } else {
 548                         if (status & ATH9K_INT_SWBA) {
 549                                 /* schedule a tasklet for beacon handling */
 550                                 tasklet_schedule(&sc->bcon_tasklet);
 551                         }
 552                         if (status & ATH9K_INT_RXEOL) {
 553                                 /*
 554                                  * NB: the hardware should re-read the link when
 555                                  *     RXE bit is written, but it doesn't work
 556                                  *     at least on older hardware revs.
 557                                  */
 558                                 sched = true;
 559                         }
 560
 561                         if (status & ATH9K_INT_TXURN)
 562                                 /* bump tx trigger level */
 563                                 ath9k_hw_updatetxtriglevel(ah, true);
 564                         /* XXX: optimize this */
 565                         if (status & ATH9K_INT_RX)
 566                                 sched = true;
 567                         if (status & ATH9K_INT_TX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_BMISS)
 570                                 sched = true;
 571                         /* carrier sense timeout */
 572                         if (status & ATH9K_INT_CST)
 573                                 sched = true;
 574                         if (status & ATH9K_INT_MIB) {
 575                                 /*
 576                                  * Disable interrupts until we service the MIB
 577                                  * interrupt; otherwise it will continue to
 578                                  * fire.
 579                                  */
 580                                 ath9k_hw_set_interrupts(ah, 0);
 581                                 /*
 582                                  * Let the hal handle the event. We assume
 583                                  * it will clear whatever condition caused
 584                                  * the interrupt.
 585                                  */
 586                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 587                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 588                         }
 589                         if (status & ATH9K_INT_TIM_TIMER) {
 590                                 if (!(ah->ah_caps.hw_caps &
 591                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 592                                         /* Clear RxAbort bit so that we can
 593                                          * receive frames */
 594                                         ath9k_hw_setrxabort(ah, 0);
 595                                         sched = true;
 596                                 }
 597                         }
 598                 }
 599         } while (0);
 600
 601         ath_debug_stat_interrupt(sc, status);
 602
 603         if (sched) {
 604                 /* turn off every interrupt except SWBA */
 605                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 606                 tasklet_schedule(&sc->intr_tq);
 607         }
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static int ath_get_channel(struct ath_softc *sc,
 613                            struct ieee80211_channel *chan)
 614 {
 615         int i;
 616
 617         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 618                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 619                         return i;
 620         }
 621
 622         return -1;
 623 }
 624
 625 /* ext_chan_offset: (-1, 0, 1) (below, none, above) */
 626
 627 static u32 ath_get_extchanmode(struct ath_softc *sc,
 628                                struct ieee80211_channel *chan,
 629                                int ext_chan_offset,
 630                                enum ath9k_ht_macmode tx_chan_width)
 631 {
 632         u32 chanmode = 0;
 633
 634         switch (chan->band) {
 635         case IEEE80211_BAND_2GHZ:
 636                 if ((ext_chan_offset == 0) &&
 637                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 638                         chanmode = CHANNEL_G_HT20;
 639                 if ((ext_chan_offset == 1) &&
 640                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 641                         chanmode = CHANNEL_G_HT40PLUS;
 642                 if ((ext_chan_offset == -1) &&
 643                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 644                         chanmode = CHANNEL_G_HT40MINUS;
 645                 break;
 646         case IEEE80211_BAND_5GHZ:
 647                 if ((ext_chan_offset == 0) &&
 648                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 649                         chanmode = CHANNEL_A_HT20;
 650                 if ((ext_chan_offset == 1) &&
 651                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 652                         chanmode = CHANNEL_A_HT40PLUS;
 653                 if ((ext_chan_offset == -1) &&
 654                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 655                         chanmode = CHANNEL_A_HT40MINUS;
 656                 break;
 657         default:
 658                 break;
 659         }
 660
 661         return chanmode;
 662 }
 663
 664 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 665 {
 666         ath9k_hw_keyreset(sc->sc_ah, keyix);
 667         if (freeslot)
 668                 clear_bit(keyix, sc->sc_keymap);
 669 }
 670
 671 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 672                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 673 {
 674         bool status;
 675
 676         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 677                 keyix, hk, mac, false);
 678
 679         return status != false;
 680 }
 681
 682 static int ath_setkey_tkip(struct ath_softc *sc,
 683                            struct ieee80211_key_conf *key,
 684                            struct ath9k_keyval *hk,
 685                            const u8 *addr)
 686 {
 687         u8 *key_rxmic = NULL;
 688         u8 *key_txmic = NULL;
 689
 690         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 691         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 692
 693         if (addr == NULL) {
 694                 /* Group key installation */
 695                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 696                 return ath_keyset(sc, key->keyidx, hk, addr);
 697         }
 698         if (!sc->sc_splitmic) {
 699                 /*
 700                  * data key goes at first index,
 701                  * the hal handles the MIC keys at index+64.
 702                  */
 703                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 704                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 705                 return ath_keyset(sc, key->keyidx, hk, addr);
 706         }
 707         /*
 708          * TX key goes at first index, RX key at +32.
 709          * The hal handles the MIC keys at index+64.
 710          */
 711         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 712         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 713                 /* Txmic entry failed. No need to proceed further */
 714                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 715                         "Setting TX MIC Key Failed\n");
 716                 return 0;
 717         }
 718
 719         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 720         /* XXX delete tx key on failure? */
 721         return ath_keyset(sc, key->keyidx+32, hk, addr);
 722 }
 723
 724 static int ath_key_config(struct ath_softc *sc,
 725                           const u8 *addr,
 726                           struct ieee80211_key_conf *key)
 727 {
 728         struct ieee80211_vif *vif;
 729         struct ath9k_keyval hk;
 730         const u8 *mac = NULL;
 731         int ret = 0;
 732         enum nl80211_iftype opmode;
 733
 734         memset(&hk, 0, sizeof(hk));
 735
 736         switch (key->alg) {
 737         case ALG_WEP:
 738                 hk.kv_type = ATH9K_CIPHER_WEP;
 739                 break;
 740         case ALG_TKIP:
 741                 hk.kv_type = ATH9K_CIPHER_TKIP;
 742                 break;
 743         case ALG_CCMP:
 744                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 745                 break;
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         hk.kv_len  = key->keylen;
 751         memcpy(hk.kv_val, key->key, key->keylen);
 752
 753         if (!sc->sc_vaps[0])
 754                 return -EIO;
 755
 756         vif = sc->sc_vaps[0];
 757         opmode = vif->type;
 758
 759         /*
 760          *  Strategy:
 761          *   For STA mc tx, we will not setup a key at
 762          *   all since we never tx mc.
 763          *
 764          *   For STA mc rx, we will use the keyID.
 765          *
 766          *   For ADHOC mc tx, we will use the keyID, and no macaddr.
 767          *
 768          *   For ADHOC mc rx, we will alloc a slot and plumb the mac of
 769          *   the peer node.
 770          *   BUT we will plumb a cleartext key so that we can do
 771          *   per-Sta default key table lookup in software.
 772          */
 773         if (is_broadcast_ether_addr(addr)) {
 774                 switch (opmode) {
 775                 case NL80211_IFTYPE_STATION:
 776                         /* default key:  could be group WPA key
 777                          * or could be static WEP key */
 778                         mac = NULL;
 779                         break;
 780                 case NL80211_IFTYPE_ADHOC:
 781                         break;
 782                 case NL80211_IFTYPE_AP:
 783                         break;
 784                 default:
 785                         ASSERT(0);
 786                         break;
 787                 }
 788         } else {
 789                 mac = addr;
 790         }
 791
 792         if (key->alg == ALG_TKIP)
 793                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 794         else
 795                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 796
 797         if (!ret)
 798                 return -EIO;
 799
 800         return 0;
 801 }
 802
 803 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 804 {
 805         int freeslot;
 806
 807         freeslot = (key->keyidx >= 4) ? 1 : 0;
 808         ath_key_reset(sc, key->keyidx, freeslot);
 809 }
 810
 811 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 812 {
 813 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 814 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 815
 816         ht_info->ht_supported = true;
 817         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 818                        IEEE80211_HT_CAP_SM_PS |
 819                        IEEE80211_HT_CAP_SGI_40 |
 820                        IEEE80211_HT_CAP_DSSSCCK40;
 821
 822         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 823         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 824         /* set up supported mcs set */
 825         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 826         ht_info->mcs.rx_mask[0] = 0xff;
 827         ht_info->mcs.rx_mask[1] = 0xff;
 828         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 829 }
 830
 831 static void ath9k_ht_conf(struct ath_softc *sc,
 832                           struct ieee80211_bss_conf *bss_conf)
 833 {
 834         if (sc->hw->conf.ht.enabled) {
 835                 if (bss_conf->ht.width_40_ok)
 836                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 837                 else
 838                         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 839
 840                 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
 841
 842                 DPRINTF(sc, ATH_DBG_CONFIG,
 843                         "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width);
 844         }
 845 }
 846
 847 static inline int ath_sec_offset(u8 ext_offset)
 848 {
 849         if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE)
 850                 return 0;
 851         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
 852                 return 1;
 853         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 860                                  struct ieee80211_vif *vif,
 861                                  struct ieee80211_bss_conf *bss_conf)
 862 {
 863         struct ieee80211_hw *hw = sc->hw;
 864         struct ieee80211_channel *curchan = hw->conf.channel;
 865         struct ath_vap *avp = (void *)vif->drv_priv;
 866         int pos;
 867
 868         if (bss_conf->assoc) {
 869                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid);
 870
 871                 /* New association, store aid */
 872                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 873                         sc->sc_curaid = bss_conf->aid;
 874                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 875                                                sc->sc_curaid);
 876                 }
 877
 878                 /* Configure the beacon */
 879                 ath_beacon_config(sc, 0);
 880                 sc->sc_flags |= SC_OP_BEACONS;
 881
 882                 /* Reset rssi stats */
 883                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 884                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 885                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 886                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 887
 888                 /* Update chainmask */
 889                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 890
 891                 DPRINTF(sc, ATH_DBG_CONFIG,
 892                         "bssid %pM aid 0x%x\n",
 893                         sc->sc_curbssid, sc->sc_curaid);
 894
 895                 pos = ath_get_channel(sc, curchan);
 896                 if (pos == -1) {
 897                         DPRINTF(sc, ATH_DBG_FATAL,
 898                                 "Invalid channel: %d\n", curchan->center_freq);
 899                         return;
 900                 }
 901
 902                 if (hw->conf.ht.enabled) {
 903                         int offset =
 904                                 ath_sec_offset(bss_conf->ht.secondary_channel_offset);
 905                         sc->tx_chan_width = (bss_conf->ht.width_40_ok) ?
 906                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
 907
 908                         sc->sc_ah->ah_channels[pos].chanmode =
 909                                 ath_get_extchanmode(sc, curchan,
 910                                                     offset, sc->tx_chan_width);
 911                 } else {
 912                         sc->sc_ah->ah_channels[pos].chanmode =
 913                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 914                                 CHANNEL_G : CHANNEL_A;
 915                 }
 916
 917                 /* set h/w channel */
 918                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 919                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n",
 920                                 curchan->center_freq);
 921
 922                 /* Start ANI */
 923                 mod_timer(&sc->sc_ani.timer,
 924                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 925
 926         } else {
 927                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 928                 sc->sc_curaid = 0;
 929         }
 930 }
 931
 932 /********************************/
 933 /*       LED functions          */
 934 /********************************/
 935
 936 static void ath_led_brightness(struct led_classdev *led_cdev,
 937                                enum led_brightness brightness)
 938 {
 939         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 940         struct ath_softc *sc = led->sc;
 941
 942         switch (brightness) {
 943         case LED_OFF:
 944                 if (led->led_type == ATH_LED_ASSOC ||
 945                     led->led_type == ATH_LED_RADIO)
 946                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 947                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 948                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 949                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 950                 break;
 951         case LED_FULL:
 952                 if (led->led_type == ATH_LED_ASSOC)
 953                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 954                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 955                 break;
 956         default:
 957                 break;
 958         }
 959 }
 960
 961 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 962                             char *trigger)
 963 {
 964         int ret;
 965
 966         led->sc = sc;
 967         led->led_cdev.name = led->name;
 968         led->led_cdev.default_trigger = trigger;
 969         led->led_cdev.brightness_set = ath_led_brightness;
 970
 971         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 972         if (ret)
 973                 DPRINTF(sc, ATH_DBG_FATAL,
 974                         "Failed to register led:%s", led->name);
 975         else
 976                 led->registered = 1;
 977         return ret;
 978 }
 979
 980 static void ath_unregister_led(struct ath_led *led)
 981 {
 982         if (led->registered) {
 983                 led_classdev_unregister(&led->led_cdev);
 984                 led->registered = 0;
 985         }
 986 }
 987
 988 static void ath_deinit_leds(struct ath_softc *sc)
 989 {
 990         ath_unregister_led(&sc->assoc_led);
 991         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 992         ath_unregister_led(&sc->tx_led);
 993         ath_unregister_led(&sc->rx_led);
 994         ath_unregister_led(&sc->radio_led);
 995         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 996 }
 997
 998 static void ath_init_leds(struct ath_softc *sc)
 999 {
1000         char *trigger;
1001         int ret;
1002
1003         /* Configure gpio 1 for output */
1004         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1005                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1006         /* LED off, active low */
1007         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1008
1009         trigger = ieee80211_get_radio_led_name(sc->hw);
1010         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1011                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1012         ret = ath_register_led(sc, &sc->radio_led, trigger);
1013         sc->radio_led.led_type = ATH_LED_RADIO;
1014         if (ret)
1015                 goto fail;
1016
1017         trigger = ieee80211_get_assoc_led_name(sc->hw);
1018         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1019                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1020         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1021         sc->assoc_led.led_type = ATH_LED_ASSOC;
1022         if (ret)
1023                 goto fail;
1024
1025         trigger = ieee80211_get_tx_led_name(sc->hw);
1026         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1027                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1028         ret = ath_register_led(sc, &sc->tx_led, trigger);
1029         sc->tx_led.led_type = ATH_LED_TX;
1030         if (ret)
1031                 goto fail;
1032
1033         trigger = ieee80211_get_rx_led_name(sc->hw);
1034         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1035                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1036         ret = ath_register_led(sc, &sc->rx_led, trigger);
1037         sc->rx_led.led_type = ATH_LED_RX;
1038         if (ret)
1039                 goto fail;
1040
1041         return;
1042
1043 fail:
1044         ath_deinit_leds(sc);
1045 }
1046
1047 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1048
1049 /*******************/
1050 /*      Rfkill     */
1051 /*******************/
1052
1053 static void ath_radio_enable(struct ath_softc *sc)
1054 {
1055         struct ath_hal *ah = sc->sc_ah;
1056         int status;
1057
1058         spin_lock_bh(&sc->sc_resetlock);
1059         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1060                             sc->tx_chan_width,
1061                             sc->sc_tx_chainmask,
1062                             sc->sc_rx_chainmask,
1063                             sc->sc_ht_extprotspacing,
1064                             false, &status)) {
1065                 DPRINTF(sc, ATH_DBG_FATAL,
1066                         "Unable to reset channel %u (%uMhz) "
1067                         "flags 0x%x hal status %u\n",
1068                         ath9k_hw_mhz2ieee(ah,
1069                                           ah->ah_curchan->channel,
1070                                           ah->ah_curchan->channelFlags),
1071                         ah->ah_curchan->channel,
1072                         ah->ah_curchan->channelFlags, status);
1073         }
1074         spin_unlock_bh(&sc->sc_resetlock);
1075
1076         ath_update_txpow(sc);
1077         if (ath_startrecv(sc) != 0) {
1078                 DPRINTF(sc, ATH_DBG_FATAL,
1079                         "Unable to restart recv logic\n");
1080                 return;
1081         }
1082
1083         if (sc->sc_flags & SC_OP_BEACONS)
1084                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1085
1086         /* Re-Enable  interrupts */
1087         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1088
1089         /* Enable LED */
1090         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1091                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1092         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1093
1094         ieee80211_wake_queues(sc->hw);
1095 }
1096
1097 static void ath_radio_disable(struct ath_softc *sc)
1098 {
1099         struct ath_hal *ah = sc->sc_ah;
1100         int status;
1101
1102
1103         ieee80211_stop_queues(sc->hw);
1104
1105         /* Disable LED */
1106         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1107         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1108
1109         /* Disable interrupts */
1110         ath9k_hw_set_interrupts(ah, 0);
1111
1112         ath_draintxq(sc, false);        /* clear pending tx frames */
1113         ath_stoprecv(sc);               /* turn off frame recv */
1114         ath_flushrecv(sc);              /* flush recv queue */
1115
1116         spin_lock_bh(&sc->sc_resetlock);
1117         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1118                             sc->tx_chan_width,
1119                             sc->sc_tx_chainmask,
1120                             sc->sc_rx_chainmask,
1121                             sc->sc_ht_extprotspacing,
1122                             false, &status)) {
1123                 DPRINTF(sc, ATH_DBG_FATAL,
1124                         "Unable to reset channel %u (%uMhz) "
1125                         "flags 0x%x hal status %u\n",
1126                         ath9k_hw_mhz2ieee(ah,
1127                                 ah->ah_curchan->channel,
1128                                 ah->ah_curchan->channelFlags),
1129                         ah->ah_curchan->channel,
1130                         ah->ah_curchan->channelFlags, status);
1131         }
1132         spin_unlock_bh(&sc->sc_resetlock);
1133
1134         ath9k_hw_phy_disable(ah);
1135         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1136 }
1137
1138 static bool ath_is_rfkill_set(struct ath_softc *sc)
1139 {
1140         struct ath_hal *ah = sc->sc_ah;
1141
1142         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1143                                   ah->ah_rfkill_polarity;
1144 }
1145
1146 /* h/w rfkill poll function */
1147 static void ath_rfkill_poll(struct work_struct *work)
1148 {
1149         struct ath_softc *sc = container_of(work, struct ath_softc,
1150                                             rf_kill.rfkill_poll.work);
1151         bool radio_on;
1152
1153         if (sc->sc_flags & SC_OP_INVALID)
1154                 return;
1155
1156         radio_on = !ath_is_rfkill_set(sc);
1157
1158         /*
1159          * enable/disable radio only when there is a
1160          * state change in RF switch
1161          */
1162         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1163                 enum rfkill_state state;
1164
1165                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1166                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1167                                 : RFKILL_STATE_HARD_BLOCKED;
1168                 } else if (radio_on) {
1169                         ath_radio_enable(sc);
1170                         state = RFKILL_STATE_UNBLOCKED;
1171                 } else {
1172                         ath_radio_disable(sc);
1173                         state = RFKILL_STATE_HARD_BLOCKED;
1174                 }
1175
1176                 if (state == RFKILL_STATE_HARD_BLOCKED)
1177                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1178                 else
1179                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1180
1181                 rfkill_force_state(sc->rf_kill.rfkill, state);
1182         }
1183
1184         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1185                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1186 }
1187
1188 /* s/w rfkill handler */
1189 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1190 {
1191         struct ath_softc *sc = data;
1192
1193         switch (state) {
1194         case RFKILL_STATE_SOFT_BLOCKED:
1195                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1196                     SC_OP_RFKILL_SW_BLOCKED)))
1197                         ath_radio_disable(sc);
1198                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1199                 return 0;
1200         case RFKILL_STATE_UNBLOCKED:
1201                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1202                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1203                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1204                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1205                                         "radio as it is disabled by h/w\n");
1206                                 return -EPERM;
1207                         }
1208                         ath_radio_enable(sc);
1209                 }
1210                 return 0;
1211         default:
1212                 return -EINVAL;
1213         }
1214 }
1215
1216 /* Init s/w rfkill */
1217 static int ath_init_sw_rfkill(struct ath_softc *sc)
1218 {
1219         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1220                                              RFKILL_TYPE_WLAN);
1221         if (!sc->rf_kill.rfkill) {
1222                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1223                 return -ENOMEM;
1224         }
1225
1226         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1227                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1228         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1229         sc->rf_kill.rfkill->data = sc;
1230         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1231         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1232         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1233
1234         return 0;
1235 }
1236
1237 /* Deinitialize rfkill */
1238 static void ath_deinit_rfkill(struct ath_softc *sc)
1239 {
1240         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1241                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1242
1243         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1244                 rfkill_unregister(sc->rf_kill.rfkill);
1245                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1246                 sc->rf_kill.rfkill = NULL;
1247         }
1248 }
1249
1250 static int ath_start_rfkill_poll(struct ath_softc *sc)
1251 {
1252         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1253                 queue_delayed_work(sc->hw->workqueue,
1254                                    &sc->rf_kill.rfkill_poll, 0);
1255
1256         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1257                 if (rfkill_register(sc->rf_kill.rfkill)) {
1258                         DPRINTF(sc, ATH_DBG_FATAL,
1259                                 "Unable to register rfkill\n");
1260                         rfkill_free(sc->rf_kill.rfkill);
1261
1262                         /* Deinitialize the device */
1263                         ath_detach(sc);
1264                         if (sc->pdev->irq)
1265                                 free_irq(sc->pdev->irq, sc);
1266                         pci_iounmap(sc->pdev, sc->mem);
1267                         pci_release_region(sc->pdev, 0);
1268                         pci_disable_device(sc->pdev);
1269                         ieee80211_free_hw(sc->hw);
1270                         return -EIO;
1271                 } else {
1272                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1273                 }
1274         }
1275
1276         return 0;
1277 }
1278 #endif /* CONFIG_RFKILL */
1279
1280 static void ath_detach(struct ath_softc *sc)
1281 {
1282         struct ieee80211_hw *hw = sc->hw;
1283         int i = 0;
1284
1285         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1286
1287 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1288         ath_deinit_rfkill(sc);
1289 #endif
1290         ath_deinit_leds(sc);
1291
1292         ieee80211_unregister_hw(hw);
1293
1294         ath_rate_control_unregister();
1295
1296         ath_rx_cleanup(sc);
1297         ath_tx_cleanup(sc);
1298
1299         tasklet_kill(&sc->intr_tq);
1300         tasklet_kill(&sc->bcon_tasklet);
1301
1302         if (!(sc->sc_flags & SC_OP_INVALID))
1303                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1304
1305         /* cleanup tx queues */
1306         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1307                 if (ATH_TXQ_SETUP(sc, i))
1308                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1309
1310         ath9k_hw_detach(sc->sc_ah);
1311         ath9k_exit_debug(sc);
1312 }
1313
1314 static int ath_init(u16 devid, struct ath_softc *sc)
1315 {
1316         struct ath_hal *ah = NULL;
1317         int status;
1318         int error = 0, i;
1319         int csz = 0;
1320
1321         /* XXX: hardware will not be ready until ath_open() being called */
1322         sc->sc_flags |= SC_OP_INVALID;
1323
1324         if (ath9k_init_debug(sc) < 0)
1325                 printk(KERN_ERR "Unable to create debugfs files\n");
1326
1327         spin_lock_init(&sc->sc_resetlock);
1328         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1329         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1330                      (unsigned long)sc);
1331
1332         /*
1333          * Cache line size is used to size and align various
1334          * structures used to communicate with the hardware.
1335          */
1336         bus_read_cachesize(sc, &csz);
1337         /* XXX assert csz is non-zero */
1338         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1339
1340         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1341         if (ah == NULL) {
1342                 DPRINTF(sc, ATH_DBG_FATAL,
1343                         "Unable to attach hardware; HAL status %u\n", status);
1344                 error = -ENXIO;
1345                 goto bad;
1346         }
1347         sc->sc_ah = ah;
1348
1349         /* Get the hardware key cache size. */
1350         sc->sc_keymax = ah->ah_caps.keycache_size;
1351         if (sc->sc_keymax > ATH_KEYMAX) {
1352                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1353                         "Warning, using only %u entries in %u key cache\n",
1354                         ATH_KEYMAX, sc->sc_keymax);
1355                 sc->sc_keymax = ATH_KEYMAX;
1356         }
1357
1358         /*
1359          * Reset the key cache since some parts do not
1360          * reset the contents on initial power up.
1361          */
1362         for (i = 0; i < sc->sc_keymax; i++)
1363                 ath9k_hw_keyreset(ah, (u16) i);
1364         /*
1365          * Mark key cache slots associated with global keys
1366          * as in use.  If we knew TKIP was not to be used we
1367          * could leave the +32, +64, and +32+64 slots free.
1368          * XXX only for splitmic.
1369          */
1370         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1371                 set_bit(i, sc->sc_keymap);
1372                 set_bit(i + 32, sc->sc_keymap);
1373                 set_bit(i + 64, sc->sc_keymap);
1374                 set_bit(i + 32 + 64, sc->sc_keymap);
1375         }
1376
1377         /* Collect the channel list using the default country code */
1378
1379         error = ath_setup_channels(sc);
1380         if (error)
1381                 goto bad;
1382
1383         /* default to MONITOR mode */
1384         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1385
1386
1387         /* Setup rate tables */
1388
1389         ath_rate_attach(sc);
1390         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1391         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1392
1393         /*
1394          * Allocate hardware transmit queues: one queue for
1395          * beacon frames and one data queue for each QoS
1396          * priority.  Note that the hal handles reseting
1397          * these queues at the needed time.
1398          */
1399         sc->sc_bhalq = ath_beaconq_setup(ah);
1400         if (sc->sc_bhalq == -1) {
1401                 DPRINTF(sc, ATH_DBG_FATAL,
1402                         "Unable to setup a beacon xmit queue\n");
1403                 error = -EIO;
1404                 goto bad2;
1405         }
1406         sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1407         if (sc->sc_cabq == NULL) {
1408                 DPRINTF(sc, ATH_DBG_FATAL,
1409                         "Unable to setup CAB xmit queue\n");
1410                 error = -EIO;
1411                 goto bad2;
1412         }
1413
1414         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1415         ath_cabq_update(sc);
1416
1417         for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1418                 sc->sc_haltype2q[i] = -1;
1419
1420         /* Setup data queues */
1421         /* NB: ensure BK queue is the lowest priority h/w queue */
1422         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1423                 DPRINTF(sc, ATH_DBG_FATAL,
1424                         "Unable to setup xmit queue for BK traffic\n");
1425                 error = -EIO;
1426                 goto bad2;
1427         }
1428
1429         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1430                 DPRINTF(sc, ATH_DBG_FATAL,
1431                         "Unable to setup xmit queue for BE traffic\n");
1432                 error = -EIO;
1433                 goto bad2;
1434         }
1435         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1436                 DPRINTF(sc, ATH_DBG_FATAL,
1437                         "Unable to setup xmit queue for VI traffic\n");
1438                 error = -EIO;
1439                 goto bad2;
1440         }
1441         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1442                 DPRINTF(sc, ATH_DBG_FATAL,
1443                         "Unable to setup xmit queue for VO traffic\n");
1444                 error = -EIO;
1445                 goto bad2;
1446         }
1447
1448         /* Initializes the noise floor to a reasonable default value.
1449          * Later on this will be updated during ANI processing. */
1450
1451         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1452         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1453
1454         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1455                                    ATH9K_CIPHER_TKIP, NULL)) {
1456                 /*
1457                  * Whether we should enable h/w TKIP MIC.
1458                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1459                  * report WMM capable, so it's always safe to turn on
1460                  * TKIP MIC in this case.
1461                  */
1462                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1463                                        0, 1, NULL);
1464         }
1465
1466         /*
1467          * Check whether the separate key cache entries
1468          * are required to handle both tx+rx MIC keys.
1469          * With split mic keys the number of stations is limited
1470          * to 27 otherwise 59.
1471          */
1472         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473                                    ATH9K_CIPHER_TKIP, NULL)
1474             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1475                                       ATH9K_CIPHER_MIC, NULL)
1476             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1477                                       0, NULL))
1478                 sc->sc_splitmic = 1;
1479
1480         /* turn on mcast key search if possible */
1481         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1482                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1483                                              1, NULL);
1484
1485         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1486         sc->sc_config.txpowlimit_override = 0;
1487
1488         /* 11n Capabilities */
1489         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1490                 sc->sc_flags |= SC_OP_TXAGGR;
1491                 sc->sc_flags |= SC_OP_RXAGGR;
1492         }
1493
1494         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1495         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1496
1497         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1498         sc->sc_defant = ath9k_hw_getdefantenna(ah);
1499
1500         ath9k_hw_getmac(ah, sc->sc_myaddr);
1501         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1502                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1503                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1504                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1505         }
1506
1507         sc->sc_slottime = ATH9K_SLOT_TIME_9;    /* default to short slot time */
1508
1509         /* initialize beacon slots */
1510         for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1511                 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1512
1513         /* save MISC configurations */
1514         sc->sc_config.swBeaconProcess = 1;
1515
1516         /* setup channels and rates */
1517
1518         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1519                 sc->channels[IEEE80211_BAND_2GHZ];
1520         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1521                 sc->rates[IEEE80211_BAND_2GHZ];
1522         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1523
1524         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1525                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1526                         sc->channels[IEEE80211_BAND_5GHZ];
1527                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1528                         sc->rates[IEEE80211_BAND_5GHZ];
1529                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1530         }
1531
1532         return 0;
1533 bad2:
1534         /* cleanup tx queues */
1535         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1536                 if (ATH_TXQ_SETUP(sc, i))
1537                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1538 bad:
1539         if (ah)
1540                 ath9k_hw_detach(ah);
1541
1542         return error;
1543 }
1544
1545 static int ath_attach(u16 devid, struct ath_softc *sc)
1546 {
1547         struct ieee80211_hw *hw = sc->hw;
1548         int error = 0;
1549
1550         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1551
1552         error = ath_init(devid, sc);
1553         if (error != 0)
1554                 return error;
1555
1556         /* get mac address from hardware and set in mac80211 */
1557
1558         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1559
1560         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1561                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1562                 IEEE80211_HW_SIGNAL_DBM |
1563                 IEEE80211_HW_AMPDU_AGGREGATION;
1564
1565         hw->wiphy->interface_modes =
1566                 BIT(NL80211_IFTYPE_AP) |
1567                 BIT(NL80211_IFTYPE_STATION) |
1568                 BIT(NL80211_IFTYPE_ADHOC);
1569
1570         hw->queues = 4;
1571         hw->max_rates = 4;
1572         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1573         hw->sta_data_size = sizeof(struct ath_node);
1574         hw->vif_data_size = sizeof(struct ath_vap);
1575
1576         /* Register rate control */
1577         hw->rate_control_algorithm = "ath9k_rate_control";
1578         error = ath_rate_control_register();
1579         if (error != 0) {
1580                 DPRINTF(sc, ATH_DBG_FATAL,
1581                         "Unable to register rate control algorithm: %d\n", error);
1582                 ath_rate_control_unregister();
1583                 goto bad;
1584         }
1585
1586         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1587                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1588                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1589                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1590         }
1591
1592         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1593         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1594                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1595                         &sc->sbands[IEEE80211_BAND_5GHZ];
1596
1597         /* initialize tx/rx engine */
1598         error = ath_tx_init(sc, ATH_TXBUF);
1599         if (error != 0)
1600                 goto detach;
1601
1602         error = ath_rx_init(sc, ATH_RXBUF);
1603         if (error != 0)
1604                 goto detach;
1605
1606 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1607         /* Initialze h/w Rfkill */
1608         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1609                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1610
1611         /* Initialize s/w rfkill */
1612         if (ath_init_sw_rfkill(sc))
1613                 goto detach;
1614 #endif
1615
1616         error = ieee80211_register_hw(hw);
1617         if (error != 0) {
1618                 ath_rate_control_unregister();
1619                 goto bad;
1620         }
1621
1622         /* Initialize LED control */
1623         ath_init_leds(sc);
1624
1625         return 0;
1626 detach:
1627         ath_detach(sc);
1628 bad:
1629         return error;
1630 }
1631
1632 int ath_reset(struct ath_softc *sc, bool retry_tx)
1633 {
1634         struct ath_hal *ah = sc->sc_ah;
1635         int status;
1636         int error = 0;
1637
1638         ath9k_hw_set_interrupts(ah, 0);
1639         ath_draintxq(sc, retry_tx);
1640         ath_stoprecv(sc);
1641         ath_flushrecv(sc);
1642
1643         spin_lock_bh(&sc->sc_resetlock);
1644         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1645                             sc->tx_chan_width,
1646                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1647                             sc->sc_ht_extprotspacing, false, &status)) {
1648                 DPRINTF(sc, ATH_DBG_FATAL,
1649                         "Unable to reset hardware; hal status %u\n", status);
1650                 error = -EIO;
1651         }
1652         spin_unlock_bh(&sc->sc_resetlock);
1653
1654         if (ath_startrecv(sc) != 0)
1655                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1656
1657         /*
1658          * We may be doing a reset in response to a request
1659          * that changes the channel so update any state that
1660          * might change as a result.
1661          */
1662         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1663
1664         ath_update_txpow(sc);
1665
1666         if (sc->sc_flags & SC_OP_BEACONS)
1667                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1668
1669         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1670
1671         if (retry_tx) {
1672                 int i;
1673                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1674                         if (ATH_TXQ_SETUP(sc, i)) {
1675                                 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1676                                 ath_txq_schedule(sc, &sc->sc_txq[i]);
1677                                 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1678                         }
1679                 }
1680         }
1681
1682         return error;
1683 }
1684
1685 /*
1686  *  This function will allocate both the DMA descriptor structure, and the
1687  *  buffers it contains.  These are used to contain the descriptors used
1688  *  by the system.
1689 */
1690 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1691                       struct list_head *head, const char *name,
1692                       int nbuf, int ndesc)
1693 {
1694 #define DS2PHYS(_dd, _ds)                                               \
1695         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1696 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1697 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1698
1699         struct ath_desc *ds;
1700         struct ath_buf *bf;
1701         int i, bsize, error;
1702
1703         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1704                 name, nbuf, ndesc);
1705
1706         /* ath_desc must be a multiple of DWORDs */
1707         if ((sizeof(struct ath_desc) % 4) != 0) {
1708                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1709                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1710                 error = -ENOMEM;
1711                 goto fail;
1712         }
1713
1714         dd->dd_name = name;
1715         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1716
1717         /*
1718          * Need additional DMA memory because we can't use
1719          * descriptors that cross the 4K page boundary. Assume
1720          * one skipped descriptor per 4K page.
1721          */
1722         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1723                 u32 ndesc_skipped =
1724                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1725                 u32 dma_len;
1726
1727                 while (ndesc_skipped) {
1728                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1729                         dd->dd_desc_len += dma_len;
1730
1731                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1732                 };
1733         }
1734
1735         /* allocate descriptors */
1736         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1737                               dd->dd_desc_len,
1738                               &dd->dd_desc_paddr);
1739         if (dd->dd_desc == NULL) {
1740                 error = -ENOMEM;
1741                 goto fail;
1742         }
1743         ds = dd->dd_desc;
1744         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1745                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1746                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1747
1748         /* allocate buffers */
1749         bsize = sizeof(struct ath_buf) * nbuf;
1750         bf = kmalloc(bsize, GFP_KERNEL);
1751         if (bf == NULL) {
1752                 error = -ENOMEM;
1753                 goto fail2;
1754         }
1755         memset(bf, 0, bsize);
1756         dd->dd_bufptr = bf;
1757
1758         INIT_LIST_HEAD(head);
1759         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1760                 bf->bf_desc = ds;
1761                 bf->bf_daddr = DS2PHYS(dd, ds);
1762
1763                 if (!(sc->sc_ah->ah_caps.hw_caps &
1764                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1765                         /*
1766                          * Skip descriptor addresses which can cause 4KB
1767                          * boundary crossing (addr + length) with a 32 dword
1768                          * descriptor fetch.
1769                          */
1770                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1771                                 ASSERT((caddr_t) bf->bf_desc <
1772                                        ((caddr_t) dd->dd_desc +
1773                                         dd->dd_desc_len));
1774
1775                                 ds += ndesc;
1776                                 bf->bf_desc = ds;
1777                                 bf->bf_daddr = DS2PHYS(dd, ds);
1778                         }
1779                 }
1780                 list_add_tail(&bf->list, head);
1781         }
1782         return 0;
1783 fail2:
1784         pci_free_consistent(sc->pdev,
1785                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1786 fail:
1787         memset(dd, 0, sizeof(*dd));
1788         return error;
1789 #undef ATH_DESC_4KB_BOUND_CHECK
1790 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1791 #undef DS2PHYS
1792 }
1793
1794 void ath_descdma_cleanup(struct ath_softc *sc,
1795                          struct ath_descdma *dd,
1796                          struct list_head *head)
1797 {
1798         pci_free_consistent(sc->pdev,
1799                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1800
1801         INIT_LIST_HEAD(head);
1802         kfree(dd->dd_bufptr);
1803         memset(dd, 0, sizeof(*dd));
1804 }
1805
1806 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1807 {
1808         int qnum;
1809
1810         switch (queue) {
1811         case 0:
1812                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1813                 break;
1814         case 1:
1815                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1816                 break;
1817         case 2:
1818                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1819                 break;
1820         case 3:
1821                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1822                 break;
1823         default:
1824                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1825                 break;
1826         }
1827
1828         return qnum;
1829 }
1830
1831 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1832 {
1833         int qnum;
1834
1835         switch (queue) {
1836         case ATH9K_WME_AC_VO:
1837                 qnum = 0;
1838                 break;
1839         case ATH9K_WME_AC_VI:
1840                 qnum = 1;
1841                 break;
1842         case ATH9K_WME_AC_BE:
1843                 qnum = 2;
1844                 break;
1845         case ATH9K_WME_AC_BK:
1846                 qnum = 3;
1847                 break;
1848         default:
1849                 qnum = -1;
1850                 break;
1851         }
1852
1853         return qnum;
1854 }
1855
1856 /**********************/
1857 /* mac80211 callbacks */
1858 /**********************/
1859
1860 static int ath9k_start(struct ieee80211_hw *hw)
1861 {
1862         struct ath_softc *sc = hw->priv;
1863         struct ieee80211_channel *curchan = hw->conf.channel;
1864         struct ath9k_channel *init_channel;
1865         int error = 0, pos, status;
1866
1867         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1868                 "initial channel: %d MHz\n", curchan->center_freq);
1869
1870         /* setup initial channel */
1871
1872         pos = ath_get_channel(sc, curchan);
1873         if (pos == -1) {
1874                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1875                 error = -EINVAL;
1876                 goto error;
1877         }
1878
1879         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1880         sc->sc_ah->ah_channels[pos].chanmode =
1881                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1882         init_channel = &sc->sc_ah->ah_channels[pos];
1883
1884         /* Reset SERDES registers */
1885         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1886
1887         /*
1888          * The basic interface to setting the hardware in a good
1889          * state is ``reset''.  On return the hardware is known to
1890          * be powered up and with interrupts disabled.  This must
1891          * be followed by initialization of the appropriate bits
1892          * and then setup of the interrupt mask.
1893          */
1894         spin_lock_bh(&sc->sc_resetlock);
1895         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1896                             sc->tx_chan_width,
1897                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1898                             sc->sc_ht_extprotspacing, false, &status)) {
1899                 DPRINTF(sc, ATH_DBG_FATAL,
1900                         "Unable to reset hardware; hal status %u "
1901                         "(freq %u flags 0x%x)\n", status,
1902                         init_channel->channel, init_channel->channelFlags);
1903                 error = -EIO;
1904                 spin_unlock_bh(&sc->sc_resetlock);
1905                 goto error;
1906         }
1907         spin_unlock_bh(&sc->sc_resetlock);
1908
1909         /*
1910          * This is needed only to setup initial state
1911          * but it's best done after a reset.
1912          */
1913         ath_update_txpow(sc);
1914
1915         /*
1916          * Setup the hardware after reset:
1917          * The receive engine is set going.
1918          * Frame transmit is handled entirely
1919          * in the frame output path; there's nothing to do
1920          * here except setup the interrupt mask.
1921          */
1922         if (ath_startrecv(sc) != 0) {
1923                 DPRINTF(sc, ATH_DBG_FATAL,
1924                         "Unable to start recv logic\n");
1925                 error = -EIO;
1926                 goto error;
1927         }
1928
1929         /* Setup our intr mask. */
1930         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1931                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1932                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1933
1934         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1935                 sc->sc_imask |= ATH9K_INT_GTT;
1936
1937         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1938                 sc->sc_imask |= ATH9K_INT_CST;
1939
1940         /*
1941          * Enable MIB interrupts when there are hardware phy counters.
1942          * Note we only do this (at the moment) for station mode.
1943          */
1944         if (ath9k_hw_phycounters(sc->sc_ah) &&
1945             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1946              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1947                 sc->sc_imask |= ATH9K_INT_MIB;
1948         /*
1949          * Some hardware processes the TIM IE and fires an
1950          * interrupt when the TIM bit is set.  For hardware
1951          * that does, if not overridden by configuration,
1952          * enable the TIM interrupt when operating as station.
1953          */
1954         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1955             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1956             !sc->sc_config.swBeaconProcess)
1957                 sc->sc_imask |= ATH9K_INT_TIM;
1958
1959         ath_setcurmode(sc, ath_chan2mode(init_channel));
1960
1961         sc->sc_flags &= ~SC_OP_INVALID;
1962
1963         /* Disable BMISS interrupt when we're not associated */
1964         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1965         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1966
1967         ieee80211_wake_queues(sc->hw);
1968
1969 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1970         error = ath_start_rfkill_poll(sc);
1971 #endif
1972
1973 error:
1974         return error;
1975 }
1976
1977 static int ath9k_tx(struct ieee80211_hw *hw,
1978                     struct sk_buff *skb)
1979 {
1980         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1981         struct ath_softc *sc = hw->priv;
1982         struct ath_tx_control txctl;
1983         int hdrlen, padsize;
1984
1985         memset(&txctl, 0, sizeof(struct ath_tx_control));
1986
1987         /*
1988          * As a temporary workaround, assign seq# here; this will likely need
1989          * to be cleaned up to work better with Beacon transmission and virtual
1990          * BSSes.
1991          */
1992         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1993                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1994                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1995                         sc->seq_no += 0x10;
1996                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1997                 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1998         }
1999
2000         /* Add the padding after the header if this is not already done */
2001         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2002         if (hdrlen & 3) {
2003                 padsize = hdrlen % 4;
2004                 if (skb_headroom(skb) < padsize)
2005                         return -1;
2006                 skb_push(skb, padsize);
2007                 memmove(skb->data, skb->data + padsize, hdrlen);
2008         }
2009
2010         /* Check if a tx queue is available */
2011
2012         txctl.txq = ath_test_get_txq(sc, skb);
2013         if (!txctl.txq)
2014                 goto exit;
2015
2016         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2017
2018         if (ath_tx_start(sc, skb, &txctl) != 0) {
2019                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2020                 goto exit;
2021         }
2022
2023         return 0;
2024 exit:
2025         dev_kfree_skb_any(skb);
2026         return 0;
2027 }
2028
2029 static void ath9k_stop(struct ieee80211_hw *hw)
2030 {
2031         struct ath_softc *sc = hw->priv;
2032
2033         if (sc->sc_flags & SC_OP_INVALID) {
2034                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2035                 return;
2036         }
2037
2038         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2039
2040         ieee80211_stop_queues(sc->hw);
2041
2042         /* make sure h/w will not generate any interrupt
2043          * before setting the invalid flag. */
2044         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2045
2046         if (!(sc->sc_flags & SC_OP_INVALID)) {
2047                 ath_draintxq(sc, false);
2048                 ath_stoprecv(sc);
2049                 ath9k_hw_phy_disable(sc->sc_ah);
2050         } else
2051                 sc->sc_rxlink = NULL;
2052
2053 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2054         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2055                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2056 #endif
2057         /* disable HAL and put h/w to sleep */
2058         ath9k_hw_disable(sc->sc_ah);
2059         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2060
2061         sc->sc_flags |= SC_OP_INVALID;
2062
2063         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2064 }
2065
2066 static int ath9k_add_interface(struct ieee80211_hw *hw,
2067                                struct ieee80211_if_init_conf *conf)
2068 {
2069         struct ath_softc *sc = hw->priv;
2070         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2071         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2072
2073         /* Support only vap for now */
2074
2075         if (sc->sc_nvaps)
2076                 return -ENOBUFS;
2077
2078         switch (conf->type) {
2079         case NL80211_IFTYPE_STATION:
2080                 ic_opmode = NL80211_IFTYPE_STATION;
2081                 break;
2082         case NL80211_IFTYPE_ADHOC:
2083                 ic_opmode = NL80211_IFTYPE_ADHOC;
2084                 break;
2085         case NL80211_IFTYPE_AP:
2086                 ic_opmode = NL80211_IFTYPE_AP;
2087                 break;
2088         default:
2089                 DPRINTF(sc, ATH_DBG_FATAL,
2090                         "Interface type %d not yet supported\n", conf->type);
2091                 return -EOPNOTSUPP;
2092         }
2093
2094         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2095
2096         /* Set the VAP opmode */
2097         avp->av_opmode = ic_opmode;
2098         avp->av_bslot = -1;
2099
2100         if (ic_opmode == NL80211_IFTYPE_AP)
2101                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2102
2103         sc->sc_vaps[0] = conf->vif;
2104         sc->sc_nvaps++;
2105
2106         /* Set the device opmode */
2107         sc->sc_ah->ah_opmode = ic_opmode;
2108
2109         if (conf->type == NL80211_IFTYPE_AP) {
2110                 /* TODO: is this a suitable place to start ANI for AP mode? */
2111                 /* Start ANI */
2112                 mod_timer(&sc->sc_ani.timer,
2113                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2114         }
2115
2116         return 0;
2117 }
2118
2119 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2120                                    struct ieee80211_if_init_conf *conf)
2121 {
2122         struct ath_softc *sc = hw->priv;
2123         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2124
2125         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2126
2127         /* Stop ANI */
2128         del_timer_sync(&sc->sc_ani.timer);
2129
2130         /* Reclaim beacon resources */
2131         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2132             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2133                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2134                 ath_beacon_return(sc, avp);
2135         }
2136
2137         sc->sc_flags &= ~SC_OP_BEACONS;
2138
2139         sc->sc_vaps[0] = NULL;
2140         sc->sc_nvaps--;
2141 }
2142
2143 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2144 {
2145         struct ath_softc *sc = hw->priv;
2146         struct ieee80211_conf *conf = &hw->conf;
2147
2148         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2149                 struct ieee80211_channel *curchan = hw->conf.channel;
2150                 int pos;
2151
2152                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2153                         curchan->center_freq);
2154
2155                 pos = ath_get_channel(sc, curchan);
2156                 if (pos == -1) {
2157                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2158                                 curchan->center_freq);
2159                         return -EINVAL;
2160                 }
2161
2162                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2163                 sc->sc_ah->ah_channels[pos].chanmode =
2164                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2165                         CHANNEL_G : CHANNEL_A;
2166
2167                 if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) &&
2168                     (conf->ht.enabled)) {
2169                         sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ?
2170                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
2171
2172                         sc->sc_ah->ah_channels[pos].chanmode =
2173                                 ath_get_extchanmode(sc, curchan,
2174                                                     conf->ht.sec_chan_offset,
2175                                                     sc->tx_chan_width);
2176                 }
2177
2178                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2179                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2180                         return -EINVAL;
2181                 }
2182         }
2183
2184         if (changed & IEEE80211_CONF_CHANGE_HT)
2185                 ath_update_chainmask(sc, conf->ht.enabled);
2186
2187         if (changed & IEEE80211_CONF_CHANGE_POWER)
2188                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2189
2190         return 0;
2191 }
2192
2193 static int ath9k_config_interface(struct ieee80211_hw *hw,
2194                                   struct ieee80211_vif *vif,
2195                                   struct ieee80211_if_conf *conf)
2196 {
2197         struct ath_softc *sc = hw->priv;
2198         struct ath_hal *ah = sc->sc_ah;
2199         struct ath_vap *avp = (void *)vif->drv_priv;
2200         u32 rfilt = 0;
2201         int error, i;
2202
2203         /* TODO: Need to decide which hw opmode to use for multi-interface
2204          * cases */
2205         if (vif->type == NL80211_IFTYPE_AP &&
2206             ah->ah_opmode != NL80211_IFTYPE_AP) {
2207                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2208                 ath9k_hw_setopmode(ah);
2209                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2210                 /* Request full reset to get hw opmode changed properly */
2211                 sc->sc_flags |= SC_OP_FULL_RESET;
2212         }
2213
2214         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2215             !is_zero_ether_addr(conf->bssid)) {
2216                 switch (vif->type) {
2217                 case NL80211_IFTYPE_STATION:
2218                 case NL80211_IFTYPE_ADHOC:
2219                         /* Set BSSID */
2220                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2221                         sc->sc_curaid = 0;
2222                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2223                                                sc->sc_curaid);
2224
2225                         /* Set aggregation protection mode parameters */
2226                         sc->sc_config.ath_aggr_prot = 0;
2227
2228                         DPRINTF(sc, ATH_DBG_CONFIG,
2229                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2230                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2231
2232                         /* need to reconfigure the beacon */
2233                         sc->sc_flags &= ~SC_OP_BEACONS ;
2234
2235                         break;
2236                 default:
2237                         break;
2238                 }
2239         }
2240
2241         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2242             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2243              (vif->type == NL80211_IFTYPE_AP))) {
2244                 /*
2245                  * Allocate and setup the beacon frame.
2246                  *
2247                  * Stop any previous beacon DMA.  This may be
2248                  * necessary, for example, when an ibss merge
2249                  * causes reconfiguration; we may be called
2250                  * with beacon transmission active.
2251                  */
2252                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2253
2254                 error = ath_beacon_alloc(sc, 0);
2255                 if (error != 0)
2256                         return error;
2257
2258                 ath_beacon_sync(sc, 0);
2259         }
2260
2261         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2262         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2263                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2264                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2265                                 ath9k_hw_keysetmac(sc->sc_ah,
2266                                                    (u16)i,
2267                                                    sc->sc_curbssid);
2268         }
2269
2270         /* Only legacy IBSS for now */
2271         if (vif->type == NL80211_IFTYPE_ADHOC)
2272                 ath_update_chainmask(sc, 0);
2273
2274         return 0;
2275 }
2276
2277 #define SUPPORTED_FILTERS                       \
2278         (FIF_PROMISC_IN_BSS |                   \
2279         FIF_ALLMULTI |                          \
2280         FIF_CONTROL |                           \
2281         FIF_OTHER_BSS |                         \
2282         FIF_BCN_PRBRESP_PROMISC |               \
2283         FIF_FCSFAIL)
2284
2285 /* FIXME: sc->sc_full_reset ? */
2286 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2287                                    unsigned int changed_flags,
2288                                    unsigned int *total_flags,
2289                                    int mc_count,
2290                                    struct dev_mc_list *mclist)
2291 {
2292         struct ath_softc *sc = hw->priv;
2293         u32 rfilt;
2294
2295         changed_flags &= SUPPORTED_FILTERS;
2296         *total_flags &= SUPPORTED_FILTERS;
2297
2298         sc->rx_filter = *total_flags;
2299         rfilt = ath_calcrxfilter(sc);
2300         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2301
2302         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2303                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2304                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2305         }
2306
2307         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter);
2308 }
2309
2310 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2311                              struct ieee80211_vif *vif,
2312                              enum sta_notify_cmd cmd,
2313                              struct ieee80211_sta *sta)
2314 {
2315         struct ath_softc *sc = hw->priv;
2316
2317         switch (cmd) {
2318         case STA_NOTIFY_ADD:
2319                 ath_node_attach(sc, sta);
2320                 break;
2321         case STA_NOTIFY_REMOVE:
2322                 ath_node_detach(sc, sta);
2323                 break;
2324         default:
2325                 break;
2326         }
2327 }
2328
2329 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2330                          u16 queue,
2331                          const struct ieee80211_tx_queue_params *params)
2332 {
2333         struct ath_softc *sc = hw->priv;
2334         struct ath9k_tx_queue_info qi;
2335         int ret = 0, qnum;
2336
2337         if (queue >= WME_NUM_AC)
2338                 return 0;
2339
2340         qi.tqi_aifs = params->aifs;
2341         qi.tqi_cwmin = params->cw_min;
2342         qi.tqi_cwmax = params->cw_max;
2343         qi.tqi_burstTime = params->txop;
2344         qnum = ath_get_hal_qnum(queue, sc);
2345
2346         DPRINTF(sc, ATH_DBG_CONFIG,
2347                 "Configure tx [queue/halq] [%d/%d],  "
2348                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2349                 queue, qnum, params->aifs, params->cw_min,
2350                 params->cw_max, params->txop);
2351
2352         ret = ath_txq_update(sc, qnum, &qi);
2353         if (ret)
2354                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2355
2356         return ret;
2357 }
2358
2359 static int ath9k_set_key(struct ieee80211_hw *hw,
2360                          enum set_key_cmd cmd,
2361                          const u8 *local_addr,
2362                          const u8 *addr,
2363                          struct ieee80211_key_conf *key)
2364 {
2365         struct ath_softc *sc = hw->priv;
2366         int ret = 0;
2367
2368         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2369
2370         switch (cmd) {
2371         case SET_KEY:
2372                 ret = ath_key_config(sc, addr, key);
2373                 if (!ret) {
2374                         set_bit(key->keyidx, sc->sc_keymap);
2375                         key->hw_key_idx = key->keyidx;
2376                         /* push IV and Michael MIC generation to stack */
2377                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2378                         if (key->alg == ALG_TKIP)
2379                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2380                 }
2381                 break;
2382         case DISABLE_KEY:
2383                 ath_key_delete(sc, key);
2384                 clear_bit(key->keyidx, sc->sc_keymap);
2385                 break;
2386         default:
2387                 ret = -EINVAL;
2388         }
2389
2390         return ret;
2391 }
2392
2393 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2394                                    struct ieee80211_vif *vif,
2395                                    struct ieee80211_bss_conf *bss_conf,
2396                                    u32 changed)
2397 {
2398         struct ath_softc *sc = hw->priv;
2399
2400         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2401                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2402                         bss_conf->use_short_preamble);
2403                 if (bss_conf->use_short_preamble)
2404                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2405                 else
2406                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2407         }
2408
2409         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2410                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2411                         bss_conf->use_cts_prot);
2412                 if (bss_conf->use_cts_prot &&
2413                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2414                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2415                 else
2416                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2417         }
2418
2419         if (changed & BSS_CHANGED_HT)
2420                 ath9k_ht_conf(sc, bss_conf);
2421
2422         if (changed & BSS_CHANGED_ASSOC) {
2423                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2424                         bss_conf->assoc);
2425                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2426         }
2427 }
2428
2429 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2430 {
2431         u64 tsf;
2432         struct ath_softc *sc = hw->priv;
2433         struct ath_hal *ah = sc->sc_ah;
2434
2435         tsf = ath9k_hw_gettsf64(ah);
2436
2437         return tsf;
2438 }
2439
2440 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2441 {
2442         struct ath_softc *sc = hw->priv;
2443         struct ath_hal *ah = sc->sc_ah;
2444
2445         ath9k_hw_reset_tsf(ah);
2446 }
2447
2448 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2449                        enum ieee80211_ampdu_mlme_action action,
2450                        struct ieee80211_sta *sta,
2451                        u16 tid, u16 *ssn)
2452 {
2453         struct ath_softc *sc = hw->priv;
2454         int ret = 0;
2455
2456         switch (action) {
2457         case IEEE80211_AMPDU_RX_START:
2458                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2459                         ret = -ENOTSUPP;
2460                 break;
2461         case IEEE80211_AMPDU_RX_STOP:
2462                 break;
2463         case IEEE80211_AMPDU_TX_START:
2464                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2465                 if (ret < 0)
2466                         DPRINTF(sc, ATH_DBG_FATAL,
2467                                 "Unable to start TX aggregation\n");
2468                 else
2469                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2470                 break;
2471         case IEEE80211_AMPDU_TX_STOP:
2472                 ret = ath_tx_aggr_stop(sc, sta, tid);
2473                 if (ret < 0)
2474                         DPRINTF(sc, ATH_DBG_FATAL,
2475                                 "Unable to stop TX aggregation\n");
2476
2477                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2478                 break;
2479         case IEEE80211_AMPDU_TX_RESUME:
2480                 ath_tx_aggr_resume(sc, sta, tid);
2481                 break;
2482         default:
2483                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2484         }
2485
2486         return ret;
2487 }
2488
2489 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2490 {
2491         return -EOPNOTSUPP;
2492 }
2493
2494 static struct ieee80211_ops ath9k_ops = {
2495         .tx                 = ath9k_tx,
2496         .start              = ath9k_start,
2497         .stop               = ath9k_stop,
2498         .add_interface      = ath9k_add_interface,
2499         .remove_interface   = ath9k_remove_interface,
2500         .config             = ath9k_config,
2501         .config_interface   = ath9k_config_interface,
2502         .configure_filter   = ath9k_configure_filter,
2503         .sta_notify         = ath9k_sta_notify,
2504         .conf_tx            = ath9k_conf_tx,
2505         .bss_info_changed   = ath9k_bss_info_changed,
2506         .set_key            = ath9k_set_key,
2507         .get_tsf            = ath9k_get_tsf,
2508         .reset_tsf          = ath9k_reset_tsf,
2509         .ampdu_action       = ath9k_ampdu_action,
2510         .set_frag_threshold = ath9k_no_fragmentation,
2511 };
2512
2513 static struct {
2514         u32 version;
2515         const char * name;
2516 } ath_mac_bb_names[] = {
2517         { AR_SREV_VERSION_5416_PCI,     "5416" },
2518         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2519         { AR_SREV_VERSION_9100,         "9100" },
2520         { AR_SREV_VERSION_9160,         "9160" },
2521         { AR_SREV_VERSION_9280,         "9280" },
2522         { AR_SREV_VERSION_9285,         "9285" }
2523 };
2524
2525 static struct {
2526         u16 version;
2527         const char * name;
2528 } ath_rf_names[] = {
2529         { 0,                            "5133" },
2530         { AR_RAD5133_SREV_MAJOR,        "5133" },
2531         { AR_RAD5122_SREV_MAJOR,        "5122" },
2532         { AR_RAD2133_SREV_MAJOR,        "2133" },
2533         { AR_RAD2122_SREV_MAJOR,        "2122" }
2534 };
2535
2536 /*
2537  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2538  */
2539 static const char *
2540 ath_mac_bb_name(u32 mac_bb_version)
2541 {
2542         int i;
2543
2544         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2545                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2546                         return ath_mac_bb_names[i].name;
2547                 }
2548         }
2549
2550         return "????";
2551 }
2552
2553 /*
2554  * Return the RF name. "????" is returned if the RF is unknown.
2555  */
2556 static const char *
2557 ath_rf_name(u16 rf_version)
2558 {
2559         int i;
2560
2561         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2562                 if (ath_rf_names[i].version == rf_version) {
2563                         return ath_rf_names[i].name;
2564                 }
2565         }
2566
2567         return "????";
2568 }
2569
2570 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2571 {
2572         void __iomem *mem;
2573         struct ath_softc *sc;
2574         struct ieee80211_hw *hw;
2575         u8 csz;
2576         u32 val;
2577         int ret = 0;
2578         struct ath_hal *ah;
2579
2580         if (pci_enable_device(pdev))
2581                 return -EIO;
2582
2583         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2584
2585         if (ret) {
2586                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2587                 goto bad;
2588         }
2589
2590         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2591
2592         if (ret) {
2593                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2594                         "DMA enable failed\n");
2595                 goto bad;
2596         }
2597
2598         /*
2599          * Cache line size is used to size and align various
2600          * structures used to communicate with the hardware.
2601          */
2602         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2603         if (csz == 0) {
2604                 /*
2605                  * Linux 2.4.18 (at least) writes the cache line size
2606                  * register as a 16-bit wide register which is wrong.
2607                  * We must have this setup properly for rx buffer
2608                  * DMA to work so force a reasonable value here if it
2609                  * comes up zero.
2610                  */
2611                 csz = L1_CACHE_BYTES / sizeof(u32);
2612                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2613         }
2614         /*
2615          * The default setting of latency timer yields poor results,
2616          * set it to the value used by other systems. It may be worth
2617          * tweaking this setting more.
2618          */
2619         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2620
2621         pci_set_master(pdev);
2622
2623         /*
2624          * Disable the RETRY_TIMEOUT register (0x41) to keep
2625          * PCI Tx retries from interfering with C3 CPU state.
2626          */
2627         pci_read_config_dword(pdev, 0x40, &val);
2628         if ((val & 0x0000ff00) != 0)
2629                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2630
2631         ret = pci_request_region(pdev, 0, "ath9k");
2632         if (ret) {
2633                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2634                 ret = -ENODEV;
2635                 goto bad;
2636         }
2637
2638         mem = pci_iomap(pdev, 0, 0);
2639         if (!mem) {
2640                 printk(KERN_ERR "PCI memory map error\n") ;
2641                 ret = -EIO;
2642                 goto bad1;
2643         }
2644
2645         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2646         if (hw == NULL) {
2647                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2648                 goto bad2;
2649         }
2650
2651         SET_IEEE80211_DEV(hw, &pdev->dev);
2652         pci_set_drvdata(pdev, hw);
2653
2654         sc = hw->priv;
2655         sc->hw = hw;
2656         sc->pdev = pdev;
2657         sc->mem = mem;
2658
2659         if (ath_attach(id->device, sc) != 0) {
2660                 ret = -ENODEV;
2661                 goto bad3;
2662         }
2663
2664         /* setup interrupt service routine */
2665
2666         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2667                 printk(KERN_ERR "%s: request_irq failed\n",
2668                         wiphy_name(hw->wiphy));
2669                 ret = -EIO;
2670                 goto bad4;
2671         }
2672
2673         ah = sc->sc_ah;
2674         printk(KERN_INFO
2675                "%s: Atheros AR%s MAC/BB Rev:%x "
2676                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2677                wiphy_name(hw->wiphy),
2678                ath_mac_bb_name(ah->ah_macVersion),
2679                ah->ah_macRev,
2680                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2681                ah->ah_phyRev,
2682                (unsigned long)mem, pdev->irq);
2683
2684         return 0;
2685 bad4:
2686         ath_detach(sc);
2687 bad3:
2688         ieee80211_free_hw(hw);
2689 bad2:
2690         pci_iounmap(pdev, mem);
2691 bad1:
2692         pci_release_region(pdev, 0);
2693 bad:
2694         pci_disable_device(pdev);
2695         return ret;
2696 }
2697
2698 static void ath_pci_remove(struct pci_dev *pdev)
2699 {
2700         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2701         struct ath_softc *sc = hw->priv;
2702
2703         ath_detach(sc);
2704         if (pdev->irq)
2705                 free_irq(pdev->irq, sc);
2706         pci_iounmap(pdev, sc->mem);
2707         pci_release_region(pdev, 0);
2708         pci_disable_device(pdev);
2709         ieee80211_free_hw(hw);
2710 }
2711
2712 #ifdef CONFIG_PM
2713
2714 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2715 {
2716         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2717         struct ath_softc *sc = hw->priv;
2718
2719         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2720
2721 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2722         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2723                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2724 #endif
2725
2726         pci_save_state(pdev);
2727         pci_disable_device(pdev);
2728         pci_set_power_state(pdev, 3);
2729
2730         return 0;
2731 }
2732
2733 static int ath_pci_resume(struct pci_dev *pdev)
2734 {
2735         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2736         struct ath_softc *sc = hw->priv;
2737         u32 val;
2738         int err;
2739
2740         err = pci_enable_device(pdev);
2741         if (err)
2742                 return err;
2743         pci_restore_state(pdev);
2744         /*
2745          * Suspend/Resume resets the PCI configuration space, so we have to
2746          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2747          * PCI Tx retries from interfering with C3 CPU state
2748          */
2749         pci_read_config_dword(pdev, 0x40, &val);
2750         if ((val & 0x0000ff00) != 0)
2751                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2752
2753         /* Enable LED */
2754         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2755                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2756         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2757
2758 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2759         /*
2760          * check the h/w rfkill state on resume
2761          * and start the rfkill poll timer
2762          */
2763         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2764                 queue_delayed_work(sc->hw->workqueue,
2765                                    &sc->rf_kill.rfkill_poll, 0);
2766 #endif
2767
2768         return 0;
2769 }
2770
2771 #endif /* CONFIG_PM */
2772
2773 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2774
2775 static struct pci_driver ath_pci_driver = {
2776         .name       = "ath9k",
2777         .id_table   = ath_pci_id_table,
2778         .probe      = ath_pci_probe,
2779         .remove     = ath_pci_remove,
2780 #ifdef CONFIG_PM
2781         .suspend    = ath_pci_suspend,
2782         .resume     = ath_pci_resume,
2783 #endif /* CONFIG_PM */
2784 };
2785
2786 static int __init init_ath_pci(void)
2787 {
2788         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2789
2790         if (pci_register_driver(&ath_pci_driver) < 0) {
2791                 printk(KERN_ERR
2792                         "ath_pci: No devices found, driver not installed.\n");
2793                 pci_unregister_driver(&ath_pci_driver);
2794                 return -ENODEV;
2795         }
2796
2797         return 0;
2798 }
2799 module_init(init_ath_pci);
2800
2801 static void __exit exit_ath_pci(void)
2802 {
2803         pci_unregister_driver(&ath_pci_driver);
2804         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2805 }
2806 module_exit(exit_ath_pci);