drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
  27 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
  28 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
  29 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
  30                                            u8 numChains);
  31 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
  32 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
  33                                          u8 numChains);
  34
  35 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  36 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
  37
  38 static const struct hal_percal_data iq_cal_multi_sample = {
  39         IQ_MISMATCH_CAL,
  40         MAX_CAL_SAMPLES,
  41         PER_MIN_LOG_COUNT,
  42         ath9k_hw_iqcal_collect,
  43         ath9k_hw_iqcalibrate
  44 };
  45 static const struct hal_percal_data iq_cal_single_sample = {
  46         IQ_MISMATCH_CAL,
  47         MIN_CAL_SAMPLES,
  48         PER_MAX_LOG_COUNT,
  49         ath9k_hw_iqcal_collect,
  50         ath9k_hw_iqcalibrate
  51 };
  52 static const struct hal_percal_data adc_gain_cal_multi_sample = {
  53         ADC_GAIN_CAL,
  54         MAX_CAL_SAMPLES,
  55         PER_MIN_LOG_COUNT,
  56         ath9k_hw_adc_gaincal_collect,
  57         ath9k_hw_adc_gaincal_calibrate
  58 };
  59 static const struct hal_percal_data adc_gain_cal_single_sample = {
  60         ADC_GAIN_CAL,
  61         MIN_CAL_SAMPLES,
  62         PER_MAX_LOG_COUNT,
  63         ath9k_hw_adc_gaincal_collect,
  64         ath9k_hw_adc_gaincal_calibrate
  65 };
  66 static const struct hal_percal_data adc_dc_cal_multi_sample = {
  67         ADC_DC_CAL,
  68         MAX_CAL_SAMPLES,
  69         PER_MIN_LOG_COUNT,
  70         ath9k_hw_adc_dccal_collect,
  71         ath9k_hw_adc_dccal_calibrate
  72 };
  73 static const struct hal_percal_data adc_dc_cal_single_sample = {
  74         ADC_DC_CAL,
  75         MIN_CAL_SAMPLES,
  76         PER_MAX_LOG_COUNT,
  77         ath9k_hw_adc_dccal_collect,
  78         ath9k_hw_adc_dccal_calibrate
  79 };
  80 static const struct hal_percal_data adc_init_dc_cal = {
  81         ADC_DC_INIT_CAL,
  82         MIN_CAL_SAMPLES,
  83         INIT_LOG_COUNT,
  84         ath9k_hw_adc_dccal_collect,
  85         ath9k_hw_adc_dccal_calibrate
  86 };
  87
  88 static struct ath9k_rate_table ar5416_11a_table = {
  89         8,
  90         {0},
  91         {
  92                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
  93                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
  94                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
  95                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
  96                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
  97                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
  98                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
  99                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
 100         },
 101 };
 102
 103 static struct ath9k_rate_table ar5416_11b_table = {
 104         4,
 105         {0},
 106         {
 107                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 108                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 109                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
 110                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
 111         },
 112 };
 113
 114 static struct ath9k_rate_table ar5416_11g_table = {
 115         12,
 116         {0},
 117         {
 118                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 119                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 120                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 121                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 122
 123                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 124                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 125                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 126                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 127                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 128                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 129                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 130                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
 131         },
 132 };
 133
 134 static struct ath9k_rate_table ar5416_11ng_table = {
 135         28,
 136         {0},
 137         {
 138                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 139                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 140                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 141                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 142
 143                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 144                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 145                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 146                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 147                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 148                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 149                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 150                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
 151                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
 152                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
 153                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
 154                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
 155                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
 156                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
 157                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
 158                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
 159                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
 160                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
 161                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
 162                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
 163                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
 164                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
 165                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
 166                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
 167         },
 168 };
 169
 170 static struct ath9k_rate_table ar5416_11na_table = {
 171         24,
 172         {0},
 173         {
 174                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
 175                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
 176                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
 177                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
 178                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
 179                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
 180                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
 181                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
 182                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
 183                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
 184                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
 185                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
 186                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
 187                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
 188                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
 189                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
 190                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
 191                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
 192                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
 193                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
 194                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
 195                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
 196                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
 197                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
 198         },
 199 };
 200
 201 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
 202                                        const struct ath9k_channel *chan)
 203 {
 204         if (IS_CHAN_CCK(chan))
 205                 return ATH9K_MODE_11A;
 206         if (IS_CHAN_G(chan))
 207                 return ATH9K_MODE_11G;
 208         return ATH9K_MODE_11A;
 209 }
 210
 211 static bool ath9k_hw_wait(struct ath_hal *ah,
 212                           u32 reg,
 213                           u32 mask,
 214                           u32 val)
 215 {
 216         int i;
 217
 218         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 219                 if ((REG_READ(ah, reg) & mask) == val)
 220                         return true;
 221
 222                 udelay(AH_TIME_QUANTUM);
 223         }
 224         DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 225                  "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 226                  __func__, reg, REG_READ(ah, reg), mask, val);
 227         return false;
 228 }
 229
 230 static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
 231                                  u16 *data)
 232 {
 233         (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 234
 235         if (!ath9k_hw_wait(ah,
 236                            AR_EEPROM_STATUS_DATA,
 237                            AR_EEPROM_STATUS_DATA_BUSY |
 238                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
 239                 return false;
 240         }
 241
 242         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 243                    AR_EEPROM_STATUS_DATA_VAL);
 244
 245         return true;
 246 }
 247
 248 static int ath9k_hw_flash_map(struct ath_hal *ah)
 249 {
 250         struct ath_hal_5416 *ahp = AH5416(ah);
 251
 252         ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
 253
 254         if (!ahp->ah_cal_mem) {
 255                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 256                          "%s: cannot remap eeprom region \n", __func__);
 257                 return -EIO;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
 264                                 u16 *data)
 265 {
 266         struct ath_hal_5416 *ahp = AH5416(ah);
 267
 268         *data = ioread16(ahp->ah_cal_mem + off);
 269         return true;
 270 }
 271
 272 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 273 {
 274         u32 val;
 275
 276         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 277
 278         if (val == 0xFF) {
 279                 val = REG_READ(ah, AR_SREV);
 280
 281                 ah->ah_macVersion =
 282                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 283
 284                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 285                 ah->ah_isPciExpress =
 286                         (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 287
 288         } else {
 289                 if (!AR_SREV_9100(ah))
 290                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 291
 292                 ah->ah_macRev = val & AR_SREV_REVISION;
 293
 294                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 295                         ah->ah_isPciExpress = true;
 296         }
 297 }
 298
 299 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 300 {
 301         u32 retval;
 302         int i;
 303
 304         for (i = 0, retval = 0; i < n; i++) {
 305                 retval = (retval << 1) | (val & 1);
 306                 val >>= 1;
 307         }
 308         return retval;
 309 }
 310
 311 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 312 {
 313         int i;
 314
 315         ah->ah_config.dma_beacon_response_time = 2;
 316         ah->ah_config.sw_beacon_response_time = 10;
 317         ah->ah_config.additional_swba_backoff = 0;
 318         ah->ah_config.ack_6mb = 0x0;
 319         ah->ah_config.cwm_ignore_extcca = 0;
 320         ah->ah_config.pcie_powersave_enable = 0;
 321         ah->ah_config.pcie_l1skp_enable = 0;
 322         ah->ah_config.pcie_clock_req = 0;
 323         ah->ah_config.pcie_power_reset = 0x100;
 324         ah->ah_config.pcie_restore = 0;
 325         ah->ah_config.pcie_waen = 0;
 326         ah->ah_config.analog_shiftreg = 1;
 327         ah->ah_config.ht_enable = 1;
 328         ah->ah_config.ofdm_trig_low = 200;
 329         ah->ah_config.ofdm_trig_high = 500;
 330         ah->ah_config.cck_trig_high = 200;
 331         ah->ah_config.cck_trig_low = 100;
 332         ah->ah_config.enable_ani = 0;
 333         ah->ah_config.noise_immunity_level = 4;
 334         ah->ah_config.ofdm_weaksignal_det = 1;
 335         ah->ah_config.cck_weaksignal_thr = 0;
 336         ah->ah_config.spur_immunity_level = 2;
 337         ah->ah_config.firstep_level = 0;
 338         ah->ah_config.rssi_thr_high = 40;
 339         ah->ah_config.rssi_thr_low = 7;
 340         ah->ah_config.diversity_control = 0;
 341         ah->ah_config.antenna_switch_swap = 0;
 342
 343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 344                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 345                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 346         }
 347
 348         ah->ah_config.intr_mitigation = 0;
 349 }
 350
 351 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
 352                                          struct ath9k_channel *chan)
 353 {
 354         if (!AR_SREV_5416_V20_OR_LATER(ah)
 355             || AR_SREV_9280_10_OR_LATER(ah))
 356                 return;
 357
 358         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 359 }
 360
 361 static inline void ath9k_hw_init_bb(struct ath_hal *ah,
 362                                     struct ath9k_channel *chan)
 363 {
 364         u32 synthDelay;
 365
 366         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 367         if (IS_CHAN_CCK(chan))
 368                 synthDelay = (4 * synthDelay) / 22;
 369         else
 370                 synthDelay /= 10;
 371
 372         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 373
 374         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 375 }
 376
 377 static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
 378                                                  enum ath9k_opmode opmode)
 379 {
 380         struct ath_hal_5416 *ahp = AH5416(ah);
 381
 382         ahp->ah_maskReg = AR_IMR_TXERR |
 383                 AR_IMR_TXURN |
 384                 AR_IMR_RXERR |
 385                 AR_IMR_RXORN |
 386                 AR_IMR_BCNMISC;
 387
 388         if (ahp->ah_intrMitigation)
 389                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 390         else
 391                 ahp->ah_maskReg |= AR_IMR_RXOK;
 392
 393         ahp->ah_maskReg |= AR_IMR_TXOK;
 394
 395         if (opmode == ATH9K_M_HOSTAP)
 396                 ahp->ah_maskReg |= AR_IMR_MIB;
 397
 398         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
 399         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
 400
 401         if (!AR_SREV_9100(ah)) {
 402                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 403                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 404                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 405         }
 406 }
 407
 408 static inline void ath9k_hw_init_qos(struct ath_hal *ah)
 409 {
 410         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 411         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 412
 413         REG_WRITE(ah, AR_QOS_NO_ACK,
 414                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 415                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 416                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 417
 418         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 419         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 420         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 421         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 422         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 423 }
 424
 425 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
 426                                       u32 reg,
 427                                       u32 mask,
 428                                       u32 shift,
 429                                       u32 val)
 430 {
 431         u32 regVal;
 432
 433         regVal = REG_READ(ah, reg) & ~mask;
 434         regVal |= (val << shift) & mask;
 435
 436         REG_WRITE(ah, reg, regVal);
 437
 438         if (ah->ah_config.analog_shiftreg)
 439                 udelay(100);
 440
 441         return;
 442 }
 443
 444 static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
 445                                       enum ieee80211_band freq_band)
 446 {
 447         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 448         struct modal_eep_header *pModal =
 449                 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
 450         struct base_eep_header *pBase = &eep->baseEepHeader;
 451         u8 num_ant_config;
 452
 453         num_ant_config = 1;
 454
 455         if (pBase->version >= 0x0E0D)
 456                 if (pModal->useAnt1)
 457                         num_ant_config += 1;
 458
 459         return num_ant_config;
 460 }
 461
 462 static int
 463 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 464                                 struct ath9k_channel *chan,
 465                                 u8 index,
 466                                 u16 *config)
 467 {
 468         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 469         struct modal_eep_header *pModal =
 470                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 471         struct base_eep_header *pBase = &eep->baseEepHeader;
 472
 473         switch (index) {
 474         case 0:
 475                 *config = pModal->antCtrlCommon & 0xFFFF;
 476                 return 0;
 477         case 1:
 478                 if (pBase->version >= 0x0E0D) {
 479                         if (pModal->useAnt1) {
 480                                 *config =
 481                                 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
 482                                 return 0;
 483                         }
 484                 }
 485                 break;
 486         default:
 487                 break;
 488         }
 489
 490         return -EINVAL;
 491 }
 492
 493 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
 494                                        u32 off,
 495                                        u16 *data)
 496 {
 497         if (ath9k_hw_use_flash(ah))
 498                 return ath9k_hw_flash_read(ah, off, data);
 499         else
 500                 return ath9k_hw_eeprom_read(ah, off, data);
 501 }
 502
 503 static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 504 {
 505         struct ath_hal_5416 *ahp = AH5416(ah);
 506         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 507         u16 *eep_data;
 508         int addr, ar5416_eep_start_loc = 0;
 509
 510         if (!ath9k_hw_use_flash(ah)) {
 511                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 512                          "%s: Reading from EEPROM, not flash\n", __func__);
 513                 ar5416_eep_start_loc = 256;
 514         }
 515         if (AR_SREV_9100(ah))
 516                 ar5416_eep_start_loc = 256;
 517
 518         eep_data = (u16 *) eep;
 519         for (addr = 0;
 520              addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
 521              addr++) {
 522                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 523                                          eep_data)) {
 524                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 525                                  "%s: Unable to read eeprom region \n",
 526                                  __func__);
 527                         return false;
 528                 }
 529                 eep_data++;
 530         }
 531         return true;
 532 }
 533
 534 /* XXX: Clean me up, make me more legible */
 535 static bool
 536 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 537                                  struct ath9k_channel *chan)
 538 {
 539         struct modal_eep_header *pModal;
 540         int i, regChainOffset;
 541         struct ath_hal_5416 *ahp = AH5416(ah);
 542         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 543         u8 txRxAttenLocal;
 544         u16 ant_config;
 545
 546         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 547
 548         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 549
 550         ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
 551         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
 552
 553         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 554                 if (AR_SREV_9280(ah)) {
 555                         if (i >= 2)
 556                                 break;
 557                 }
 558
 559                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
 560                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
 561                     && (i != 0))
 562                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 563                 else
 564                         regChainOffset = i * 0x1000;
 565
 566                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 567                           pModal->antCtrlChain[i]);
 568
 569                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 570                           (REG_READ(ah,
 571                                     AR_PHY_TIMING_CTRL4(0) +
 572                                     regChainOffset) &
 573                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 574                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 575                           SM(pModal->iqCalICh[i],
 576                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 577                           SM(pModal->iqCalQCh[i],
 578                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 579
 580                 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
 581                         if ((eep->baseEepHeader.version &
 582                              AR5416_EEP_VER_MINOR_MASK) >=
 583                             AR5416_EEP_MINOR_VER_3) {
 584                                 txRxAttenLocal = pModal->txRxAttenCh[i];
 585                                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 586                                         REG_RMW_FIELD(ah,
 587                                                 AR_PHY_GAIN_2GHZ +
 588                                                 regChainOffset,
 589                                                 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 590                                                 pModal->
 591                                                 bswMargin[i]);
 592                                         REG_RMW_FIELD(ah,
 593                                                 AR_PHY_GAIN_2GHZ +
 594                                                 regChainOffset,
 595                                                 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 596                                                 pModal->
 597                                                 bswAtten[i]);
 598                                         REG_RMW_FIELD(ah,
 599                                                 AR_PHY_GAIN_2GHZ +
 600                                                 regChainOffset,
 601                                                 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 602                                                 pModal->
 603                                                 xatten2Margin[i]);
 604                                         REG_RMW_FIELD(ah,
 605                                                 AR_PHY_GAIN_2GHZ +
 606                                                 regChainOffset,
 607                                                 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 608                                                 pModal->
 609                                                 xatten2Db[i]);
 610                                 } else {
 611                                         REG_WRITE(ah,
 612                                                   AR_PHY_GAIN_2GHZ +
 613                                                   regChainOffset,
 614                                                   (REG_READ(ah,
 615                                                             AR_PHY_GAIN_2GHZ +
 616                                                             regChainOffset) &
 617                                                    ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 618                                                   | SM(pModal->
 619                                                   bswMargin[i],
 620                                                   AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 621                                         REG_WRITE(ah,
 622                                                   AR_PHY_GAIN_2GHZ +
 623                                                   regChainOffset,
 624                                                   (REG_READ(ah,
 625                                                             AR_PHY_GAIN_2GHZ +
 626                                                             regChainOffset) &
 627                                                    ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 628                                                   | SM(pModal->bswAtten[i],
 629                                                   AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 630                                 }
 631                         }
 632                         if (AR_SREV_9280_10_OR_LATER(ah)) {
 633                                 REG_RMW_FIELD(ah,
 634                                               AR_PHY_RXGAIN +
 635                                               regChainOffset,
 636                                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
 637                                               txRxAttenLocal);
 638                                 REG_RMW_FIELD(ah,
 639                                               AR_PHY_RXGAIN +
 640                                               regChainOffset,
 641                                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
 642                                               pModal->rxTxMarginCh[i]);
 643                         } else {
 644                                 REG_WRITE(ah,
 645                                           AR_PHY_RXGAIN + regChainOffset,
 646                                           (REG_READ(ah,
 647                                                     AR_PHY_RXGAIN +
 648                                                     regChainOffset) &
 649                                            ~AR_PHY_RXGAIN_TXRX_ATTEN) |
 650                                           SM(txRxAttenLocal,
 651                                              AR_PHY_RXGAIN_TXRX_ATTEN));
 652                                 REG_WRITE(ah,
 653                                           AR_PHY_GAIN_2GHZ +
 654                                           regChainOffset,
 655                                           (REG_READ(ah,
 656                                                     AR_PHY_GAIN_2GHZ +
 657                                                     regChainOffset) &
 658                                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 659                                           SM(pModal->rxTxMarginCh[i],
 660                                              AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 661                         }
 662                 }
 663         }
 664
 665         if (AR_SREV_9280_10_OR_LATER(ah)) {
 666                 if (IS_CHAN_2GHZ(chan)) {
 667                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 668                                                   AR_AN_RF2G1_CH0_OB,
 669                                                   AR_AN_RF2G1_CH0_OB_S,
 670                                                   pModal->ob);
 671                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 672                                                   AR_AN_RF2G1_CH0_DB,
 673                                                   AR_AN_RF2G1_CH0_DB_S,
 674                                                   pModal->db);
 675                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 676                                                   AR_AN_RF2G1_CH1_OB,
 677                                                   AR_AN_RF2G1_CH1_OB_S,
 678                                                   pModal->ob_ch1);
 679                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 680                                                   AR_AN_RF2G1_CH1_DB,
 681                                                   AR_AN_RF2G1_CH1_DB_S,
 682                                                   pModal->db_ch1);
 683                 } else {
 684                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 685                                                   AR_AN_RF5G1_CH0_OB5,
 686                                                   AR_AN_RF5G1_CH0_OB5_S,
 687                                                   pModal->ob);
 688                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 689                                                   AR_AN_RF5G1_CH0_DB5,
 690                                                   AR_AN_RF5G1_CH0_DB5_S,
 691                                                   pModal->db);
 692                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 693                                                   AR_AN_RF5G1_CH1_OB5,
 694                                                   AR_AN_RF5G1_CH1_OB5_S,
 695                                                   pModal->ob_ch1);
 696                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 697                                                   AR_AN_RF5G1_CH1_DB5,
 698                                                   AR_AN_RF5G1_CH1_DB5_S,
 699                                                   pModal->db_ch1);
 700                 }
 701                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 702                                           AR_AN_TOP2_XPABIAS_LVL,
 703                                           AR_AN_TOP2_XPABIAS_LVL_S,
 704                                           pModal->xpaBiasLvl);
 705                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 706                                           AR_AN_TOP2_LOCALBIAS,
 707                                           AR_AN_TOP2_LOCALBIAS_S,
 708                                           pModal->local_bias);
 709                 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
 710                         pModal->force_xpaon);
 711                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 712                               pModal->force_xpaon);
 713         }
 714
 715         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 716                       pModal->switchSettling);
 717         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 718                       pModal->adcDesiredSize);
 719
 720         if (!AR_SREV_9280_10_OR_LATER(ah))
 721                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 722                               AR_PHY_DESIRED_SZ_PGA,
 723                               pModal->pgaDesiredSize);
 724
 725         REG_WRITE(ah, AR_PHY_RF_CTL4,
 726                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 727                   | SM(pModal->txEndToXpaOff,
 728                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 729                   | SM(pModal->txFrameToXpaOn,
 730                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 731                   | SM(pModal->txFrameToXpaOn,
 732                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 733
 734         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 735                       pModal->txEndToRxOn);
 736         if (AR_SREV_9280_10_OR_LATER(ah)) {
 737                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 738                               pModal->thresh62);
 739                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 740                               AR_PHY_EXT_CCA0_THRESH62,
 741                               pModal->thresh62);
 742         } else {
 743                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 744                               pModal->thresh62);
 745                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 746                               AR_PHY_EXT_CCA_THRESH62,
 747                               pModal->thresh62);
 748         }
 749
 750         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 751             AR5416_EEP_MINOR_VER_2) {
 752                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 753                               AR_PHY_TX_END_DATA_START,
 754                               pModal->txFrameToDataStart);
 755                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 756                               pModal->txFrameToPaOn);
 757         }
 758
 759         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 760             AR5416_EEP_MINOR_VER_3) {
 761                 if (IS_CHAN_HT40(chan))
 762                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 763                                       AR_PHY_SETTLING_SWITCH,
 764                                       pModal->swSettleHt40);
 765         }
 766
 767         return true;
 768 }
 769
 770 static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)
 771 {
 772         u32 sum = 0, el;
 773         u16 *eepdata;
 774         int i;
 775         struct ath_hal_5416 *ahp = AH5416(ah);
 776         bool need_swap = false;
 777         struct ar5416_eeprom *eep =
 778                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
 779
 780         if (!ath9k_hw_use_flash(ah)) {
 781                 u16 magic, magic2;
 782                 int addr;
 783
 784                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 785                                         &magic)) {
 786                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 787                                  "%s: Reading Magic # failed\n", __func__);
 788                         return false;
 789                 }
 790                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
 791                          __func__, magic);
 792
 793                 if (magic != AR5416_EEPROM_MAGIC) {
 794                         magic2 = swab16(magic);
 795
 796                         if (magic2 == AR5416_EEPROM_MAGIC) {
 797                                 need_swap = true;
 798                                 eepdata = (u16 *) (&ahp->ah_eeprom);
 799
 800                                 for (addr = 0;
 801                                      addr <
 802                                              sizeof(struct ar5416_eeprom) /
 803                                              sizeof(u16); addr++) {
 804                                         u16 temp;
 805
 806                                         temp = swab16(*eepdata);
 807                                         *eepdata = temp;
 808                                         eepdata++;
 809
 810                                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 811                                                  "0x%04X  ", *eepdata);
 812                                         if (((addr + 1) % 6) == 0)
 813                                                 DPRINTF(ah->ah_sc,
 814                                                          ATH_DBG_EEPROM,
 815                                                          "\n");
 816                                 }
 817                         } else {
 818                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 819                                          "Invalid EEPROM Magic. "
 820                                         "endianness missmatch.\n");
 821                                 return -EINVAL;
 822                         }
 823                 }
 824         }
 825         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 826                  need_swap ? "True" : "False");
 827
 828         if (need_swap)
 829                 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
 830         else
 831                 el = ahp->ah_eeprom.baseEepHeader.length;
 832
 833         if (el > sizeof(struct ar5416_eeprom))
 834                 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
 835         else
 836                 el = el / sizeof(u16);
 837
 838         eepdata = (u16 *) (&ahp->ah_eeprom);
 839
 840         for (i = 0; i < el; i++)
 841                 sum ^= *eepdata++;
 842
 843         if (need_swap) {
 844                 u32 integer, j;
 845                 u16 word;
 846
 847                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 848                          "EEPROM Endianness is not native.. Changing \n");
 849
 850                 word = swab16(eep->baseEepHeader.length);
 851                 eep->baseEepHeader.length = word;
 852
 853                 word = swab16(eep->baseEepHeader.checksum);
 854                 eep->baseEepHeader.checksum = word;
 855
 856                 word = swab16(eep->baseEepHeader.version);
 857                 eep->baseEepHeader.version = word;
 858
 859                 word = swab16(eep->baseEepHeader.regDmn[0]);
 860                 eep->baseEepHeader.regDmn[0] = word;
 861
 862                 word = swab16(eep->baseEepHeader.regDmn[1]);
 863                 eep->baseEepHeader.regDmn[1] = word;
 864
 865                 word = swab16(eep->baseEepHeader.rfSilent);
 866                 eep->baseEepHeader.rfSilent = word;
 867
 868                 word = swab16(eep->baseEepHeader.blueToothOptions);
 869                 eep->baseEepHeader.blueToothOptions = word;
 870
 871                 word = swab16(eep->baseEepHeader.deviceCap);
 872                 eep->baseEepHeader.deviceCap = word;
 873
 874                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 875                         struct modal_eep_header *pModal =
 876                                 &eep->modalHeader[j];
 877                         integer = swab32(pModal->antCtrlCommon);
 878                         pModal->antCtrlCommon = integer;
 879
 880                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 881                                 integer = swab32(pModal->antCtrlChain[i]);
 882                                 pModal->antCtrlChain[i] = integer;
 883                         }
 884
 885                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 886                                 word = swab16(pModal->spurChans[i].spurChan);
 887                                 pModal->spurChans[i].spurChan = word;
 888                         }
 889                 }
 890         }
 891
 892         if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
 893             ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
 894                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 895                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 896                          sum, ar5416_get_eep_ver(ahp));
 897                 return -EINVAL;
 898         }
 899
 900         return 0;
 901 }
 902
 903 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 904 {
 905         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 906         u32 regHold[2];
 907         u32 patternData[4] = { 0x55555555,
 908                                      0xaaaaaaaa,
 909                                      0x66666666,
 910                                      0x99999999 };
 911         int i, j;
 912
 913         for (i = 0; i < 2; i++) {
 914                 u32 addr = regAddr[i];
 915                 u32 wrData, rdData;
 916
 917                 regHold[i] = REG_READ(ah, addr);
 918                 for (j = 0; j < 0x100; j++) {
 919                         wrData = (j << 16) | j;
 920                         REG_WRITE(ah, addr, wrData);
 921                         rdData = REG_READ(ah, addr);
 922                         if (rdData != wrData) {
 923                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 924                                  "%s: address test failed "
 925                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 926                                  __func__, addr, wrData, rdData);
 927                                 return false;
 928                         }
 929                 }
 930                 for (j = 0; j < 4; j++) {
 931                         wrData = patternData[j];
 932                         REG_WRITE(ah, addr, wrData);
 933                         rdData = REG_READ(ah, addr);
 934                         if (wrData != rdData) {
 935                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 936                                  "%s: address test failed "
 937                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 938                                  __func__, addr, wrData, rdData);
 939                                 return false;
 940                         }
 941                 }
 942                 REG_WRITE(ah, regAddr[i], regHold[i]);
 943         }
 944         udelay(100);
 945         return true;
 946 }
 947
 948 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
 949 {
 950         u32 bits = REG_READ(ah, AR_RX_FILTER);
 951         u32 phybits = REG_READ(ah, AR_PHY_ERR);
 952
 953         if (phybits & AR_PHY_ERR_RADAR)
 954                 bits |= ATH9K_RX_FILTER_PHYRADAR;
 955         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
 956                 bits |= ATH9K_RX_FILTER_PHYERR;
 957         return bits;
 958 }
 959
 960 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
 961 {
 962         u32 phybits;
 963
 964         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
 965         phybits = 0;
 966         if (bits & ATH9K_RX_FILTER_PHYRADAR)
 967                 phybits |= AR_PHY_ERR_RADAR;
 968         if (bits & ATH9K_RX_FILTER_PHYERR)
 969                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
 970         REG_WRITE(ah, AR_PHY_ERR, phybits);
 971
 972         if (phybits)
 973                 REG_WRITE(ah, AR_RXCFG,
 974                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
 975         else
 976                 REG_WRITE(ah, AR_RXCFG,
 977                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 978 }
 979
 980 bool ath9k_hw_setcapability(struct ath_hal *ah,
 981                             enum ath9k_capability_type type,
 982                             u32 capability,
 983                             u32 setting,
 984                             int *status)
 985 {
 986         struct ath_hal_5416 *ahp = AH5416(ah);
 987         u32 v;
 988
 989         switch (type) {
 990         case ATH9K_CAP_TKIP_MIC:
 991                 if (setting)
 992                         ahp->ah_staId1Defaults |=
 993                                 AR_STA_ID1_CRPT_MIC_ENABLE;
 994                 else
 995                         ahp->ah_staId1Defaults &=
 996                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
 997                 return true;
 998         case ATH9K_CAP_DIVERSITY:
 999                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000                 if (setting)
1001                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002                 else
1003                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005                 return true;
1006         case ATH9K_CAP_MCAST_KEYSRCH:
1007                 if (setting)
1008                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009                 else
1010                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011                 return true;
1012         case ATH9K_CAP_TSF_ADJUST:
1013                 if (setting)
1014                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015                 else
1016                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017                 return true;
1018         default:
1019                 return false;
1020         }
1021 }
1022
1023 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024 {
1025         u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
1026         int qcuOffset = 0, dcuOffset = 0;
1027         u32 *qcuBase = &val[0], *dcuBase = &val[4];
1028         int i;
1029
1030         REG_WRITE(ah, AR_MACMISC,
1031                   ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1032                    (AR_MACMISC_MISC_OBS_BUS_1 <<
1033                     AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1034
1035         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
1036         for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1037                 if (i % 4 == 0)
1038                         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040                 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042         }
1043
1044         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046                  "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048         for (i = 0; i < ATH9K_NUM_QUEUES;
1049              i++, qcuOffset += 4, dcuOffset += 5) {
1050                 if (i == 8) {
1051                         qcuOffset = 0;
1052                         qcuBase++;
1053                 }
1054
1055                 if (i == 6) {
1056                         dcuOffset = 0;
1057                         dcuBase++;
1058                 }
1059
1060                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061                          "%2d          %2x      %1x     %2x           %2x\n",
1062                          i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063                          (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064                                                              3),
1065                          val[2] & (0x7 << (i * 3)) >> (i * 3),
1066                          (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067         }
1068
1069         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1070         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071                  "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
1072                  (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074                  "qcu_complete state: %2x    dcu_complete state:     %2x\n",
1075                  (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077                  "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
1078                  (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080                  "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
1081                  (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083                  "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
1084                  (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086                  "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
1087                  (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090                 REG_READ(ah, AR_OBS_BUS_1));
1091         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092                 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093 }
1094
1095 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1096                                         u32 *rxc_pcnt,
1097                                         u32 *rxf_pcnt,
1098                                         u32 *txf_pcnt)
1099 {
1100         static u32 cycles, rx_clear, rx_frame, tx_frame;
1101         u32 good = 1;
1102
1103         u32 rc = REG_READ(ah, AR_RCCNT);
1104         u32 rf = REG_READ(ah, AR_RFCNT);
1105         u32 tf = REG_READ(ah, AR_TFCNT);
1106         u32 cc = REG_READ(ah, AR_CCCNT);
1107
1108         if (cycles == 0 || cycles > cc) {
1109                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1110                          "%s: cycle counter wrap. ExtBusy = 0\n",
1111                          __func__);
1112                 good = 0;
1113         } else {
1114                 u32 cc_d = cc - cycles;
1115                 u32 rc_d = rc - rx_clear;
1116                 u32 rf_d = rf - rx_frame;
1117                 u32 tf_d = tf - tx_frame;
1118
1119                 if (cc_d != 0) {
1120                         *rxc_pcnt = rc_d * 100 / cc_d;
1121                         *rxf_pcnt = rf_d * 100 / cc_d;
1122                         *txf_pcnt = tf_d * 100 / cc_d;
1123                 } else {
1124                         good = 0;
1125                 }
1126         }
1127
1128         cycles = cc;
1129         rx_frame = rf;
1130         rx_clear = rc;
1131         tx_frame = tf;
1132
1133         return good;
1134 }
1135
1136 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137 {
1138         u32 macmode;
1139
1140         if (mode == ATH9K_HT_MACMODE_2040 &&
1141             !ah->ah_config.cwm_ignore_extcca)
1142                 macmode = AR_2040_JOINED_RX_CLEAR;
1143         else
1144                 macmode = 0;
1145
1146         REG_WRITE(ah, AR_2040_MODE, macmode);
1147 }
1148
1149 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150 {
1151         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152 }
1153
1154
1155 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156                                               struct ath_softc *sc,
1157                                               void __iomem *mem,
1158                                               int *status)
1159 {
1160         static const u8 defbssidmask[ETH_ALEN] =
1161                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1162         struct ath_hal_5416 *ahp;
1163         struct ath_hal *ah;
1164
1165         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166         if (ahp == NULL) {
1167                 DPRINTF(sc, ATH_DBG_FATAL,
1168                          "%s: cannot allocate memory for state block\n",
1169                          __func__);
1170                 *status = -ENOMEM;
1171                 return NULL;
1172         }
1173
1174         ah = &ahp->ah;
1175
1176         ah->ah_sc = sc;
1177         ah->ah_sh = mem;
1178
1179         ah->ah_magic = AR5416_MAGIC;
1180         ah->ah_countryCode = CTRY_DEFAULT;
1181
1182         ah->ah_devid = devid;
1183         ah->ah_subvendorid = 0;
1184
1185         ah->ah_flags = 0;
1186         if ((devid == AR5416_AR9100_DEVID))
1187                 ah->ah_macVersion = AR_SREV_VERSION_9100;
1188         if (!AR_SREV_9100(ah))
1189                 ah->ah_flags = AH_USE_EEPROM;
1190
1191         ah->ah_powerLimit = MAX_RATE_POWER;
1192         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194         ahp->ah_atimWindow = 0;
1195         ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196         ahp->ah_antennaSwitchSwap =
1197                 ah->ah_config.antenna_switch_swap;
1198
1199         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200         ahp->ah_beaconInterval = 100;
1201         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1202         ahp->ah_slottime = (u32) -1;
1203         ahp->ah_acktimeout = (u32) -1;
1204         ahp->ah_ctstimeout = (u32) -1;
1205         ahp->ah_globaltxtimeout = (u32) -1;
1206         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1207
1208         ahp->ah_gBeaconRate = 0;
1209
1210         return ahp;
1211 }
1212
1213 static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214 {
1215         int status;
1216
1217         if (ath9k_hw_use_flash(ah))
1218                 ath9k_hw_flash_map(ah);
1219
1220         if (!ath9k_hw_fill_eeprom(ah))
1221                 return -EIO;
1222
1223         status = ath9k_hw_check_eeprom(ah);
1224
1225         return status;
1226 }
1227
1228 u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229                               enum eeprom_param param)
1230 {
1231         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232         struct modal_eep_header *pModal = eep->modalHeader;
1233         struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235         switch (param) {
1236         case EEP_NFTHRESH_5:
1237                 return -pModal[0].noiseFloorThreshCh[0];
1238         case EEP_NFTHRESH_2:
1239                 return -pModal[1].noiseFloorThreshCh[0];
1240         case AR_EEPROM_MAC(0):
1241                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242         case AR_EEPROM_MAC(1):
1243                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244         case AR_EEPROM_MAC(2):
1245                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246         case EEP_REG_0:
1247                 return pBase->regDmn[0];
1248         case EEP_REG_1:
1249                 return pBase->regDmn[1];
1250         case EEP_OP_CAP:
1251                 return pBase->deviceCap;
1252         case EEP_OP_MODE:
1253                 return pBase->opCapFlags;
1254         case EEP_RF_SILENT:
1255                 return pBase->rfSilent;
1256         case EEP_OB_5:
1257                 return pModal[0].ob;
1258         case EEP_DB_5:
1259                 return pModal[0].db;
1260         case EEP_OB_2:
1261                 return pModal[1].ob;
1262         case EEP_DB_2:
1263                 return pModal[1].db;
1264         case EEP_MINOR_REV:
1265                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266         case EEP_TX_MASK:
1267                 return pBase->txMask;
1268         case EEP_RX_MASK:
1269                 return pBase->rxMask;
1270         default:
1271                 return 0;
1272         }
1273 }
1274
1275 static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276 {
1277         u32 val;
1278         int i;
1279
1280         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281         for (i = 0; i < 8; i++)
1282                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285         return ath9k_hw_reverse_bits(val, 8);
1286 }
1287
1288 static inline int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289 {
1290         u32 sum;
1291         int i;
1292         u16 eeval;
1293         struct ath_hal_5416 *ahp = AH5416(ah);
1294         DECLARE_MAC_BUF(mac);
1295
1296         sum = 0;
1297         for (i = 0; i < 3; i++) {
1298                 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1299                 sum += eeval;
1300                 ahp->ah_macaddr[2 * i] = eeval >> 8;
1301                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1302         }
1303         if (sum == 0 || sum == 0xffff * 3) {
1304                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1305                          "%s: mac address read failed: %s\n", __func__,
1306                          print_mac(mac, ahp->ah_macaddr));
1307                 return -EADDRNOTAVAIL;
1308         }
1309
1310         return 0;
1311 }
1312
1313 static inline int16_t ath9k_hw_interpolate(u16 target,
1314                                            u16 srcLeft,
1315                                            u16 srcRight,
1316                                            int16_t targetLeft,
1317                                            int16_t targetRight)
1318 {
1319         int16_t rv;
1320
1321         if (srcRight == srcLeft) {
1322                 rv = targetLeft;
1323         } else {
1324                 rv = (int16_t) (((target - srcLeft) * targetRight +
1325                                  (srcRight - target) * targetLeft) /
1326                                 (srcRight - srcLeft));
1327         }
1328         return rv;
1329 }
1330
1331 static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1332                                            bool is2GHz)
1333 {
1334
1335         if (fbin == AR5416_BCHAN_UNUSED)
1336                 return fbin;
1337
1338         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1339 }
1340
1341 static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1342                                                u16 i,
1343                                                bool is2GHz)
1344 {
1345         struct ath_hal_5416 *ahp = AH5416(ah);
1346         struct ar5416_eeprom *eep =
1347                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1348         u16 spur_val = AR_NO_SPUR;
1349
1350         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1351                  "Getting spur idx %d is2Ghz. %d val %x\n",
1352                  i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1353
1354         switch (ah->ah_config.spurmode) {
1355         case SPUR_DISABLE:
1356                 break;
1357         case SPUR_ENABLE_IOCTL:
1358                 spur_val = ah->ah_config.spurchans[i][is2GHz];
1359                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360                          "Getting spur val from new loc. %d\n", spur_val);
1361                 break;
1362         case SPUR_ENABLE_EEPROM:
1363                 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1364                 break;
1365
1366         }
1367         return spur_val;
1368 }
1369
1370 static inline int ath9k_hw_rfattach(struct ath_hal *ah)
1371 {
1372         bool rfStatus = false;
1373         int ecode = 0;
1374
1375         rfStatus = ath9k_hw_init_rf(ah, &ecode);
1376         if (!rfStatus) {
1377                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1378                          "%s: RF setup failed, status %u\n", __func__,
1379                          ecode);
1380                 return ecode;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int ath9k_hw_rf_claim(struct ath_hal *ah)
1387 {
1388         u32 val;
1389
1390         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1391
1392         val = ath9k_hw_get_radiorev(ah);
1393         switch (val & AR_RADIO_SREV_MAJOR) {
1394         case 0:
1395                 val = AR_RAD5133_SREV_MAJOR;
1396                 break;
1397         case AR_RAD5133_SREV_MAJOR:
1398         case AR_RAD5122_SREV_MAJOR:
1399         case AR_RAD2133_SREV_MAJOR:
1400         case AR_RAD2122_SREV_MAJOR:
1401                 break;
1402         default:
1403                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1404                          "%s: 5G Radio Chip Rev 0x%02X is not "
1405                         "supported by this driver\n",
1406                          __func__, ah->ah_analog5GhzRev);
1407                 return -EOPNOTSUPP;
1408         }
1409
1410         ah->ah_analog5GhzRev = val;
1411
1412         return 0;
1413 }
1414
1415 static inline void ath9k_hw_init_pll(struct ath_hal *ah,
1416                                      struct ath9k_channel *chan)
1417 {
1418         u32 pll;
1419
1420         if (AR_SREV_9100(ah)) {
1421                 if (chan && IS_CHAN_5GHZ(chan))
1422                         pll = 0x1450;
1423                 else
1424                         pll = 0x1458;
1425         } else {
1426                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1427                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1428
1429                         if (chan && IS_CHAN_HALF_RATE(chan))
1430                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1431                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1432                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1433
1434                         if (chan && IS_CHAN_5GHZ(chan)) {
1435                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1436
1437
1438                                 if (AR_SREV_9280_20(ah)) {
1439                                         if (((chan->channel % 20) == 0)
1440                                             || ((chan->channel % 10) == 0))
1441                                                 pll = 0x2850;
1442                                         else
1443                                                 pll = 0x142c;
1444                                 }
1445                         } else {
1446                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1447                         }
1448
1449                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1450
1451                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1452
1453                         if (chan && IS_CHAN_HALF_RATE(chan))
1454                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1455                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1456                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1457
1458                         if (chan && IS_CHAN_5GHZ(chan))
1459                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1460                         else
1461                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1462                 } else {
1463                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1464
1465                         if (chan && IS_CHAN_HALF_RATE(chan))
1466                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1467                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1468                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1469
1470                         if (chan && IS_CHAN_5GHZ(chan))
1471                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1472                         else
1473                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1474                 }
1475         }
1476         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1477
1478         udelay(RTC_PLL_SETTLE_DELAY);
1479
1480         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1481 }
1482
1483 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1484                               enum ath9k_ht_macmode macmode)
1485 {
1486         u32 phymode;
1487         struct ath_hal_5416 *ahp = AH5416(ah);
1488
1489         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1490                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1491
1492         if (IS_CHAN_HT40(chan)) {
1493                 phymode |= AR_PHY_FC_DYN2040_EN;
1494
1495                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1496                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1497                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1498
1499                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1500                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1501         }
1502         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1503
1504         ath9k_hw_set11nmac2040(ah, macmode);
1505
1506         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1507         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1508 }
1509
1510 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1511 {
1512         u32 val;
1513
1514         val = REG_READ(ah, AR_STA_ID1);
1515         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1516         switch (opmode) {
1517         case ATH9K_M_HOSTAP:
1518                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1519                           | AR_STA_ID1_KSRCH_MODE);
1520                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1521                 break;
1522         case ATH9K_M_IBSS:
1523                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1524                           | AR_STA_ID1_KSRCH_MODE);
1525                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1526                 break;
1527         case ATH9K_M_STA:
1528         case ATH9K_M_MONITOR:
1529                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1530                 break;
1531         }
1532 }
1533
1534 static inline void
1535 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1536 {
1537         u32 rfMode = 0;
1538
1539         if (chan == NULL)
1540                 return;
1541
1542         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1543                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1544
1545         if (!AR_SREV_9280_10_OR_LATER(ah))
1546                 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1547                         AR_PHY_MODE_RF2GHZ;
1548
1549         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1550                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1551
1552         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1553 }
1554
1555 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1556 {
1557         u32 rst_flags;
1558         u32 tmpReg;
1559
1560         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1561                   AR_RTC_FORCE_WAKE_ON_INT);
1562
1563         if (AR_SREV_9100(ah)) {
1564                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1565                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1566         } else {
1567                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1568                 if (tmpReg &
1569                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1570                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1571                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1572                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1573                 } else {
1574                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1575                 }
1576
1577                 rst_flags = AR_RTC_RC_MAC_WARM;
1578                 if (type == ATH9K_RESET_COLD)
1579                         rst_flags |= AR_RTC_RC_MAC_COLD;
1580         }
1581
1582         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1583         udelay(50);
1584
1585         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1586         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1587                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1588                         "%s: RTC stuck in MAC reset\n",
1589                         __func__);
1590                 return false;
1591         }
1592
1593         if (!AR_SREV_9100(ah))
1594                 REG_WRITE(ah, AR_RC, 0);
1595
1596         ath9k_hw_init_pll(ah, NULL);
1597
1598         if (AR_SREV_9100(ah))
1599                 udelay(50);
1600
1601         return true;
1602 }
1603
1604 static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1605 {
1606         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1607                   AR_RTC_FORCE_WAKE_ON_INT);
1608
1609         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1610         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1611
1612         if (!ath9k_hw_wait(ah,
1613                            AR_RTC_STATUS,
1614                            AR_RTC_STATUS_M,
1615                            AR_RTC_STATUS_ON)) {
1616                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1617                          __func__);
1618                 return false;
1619         }
1620
1621         ath9k_hw_read_revisions(ah);
1622
1623         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1624 }
1625
1626 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1627                                    u32 type)
1628 {
1629         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1630                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1631
1632         switch (type) {
1633         case ATH9K_RESET_POWER_ON:
1634                 return ath9k_hw_set_reset_power_on(ah);
1635                 break;
1636         case ATH9K_RESET_WARM:
1637         case ATH9K_RESET_COLD:
1638                 return ath9k_hw_set_reset(ah, type);
1639                 break;
1640         default:
1641                 return false;
1642         }
1643 }
1644
1645 static inline
1646 struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1647                                           struct ath9k_channel *chan)
1648 {
1649         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1650                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1651                          "%s: invalid channel %u/0x%x; not marked as "
1652                          "2GHz or 5GHz\n", __func__, chan->channel,
1653                          chan->channelFlags);
1654                 return NULL;
1655         }
1656
1657         if (!IS_CHAN_OFDM(chan) &&
1658               !IS_CHAN_CCK(chan) &&
1659               !IS_CHAN_HT20(chan) &&
1660               !IS_CHAN_HT40(chan)) {
1661                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1662                         "%s: invalid channel %u/0x%x; not marked as "
1663                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1664                         __func__, chan->channel, chan->channelFlags);
1665                 return NULL;
1666         }
1667
1668         return ath9k_regd_check_channel(ah, chan);
1669 }
1670
1671 static inline bool
1672 ath9k_hw_get_lower_upper_index(u8 target,
1673                                u8 *pList,
1674                                u16 listSize,
1675                                u16 *indexL,
1676                                u16 *indexR)
1677 {
1678         u16 i;
1679
1680         if (target <= pList[0]) {
1681                 *indexL = *indexR = 0;
1682                 return true;
1683         }
1684         if (target >= pList[listSize - 1]) {
1685                 *indexL = *indexR = (u16) (listSize - 1);
1686                 return true;
1687         }
1688
1689         for (i = 0; i < listSize - 1; i++) {
1690                 if (pList[i] == target) {
1691                         *indexL = *indexR = i;
1692                         return true;
1693                 }
1694                 if (target < pList[i + 1]) {
1695                         *indexL = i;
1696                         *indexR = (u16) (i + 1);
1697                         return false;
1698                 }
1699         }
1700         return false;
1701 }
1702
1703 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1704 {
1705         int16_t nfval;
1706         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1707         int i, j;
1708
1709         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1710                 sort[i] = nfCalBuffer[i];
1711
1712         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1713                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1714                         if (sort[j] > sort[j - 1]) {
1715                                 nfval = sort[j];
1716                                 sort[j] = sort[j - 1];
1717                                 sort[j - 1] = nfval;
1718                         }
1719                 }
1720         }
1721         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1722
1723         return nfval;
1724 }
1725
1726 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1727                                               int16_t *nfarray)
1728 {
1729         int i;
1730
1731         for (i = 0; i < NUM_NF_READINGS; i++) {
1732                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1733
1734                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1735                         h[i].currIndex = 0;
1736
1737                 if (h[i].invalidNFcount > 0) {
1738                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1739                             || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1740                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1741                         } else {
1742                                 h[i].invalidNFcount--;
1743                                 h[i].privNF = nfarray[i];
1744                         }
1745                 } else {
1746                         h[i].privNF =
1747                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1748                 }
1749         }
1750         return;
1751 }
1752
1753 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1754                                 int16_t nfarray[NUM_NF_READINGS])
1755 {
1756         int16_t nf;
1757
1758         if (AR_SREV_9280_10_OR_LATER(ah))
1759                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1760         else
1761                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1762
1763         if (nf & 0x100)
1764                 nf = 0 - ((nf ^ 0x1ff) + 1);
1765         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1766                  "NF calibrated [ctl] [chain 0] is %d\n", nf);
1767         nfarray[0] = nf;
1768
1769         if (AR_SREV_9280_10_OR_LATER(ah))
1770                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1771                         AR9280_PHY_CH1_MINCCA_PWR);
1772         else
1773                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1774                         AR_PHY_CH1_MINCCA_PWR);
1775
1776         if (nf & 0x100)
1777                 nf = 0 - ((nf ^ 0x1ff) + 1);
1778         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1779                  "NF calibrated [ctl] [chain 1] is %d\n", nf);
1780         nfarray[1] = nf;
1781
1782         if (!AR_SREV_9280(ah)) {
1783                 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1784                         AR_PHY_CH2_MINCCA_PWR);
1785                 if (nf & 0x100)
1786                         nf = 0 - ((nf ^ 0x1ff) + 1);
1787                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1788                          "NF calibrated [ctl] [chain 2] is %d\n", nf);
1789                 nfarray[2] = nf;
1790         }
1791
1792         if (AR_SREV_9280_10_OR_LATER(ah))
1793                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1794                         AR9280_PHY_EXT_MINCCA_PWR);
1795         else
1796                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1797                         AR_PHY_EXT_MINCCA_PWR);
1798
1799         if (nf & 0x100)
1800                 nf = 0 - ((nf ^ 0x1ff) + 1);
1801         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1802                  "NF calibrated [ext] [chain 0] is %d\n", nf);
1803         nfarray[3] = nf;
1804
1805         if (AR_SREV_9280_10_OR_LATER(ah))
1806                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1807                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
1808         else
1809                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1810                         AR_PHY_CH1_EXT_MINCCA_PWR);
1811
1812         if (nf & 0x100)
1813                 nf = 0 - ((nf ^ 0x1ff) + 1);
1814         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1815                  "NF calibrated [ext] [chain 1] is %d\n", nf);
1816         nfarray[4] = nf;
1817
1818         if (!AR_SREV_9280(ah)) {
1819                 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1820                         AR_PHY_CH2_EXT_MINCCA_PWR);
1821                 if (nf & 0x100)
1822                         nf = 0 - ((nf ^ 0x1ff) + 1);
1823                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1824                          "NF calibrated [ext] [chain 2] is %d\n", nf);
1825                 nfarray[5] = nf;
1826         }
1827 }
1828
1829 static bool
1830 getNoiseFloorThresh(struct ath_hal *ah,
1831                     const struct ath9k_channel *chan,
1832                     int16_t *nft)
1833 {
1834         struct ath_hal_5416 *ahp = AH5416(ah);
1835
1836         switch (chan->chanmode) {
1837         case CHANNEL_A:
1838         case CHANNEL_A_HT20:
1839         case CHANNEL_A_HT40PLUS:
1840         case CHANNEL_A_HT40MINUS:
1841                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1842                 break;
1843         case CHANNEL_B:
1844         case CHANNEL_G:
1845         case CHANNEL_G_HT20:
1846         case CHANNEL_G_HT40PLUS:
1847         case CHANNEL_G_HT40MINUS:
1848                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1849                 break;
1850         default:
1851                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1852                          "%s: invalid channel flags 0x%x\n", __func__,
1853                          chan->channelFlags);
1854                 return false;
1855         }
1856         return true;
1857 }
1858
1859 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1860 {
1861         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1862                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1863         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1864                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1865         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1866 }
1867
1868 static void
1869 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1870 {
1871         struct ath9k_nfcal_hist *h;
1872         int i, j;
1873         int32_t val;
1874         const u32 ar5416_cca_regs[6] = {
1875                 AR_PHY_CCA,
1876                 AR_PHY_CH1_CCA,
1877                 AR_PHY_CH2_CCA,
1878                 AR_PHY_EXT_CCA,
1879                 AR_PHY_CH1_EXT_CCA,
1880                 AR_PHY_CH2_EXT_CCA
1881         };
1882         u8 chainmask;
1883
1884         if (AR_SREV_9280(ah))
1885                 chainmask = 0x1B;
1886         else
1887                 chainmask = 0x3F;
1888
1889 #ifdef ATH_NF_PER_CHAN
1890         h = chan->nfCalHist;
1891 #else
1892         h = ah->nfCalHist;
1893 #endif
1894
1895         for (i = 0; i < NUM_NF_READINGS; i++) {
1896                 if (chainmask & (1 << i)) {
1897                         val = REG_READ(ah, ar5416_cca_regs[i]);
1898                         val &= 0xFFFFFE00;
1899                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1900                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1901                 }
1902         }
1903
1904         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1905                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1906         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1907                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1908         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1909
1910         for (j = 0; j < 1000; j++) {
1911                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1912                      AR_PHY_AGC_CONTROL_NF) == 0)
1913                         break;
1914                 udelay(10);
1915         }
1916
1917         for (i = 0; i < NUM_NF_READINGS; i++) {
1918                 if (chainmask & (1 << i)) {
1919                         val = REG_READ(ah, ar5416_cca_regs[i]);
1920                         val &= 0xFFFFFE00;
1921                         val |= (((u32) (-50) << 1) & 0x1ff);
1922                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1923                 }
1924         }
1925 }
1926
1927 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1928                               struct ath9k_channel *chan)
1929 {
1930         int16_t nf, nfThresh;
1931         int16_t nfarray[NUM_NF_READINGS] = { 0 };
1932         struct ath9k_nfcal_hist *h;
1933         u8 chainmask;
1934
1935         if (AR_SREV_9280(ah))
1936                 chainmask = 0x1B;
1937         else
1938                 chainmask = 0x3F;
1939
1940         chan->channelFlags &= (~CHANNEL_CW_INT);
1941         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1942                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1943                          "%s: NF did not complete in calibration window\n",
1944                          __func__);
1945                 nf = 0;
1946                 chan->rawNoiseFloor = nf;
1947                 return chan->rawNoiseFloor;
1948         } else {
1949                 ar5416GetNoiseFloor(ah, nfarray);
1950                 nf = nfarray[0];
1951                 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1952                     && nf > nfThresh) {
1953                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1954                                  "%s: noise floor failed detected; "
1955                                  "detected %d, threshold %d\n", __func__,
1956                                  nf, nfThresh);
1957                         chan->channelFlags |= CHANNEL_CW_INT;
1958                 }
1959         }
1960
1961 #ifdef ATH_NF_PER_CHAN
1962         h = chan->nfCalHist;
1963 #else
1964         h = ah->nfCalHist;
1965 #endif
1966
1967         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1968         chan->rawNoiseFloor = h[0].privNF;
1969
1970         return chan->rawNoiseFloor;
1971 }
1972
1973 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1974                               struct ath9k_mib_stats *stats)
1975 {
1976         stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1977         stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1978         stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1979         stats->rts_good += REG_READ(ah, AR_RTS_OK);
1980         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1981 }
1982
1983 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1984 {
1985         struct ath_hal_5416 *ahp = AH5416(ah);
1986
1987         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1988
1989         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1990
1991         REG_WRITE(ah, AR_FILT_OFDM, 0);
1992         REG_WRITE(ah, AR_FILT_CCK, 0);
1993         REG_WRITE(ah, AR_MIBC,
1994                   ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1995                   & 0x0f);
1996         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1997         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1998 }
1999
2000 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2001 {
2002         struct ath_hal_5416 *ahp = AH5416(ah);
2003
2004         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2005
2006         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2007
2008         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2009
2010         REG_WRITE(ah, AR_FILT_OFDM, 0);
2011         REG_WRITE(ah, AR_FILT_CCK, 0);
2012 }
2013
2014 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2015                                         struct ath9k_channel *chan)
2016 {
2017         struct ath_hal_5416 *ahp = AH5416(ah);
2018         int i;
2019
2020         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2021                 if (ahp->ah_ani[i].c.channel == chan->channel)
2022                         return i;
2023                 if (ahp->ah_ani[i].c.channel == 0) {
2024                         ahp->ah_ani[i].c.channel = chan->channel;
2025                         ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2026                         return i;
2027                 }
2028         }
2029
2030         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2031                  "No more channel states left. Using channel 0\n");
2032         return 0;
2033 }
2034
2035 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2036 {
2037         struct ath_hal_5416 *ahp = AH5416(ah);
2038         int i;
2039
2040         ahp->ah_hasHwPhyCounters = 1;
2041
2042         memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2043         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2044                 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2045                 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2046                 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2047                 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2048                 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2049                 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2050                 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2051                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2052                 ahp->ah_ani[i].cckWeakSigThreshold =
2053                         ATH9K_ANI_CCK_WEAK_SIG_THR;
2054                 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2055                 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2056                 if (ahp->ah_hasHwPhyCounters) {
2057                         ahp->ah_ani[i].ofdmPhyErrBase =
2058                                 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2059                         ahp->ah_ani[i].cckPhyErrBase =
2060                                 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2061                 }
2062         }
2063         if (ahp->ah_hasHwPhyCounters) {
2064                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2065                         "Setting OfdmErrBase = 0x%08x\n",
2066                         ahp->ah_ani[0].ofdmPhyErrBase);
2067                 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2068                         ahp->ah_ani[0].cckPhyErrBase);
2069
2070                 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2071                 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2072                 ath9k_enable_mib_counters(ah);
2073         }
2074         ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2075         if (ah->ah_config.enable_ani)
2076                 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2077 }
2078
2079 static inline void ath9k_hw_ani_setup(struct ath_hal *ah)
2080 {
2081         struct ath_hal_5416 *ahp = AH5416(ah);
2082         int i;
2083
2084         const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2085         const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2086         const int coarseLow[] = { -64, -64, -64, -64, -70 };
2087         const int firpwr[] = { -78, -78, -78, -78, -80 };
2088
2089         for (i = 0; i < 5; i++) {
2090                 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2091                 ahp->ah_coarseHigh[i] = coarseHigh[i];
2092                 ahp->ah_coarseLow[i] = coarseLow[i];
2093                 ahp->ah_firpwr[i] = firpwr[i];
2094         }
2095 }
2096
2097 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2098 {
2099         struct ath_hal_5416 *ahp = AH5416(ah);
2100
2101         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2102         if (ahp->ah_hasHwPhyCounters) {
2103                 ath9k_hw_disable_mib_counters(ah);
2104                 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2105                 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2106         }
2107 }
2108
2109
2110 static bool ath9k_hw_ani_control(struct ath_hal *ah,
2111                                  enum ath9k_ani_cmd cmd, int param)
2112 {
2113         struct ath_hal_5416 *ahp = AH5416(ah);
2114         struct ar5416AniState *aniState = ahp->ah_curani;
2115
2116         switch (cmd & ahp->ah_ani_function) {
2117         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2118                 u32 level = param;
2119
2120                 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2121                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2122                                  "%s: level out of range (%u > %u)\n",
2123                                  __func__, level,
2124                                  (unsigned) ARRAY_SIZE(ahp->
2125                                                        ah_totalSizeDesired));
2126                         return false;
2127                 }
2128
2129                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2130                               AR_PHY_DESIRED_SZ_TOT_DES,
2131                               ahp->ah_totalSizeDesired[level]);
2132                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2133                               AR_PHY_AGC_CTL1_COARSE_LOW,
2134                               ahp->ah_coarseLow[level]);
2135                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2136                               AR_PHY_AGC_CTL1_COARSE_HIGH,
2137                               ahp->ah_coarseHigh[level]);
2138                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2139                               AR_PHY_FIND_SIG_FIRPWR,
2140                               ahp->ah_firpwr[level]);
2141
2142                 if (level > aniState->noiseImmunityLevel)
2143                         ahp->ah_stats.ast_ani_niup++;
2144                 else if (level < aniState->noiseImmunityLevel)
2145                         ahp->ah_stats.ast_ani_nidown++;
2146                 aniState->noiseImmunityLevel = level;
2147                 break;
2148         }
2149         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2150                 const int m1ThreshLow[] = { 127, 50 };
2151                 const int m2ThreshLow[] = { 127, 40 };
2152                 const int m1Thresh[] = { 127, 0x4d };
2153                 const int m2Thresh[] = { 127, 0x40 };
2154                 const int m2CountThr[] = { 31, 16 };
2155                 const int m2CountThrLow[] = { 63, 48 };
2156                 u32 on = param ? 1 : 0;
2157
2158                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2159                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2160                               m1ThreshLow[on]);
2161                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2162                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2163                               m2ThreshLow[on]);
2164                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2165                               AR_PHY_SFCORR_M1_THRESH,
2166                               m1Thresh[on]);
2167                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2168                               AR_PHY_SFCORR_M2_THRESH,
2169                               m2Thresh[on]);
2170                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2171                               AR_PHY_SFCORR_M2COUNT_THR,
2172                               m2CountThr[on]);
2173                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2174                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2175                               m2CountThrLow[on]);
2176
2177                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2178                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2179                               m1ThreshLow[on]);
2180                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2181                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2182                               m2ThreshLow[on]);
2183                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2184                               AR_PHY_SFCORR_EXT_M1_THRESH,
2185                               m1Thresh[on]);
2186                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2187                               AR_PHY_SFCORR_EXT_M2_THRESH,
2188                               m2Thresh[on]);
2189
2190                 if (on)
2191                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2192                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2193                 else
2194                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2195                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2196
2197                 if (!on != aniState->ofdmWeakSigDetectOff) {
2198                         if (on)
2199                                 ahp->ah_stats.ast_ani_ofdmon++;
2200                         else
2201                                 ahp->ah_stats.ast_ani_ofdmoff++;
2202                         aniState->ofdmWeakSigDetectOff = !on;
2203                 }
2204                 break;
2205         }
2206         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2207                 const int weakSigThrCck[] = { 8, 6 };
2208                 u32 high = param ? 1 : 0;
2209
2210                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2211                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2212                               weakSigThrCck[high]);
2213                 if (high != aniState->cckWeakSigThreshold) {
2214                         if (high)
2215                                 ahp->ah_stats.ast_ani_cckhigh++;
2216                         else
2217                                 ahp->ah_stats.ast_ani_ccklow++;
2218                         aniState->cckWeakSigThreshold = high;
2219                 }
2220                 break;
2221         }
2222         case ATH9K_ANI_FIRSTEP_LEVEL:{
2223                 const int firstep[] = { 0, 4, 8 };
2224                 u32 level = param;
2225
2226                 if (level >= ARRAY_SIZE(firstep)) {
2227                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2228                                  "%s: level out of range (%u > %u)\n",
2229                                  __func__, level,
2230                                 (unsigned) ARRAY_SIZE(firstep));
2231                         return false;
2232                 }
2233                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2234                               AR_PHY_FIND_SIG_FIRSTEP,
2235                               firstep[level]);
2236                 if (level > aniState->firstepLevel)
2237                         ahp->ah_stats.ast_ani_stepup++;
2238                 else if (level < aniState->firstepLevel)
2239                         ahp->ah_stats.ast_ani_stepdown++;
2240                 aniState->firstepLevel = level;
2241                 break;
2242         }
2243         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2244                 const int cycpwrThr1[] =
2245                         { 2, 4, 6, 8, 10, 12, 14, 16 };
2246                 u32 level = param;
2247
2248                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2249                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2250                                  "%s: level out of range (%u > %u)\n",
2251                                  __func__, level,
2252                                  (unsigned)
2253                                 ARRAY_SIZE(cycpwrThr1));
2254                         return false;
2255                 }
2256                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2257                               AR_PHY_TIMING5_CYCPWR_THR1,
2258                               cycpwrThr1[level]);
2259                 if (level > aniState->spurImmunityLevel)
2260                         ahp->ah_stats.ast_ani_spurup++;
2261                 else if (level < aniState->spurImmunityLevel)
2262                         ahp->ah_stats.ast_ani_spurdown++;
2263                 aniState->spurImmunityLevel = level;
2264                 break;
2265         }
2266         case ATH9K_ANI_PRESENT:
2267                 break;
2268         default:
2269                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2270                         "%s: invalid cmd %u\n", __func__, cmd);
2271                 return false;
2272         }
2273
2274         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2275         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2276                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2277                 "ofdmWeakSigDetectOff=%d\n",
2278                  aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2279                  !aniState->ofdmWeakSigDetectOff);
2280         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2281                 "cckWeakSigThreshold=%d, "
2282                 "firstepLevel=%d, listenTime=%d\n",
2283                  aniState->cckWeakSigThreshold, aniState->firstepLevel,
2284                  aniState->listenTime);
2285         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2286                  "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2287                  aniState->cycleCount, aniState->ofdmPhyErrCount,
2288                  aniState->cckPhyErrCount);
2289         return true;
2290 }
2291
2292 static void ath9k_ani_restart(struct ath_hal *ah)
2293 {
2294         struct ath_hal_5416 *ahp = AH5416(ah);
2295         struct ar5416AniState *aniState;
2296
2297         if (!DO_ANI(ah))
2298                 return;
2299
2300         aniState = ahp->ah_curani;
2301
2302         aniState->listenTime = 0;
2303         if (ahp->ah_hasHwPhyCounters) {
2304                 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2305                         aniState->ofdmPhyErrBase = 0;
2306                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2307                                  "OFDM Trigger is too high for hw counters\n");
2308                 } else {
2309                         aniState->ofdmPhyErrBase =
2310                                 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2311                 }
2312                 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2313                         aniState->cckPhyErrBase = 0;
2314                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2315                                  "CCK Trigger is too high for hw counters\n");
2316                 } else {
2317                         aniState->cckPhyErrBase =
2318                                 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2319                 }
2320                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2321                          "%s: Writing ofdmbase=%u   cckbase=%u\n",
2322                          __func__, aniState->ofdmPhyErrBase,
2323                          aniState->cckPhyErrBase);
2324                 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2325                 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2326                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2327                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2328
2329                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2330         }
2331         aniState->ofdmPhyErrCount = 0;
2332         aniState->cckPhyErrCount = 0;
2333 }
2334
2335 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2336 {
2337         struct ath_hal_5416 *ahp = AH5416(ah);
2338         struct ath9k_channel *chan = ah->ah_curchan;
2339         struct ar5416AniState *aniState;
2340         enum wireless_mode mode;
2341         int32_t rssi;
2342
2343         if (!DO_ANI(ah))
2344                 return;
2345
2346         aniState = ahp->ah_curani;
2347
2348         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2349                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2350                                          aniState->noiseImmunityLevel + 1)) {
2351                         return;
2352                 }
2353         }
2354
2355         if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2356                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2357                                          aniState->spurImmunityLevel + 1)) {
2358                         return;
2359                 }
2360         }
2361
2362         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2363                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2364                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2365                                              aniState->firstepLevel + 1);
2366                 }
2367                 return;
2368         }
2369         rssi = BEACON_RSSI(ahp);
2370         if (rssi > aniState->rssiThrHigh) {
2371                 if (!aniState->ofdmWeakSigDetectOff) {
2372                         if (ath9k_hw_ani_control(ah,
2373                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2374                                          false)) {
2375                                 ath9k_hw_ani_control(ah,
2376                                         ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2377                                         0);
2378                                 return;
2379                         }
2380                 }
2381                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2382                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2383                                              aniState->firstepLevel + 1);
2384                         return;
2385                 }
2386         } else if (rssi > aniState->rssiThrLow) {
2387                 if (aniState->ofdmWeakSigDetectOff)
2388                         ath9k_hw_ani_control(ah,
2389                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2390                                      true);
2391                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2392                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2393                                              aniState->firstepLevel + 1);
2394                 return;
2395         } else {
2396                 mode = ath9k_hw_chan2wmode(ah, chan);
2397                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2398                         if (!aniState->ofdmWeakSigDetectOff)
2399                                 ath9k_hw_ani_control(ah,
2400                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2401                                      false);
2402                         if (aniState->firstepLevel > 0)
2403                                 ath9k_hw_ani_control(ah,
2404                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2405                                                      0);
2406                         return;
2407                 }
2408         }
2409 }
2410
2411 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2412 {
2413         struct ath_hal_5416 *ahp = AH5416(ah);
2414         struct ath9k_channel *chan = ah->ah_curchan;
2415         struct ar5416AniState *aniState;
2416         enum wireless_mode mode;
2417         int32_t rssi;
2418
2419         if (!DO_ANI(ah))
2420                 return;
2421
2422         aniState = ahp->ah_curani;
2423         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2424                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2425                                          aniState->noiseImmunityLevel + 1)) {
2426                         return;
2427                 }
2428         }
2429         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2430                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2431                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2432                                              aniState->firstepLevel + 1);
2433                 }
2434                 return;
2435         }
2436         rssi = BEACON_RSSI(ahp);
2437         if (rssi > aniState->rssiThrLow) {
2438                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2439                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2440                                              aniState->firstepLevel + 1);
2441         } else {
2442                 mode = ath9k_hw_chan2wmode(ah, chan);
2443                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2444                         if (aniState->firstepLevel > 0)
2445                                 ath9k_hw_ani_control(ah,
2446                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2447                                                      0);
2448                 }
2449         }
2450 }
2451
2452 static void ath9k_ani_reset(struct ath_hal *ah)
2453 {
2454         struct ath_hal_5416 *ahp = AH5416(ah);
2455         struct ar5416AniState *aniState;
2456         struct ath9k_channel *chan = ah->ah_curchan;
2457         int index;
2458
2459         if (!DO_ANI(ah))
2460                 return;
2461
2462         index = ath9k_hw_get_ani_channel_idx(ah, chan);
2463         aniState = &ahp->ah_ani[index];
2464         ahp->ah_curani = aniState;
2465
2466         if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2467             && ah->ah_opmode != ATH9K_M_IBSS) {
2468                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2469                          "%s: Reset ANI state opmode %u\n", __func__,
2470                          ah->ah_opmode);
2471                 ahp->ah_stats.ast_ani_reset++;
2472                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2473                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2474                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2475                 ath9k_hw_ani_control(ah,
2476                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2477                                      !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2478                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2479                                      ATH9K_ANI_CCK_WEAK_SIG_THR);
2480                 ath9k_hw_setrxfilter(ah,
2481                                      ath9k_hw_getrxfilter(ah) |
2482                                      ATH9K_RX_FILTER_PHYERR);
2483                 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2484                         ahp->ah_curani->ofdmTrigHigh =
2485                                 ah->ah_config.ofdm_trig_high;
2486                         ahp->ah_curani->ofdmTrigLow =
2487                                 ah->ah_config.ofdm_trig_low;
2488                         ahp->ah_curani->cckTrigHigh =
2489                                 ah->ah_config.cck_trig_high;
2490                         ahp->ah_curani->cckTrigLow =
2491                                 ah->ah_config.cck_trig_low;
2492                 }
2493                 ath9k_ani_restart(ah);
2494                 return;
2495         }
2496
2497         if (aniState->noiseImmunityLevel != 0)
2498                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2499                                      aniState->noiseImmunityLevel);
2500         if (aniState->spurImmunityLevel != 0)
2501                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2502                                      aniState->spurImmunityLevel);
2503         if (aniState->ofdmWeakSigDetectOff)
2504                 ath9k_hw_ani_control(ah,
2505                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2506                                      !aniState->ofdmWeakSigDetectOff);
2507         if (aniState->cckWeakSigThreshold)
2508                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2509                                      aniState->cckWeakSigThreshold);
2510         if (aniState->firstepLevel != 0)
2511                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2512                                      aniState->firstepLevel);
2513         if (ahp->ah_hasHwPhyCounters) {
2514                 ath9k_hw_setrxfilter(ah,
2515                                      ath9k_hw_getrxfilter(ah) &
2516                                      ~ATH9K_RX_FILTER_PHYERR);
2517                 ath9k_ani_restart(ah);
2518                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2519                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2520
2521         } else {
2522                 ath9k_ani_restart(ah);
2523                 ath9k_hw_setrxfilter(ah,
2524                                      ath9k_hw_getrxfilter(ah) |
2525                                      ATH9K_RX_FILTER_PHYERR);
2526         }
2527 }
2528
2529 void ath9k_hw_procmibevent(struct ath_hal *ah,
2530                            const struct ath9k_node_stats *stats)
2531 {
2532         struct ath_hal_5416 *ahp = AH5416(ah);
2533         u32 phyCnt1, phyCnt2;
2534
2535         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2536
2537         REG_WRITE(ah, AR_FILT_OFDM, 0);
2538         REG_WRITE(ah, AR_FILT_CCK, 0);
2539         if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2540                 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2541
2542         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2543         ahp->ah_stats.ast_nodestats = *stats;
2544
2545         if (!DO_ANI(ah))
2546                 return;
2547
2548         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2549         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2550         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2551             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2552                 struct ar5416AniState *aniState = ahp->ah_curani;
2553                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2554
2555                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2556                 ahp->ah_stats.ast_ani_ofdmerrs +=
2557                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2558                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2559
2560                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2561                 ahp->ah_stats.ast_ani_cckerrs +=
2562                         cckPhyErrCnt - aniState->cckPhyErrCount;
2563                 aniState->cckPhyErrCount = cckPhyErrCnt;
2564
2565                 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2566                         ath9k_hw_ani_ofdm_err_trigger(ah);
2567                 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2568                         ath9k_hw_ani_cck_err_trigger(ah);
2569
2570                 ath9k_ani_restart(ah);
2571         }
2572 }
2573
2574 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2575 {
2576         struct ath_hal_5416 *ahp = AH5416(ah);
2577         struct ar5416AniState *aniState;
2578         int32_t rssi;
2579
2580         aniState = ahp->ah_curani;
2581
2582         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2583                 if (aniState->firstepLevel > 0) {
2584                         if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2585                                                  aniState->firstepLevel - 1)) {
2586                                 return;
2587                         }
2588                 }
2589         } else {
2590                 rssi = BEACON_RSSI(ahp);
2591                 if (rssi > aniState->rssiThrHigh) {
2592                         /* XXX: Handle me */
2593                 } else if (rssi > aniState->rssiThrLow) {
2594                         if (aniState->ofdmWeakSigDetectOff) {
2595                                 if (ath9k_hw_ani_control(ah,
2596                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2597                                          true) ==
2598                                     true) {
2599                                         return;
2600                                 }
2601                         }
2602                         if (aniState->firstepLevel > 0) {
2603                                 if (ath9k_hw_ani_control
2604                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2605                                      aniState->firstepLevel - 1) ==
2606                                     true) {
2607                                         return;
2608                                 }
2609                         }
2610                 } else {
2611                         if (aniState->firstepLevel > 0) {
2612                                 if (ath9k_hw_ani_control
2613                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2614                                      aniState->firstepLevel - 1) ==
2615                                     true) {
2616                                         return;
2617                                 }
2618                         }
2619                 }
2620         }
2621
2622         if (aniState->spurImmunityLevel > 0) {
2623                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2624                                          aniState->spurImmunityLevel - 1)) {
2625                         return;
2626                 }
2627         }
2628
2629         if (aniState->noiseImmunityLevel > 0) {
2630                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2631                                      aniState->noiseImmunityLevel - 1);
2632                 return;
2633         }
2634 }
2635
2636 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2637 {
2638         struct ath_hal_5416 *ahp = AH5416(ah);
2639         struct ar5416AniState *aniState;
2640         u32 txFrameCount, rxFrameCount, cycleCount;
2641         int32_t listenTime;
2642
2643         txFrameCount = REG_READ(ah, AR_TFCNT);
2644         rxFrameCount = REG_READ(ah, AR_RFCNT);
2645         cycleCount = REG_READ(ah, AR_CCCNT);
2646
2647         aniState = ahp->ah_curani;
2648         if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2649
2650                 listenTime = 0;
2651                 ahp->ah_stats.ast_ani_lzero++;
2652         } else {
2653                 int32_t ccdelta = cycleCount - aniState->cycleCount;
2654                 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2655                 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2656                 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2657         }
2658         aniState->cycleCount = cycleCount;
2659         aniState->txFrameCount = txFrameCount;
2660         aniState->rxFrameCount = rxFrameCount;
2661
2662         return listenTime;
2663 }
2664
2665 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2666                           const struct ath9k_node_stats *stats,
2667                           struct ath9k_channel *chan)
2668 {
2669         struct ath_hal_5416 *ahp = AH5416(ah);
2670         struct ar5416AniState *aniState;
2671         int32_t listenTime;
2672
2673         aniState = ahp->ah_curani;
2674         ahp->ah_stats.ast_nodestats = *stats;
2675
2676         listenTime = ath9k_hw_ani_get_listen_time(ah);
2677         if (listenTime < 0) {
2678                 ahp->ah_stats.ast_ani_lneg++;
2679                 ath9k_ani_restart(ah);
2680                 return;
2681         }
2682
2683         aniState->listenTime += listenTime;
2684
2685         if (ahp->ah_hasHwPhyCounters) {
2686                 u32 phyCnt1, phyCnt2;
2687                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2688
2689                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2690
2691                 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2692                 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2693
2694                 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2695                     phyCnt2 < aniState->cckPhyErrBase) {
2696                         if (phyCnt1 < aniState->ofdmPhyErrBase) {
2697                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2698                                          "%s: phyCnt1 0x%x, resetting "
2699                                          "counter value to 0x%x\n",
2700                                          __func__, phyCnt1,
2701                                          aniState->ofdmPhyErrBase);
2702                                 REG_WRITE(ah, AR_PHY_ERR_1,
2703                                           aniState->ofdmPhyErrBase);
2704                                 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2705                                           AR_PHY_ERR_OFDM_TIMING);
2706                         }
2707                         if (phyCnt2 < aniState->cckPhyErrBase) {
2708                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2709                                          "%s: phyCnt2 0x%x, resetting "
2710                                          "counter value to 0x%x\n",
2711                                          __func__, phyCnt2,
2712                                          aniState->cckPhyErrBase);
2713                                 REG_WRITE(ah, AR_PHY_ERR_2,
2714                                           aniState->cckPhyErrBase);
2715                                 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2716                                           AR_PHY_ERR_CCK_TIMING);
2717                         }
2718                         return;
2719                 }
2720
2721                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2722                 ahp->ah_stats.ast_ani_ofdmerrs +=
2723                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2724                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2725
2726                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2727                 ahp->ah_stats.ast_ani_cckerrs +=
2728                         cckPhyErrCnt - aniState->cckPhyErrCount;
2729                 aniState->cckPhyErrCount = cckPhyErrCnt;
2730         }
2731
2732         if (!DO_ANI(ah))
2733                 return;
2734
2735         if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2736                 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2737                     aniState->ofdmTrigLow / 1000 &&
2738                     aniState->cckPhyErrCount <= aniState->listenTime *
2739                     aniState->cckTrigLow / 1000)
2740                         ath9k_hw_ani_lower_immunity(ah);
2741                 ath9k_ani_restart(ah);
2742         } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2743                 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2744                     aniState->ofdmTrigHigh / 1000) {
2745                         ath9k_hw_ani_ofdm_err_trigger(ah);
2746                         ath9k_ani_restart(ah);
2747                 } else if (aniState->cckPhyErrCount >
2748                            aniState->listenTime * aniState->cckTrigHigh /
2749                            1000) {
2750                         ath9k_hw_ani_cck_err_trigger(ah);
2751                         ath9k_ani_restart(ah);
2752                 }
2753         }
2754 }
2755
2756 #ifndef ATH_NF_PER_CHAN
2757 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2758 {
2759         int i, j;
2760
2761         for (i = 0; i < NUM_NF_READINGS; i++) {
2762                 ah->nfCalHist[i].currIndex = 0;
2763                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2764                 ah->nfCalHist[i].invalidNFcount =
2765                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
2766                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2767                         ah->nfCalHist[i].nfCalBuffer[j] =
2768                                 AR_PHY_CCA_MAX_GOOD_VALUE;
2769                 }
2770         }
2771         return;
2772 }
2773 #endif
2774
2775 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2776                                          u32 gpio, u32 type)
2777 {
2778         int addr;
2779         u32 gpio_shift, tmp;
2780
2781         if (gpio > 11)
2782                 addr = AR_GPIO_OUTPUT_MUX3;
2783         else if (gpio > 5)
2784                 addr = AR_GPIO_OUTPUT_MUX2;
2785         else
2786                 addr = AR_GPIO_OUTPUT_MUX1;
2787
2788         gpio_shift = (gpio % 6) * 5;
2789
2790         if (AR_SREV_9280_20_OR_LATER(ah)
2791             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2792                 REG_RMW(ah, addr, (type << gpio_shift),
2793                         (0x1f << gpio_shift));
2794         } else {
2795                 tmp = REG_READ(ah, addr);
2796                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2797                 tmp &= ~(0x1f << gpio_shift);
2798                 tmp |= (type << gpio_shift);
2799                 REG_WRITE(ah, addr, tmp);
2800         }
2801 }
2802
2803 static bool ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2804                                 enum ath9k_gpio_output_mux_type
2805                                 halSignalType)
2806 {
2807         u32 ah_signal_type;
2808         u32 gpio_shift;
2809
2810         static u32 MuxSignalConversionTable[] = {
2811
2812                 AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
2813
2814                 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
2815
2816                 AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
2817
2818                 AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
2819
2820                 AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
2821         };
2822
2823         if ((halSignalType >= 0)
2824             && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable)))
2825                 ah_signal_type = MuxSignalConversionTable[halSignalType];
2826         else
2827                 return false;
2828
2829         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2830
2831         gpio_shift = 2 * gpio;
2832
2833         REG_RMW(ah,
2834                 AR_GPIO_OE_OUT,
2835                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2836                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2837
2838         return true;
2839 }
2840
2841 static bool ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio,
2842                               u32 val)
2843 {
2844         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2845                 AR_GPIO_BIT(gpio));
2846         return true;
2847 }
2848
2849 static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2850 {
2851         if (gpio >= ah->ah_caps.num_gpio_pins)
2852                 return 0xffffffff;
2853
2854         if (AR_SREV_9280_10_OR_LATER(ah)) {
2855                 return (MS
2856                         (REG_READ(ah, AR_GPIO_IN_OUT),
2857                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2858         } else {
2859                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2860                         AR_GPIO_BIT(gpio)) != 0;
2861         }
2862 }
2863
2864 static inline int ath9k_hw_post_attach(struct ath_hal *ah)
2865 {
2866         int ecode;
2867
2868         if (!ath9k_hw_chip_test(ah)) {
2869                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2870                          "%s: hardware self-test failed\n", __func__);
2871                 return -ENODEV;
2872         }
2873
2874         ecode = ath9k_hw_rf_claim(ah);
2875         if (ecode != 0)
2876                 return ecode;
2877
2878         ecode = ath9k_hw_eeprom_attach(ah);
2879         if (ecode != 0)
2880                 return ecode;
2881         ecode = ath9k_hw_rfattach(ah);
2882         if (ecode != 0)
2883                 return ecode;
2884
2885         if (!AR_SREV_9100(ah)) {
2886                 ath9k_hw_ani_setup(ah);
2887                 ath9k_hw_ani_attach(ah);
2888         }
2889         return 0;
2890 }
2891
2892 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2893                                     struct ar5416_eeprom *pEepData,
2894                                     u32 reg, u32 value)
2895 {
2896         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2897
2898         switch (ah->ah_devid) {
2899         case AR9280_DEVID_PCI:
2900                 if (reg == 0x7894) {
2901                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2902                                  "ini VAL: %x  EEPROM: %x\n", value,
2903                                  (pBase->version & 0xff));
2904
2905                         if ((pBase->version & 0xff) > 0x0a) {
2906                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2907                                          "PWDCLKIND: %d\n",
2908                                          pBase->pwdclkind);
2909                                 value &= ~AR_AN_TOP2_PWDCLKIND;
2910                                 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2911                                          pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2912                         } else {
2913                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2914                                          "PWDCLKIND Earlier Rev\n");
2915                         }
2916
2917                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2918                                  "final ini VAL: %x\n", value);
2919                 }
2920                 break;
2921         }
2922         return value;
2923 }
2924
2925 static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2926 {
2927         struct ath_hal_5416 *ahp = AH5416(ah);
2928         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2929         u16 capField = 0, eeval;
2930
2931         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2932
2933         ah->ah_currentRD = eeval;
2934
2935         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2936         ah->ah_currentRDExt = eeval;
2937
2938         capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2939
2940         if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2941             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2942                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2943                         ah->ah_currentRD += 5;
2944                 else if (ah->ah_currentRD == 0x41)
2945                         ah->ah_currentRD = 0x43;
2946                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2947                          "%s: regdomain mapped to 0x%x\n", __func__,
2948                          ah->ah_currentRD);
2949         }
2950
2951         eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2952         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2953
2954         if (eeval & AR5416_OPFLAGS_11A) {
2955                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2956                 if (ah->ah_config.ht_enable) {
2957                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2958                                 set_bit(ATH9K_MODE_11NA_HT20,
2959                                         pCap->wireless_modes);
2960                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2961                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2962                                         pCap->wireless_modes);
2963                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2964                                         pCap->wireless_modes);
2965                         }
2966                 }
2967         }
2968
2969         if (eeval & AR5416_OPFLAGS_11G) {
2970                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2971                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2972                 if (ah->ah_config.ht_enable) {
2973                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2974                                 set_bit(ATH9K_MODE_11NG_HT20,
2975                                         pCap->wireless_modes);
2976                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2977                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2978                                         pCap->wireless_modes);
2979                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2980                                         pCap->wireless_modes);
2981                         }
2982                 }
2983         }
2984
2985         pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
2986         if ((ah->ah_isPciExpress)
2987             || (eeval & AR5416_OPFLAGS_11A)) {
2988                 pCap->rx_chainmask =
2989                         ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
2990         } else {
2991                 pCap->rx_chainmask =
2992                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
2993         }
2994
2995         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
2996                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
2997
2998         pCap->low_2ghz_chan = 2312;
2999         pCap->high_2ghz_chan = 2732;
3000
3001         pCap->low_5ghz_chan = 4920;
3002         pCap->high_5ghz_chan = 6100;
3003
3004         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3005         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3006         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3007
3008         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3009         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3010         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3011
3012         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3013
3014         if (ah->ah_config.ht_enable)
3015                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3016         else
3017                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3018
3019         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3020         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3021         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3022         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3023
3024         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3025                 pCap->total_queues =
3026                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3027         else
3028                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3029
3030         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3031                 pCap->keycache_size =
3032                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3033         else
3034                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3035
3036         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3037         pCap->num_mr_retries = 4;
3038         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3039
3040         if (AR_SREV_9280_10_OR_LATER(ah))
3041                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3042         else
3043                 pCap->num_gpio_pins = AR_NUM_GPIO;
3044
3045         if (AR_SREV_9280_10_OR_LATER(ah)) {
3046                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3047                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3048         } else {
3049                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3050                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3051         }
3052
3053         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3054                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3055                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3056         } else {
3057                 pCap->rts_aggr_limit = (8 * 1024);
3058         }
3059
3060         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3061
3062         ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3063         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3064                 ahp->ah_gpioSelect =
3065                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3066                 ahp->ah_polarity =
3067                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3068
3069                 ath9k_hw_setcapability(ah, ATH9K_CAP_RFSILENT, 1, true,
3070                                        NULL);
3071                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3072         }
3073
3074         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3075             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3076             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3077             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3078             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3079                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3080         else
3081                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3082
3083         if (AR_SREV_9280(ah))
3084                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3085         else
3086                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3087
3088         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3089                 pCap->reg_cap =
3090                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3091                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3092                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3093                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3094         } else {
3095                 pCap->reg_cap =
3096                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3097                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3098         }
3099
3100         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3101
3102         pCap->num_antcfg_5ghz =
3103                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3104         pCap->num_antcfg_2ghz =
3105                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3106
3107         return true;
3108 }
3109
3110 static void ar5416DisablePciePhy(struct ath_hal *ah)
3111 {
3112         if (!AR_SREV_9100(ah))
3113                 return;
3114
3115         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3116         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3117         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3118         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3119         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3120         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3121         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3122         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3123         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3124
3125         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3126 }
3127
3128 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3129 {
3130         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3131         if (setChip) {
3132                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3133                             AR_RTC_FORCE_WAKE_EN);
3134                 if (!AR_SREV_9100(ah))
3135                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3136
3137                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3138                             AR_RTC_RESET_EN);
3139         }
3140 }
3141
3142 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3143 {
3144         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3145         if (setChip) {
3146                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3147
3148                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3149                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3150                                   AR_RTC_FORCE_WAKE_ON_INT);
3151                 } else {
3152                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3153                                     AR_RTC_FORCE_WAKE_EN);
3154                 }
3155         }
3156 }
3157
3158 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3159                                      int setChip)
3160 {
3161         u32 val;
3162         int i;
3163
3164         if (setChip) {
3165                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3166                     AR_RTC_STATUS_SHUTDOWN) {
3167                         if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3168                             != true) {
3169                                 return false;
3170                         }
3171                 }
3172                 if (AR_SREV_9100(ah))
3173                         REG_SET_BIT(ah, AR_RTC_RESET,
3174                                        AR_RTC_RESET_EN);
3175
3176                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3177                             AR_RTC_FORCE_WAKE_EN);
3178                 udelay(50);
3179
3180                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3181                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3182                         if (val == AR_RTC_STATUS_ON)
3183                                 break;
3184                         udelay(50);
3185                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3186                                        AR_RTC_FORCE_WAKE_EN);
3187                 }
3188                 if (i == 0) {
3189                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3190                                  "%s: Failed to wakeup in %uus\n",
3191                                  __func__, POWER_UP_TIME / 20);
3192                         return false;
3193                 }
3194         }
3195
3196         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3197         return true;
3198 }
3199
3200 bool ath9k_hw_setpower(struct ath_hal *ah,
3201                        enum ath9k_power_mode mode)
3202 {
3203         struct ath_hal_5416 *ahp = AH5416(ah);
3204         static const char *modes[] = {
3205                 "AWAKE",
3206                 "FULL-SLEEP",
3207                 "NETWORK SLEEP",
3208                 "UNDEFINED"
3209         };
3210         int status = true, setChip = true;
3211
3212         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3213                  modes[ahp->ah_powerMode], modes[mode],
3214                  setChip ? "set chip " : "");
3215
3216         switch (mode) {
3217         case ATH9K_PM_AWAKE:
3218                 status = ath9k_hw_set_power_awake(ah, setChip);
3219                 break;
3220         case ATH9K_PM_FULL_SLEEP:
3221                 ath9k_set_power_sleep(ah, setChip);
3222                 ahp->ah_chipFullSleep = true;
3223                 break;
3224         case ATH9K_PM_NETWORK_SLEEP:
3225                 ath9k_set_power_network_sleep(ah, setChip);
3226                 break;
3227         default:
3228                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3229                          "%s: unknown power mode %u\n", __func__, mode);
3230                 return false;
3231         }
3232         ahp->ah_powerMode = mode;
3233         return status;
3234 }
3235
3236 static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3237                                           struct ath_softc *sc,
3238                                           void __iomem *mem,
3239                                           int *status)
3240 {
3241         struct ath_hal_5416 *ahp;
3242         struct ath_hal *ah;
3243         int ecode;
3244 #ifndef CONFIG_SLOW_ANT_DIV
3245         u32 i;
3246         u32 j;
3247 #endif
3248
3249         ahp = ath9k_hw_newstate(devid, sc, mem, status);
3250         if (ahp == NULL)
3251                 return NULL;
3252
3253         ah = &ahp->ah;
3254
3255         ath9k_hw_set_defaults(ah);
3256
3257         if (ah->ah_config.intr_mitigation != 0)
3258                 ahp->ah_intrMitigation = true;
3259
3260         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3261                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
3262                          __func__);
3263                 ecode = -EIO;
3264                 goto bad;
3265         }
3266
3267         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3268                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
3269                          __func__);
3270                 ecode = -EIO;
3271                 goto bad;
3272         }
3273
3274         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
3275                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3276                         ah->ah_config.serialize_regmode =
3277                                 SER_REG_MODE_ON;
3278                 } else {
3279                         ah->ah_config.serialize_regmode =
3280                                 SER_REG_MODE_OFF;
3281                 }
3282         }
3283         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3284                 "%s: serialize_regmode is %d\n",
3285                 __func__, ah->ah_config.serialize_regmode);
3286
3287         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3288             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3289             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3290             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3291                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3292                          "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3293                          "this driver\n", __func__,
3294                          ah->ah_macVersion, ah->ah_macRev);
3295                 ecode = -EOPNOTSUPP;
3296                 goto bad;
3297         }
3298
3299         if (AR_SREV_9100(ah)) {
3300                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3301                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3302                 ah->ah_isPciExpress = false;
3303         }
3304         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3305
3306         if (AR_SREV_9160_10_OR_LATER(ah)) {
3307                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3308                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3309                         ahp->ah_adcGainCalData.calData =
3310                                 &adc_gain_cal_single_sample;
3311                         ahp->ah_adcDcCalData.calData =
3312                                 &adc_dc_cal_single_sample;
3313                         ahp->ah_adcDcCalInitData.calData =
3314                                 &adc_init_dc_cal;
3315                 } else {
3316                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3317                         ahp->ah_adcGainCalData.calData =
3318                                 &adc_gain_cal_multi_sample;
3319                         ahp->ah_adcDcCalData.calData =
3320                                 &adc_dc_cal_multi_sample;
3321                         ahp->ah_adcDcCalInitData.calData =
3322                                 &adc_init_dc_cal;
3323                 }
3324                 ahp->ah_suppCals =
3325                         ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3326         }
3327
3328         if (AR_SREV_9160(ah)) {
3329                 ah->ah_config.enable_ani = 1;
3330                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
3331                                         ATH9K_ANI_FIRSTEP_LEVEL);
3332         } else {
3333                 ahp->ah_ani_function = ATH9K_ANI_ALL;
3334                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3335                         ahp->ah_ani_function &=
3336                                 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3337                 }
3338         }
3339
3340         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3341                  "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3342                  ah->ah_macVersion, ah->ah_macRev);
3343
3344         if (AR_SREV_9280_20_OR_LATER(ah)) {
3345                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3346                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
3347                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3348                                ARRAY_SIZE(ar9280Common_9280_2), 2);
3349
3350                 if (ah->ah_config.pcie_clock_req) {
3351                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3352                                        ar9280PciePhy_clkreq_off_L1_9280,
3353                                        ARRAY_SIZE
3354                                        (ar9280PciePhy_clkreq_off_L1_9280),
3355                                        2);
3356                 } else {
3357                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3358                                        ar9280PciePhy_clkreq_always_on_L1_9280,
3359                                        ARRAY_SIZE
3360                                        (ar9280PciePhy_clkreq_always_on_L1_9280),
3361                                        2);
3362                 }
3363                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3364                                ar9280Modes_fast_clock_9280_2,
3365                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3366                                3);
3367         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3368                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3369                                ARRAY_SIZE(ar9280Modes_9280), 6);
3370                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3371                                ARRAY_SIZE(ar9280Common_9280), 2);
3372         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3373                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3374                                ARRAY_SIZE(ar5416Modes_9160), 6);
3375                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3376                                ARRAY_SIZE(ar5416Common_9160), 2);
3377                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3378                                ARRAY_SIZE(ar5416Bank0_9160), 2);
3379                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3380                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3381                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3382                                ARRAY_SIZE(ar5416Bank1_9160), 2);
3383                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3384                                ARRAY_SIZE(ar5416Bank2_9160), 2);
3385                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3386                                ARRAY_SIZE(ar5416Bank3_9160), 3);
3387                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3388                                ARRAY_SIZE(ar5416Bank6_9160), 3);
3389                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3390                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3391                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3392                                ARRAY_SIZE(ar5416Bank7_9160), 2);
3393                 if (AR_SREV_9160_11(ah)) {
3394                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
3395                                        ar5416Addac_91601_1,
3396                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
3397                 } else {
3398                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3399                                        ARRAY_SIZE(ar5416Addac_9160), 2);
3400                 }
3401         } else if (AR_SREV_9100_OR_LATER(ah)) {
3402                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3403                                ARRAY_SIZE(ar5416Modes_9100), 6);
3404                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3405                                ARRAY_SIZE(ar5416Common_9100), 2);
3406                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3407                                ARRAY_SIZE(ar5416Bank0_9100), 2);
3408                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3409                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3410                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3411                                ARRAY_SIZE(ar5416Bank1_9100), 2);
3412                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3413                                ARRAY_SIZE(ar5416Bank2_9100), 2);
3414                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3415                                ARRAY_SIZE(ar5416Bank3_9100), 3);
3416                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3417                                ARRAY_SIZE(ar5416Bank6_9100), 3);
3418                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3419                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3420                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3421                                ARRAY_SIZE(ar5416Bank7_9100), 2);
3422                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3423                                ARRAY_SIZE(ar5416Addac_9100), 2);
3424         } else {
3425                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3426                                ARRAY_SIZE(ar5416Modes), 6);
3427                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3428                                ARRAY_SIZE(ar5416Common), 2);
3429                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3430                                ARRAY_SIZE(ar5416Bank0), 2);
3431                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3432                                ARRAY_SIZE(ar5416BB_RfGain), 3);
3433                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3434                                ARRAY_SIZE(ar5416Bank1), 2);
3435                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3436                                ARRAY_SIZE(ar5416Bank2), 2);
3437                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3438                                ARRAY_SIZE(ar5416Bank3), 3);
3439                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3440                                ARRAY_SIZE(ar5416Bank6), 3);
3441                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3442                                ARRAY_SIZE(ar5416Bank6TPC), 3);
3443                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3444                                ARRAY_SIZE(ar5416Bank7), 2);
3445                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3446                                ARRAY_SIZE(ar5416Addac), 2);
3447         }
3448
3449         if (ah->ah_isPciExpress)
3450                 ath9k_hw_configpcipowersave(ah, 0);
3451         else
3452                 ar5416DisablePciePhy(ah);
3453
3454         ecode = ath9k_hw_post_attach(ah);
3455         if (ecode != 0)
3456                 goto bad;
3457
3458 #ifndef CONFIG_SLOW_ANT_DIV
3459         if (ah->ah_devid == AR9280_DEVID_PCI) {
3460                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3461                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
3462
3463                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3464                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
3465
3466                                 INI_RA(&ahp->ah_iniModes, i, j) =
3467                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3468                                                            reg, val);
3469                         }
3470                 }
3471         }
3472 #endif
3473
3474         if (!ath9k_hw_fill_cap_info(ah)) {
3475                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3476                          "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3477                 ecode = -EINVAL;
3478                 goto bad;
3479         }
3480
3481         ecode = ath9k_hw_init_macaddr(ah);
3482         if (ecode != 0) {
3483                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3484                          "%s: failed initializing mac address\n",
3485                          __func__);
3486                 goto bad;
3487         }
3488
3489         if (AR_SREV_9285(ah))
3490                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3491         else
3492                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3493
3494 #ifndef ATH_NF_PER_CHAN
3495
3496         ath9k_init_nfcal_hist_buffer(ah);
3497 #endif
3498
3499         return ah;
3500
3501 bad:
3502         if (ahp)
3503                 ath9k_hw_detach((struct ath_hal *) ahp);
3504         if (status)
3505                 *status = ecode;
3506         return NULL;
3507 }
3508
3509 void ath9k_hw_detach(struct ath_hal *ah)
3510 {
3511         if (!AR_SREV_9100(ah))
3512                 ath9k_hw_ani_detach(ah);
3513         ath9k_hw_rfdetach(ah);
3514
3515         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3516         kfree(ah);
3517 }
3518
3519 bool ath9k_get_channel_edges(struct ath_hal *ah,
3520                              u16 flags, u16 *low,
3521                              u16 *high)
3522 {
3523         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3524
3525         if (flags & CHANNEL_5GHZ) {
3526                 *low = pCap->low_5ghz_chan;
3527                 *high = pCap->high_5ghz_chan;
3528                 return true;
3529         }
3530         if ((flags & CHANNEL_2GHZ)) {
3531                 *low = pCap->low_2ghz_chan;
3532                 *high = pCap->high_2ghz_chan;
3533
3534                 return true;
3535         }
3536         return false;
3537 }
3538
3539 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
3540                                            u8 pwrMax,
3541                                            u8 *pPwrList,
3542                                            u8 *pVpdList,
3543                                            u16
3544                                            numIntercepts,
3545                                            u8 *pRetVpdList)
3546 {
3547         u16 i, k;
3548         u8 currPwr = pwrMin;
3549         u16 idxL = 0, idxR = 0;
3550
3551         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3552                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3553                                                numIntercepts, &(idxL),
3554                                                &(idxR));
3555                 if (idxR < 1)
3556                         idxR = 1;
3557                 if (idxL == numIntercepts - 1)
3558                         idxL = (u16) (numIntercepts - 2);
3559                 if (pPwrList[idxL] == pPwrList[idxR])
3560                         k = pVpdList[idxL];
3561                 else
3562                         k = (u16) (((currPwr -
3563                                            pPwrList[idxL]) *
3564                                           pVpdList[idxR] +
3565                                           (pPwrList[idxR] -
3566                                            currPwr) * pVpdList[idxL]) /
3567                                          (pPwrList[idxR] -
3568                                           pPwrList[idxL]));
3569                 pRetVpdList[i] = (u8) k;
3570                 currPwr += 2;
3571         }
3572
3573         return true;
3574 }
3575
3576 static inline void
3577 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3578                                     struct ath9k_channel *chan,
3579                                     struct cal_data_per_freq *pRawDataSet,
3580                                     u8 *bChans,
3581                                     u16 availPiers,
3582                                     u16 tPdGainOverlap,
3583                                     int16_t *pMinCalPower,
3584                                     u16 *pPdGainBoundaries,
3585                                     u8 *pPDADCValues,
3586                                     u16 numXpdGains)
3587 {
3588         int i, j, k;
3589         int16_t ss;
3590         u16 idxL = 0, idxR = 0, numPiers;
3591         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3592                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3593         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3594                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3595         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3596                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3597
3598         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3599         u8 minPwrT4[AR5416_NUM_PD_GAINS];
3600         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3601         int16_t vpdStep;
3602         int16_t tmpVal;
3603         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3604         bool match;
3605         int16_t minDelta = 0;
3606         struct chan_centers centers;
3607
3608         ath9k_hw_get_channel_centers(ah, chan, &centers);
3609
3610         for (numPiers = 0; numPiers < availPiers; numPiers++) {
3611                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3612                         break;
3613         }
3614
3615         match = ath9k_hw_get_lower_upper_index((u8)
3616                                                FREQ2FBIN(centers.
3617                                                          synth_center,
3618                                                          IS_CHAN_2GHZ
3619                                                          (chan)), bChans,
3620                                                numPiers, &idxL, &idxR);
3621
3622         if (match) {
3623                 for (i = 0; i < numXpdGains; i++) {
3624                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3625                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3626                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3627                                                 pRawDataSet[idxL].
3628                                                 pwrPdg[i],
3629                                                 pRawDataSet[idxL].
3630                                                 vpdPdg[i],
3631                                                 AR5416_PD_GAIN_ICEPTS,
3632                                                 vpdTableI[i]);
3633                 }
3634         } else {
3635                 for (i = 0; i < numXpdGains; i++) {
3636                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
3637                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
3638                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
3639                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
3640
3641                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3642
3643                         maxPwrT4[i] =
3644                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3645                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3646
3647
3648                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3649                                                 pPwrL, pVpdL,
3650                                                 AR5416_PD_GAIN_ICEPTS,
3651                                                 vpdTableL[i]);
3652                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3653                                                 pPwrR, pVpdR,
3654                                                 AR5416_PD_GAIN_ICEPTS,
3655                                                 vpdTableR[i]);
3656
3657                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3658                                 vpdTableI[i][j] =
3659                                         (u8) (ath9k_hw_interpolate
3660                                                     ((u16)
3661                                                      FREQ2FBIN(centers.
3662                                                                synth_center,
3663                                                                IS_CHAN_2GHZ
3664                                                                (chan)),
3665                                                      bChans[idxL],
3666                                                      bChans[idxR], vpdTableL[i]
3667                                                      [j], vpdTableR[i]
3668                                                      [j]));
3669                         }
3670                 }
3671         }
3672
3673         *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3674
3675         k = 0;
3676         for (i = 0; i < numXpdGains; i++) {
3677                 if (i == (numXpdGains - 1))
3678                         pPdGainBoundaries[i] =
3679                                 (u16) (maxPwrT4[i] / 2);
3680                 else
3681                         pPdGainBoundaries[i] =
3682                                 (u16) ((maxPwrT4[i] +
3683                                               minPwrT4[i + 1]) / 4);
3684
3685                 pPdGainBoundaries[i] =
3686                         min((u16) AR5416_MAX_RATE_POWER,
3687                             pPdGainBoundaries[i]);
3688
3689                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3690                         minDelta = pPdGainBoundaries[0] - 23;
3691                         pPdGainBoundaries[0] = 23;
3692                 } else {
3693                         minDelta = 0;
3694                 }
3695
3696                 if (i == 0) {
3697                         if (AR_SREV_9280_10_OR_LATER(ah))
3698                                 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3699                         else
3700                                 ss = 0;
3701                 } else {
3702                         ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3703                                          (minPwrT4[i] / 2)) -
3704                                         tPdGainOverlap + 1 + minDelta);
3705                 }
3706                 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3707                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3708
3709                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3710                         tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3711                         pPDADCValues[k++] =
3712                                 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3713                         ss++;
3714                 }
3715
3716                 sizeCurrVpdTable =
3717                         (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3718                 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3719                                        (minPwrT4[i] / 2));
3720                 maxIndex = (tgtIndex <
3721                             sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3722
3723                 while ((ss < maxIndex)
3724                        && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3725                         pPDADCValues[k++] = vpdTableI[i][ss++];
3726                 }
3727
3728                 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3729                                      vpdTableI[i][sizeCurrVpdTable - 2]);
3730                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3731
3732                 if (tgtIndex > maxIndex) {
3733                         while ((ss <= tgtIndex)
3734                                && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3735                                 tmpVal = (int16_t) ((vpdTableI[i]
3736                                                      [sizeCurrVpdTable -
3737                                                       1] + (ss - maxIndex +
3738                                                             1) * vpdStep));
3739                                 pPDADCValues[k++] = (u8) ((tmpVal >
3740                                                  255) ? 255 : tmpVal);
3741                                 ss++;
3742                         }
3743                 }
3744         }
3745
3746         while (i < AR5416_PD_GAINS_IN_MASK) {
3747                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3748                 i++;
3749         }
3750
3751         while (k < AR5416_NUM_PDADC_VALUES) {
3752                 pPDADCValues[k] = pPDADCValues[k - 1];
3753                 k++;
3754         }
3755         return;
3756 }
3757
3758 static inline bool
3759 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3760                              struct ar5416_eeprom *pEepData,
3761                              struct ath9k_channel *chan,
3762                              int16_t *pTxPowerIndexOffset)
3763 {
3764         struct cal_data_per_freq *pRawDataset;
3765         u8 *pCalBChans = NULL;
3766         u16 pdGainOverlap_t2;
3767         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3768         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3769         u16 numPiers, i, j;
3770         int16_t tMinCalPower;
3771         u16 numXpdGain, xpdMask;
3772         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3773         u32 reg32, regOffset, regChainOffset;
3774         int16_t modalIdx;
3775         struct ath_hal_5416 *ahp = AH5416(ah);
3776
3777         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3778         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3779
3780         if ((pEepData->baseEepHeader.
3781              version & AR5416_EEP_VER_MINOR_MASK) >=
3782             AR5416_EEP_MINOR_VER_2) {
3783                 pdGainOverlap_t2 =
3784                         pEepData->modalHeader[modalIdx].pdGainOverlap;
3785         } else {
3786                 pdGainOverlap_t2 =
3787                         (u16) (MS
3788                                      (REG_READ(ah, AR_PHY_TPCRG5),
3789                                       AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3790         }
3791
3792         if (IS_CHAN_2GHZ(chan)) {
3793                 pCalBChans = pEepData->calFreqPier2G;
3794                 numPiers = AR5416_NUM_2G_CAL_PIERS;
3795         } else {
3796                 pCalBChans = pEepData->calFreqPier5G;
3797                 numPiers = AR5416_NUM_5G_CAL_PIERS;
3798         }
3799
3800         numXpdGain = 0;
3801
3802         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3803                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3804                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
3805                                 break;
3806                         xpdGainValues[numXpdGain] =
3807                                 (u16) (AR5416_PD_GAINS_IN_MASK - i);
3808                         numXpdGain++;
3809                 }
3810         }
3811
3812         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3813                       (numXpdGain - 1) & 0x3);
3814         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3815                       xpdGainValues[0]);
3816         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3817                       xpdGainValues[1]);
3818         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3819                       xpdGainValues[2]);
3820
3821         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3822                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3823                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3824                     && (i != 0)) {
3825                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3826                 } else
3827                         regChainOffset = i * 0x1000;
3828                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3829                         if (IS_CHAN_2GHZ(chan))
3830                                 pRawDataset = pEepData->calPierData2G[i];
3831                         else
3832                                 pRawDataset = pEepData->calPierData5G[i];
3833
3834                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3835                                                             pRawDataset,
3836                                                             pCalBChans,
3837                                                             numPiers,
3838                                                             pdGainOverlap_t2,
3839                                                             &tMinCalPower,
3840                                                             gainBoundaries,
3841                                                             pdadcValues,
3842                                                             numXpdGain);
3843
3844                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3845
3846                                 REG_WRITE(ah,
3847                                           AR_PHY_TPCRG5 + regChainOffset,
3848                                           SM(pdGainOverlap_t2,
3849                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3850                                           | SM(gainBoundaries[0],
3851                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3852                                           | SM(gainBoundaries[1],
3853                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3854                                           | SM(gainBoundaries[2],
3855                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3856                                           | SM(gainBoundaries[3],
3857                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3858                         }
3859
3860                         regOffset =
3861                                 AR_PHY_BASE + (672 << 2) + regChainOffset;
3862                         for (j = 0; j < 32; j++) {
3863                                 reg32 =
3864                                         ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3865                                         | ((pdadcValues[4 * j + 1] & 0xFF) <<
3866                                            8) | ((pdadcValues[4 * j + 2] &
3867                                                   0xFF) << 16) |
3868                                         ((pdadcValues[4 * j + 3] & 0xFF) <<
3869                                          24);
3870                                 REG_WRITE(ah, regOffset, reg32);
3871
3872                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3873                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
3874                                          i, regChainOffset, regOffset,
3875                                          reg32);
3876                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3877                                 "PDADC: Chain %d | PDADC %3d Value %3d | "
3878                                 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3879                                 "PDADC %3d Value %3d |\n",
3880                                          i, 4 * j, pdadcValues[4 * j],
3881                                          4 * j + 1, pdadcValues[4 * j + 1],
3882                                          4 * j + 2, pdadcValues[4 * j + 2],
3883                                          4 * j + 3,
3884                                          pdadcValues[4 * j + 3]);
3885
3886                                 regOffset += 4;
3887                         }
3888                 }
3889         }
3890         *pTxPowerIndexOffset = 0;
3891
3892         return true;
3893 }
3894
3895 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3896 {
3897         struct ath_hal_5416 *ahp = AH5416(ah);
3898         u8 i;
3899
3900         if (ah->ah_isPciExpress != true)
3901                 return;
3902
3903         if (ah->ah_config.pcie_powersave_enable == 2)
3904                 return;
3905
3906         if (restore)
3907                 return;
3908
3909         if (AR_SREV_9280_20_OR_LATER(ah)) {
3910                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3911                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3912                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3913                 }
3914                 udelay(1000);
3915         } else if (AR_SREV_9280(ah)
3916                    && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3917                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3918                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3919
3920                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3921                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3922                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3923
3924                 if (ah->ah_config.pcie_clock_req)
3925                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3926                 else
3927                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3928
3929                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3930                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3931                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3932
3933                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3934
3935                 udelay(1000);
3936         } else {
3937                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3938                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3939                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3940                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3941                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3942                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3943                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3944                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3945                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3946                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3947         }
3948
3949         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3950
3951         if (ah->ah_config.pcie_waen) {
3952                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3953         } else {
3954                 if (AR_SREV_9280(ah))
3955                         REG_WRITE(ah, AR_WA, 0x0040073f);
3956                 else
3957                         REG_WRITE(ah, AR_WA, 0x0000073f);
3958         }
3959 }
3960
3961 static inline void
3962 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3963                                   struct ath9k_channel *chan,
3964                                   struct cal_target_power_leg *powInfo,
3965                                   u16 numChannels,
3966                                   struct cal_target_power_leg *pNewPower,
3967                                   u16 numRates,
3968                                   bool isExtTarget)
3969 {
3970         u16 clo, chi;
3971         int i;
3972         int matchIndex = -1, lowIndex = -1;
3973         u16 freq;
3974         struct chan_centers centers;
3975
3976         ath9k_hw_get_channel_centers(ah, chan, &centers);
3977         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3978
3979         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
3980                 IS_CHAN_2GHZ(chan))) {
3981                 matchIndex = 0;
3982         } else {
3983                 for (i = 0; (i < numChannels)
3984                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
3985                         if (freq ==
3986                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
3987                                                IS_CHAN_2GHZ(chan))) {
3988                                 matchIndex = i;
3989                                 break;
3990                         } else if ((freq <
3991                                     ath9k_hw_fbin2freq(powInfo[i].bChannel,
3992                                                        IS_CHAN_2GHZ(chan)))
3993                                    && (freq >
3994                                        ath9k_hw_fbin2freq(powInfo[i - 1].
3995                                                           bChannel,
3996                                                           IS_CHAN_2GHZ
3997                                                           (chan)))) {
3998                                 lowIndex = i - 1;
3999                                 break;
4000                         }
4001                 }
4002                 if ((matchIndex == -1) && (lowIndex == -1))
4003                         matchIndex = i - 1;
4004         }
4005
4006         if (matchIndex != -1) {
4007                 *pNewPower = powInfo[matchIndex];
4008         } else {
4009                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4010                                          IS_CHAN_2GHZ(chan));
4011                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4012                                          IS_CHAN_2GHZ(chan));
4013
4014                 for (i = 0; i < numRates; i++) {
4015                         pNewPower->tPow2x[i] =
4016                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4017                                                                 powInfo
4018                                                                 [lowIndex].
4019                                                                 tPow2x[i],
4020                                                                 powInfo
4021                                                                 [lowIndex +
4022                                                                  1].tPow2x[i]);
4023                 }
4024         }
4025 }
4026
4027 static inline void
4028 ath9k_hw_get_target_powers(struct ath_hal *ah,
4029                            struct ath9k_channel *chan,
4030                            struct cal_target_power_ht *powInfo,
4031                            u16 numChannels,
4032                            struct cal_target_power_ht *pNewPower,
4033                            u16 numRates,
4034                            bool isHt40Target)
4035 {
4036         u16 clo, chi;
4037         int i;
4038         int matchIndex = -1, lowIndex = -1;
4039         u16 freq;
4040         struct chan_centers centers;
4041
4042         ath9k_hw_get_channel_centers(ah, chan, &centers);
4043         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4044
4045         if (freq <=
4046                 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4047                 matchIndex = 0;
4048         } else {
4049                 for (i = 0; (i < numChannels)
4050                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4051                         if (freq ==
4052                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
4053                                                IS_CHAN_2GHZ(chan))) {
4054                                 matchIndex = i;
4055                                 break;
4056                         } else
4057                                 if ((freq <
4058                                      ath9k_hw_fbin2freq(powInfo[i].bChannel,
4059                                                         IS_CHAN_2GHZ(chan)))
4060                                     && (freq >
4061                                         ath9k_hw_fbin2freq(powInfo[i - 1].
4062                                                            bChannel,
4063                                                            IS_CHAN_2GHZ
4064                                                            (chan)))) {
4065                                         lowIndex = i - 1;
4066                                         break;
4067                                 }
4068                 }
4069                 if ((matchIndex == -1) && (lowIndex == -1))
4070                         matchIndex = i - 1;
4071         }
4072
4073         if (matchIndex != -1) {
4074                 *pNewPower = powInfo[matchIndex];
4075         } else {
4076                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4077                                          IS_CHAN_2GHZ(chan));
4078                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4079                                          IS_CHAN_2GHZ(chan));
4080
4081                 for (i = 0; i < numRates; i++) {
4082                         pNewPower->tPow2x[i] =
4083                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4084                                                                 powInfo
4085                                                                 [lowIndex].
4086                                                                 tPow2x[i],
4087                                                                 powInfo
4088                                                                 [lowIndex +
4089                                                                  1].tPow2x[i]);
4090                 }
4091         }
4092 }
4093
4094 static inline u16
4095 ath9k_hw_get_max_edge_power(u16 freq,
4096                             struct cal_ctl_edges *pRdEdgesPower,
4097                             bool is2GHz)
4098 {
4099         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4100         int i;
4101
4102         for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4103              && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4104                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4105                                                is2GHz)) {
4106                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4107                         break;
4108                 } else if ((i > 0)
4109                            && (freq <
4110                                ath9k_hw_fbin2freq(pRdEdgesPower[i].
4111                                                   bChannel, is2GHz))) {
4112                         if (ath9k_hw_fbin2freq
4113                             (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4114                             && pRdEdgesPower[i - 1].flag) {
4115                                 twiceMaxEdgePower =
4116                                         pRdEdgesPower[i - 1].tPower;
4117                         }
4118                         break;
4119                 }
4120         }
4121         return twiceMaxEdgePower;
4122 }
4123
4124 static inline bool
4125 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4126                                   struct ar5416_eeprom *pEepData,
4127                                   struct ath9k_channel *chan,
4128                                   int16_t *ratesArray,
4129                                   u16 cfgCtl,
4130                                   u8 AntennaReduction,
4131                                   u8 twiceMaxRegulatoryPower,
4132                                   u8 powerLimit)
4133 {
4134         u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4135         static const u16 tpScaleReductionTable[5] =
4136                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4137
4138         int i;
4139         int8_t twiceLargestAntenna;
4140         struct cal_ctl_data *rep;
4141         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4142                 0, { 0, 0, 0, 0}
4143         };
4144         struct cal_target_power_leg targetPowerOfdmExt = {
4145                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4146                 0, { 0, 0, 0, 0 }
4147         };
4148         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4149                 0, {0, 0, 0, 0}
4150         };
4151         u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4152         u16 ctlModesFor11a[] =
4153                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4154         u16 ctlModesFor11g[] =
4155                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4156                   CTL_2GHT40
4157                 };
4158         u16 numCtlModes, *pCtlMode, ctlMode, freq;
4159         struct chan_centers centers;
4160         int tx_chainmask;
4161         u8 twiceMinEdgePower;
4162         struct ath_hal_5416 *ahp = AH5416(ah);
4163
4164         tx_chainmask = ahp->ah_txchainmask;
4165
4166         ath9k_hw_get_channel_centers(ah, chan, &centers);
4167
4168         twiceLargestAntenna = max(
4169                 pEepData->modalHeader
4170                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4171                 pEepData->modalHeader
4172                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4173
4174         twiceLargestAntenna = max((u8) twiceLargestAntenna,
4175                 pEepData->modalHeader
4176                         [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4177
4178         twiceLargestAntenna =
4179                 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4180
4181         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4182
4183         if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
4184                 maxRegAllowedPower -=
4185                         (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4186         }
4187
4188         scaledPower = min(powerLimit, maxRegAllowedPower);
4189
4190         switch (ar5416_get_ntxchains(tx_chainmask)) {
4191         case 1:
4192                 break;
4193         case 2:
4194                 scaledPower -=
4195                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4196                         pwrDecreaseFor2Chain;
4197                 break;
4198         case 3:
4199                 scaledPower -=
4200                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4201                         pwrDecreaseFor3Chain;
4202                 break;
4203         }
4204
4205         scaledPower = max(0, (int32_t) scaledPower);
4206
4207         if (IS_CHAN_2GHZ(chan)) {
4208                 numCtlModes =
4209                         ARRAY_SIZE(ctlModesFor11g) -
4210                         SUB_NUM_CTL_MODES_AT_2G_40;
4211                 pCtlMode = ctlModesFor11g;
4212
4213                 ath9k_hw_get_legacy_target_powers(ah, chan,
4214                         pEepData->
4215                         calTargetPowerCck,
4216                         AR5416_NUM_2G_CCK_TARGET_POWERS,
4217                         &targetPowerCck, 4,
4218                         false);
4219                 ath9k_hw_get_legacy_target_powers(ah, chan,
4220                         pEepData->
4221                         calTargetPower2G,
4222                         AR5416_NUM_2G_20_TARGET_POWERS,
4223                         &targetPowerOfdm, 4,
4224                         false);
4225                 ath9k_hw_get_target_powers(ah, chan,
4226                         pEepData->calTargetPower2GHT20,
4227                         AR5416_NUM_2G_20_TARGET_POWERS,
4228                         &targetPowerHt20, 8, false);
4229
4230                 if (IS_CHAN_HT40(chan)) {
4231                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4232                         ath9k_hw_get_target_powers(ah, chan,
4233                                 pEepData->
4234                                 calTargetPower2GHT40,
4235                                 AR5416_NUM_2G_40_TARGET_POWERS,
4236                                 &targetPowerHt40, 8,
4237                                 true);
4238                         ath9k_hw_get_legacy_target_powers(ah, chan,
4239                                 pEepData->
4240                                 calTargetPowerCck,
4241                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
4242                                 &targetPowerCckExt,
4243                                 4, true);
4244                         ath9k_hw_get_legacy_target_powers(ah, chan,
4245                                 pEepData->
4246                                 calTargetPower2G,
4247                                 AR5416_NUM_2G_20_TARGET_POWERS,
4248                                 &targetPowerOfdmExt,
4249                                 4, true);
4250                 }
4251         } else {
4252
4253                 numCtlModes =
4254                         ARRAY_SIZE(ctlModesFor11a) -
4255                         SUB_NUM_CTL_MODES_AT_5G_40;
4256                 pCtlMode = ctlModesFor11a;
4257
4258                 ath9k_hw_get_legacy_target_powers(ah, chan,
4259                         pEepData->
4260                         calTargetPower5G,
4261                         AR5416_NUM_5G_20_TARGET_POWERS,
4262                         &targetPowerOfdm, 4,
4263                         false);
4264                 ath9k_hw_get_target_powers(ah, chan,
4265                         pEepData->calTargetPower5GHT20,
4266                         AR5416_NUM_5G_20_TARGET_POWERS,
4267                         &targetPowerHt20, 8, false);
4268
4269                 if (IS_CHAN_HT40(chan)) {
4270                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4271                         ath9k_hw_get_target_powers(ah, chan,
4272                                 pEepData->
4273                                 calTargetPower5GHT40,
4274                                 AR5416_NUM_5G_40_TARGET_POWERS,
4275                                 &targetPowerHt40, 8,
4276                                 true);
4277                         ath9k_hw_get_legacy_target_powers(ah, chan,
4278                                 pEepData->
4279                                 calTargetPower5G,
4280                                 AR5416_NUM_5G_20_TARGET_POWERS,
4281                                 &targetPowerOfdmExt,
4282                                 4, true);
4283                 }
4284         }
4285
4286         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4287                 bool isHt40CtlMode =
4288                         (pCtlMode[ctlMode] == CTL_5GHT40)
4289                         || (pCtlMode[ctlMode] == CTL_2GHT40);
4290                 if (isHt40CtlMode)
4291                         freq = centers.synth_center;
4292                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4293                         freq = centers.ext_center;
4294                 else
4295                         freq = centers.ctl_center;
4296
4297                 if (ar5416_get_eep_ver(ahp) == 14
4298                     && ar5416_get_eep_rev(ahp) <= 2)
4299                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4300
4301                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4302                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4303                         "EXT_ADDITIVE %d\n",
4304                          ctlMode, numCtlModes, isHt40CtlMode,
4305                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
4306
4307                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4308                      i++) {
4309                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4310                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4311                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4312                                 "chan %d\n",
4313                                 i, cfgCtl, pCtlMode[ctlMode],
4314                                 pEepData->ctlIndex[i], chan->channel);
4315
4316                         if ((((cfgCtl & ~CTL_MODE_M) |
4317                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4318                              pEepData->ctlIndex[i])
4319                             ||
4320                             (((cfgCtl & ~CTL_MODE_M) |
4321                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4322                              ((pEepData->
4323                                ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4324                                 rep = &(pEepData->ctlData[i]);
4325
4326                                 twiceMinEdgePower =
4327                                         ath9k_hw_get_max_edge_power(freq,
4328                                                 rep->
4329                                                 ctlEdges
4330                                                 [ar5416_get_ntxchains
4331                                                 (tx_chainmask)
4332                                                 - 1],
4333                                                 IS_CHAN_2GHZ
4334                                                 (chan));
4335
4336                                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4337                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
4338                                         "2xMinEdge %d chainmask %d chains %d\n",
4339                                          i, freq, IS_CHAN_2GHZ(chan),
4340                                          twiceMinEdgePower, tx_chainmask,
4341                                          ar5416_get_ntxchains
4342                                          (tx_chainmask));
4343                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4344                                         twiceMaxEdgePower =
4345                                                 min(twiceMaxEdgePower,
4346                                                     twiceMinEdgePower);
4347                                 } else {
4348                                         twiceMaxEdgePower =
4349                                                 twiceMinEdgePower;
4350                                         break;
4351                                 }
4352                         }
4353                 }
4354
4355                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4356
4357                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4358                                 "    SEL-Min ctlMode %d pCtlMode %d "
4359                                 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4360                          ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4361                          scaledPower, minCtlPower);
4362
4363                 switch (pCtlMode[ctlMode]) {
4364                 case CTL_11B:
4365                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4366                              i++) {
4367                                 targetPowerCck.tPow2x[i] =
4368                                         min(targetPowerCck.tPow2x[i],
4369                                             minCtlPower);
4370                         }
4371                         break;
4372                 case CTL_11A:
4373                 case CTL_11G:
4374                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4375                              i++) {
4376                                 targetPowerOfdm.tPow2x[i] =
4377                                         min(targetPowerOfdm.tPow2x[i],
4378                                             minCtlPower);
4379                         }
4380                         break;
4381                 case CTL_5GHT20:
4382                 case CTL_2GHT20:
4383                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4384                              i++) {
4385                                 targetPowerHt20.tPow2x[i] =
4386                                         min(targetPowerHt20.tPow2x[i],
4387                                             minCtlPower);
4388                         }
4389                         break;
4390                 case CTL_11B_EXT:
4391                         targetPowerCckExt.tPow2x[0] =
4392                                 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4393                         break;
4394                 case CTL_11A_EXT:
4395                 case CTL_11G_EXT:
4396                         targetPowerOfdmExt.tPow2x[0] =
4397                                 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4398                         break;
4399                 case CTL_5GHT40:
4400                 case CTL_2GHT40:
4401                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4402                              i++) {
4403                                 targetPowerHt40.tPow2x[i] =
4404                                         min(targetPowerHt40.tPow2x[i],
4405                                             minCtlPower);
4406                         }
4407                         break;
4408                 default:
4409                         break;
4410                 }
4411         }
4412
4413         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4414                 ratesArray[rate18mb] = ratesArray[rate24mb] =
4415                 targetPowerOfdm.tPow2x[0];
4416         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4417         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4418         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4419         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4420
4421         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4422                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4423
4424         if (IS_CHAN_2GHZ(chan)) {
4425                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4426                 ratesArray[rate2s] = ratesArray[rate2l] =
4427                         targetPowerCck.tPow2x[1];
4428                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4429                         targetPowerCck.tPow2x[2];
4430                 ;
4431                 ratesArray[rate11s] = ratesArray[rate11l] =
4432                         targetPowerCck.tPow2x[3];
4433                 ;
4434         }
4435         if (IS_CHAN_HT40(chan)) {
4436                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4437                         ratesArray[rateHt40_0 + i] =
4438                                 targetPowerHt40.tPow2x[i];
4439                 }
4440                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4441                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4442                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4443                 if (IS_CHAN_2GHZ(chan)) {
4444                         ratesArray[rateExtCck] =
4445                                 targetPowerCckExt.tPow2x[0];
4446                 }
4447         }
4448         return true;
4449 }
4450
4451 static int
4452 ath9k_hw_set_txpower(struct ath_hal *ah,
4453                      struct ar5416_eeprom *pEepData,
4454                      struct ath9k_channel *chan,
4455                      u16 cfgCtl,
4456                      u8 twiceAntennaReduction,
4457                      u8 twiceMaxRegulatoryPower,
4458                      u8 powerLimit)
4459 {
4460         struct modal_eep_header *pModal =
4461                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4462         int16_t ratesArray[Ar5416RateSize];
4463         int16_t txPowerIndexOffset = 0;
4464         u8 ht40PowerIncForPdadc = 2;
4465         int i;
4466
4467         memset(ratesArray, 0, sizeof(ratesArray));
4468
4469         if ((pEepData->baseEepHeader.
4470              version & AR5416_EEP_VER_MINOR_MASK) >=
4471             AR5416_EEP_MINOR_VER_2) {
4472                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4473         }
4474
4475         if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4476                                                &ratesArray[0], cfgCtl,
4477                                                twiceAntennaReduction,
4478                                                twiceMaxRegulatoryPower,
4479                                                powerLimit)) {
4480                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4481                         "ath9k_hw_set_txpower: unable to set "
4482                         "tx power per rate table\n");
4483                 return -EIO;
4484         }
4485
4486         if (!ath9k_hw_set_power_cal_table
4487             (ah, pEepData, chan, &txPowerIndexOffset)) {
4488                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4489                          "ath9k_hw_set_txpower: unable to set power table\n");
4490                 return -EIO;
4491         }
4492
4493         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4494                 ratesArray[i] =
4495                         (int16_t) (txPowerIndexOffset + ratesArray[i]);
4496                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4497                         ratesArray[i] = AR5416_MAX_RATE_POWER;
4498         }
4499
4500         if (AR_SREV_9280_10_OR_LATER(ah)) {
4501                 for (i = 0; i < Ar5416RateSize; i++)
4502                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4503         }
4504
4505         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4506                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
4507                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4508                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4509                   | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4510                 );
4511         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4512                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
4513                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4514                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4515                   | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4516                 );
4517
4518         if (IS_CHAN_2GHZ(chan)) {
4519                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4520                           ATH9K_POW_SM(ratesArray[rate2s], 24)
4521                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
4522                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
4523                           | ATH9K_POW_SM(ratesArray[rate1l], 0)
4524                         );
4525                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4526                           ATH9K_POW_SM(ratesArray[rate11s], 24)
4527                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
4528                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4529                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4530                         );
4531         }
4532
4533         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4534                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4535                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4536                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4537                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4538                 );
4539         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4540                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4541                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4542                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4543                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4544                 );
4545
4546         if (IS_CHAN_HT40(chan)) {
4547                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4548                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
4549                                        ht40PowerIncForPdadc, 24)
4550                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4551                                          ht40PowerIncForPdadc, 16)
4552                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4553                                          ht40PowerIncForPdadc, 8)
4554                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4555                                          ht40PowerIncForPdadc, 0)
4556                         );
4557                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4558                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
4559                                        ht40PowerIncForPdadc, 24)
4560                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4561                                          ht40PowerIncForPdadc, 16)
4562                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4563                                          ht40PowerIncForPdadc, 8)
4564                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4565                                          ht40PowerIncForPdadc, 0)
4566                         );
4567
4568                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4569                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4570                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4571                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4572                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4573                         );
4574         }
4575
4576         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4577                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4578                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4579                 );
4580
4581         i = rate6mb;
4582         if (IS_CHAN_HT40(chan))
4583                 i = rateHt40_0;
4584         else if (IS_CHAN_HT20(chan))
4585                 i = rateHt20_0;
4586
4587         if (AR_SREV_9280_10_OR_LATER(ah))
4588                 ah->ah_maxPowerLevel =
4589                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4590         else
4591                 ah->ah_maxPowerLevel = ratesArray[i];
4592
4593         return 0;
4594 }
4595
4596 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4597                                                  u32 coef_scaled,
4598                                                  u32 *coef_mantissa,
4599                                                  u32 *coef_exponent)
4600 {
4601         u32 coef_exp, coef_man;
4602
4603         for (coef_exp = 31; coef_exp > 0; coef_exp--)
4604                 if ((coef_scaled >> coef_exp) & 0x1)
4605                         break;
4606
4607         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4608
4609         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4610
4611         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4612         *coef_exponent = coef_exp - 16;
4613 }
4614
4615 static void
4616 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4617                          struct ath9k_channel *chan)
4618 {
4619         u32 coef_scaled, ds_coef_exp, ds_coef_man;
4620         u32 clockMhzScaled = 0x64000000;
4621         struct chan_centers centers;
4622
4623         if (IS_CHAN_HALF_RATE(chan))
4624                 clockMhzScaled = clockMhzScaled >> 1;
4625         else if (IS_CHAN_QUARTER_RATE(chan))
4626                 clockMhzScaled = clockMhzScaled >> 2;
4627
4628         ath9k_hw_get_channel_centers(ah, chan, &centers);
4629         coef_scaled = clockMhzScaled / centers.synth_center;
4630
4631         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4632                                       &ds_coef_exp);
4633
4634         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4635                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4636         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4637                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4638
4639         coef_scaled = (9 * coef_scaled) / 10;
4640
4641         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4642                                       &ds_coef_exp);
4643
4644         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4645                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4646         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4647                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4648 }
4649
4650 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4651                                         struct ath9k_channel *chan)
4652 {
4653         int bb_spur = AR_NO_SPUR;
4654         int freq;
4655         int bin, cur_bin;
4656         int bb_spur_off, spur_subchannel_sd;
4657         int spur_freq_sd;
4658         int spur_delta_phase;
4659         int denominator;
4660         int upper, lower, cur_vit_mask;
4661         int tmp, newVal;
4662         int i;
4663         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4664                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4665         };
4666         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4667                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4668         };
4669         int inc[4] = { 0, 100, 0, 0 };
4670         struct chan_centers centers;
4671
4672         int8_t mask_m[123];
4673         int8_t mask_p[123];
4674         int8_t mask_amt;
4675         int tmp_mask;
4676         int cur_bb_spur;
4677         bool is2GHz = IS_CHAN_2GHZ(chan);
4678
4679         memset(&mask_m, 0, sizeof(int8_t) * 123);
4680         memset(&mask_p, 0, sizeof(int8_t) * 123);
4681
4682         ath9k_hw_get_channel_centers(ah, chan, &centers);
4683         freq = centers.synth_center;
4684
4685         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
4686         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4687                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4688
4689                 if (is2GHz)
4690                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4691                 else
4692                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4693
4694                 if (AR_NO_SPUR == cur_bb_spur)
4695                         break;
4696                 cur_bb_spur = cur_bb_spur - freq;
4697
4698                 if (IS_CHAN_HT40(chan)) {
4699                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4700                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4701                                 bb_spur = cur_bb_spur;
4702                                 break;
4703                         }
4704                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4705                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4706                         bb_spur = cur_bb_spur;
4707                         break;
4708                 }
4709         }
4710
4711         if (AR_NO_SPUR == bb_spur) {
4712                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4713                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4714                 return;
4715         } else {
4716                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4717                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4718         }
4719
4720         bin = bb_spur * 320;
4721
4722         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4723
4724         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4725                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4726                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4727                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4728         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4729
4730         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4731                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4732                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4733                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4734                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4735         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4736
4737         if (IS_CHAN_HT40(chan)) {
4738                 if (bb_spur < 0) {
4739                         spur_subchannel_sd = 1;
4740                         bb_spur_off = bb_spur + 10;
4741                 } else {
4742                         spur_subchannel_sd = 0;
4743                         bb_spur_off = bb_spur - 10;
4744                 }
4745         } else {
4746                 spur_subchannel_sd = 0;
4747                 bb_spur_off = bb_spur;
4748         }
4749
4750         if (IS_CHAN_HT40(chan))
4751                 spur_delta_phase =
4752                         ((bb_spur * 262144) /
4753                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4754         else
4755                 spur_delta_phase =
4756                         ((bb_spur * 524288) /
4757                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4758
4759         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4760         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4761
4762         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4763                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4764                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4765         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4766
4767         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4768         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4769
4770         cur_bin = -6000;
4771         upper = bin + 100;
4772         lower = bin - 100;
4773
4774         for (i = 0; i < 4; i++) {
4775                 int pilot_mask = 0;
4776                 int chan_mask = 0;
4777                 int bp = 0;
4778                 for (bp = 0; bp < 30; bp++) {
4779                         if ((cur_bin > lower) && (cur_bin < upper)) {
4780                                 pilot_mask = pilot_mask | 0x1 << bp;
4781                                 chan_mask = chan_mask | 0x1 << bp;
4782                         }
4783                         cur_bin += 100;
4784                 }
4785                 cur_bin += inc[i];
4786                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4787                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4788         }
4789
4790         cur_vit_mask = 6100;
4791         upper = bin + 120;
4792         lower = bin - 120;
4793
4794         for (i = 0; i < 123; i++) {
4795                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4796
4797                         /* workaround for gcc bug #37014 */
4798                         volatile int tmp = abs(cur_vit_mask - bin);
4799
4800                         if (tmp < 75)
4801                                 mask_amt = 1;
4802                         else
4803                                 mask_amt = 0;
4804                         if (cur_vit_mask < 0)
4805                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4806                         else
4807                                 mask_p[cur_vit_mask / 100] = mask_amt;
4808                 }
4809                 cur_vit_mask -= 100;
4810         }
4811
4812         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4813                 | (mask_m[48] << 26) | (mask_m[49] << 24)
4814                 | (mask_m[50] << 22) | (mask_m[51] << 20)
4815                 | (mask_m[52] << 18) | (mask_m[53] << 16)
4816                 | (mask_m[54] << 14) | (mask_m[55] << 12)
4817                 | (mask_m[56] << 10) | (mask_m[57] << 8)
4818                 | (mask_m[58] << 6) | (mask_m[59] << 4)
4819                 | (mask_m[60] << 2) | (mask_m[61] << 0);
4820         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4821         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4822
4823         tmp_mask = (mask_m[31] << 28)
4824                 | (mask_m[32] << 26) | (mask_m[33] << 24)
4825                 | (mask_m[34] << 22) | (mask_m[35] << 20)
4826                 | (mask_m[36] << 18) | (mask_m[37] << 16)
4827                 | (mask_m[48] << 14) | (mask_m[39] << 12)
4828                 | (mask_m[40] << 10) | (mask_m[41] << 8)
4829                 | (mask_m[42] << 6) | (mask_m[43] << 4)
4830                 | (mask_m[44] << 2) | (mask_m[45] << 0);
4831         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4832         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4833
4834         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4835                 | (mask_m[18] << 26) | (mask_m[18] << 24)
4836                 | (mask_m[20] << 22) | (mask_m[20] << 20)
4837                 | (mask_m[22] << 18) | (mask_m[22] << 16)
4838                 | (mask_m[24] << 14) | (mask_m[24] << 12)
4839                 | (mask_m[25] << 10) | (mask_m[26] << 8)
4840                 | (mask_m[27] << 6) | (mask_m[28] << 4)
4841                 | (mask_m[29] << 2) | (mask_m[30] << 0);
4842         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4843         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4844
4845         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4846                 | (mask_m[2] << 26) | (mask_m[3] << 24)
4847                 | (mask_m[4] << 22) | (mask_m[5] << 20)
4848                 | (mask_m[6] << 18) | (mask_m[7] << 16)
4849                 | (mask_m[8] << 14) | (mask_m[9] << 12)
4850                 | (mask_m[10] << 10) | (mask_m[11] << 8)
4851                 | (mask_m[12] << 6) | (mask_m[13] << 4)
4852                 | (mask_m[14] << 2) | (mask_m[15] << 0);
4853         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4854         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4855
4856         tmp_mask = (mask_p[15] << 28)
4857                 | (mask_p[14] << 26) | (mask_p[13] << 24)
4858                 | (mask_p[12] << 22) | (mask_p[11] << 20)
4859                 | (mask_p[10] << 18) | (mask_p[9] << 16)
4860                 | (mask_p[8] << 14) | (mask_p[7] << 12)
4861                 | (mask_p[6] << 10) | (mask_p[5] << 8)
4862                 | (mask_p[4] << 6) | (mask_p[3] << 4)
4863                 | (mask_p[2] << 2) | (mask_p[1] << 0);
4864         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4865         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4866
4867         tmp_mask = (mask_p[30] << 28)
4868                 | (mask_p[29] << 26) | (mask_p[28] << 24)
4869                 | (mask_p[27] << 22) | (mask_p[26] << 20)
4870                 | (mask_p[25] << 18) | (mask_p[24] << 16)
4871                 | (mask_p[23] << 14) | (mask_p[22] << 12)
4872                 | (mask_p[21] << 10) | (mask_p[20] << 8)
4873                 | (mask_p[19] << 6) | (mask_p[18] << 4)
4874                 | (mask_p[17] << 2) | (mask_p[16] << 0);
4875         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4876         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4877
4878         tmp_mask = (mask_p[45] << 28)
4879                 | (mask_p[44] << 26) | (mask_p[43] << 24)
4880                 | (mask_p[42] << 22) | (mask_p[41] << 20)
4881                 | (mask_p[40] << 18) | (mask_p[39] << 16)
4882                 | (mask_p[38] << 14) | (mask_p[37] << 12)
4883                 | (mask_p[36] << 10) | (mask_p[35] << 8)
4884                 | (mask_p[34] << 6) | (mask_p[33] << 4)
4885                 | (mask_p[32] << 2) | (mask_p[31] << 0);
4886         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4887         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4888
4889         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4890                 | (mask_p[59] << 26) | (mask_p[58] << 24)
4891                 | (mask_p[57] << 22) | (mask_p[56] << 20)
4892                 | (mask_p[55] << 18) | (mask_p[54] << 16)
4893                 | (mask_p[53] << 14) | (mask_p[52] << 12)
4894                 | (mask_p[51] << 10) | (mask_p[50] << 8)
4895                 | (mask_p[49] << 6) | (mask_p[48] << 4)
4896                 | (mask_p[47] << 2) | (mask_p[46] << 0);
4897         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4898         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4899 }
4900
4901 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4902                                    struct ath9k_channel *chan)
4903 {
4904         int bb_spur = AR_NO_SPUR;
4905         int bin, cur_bin;
4906         int spur_freq_sd;
4907         int spur_delta_phase;
4908         int denominator;
4909         int upper, lower, cur_vit_mask;
4910         int tmp, new;
4911         int i;
4912         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4913                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4914         };
4915         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4916                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4917         };
4918         int inc[4] = { 0, 100, 0, 0 };
4919
4920         int8_t mask_m[123];
4921         int8_t mask_p[123];
4922         int8_t mask_amt;
4923         int tmp_mask;
4924         int cur_bb_spur;
4925         bool is2GHz = IS_CHAN_2GHZ(chan);
4926
4927         memset(&mask_m, 0, sizeof(int8_t) * 123);
4928         memset(&mask_p, 0, sizeof(int8_t) * 123);
4929
4930         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4931                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4932                 if (AR_NO_SPUR == cur_bb_spur)
4933                         break;
4934                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4935                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4936                         bb_spur = cur_bb_spur;
4937                         break;
4938                 }
4939         }
4940
4941         if (AR_NO_SPUR == bb_spur)
4942                 return;
4943
4944         bin = bb_spur * 32;
4945
4946         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4947         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4948                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4949                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4950                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4951
4952         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4953
4954         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4955                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4956                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4957                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4958                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4959         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4960
4961         spur_delta_phase = ((bb_spur * 524288) / 100) &
4962                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4963
4964         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4965         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4966
4967         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4968                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4969                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4970         REG_WRITE(ah, AR_PHY_TIMING11, new);
4971
4972         cur_bin = -6000;
4973         upper = bin + 100;
4974         lower = bin - 100;
4975
4976         for (i = 0; i < 4; i++) {
4977                 int pilot_mask = 0;
4978                 int chan_mask = 0;
4979                 int bp = 0;
4980                 for (bp = 0; bp < 30; bp++) {
4981                         if ((cur_bin > lower) && (cur_bin < upper)) {
4982                                 pilot_mask = pilot_mask | 0x1 << bp;
4983                                 chan_mask = chan_mask | 0x1 << bp;
4984                         }
4985                         cur_bin += 100;
4986                 }
4987                 cur_bin += inc[i];
4988                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4989                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4990         }
4991
4992         cur_vit_mask = 6100;
4993         upper = bin + 120;
4994         lower = bin - 120;
4995
4996         for (i = 0; i < 123; i++) {
4997                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4998
4999                         /* workaround for gcc bug #37014 */
5000                         volatile int tmp = abs(cur_vit_mask - bin);
5001
5002                         if (tmp < 75)
5003                                 mask_amt = 1;
5004                         else
5005                                 mask_amt = 0;
5006                         if (cur_vit_mask < 0)
5007                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
5008                         else
5009                                 mask_p[cur_vit_mask / 100] = mask_amt;
5010                 }
5011                 cur_vit_mask -= 100;
5012         }
5013
5014         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
5015                 | (mask_m[48] << 26) | (mask_m[49] << 24)
5016                 | (mask_m[50] << 22) | (mask_m[51] << 20)
5017                 | (mask_m[52] << 18) | (mask_m[53] << 16)
5018                 | (mask_m[54] << 14) | (mask_m[55] << 12)
5019                 | (mask_m[56] << 10) | (mask_m[57] << 8)
5020                 | (mask_m[58] << 6) | (mask_m[59] << 4)
5021                 | (mask_m[60] << 2) | (mask_m[61] << 0);
5022         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
5023         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
5024
5025         tmp_mask = (mask_m[31] << 28)
5026                 | (mask_m[32] << 26) | (mask_m[33] << 24)
5027                 | (mask_m[34] << 22) | (mask_m[35] << 20)
5028                 | (mask_m[36] << 18) | (mask_m[37] << 16)
5029                 | (mask_m[48] << 14) | (mask_m[39] << 12)
5030                 | (mask_m[40] << 10) | (mask_m[41] << 8)
5031                 | (mask_m[42] << 6) | (mask_m[43] << 4)
5032                 | (mask_m[44] << 2) | (mask_m[45] << 0);
5033         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5034         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5035
5036         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5037                 | (mask_m[18] << 26) | (mask_m[18] << 24)
5038                 | (mask_m[20] << 22) | (mask_m[20] << 20)
5039                 | (mask_m[22] << 18) | (mask_m[22] << 16)
5040                 | (mask_m[24] << 14) | (mask_m[24] << 12)
5041                 | (mask_m[25] << 10) | (mask_m[26] << 8)
5042                 | (mask_m[27] << 6) | (mask_m[28] << 4)
5043                 | (mask_m[29] << 2) | (mask_m[30] << 0);
5044         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5045         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5046
5047         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5048                 | (mask_m[2] << 26) | (mask_m[3] << 24)
5049                 | (mask_m[4] << 22) | (mask_m[5] << 20)
5050                 | (mask_m[6] << 18) | (mask_m[7] << 16)
5051                 | (mask_m[8] << 14) | (mask_m[9] << 12)
5052                 | (mask_m[10] << 10) | (mask_m[11] << 8)
5053                 | (mask_m[12] << 6) | (mask_m[13] << 4)
5054                 | (mask_m[14] << 2) | (mask_m[15] << 0);
5055         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5056         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5057
5058         tmp_mask = (mask_p[15] << 28)
5059                 | (mask_p[14] << 26) | (mask_p[13] << 24)
5060                 | (mask_p[12] << 22) | (mask_p[11] << 20)
5061                 | (mask_p[10] << 18) | (mask_p[9] << 16)
5062                 | (mask_p[8] << 14) | (mask_p[7] << 12)
5063                 | (mask_p[6] << 10) | (mask_p[5] << 8)
5064                 | (mask_p[4] << 6) | (mask_p[3] << 4)
5065                 | (mask_p[2] << 2) | (mask_p[1] << 0);
5066         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5067         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5068
5069         tmp_mask = (mask_p[30] << 28)
5070                 | (mask_p[29] << 26) | (mask_p[28] << 24)
5071                 | (mask_p[27] << 22) | (mask_p[26] << 20)
5072                 | (mask_p[25] << 18) | (mask_p[24] << 16)
5073                 | (mask_p[23] << 14) | (mask_p[22] << 12)
5074                 | (mask_p[21] << 10) | (mask_p[20] << 8)
5075                 | (mask_p[19] << 6) | (mask_p[18] << 4)
5076                 | (mask_p[17] << 2) | (mask_p[16] << 0);
5077         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5078         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5079
5080         tmp_mask = (mask_p[45] << 28)
5081                 | (mask_p[44] << 26) | (mask_p[43] << 24)
5082                 | (mask_p[42] << 22) | (mask_p[41] << 20)
5083                 | (mask_p[40] << 18) | (mask_p[39] << 16)
5084                 | (mask_p[38] << 14) | (mask_p[37] << 12)
5085                 | (mask_p[36] << 10) | (mask_p[35] << 8)
5086                 | (mask_p[34] << 6) | (mask_p[33] << 4)
5087                 | (mask_p[32] << 2) | (mask_p[31] << 0);
5088         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5089         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5090
5091         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5092                 | (mask_p[59] << 26) | (mask_p[58] << 24)
5093                 | (mask_p[57] << 22) | (mask_p[56] << 20)
5094                 | (mask_p[55] << 18) | (mask_p[54] << 16)
5095                 | (mask_p[53] << 14) | (mask_p[52] << 12)
5096                 | (mask_p[51] << 10) | (mask_p[50] << 8)
5097                 | (mask_p[49] << 6) | (mask_p[48] << 4)
5098                 | (mask_p[47] << 2) | (mask_p[46] << 0);
5099         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5100         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5101 }
5102
5103 static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5104 {
5105         struct ath_hal_5416 *ahp = AH5416(ah);
5106         int rx_chainmask, tx_chainmask;
5107
5108         rx_chainmask = ahp->ah_rxchainmask;
5109         tx_chainmask = ahp->ah_txchainmask;
5110
5111         switch (rx_chainmask) {
5112         case 0x5:
5113                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5114                             AR_PHY_SWAP_ALT_CHAIN);
5115         case 0x3:
5116                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5117                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5118                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5119                         break;
5120                 }
5121         case 0x1:
5122         case 0x2:
5123                 if (!AR_SREV_9280(ah))
5124                         break;
5125         case 0x7:
5126                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5127                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5128                 break;
5129         default:
5130                 break;
5131         }
5132
5133         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5134         if (tx_chainmask == 0x5) {
5135                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5136                             AR_PHY_SWAP_ALT_CHAIN);
5137         }
5138         if (AR_SREV_9100(ah))
5139                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5140                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5141 }
5142
5143 static void ath9k_hw_set_addac(struct ath_hal *ah,
5144                                struct ath9k_channel *chan)
5145 {
5146         struct modal_eep_header *pModal;
5147         struct ath_hal_5416 *ahp = AH5416(ah);
5148         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5149         u8 biaslevel;
5150
5151         if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5152                 return;
5153
5154         if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5155                 return;
5156
5157         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5158
5159         if (pModal->xpaBiasLvl != 0xff) {
5160                 biaslevel = pModal->xpaBiasLvl;
5161         } else {
5162
5163                 u16 resetFreqBin, freqBin, freqCount = 0;
5164                 struct chan_centers centers;
5165
5166                 ath9k_hw_get_channel_centers(ah, chan, &centers);
5167
5168                 resetFreqBin =
5169                         FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5170                 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5171                 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5172
5173                 freqCount++;
5174
5175                 while (freqCount < 3) {
5176                         if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5177                                 break;
5178
5179                         freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5180                         if (resetFreqBin >= freqBin) {
5181                                 biaslevel =
5182                                         (u8) (pModal->
5183                                                     xpaBiasLvlFreq[freqCount]
5184                                                     >> 14);
5185                         } else {
5186                                 break;
5187                         }
5188                         freqCount++;
5189                 }
5190         }
5191
5192         if (IS_CHAN_2GHZ(chan)) {
5193                 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5194                         (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5195                         << 3;
5196         } else {
5197                 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5198                         (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5199                         << 6;
5200         }
5201 }
5202
5203 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
5204 {
5205         if (ah->ah_curchan != NULL)
5206                 return clks /
5207                 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
5208         else
5209                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
5210 }
5211
5212 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
5213 {
5214         struct ath9k_channel *chan = ah->ah_curchan;
5215
5216         if (chan && IS_CHAN_HT40(chan))
5217                 return ath9k_hw_mac_usec(ah, clks) / 2;
5218         else
5219                 return ath9k_hw_mac_usec(ah, clks);
5220 }
5221
5222 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
5223 {
5224         if (ah->ah_curchan != NULL)
5225                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
5226                         ah->ah_curchan)];
5227         else
5228                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
5229 }
5230
5231 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
5232 {
5233         struct ath9k_channel *chan = ah->ah_curchan;
5234
5235         if (chan && IS_CHAN_HT40(chan))
5236                 return ath9k_hw_mac_clks(ah, usecs) * 2;
5237         else
5238                 return ath9k_hw_mac_clks(ah, usecs);
5239 }
5240
5241 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
5242 {
5243         struct ath_hal_5416 *ahp = AH5416(ah);
5244
5245         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5246                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
5247                          __func__, us);
5248                 ahp->ah_acktimeout = (u32) -1;
5249                 return false;
5250         } else {
5251                 REG_RMW_FIELD(ah, AR_TIME_OUT,
5252                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5253                 ahp->ah_acktimeout = us;
5254                 return true;
5255         }
5256 }
5257
5258 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
5259 {
5260         struct ath_hal_5416 *ahp = AH5416(ah);
5261
5262         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5263                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
5264                          __func__, us);
5265                 ahp->ah_ctstimeout = (u32) -1;
5266                 return false;
5267         } else {
5268                 REG_RMW_FIELD(ah, AR_TIME_OUT,
5269                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5270                 ahp->ah_ctstimeout = us;
5271                 return true;
5272         }
5273 }
5274 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5275                                           u32 tu)
5276 {
5277         struct ath_hal_5416 *ahp = AH5416(ah);
5278
5279         if (tu > 0xFFFF) {
5280                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
5281                         "%s: bad global tx timeout %u\n", __func__, tu);
5282                 ahp->ah_globaltxtimeout = (u32) -1;
5283                 return false;
5284         } else {
5285                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5286                 ahp->ah_globaltxtimeout = tu;
5287                 return true;
5288         }
5289 }
5290
5291 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
5292 {
5293         struct ath_hal_5416 *ahp = AH5416(ah);
5294
5295         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5296                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
5297                          __func__, us);
5298                 ahp->ah_slottime = (u32) -1;
5299                 return false;
5300         } else {
5301                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5302                 ahp->ah_slottime = us;
5303                 return true;
5304         }
5305 }
5306
5307 static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)
5308 {
5309         struct ath_hal_5416 *ahp = AH5416(ah);
5310
5311         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5312                  __func__, ahp->ah_miscMode);
5313         if (ahp->ah_miscMode != 0)
5314                 REG_WRITE(ah, AR_PCU_MISC,
5315                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5316         if (ahp->ah_slottime != (u32) -1)
5317                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5318         if (ahp->ah_acktimeout != (u32) -1)
5319                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5320         if (ahp->ah_ctstimeout != (u32) -1)
5321                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5322         if (ahp->ah_globaltxtimeout != (u32) -1)
5323                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5324 }
5325
5326 static inline int
5327 ath9k_hw_process_ini(struct ath_hal *ah,
5328                      struct ath9k_channel *chan,
5329                      enum ath9k_ht_macmode macmode)
5330 {
5331         int i, regWrites = 0;
5332         struct ath_hal_5416 *ahp = AH5416(ah);
5333         u32 modesIndex, freqIndex;
5334         int status;
5335
5336         switch (chan->chanmode) {
5337         case CHANNEL_A:
5338         case CHANNEL_A_HT20:
5339                 modesIndex = 1;
5340                 freqIndex = 1;
5341                 break;
5342         case CHANNEL_A_HT40PLUS:
5343         case CHANNEL_A_HT40MINUS:
5344                 modesIndex = 2;
5345                 freqIndex = 1;
5346                 break;
5347         case CHANNEL_G:
5348         case CHANNEL_G_HT20:
5349         case CHANNEL_B:
5350                 modesIndex = 4;
5351                 freqIndex = 2;
5352                 break;
5353         case CHANNEL_G_HT40PLUS:
5354         case CHANNEL_G_HT40MINUS:
5355                 modesIndex = 3;
5356                 freqIndex = 2;
5357                 break;
5358
5359         default:
5360                 return -EINVAL;
5361         }
5362
5363         REG_WRITE(ah, AR_PHY(0), 0x00000007);
5364
5365         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5366
5367         ath9k_hw_set_addac(ah, chan);
5368
5369         if (AR_SREV_5416_V22_OR_LATER(ah)) {
5370                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5371         } else {
5372                 struct ar5416IniArray temp;
5373                 u32 addacSize =
5374                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
5375                         ahp->ah_iniAddac.ia_columns;
5376
5377                 memcpy(ahp->ah_addac5416_21,
5378                        ahp->ah_iniAddac.ia_array, addacSize);
5379
5380                 (ahp->ah_addac5416_21)[31 *
5381                                        ahp->ah_iniAddac.ia_columns + 1] = 0;
5382
5383                 temp.ia_array = ahp->ah_addac5416_21;
5384                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5385                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5386                 REG_WRITE_ARRAY(&temp, 1, regWrites);
5387         }
5388         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5389
5390         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5391                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
5392                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5393
5394 #ifdef CONFIG_SLOW_ANT_DIV
5395                 if (ah->ah_devid == AR9280_DEVID_PCI)
5396                         val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5397                                                  val);
5398 #endif
5399
5400                 REG_WRITE(ah, reg, val);
5401
5402                 if (reg >= 0x7800 && reg < 0x78a0
5403                     && ah->ah_config.analog_shiftreg) {
5404                         udelay(100);
5405                 }
5406
5407                 DO_DELAY(regWrites);
5408         }
5409
5410         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5411                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5412                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
5413
5414                 REG_WRITE(ah, reg, val);
5415
5416                 if (reg >= 0x7800 && reg < 0x78a0
5417                     && ah->ah_config.analog_shiftreg) {
5418                         udelay(100);
5419                 }
5420
5421                 DO_DELAY(regWrites);
5422         }
5423
5424         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5425
5426         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5427                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5428                                 regWrites);
5429         }
5430
5431         ath9k_hw_override_ini(ah, chan);
5432         ath9k_hw_set_regs(ah, chan, macmode);
5433         ath9k_hw_init_chain_masks(ah);
5434
5435         status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5436                                       ath9k_regd_get_ctl(ah, chan),
5437                                       ath9k_regd_get_antenna_allowed(ah,
5438                                                                      chan),
5439                                       chan->maxRegTxPower * 2,
5440                                       min((u32) MAX_RATE_POWER,
5441                                           (u32) ah->ah_powerLimit));
5442         if (status != 0) {
5443                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
5444                          "%s: error init'ing transmit power\n", __func__);
5445                 return -EIO;
5446         }
5447
5448         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
5449                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
5450                          "%s: ar5416SetRfRegs failed\n", __func__);
5451                 return -EIO;
5452         }
5453
5454         return 0;
5455 }
5456
5457 static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
5458                                               struct hal_cal_list *currCal)
5459 {
5460         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5461                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5462                       currCal->calData->calCountMax);
5463
5464         switch (currCal->calData->calType) {
5465         case IQ_MISMATCH_CAL:
5466                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5467                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5468                          "%s: starting IQ Mismatch Calibration\n",
5469                          __func__);
5470                 break;
5471         case ADC_GAIN_CAL:
5472                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5473                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5474                          "%s: starting ADC Gain Calibration\n", __func__);
5475                 break;
5476         case ADC_DC_CAL:
5477                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5478                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5479                          "%s: starting ADC DC Calibration\n", __func__);
5480                 break;
5481         case ADC_DC_INIT_CAL:
5482                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5483                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5484                          "%s: starting Init ADC DC Calibration\n",
5485                          __func__);
5486                 break;
5487         }
5488
5489         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5490                     AR_PHY_TIMING_CTRL4_DO_CAL);
5491 }
5492
5493 static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,
5494                                               struct hal_cal_list *currCal)
5495 {
5496         struct ath_hal_5416 *ahp = AH5416(ah);
5497         int i;
5498
5499         ath9k_hw_setup_calibration(ah, currCal);
5500
5501         currCal->calState = CAL_RUNNING;
5502
5503         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5504                 ahp->ah_Meas0.sign[i] = 0;
5505                 ahp->ah_Meas1.sign[i] = 0;
5506                 ahp->ah_Meas2.sign[i] = 0;
5507                 ahp->ah_Meas3.sign[i] = 0;
5508         }
5509
5510         ahp->ah_CalSamples = 0;
5511 }
5512
5513 static inline void
5514 ath9k_hw_per_calibration(struct ath_hal *ah,
5515                          struct ath9k_channel *ichan,
5516                          u8 rxchainmask,
5517                          struct hal_cal_list *currCal,
5518                          bool *isCalDone)
5519 {
5520         struct ath_hal_5416 *ahp = AH5416(ah);
5521
5522         *isCalDone = false;
5523
5524         if (currCal->calState == CAL_RUNNING) {
5525                 if (!(REG_READ(ah,
5526                                AR_PHY_TIMING_CTRL4(0)) &
5527                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
5528
5529                         currCal->calData->calCollect(ah);
5530
5531                         ahp->ah_CalSamples++;
5532
5533                         if (ahp->ah_CalSamples >=
5534                             currCal->calData->calNumSamples) {
5535                                 int i, numChains = 0;
5536                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5537                                         if (rxchainmask & (1 << i))
5538                                                 numChains++;
5539                                 }
5540
5541                                 currCal->calData->calPostProc(ah,
5542                                                               numChains);
5543
5544                                 ichan->CalValid |=
5545                                         currCal->calData->calType;
5546                                 currCal->calState = CAL_DONE;
5547                                 *isCalDone = true;
5548                         } else {
5549                                 ath9k_hw_setup_calibration(ah, currCal);
5550                         }
5551                 }
5552         } else if (!(ichan->CalValid & currCal->calData->calType)) {
5553                 ath9k_hw_reset_calibration(ah, currCal);
5554         }
5555 }
5556
5557 static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5558                                           int init_cal_count)
5559 {
5560         struct ath_hal_5416 *ahp = AH5416(ah);
5561         struct ath9k_channel ichan;
5562         bool isCalDone;
5563         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5564         const struct hal_percal_data *calData = currCal->calData;
5565         int i;
5566
5567         if (currCal == NULL)
5568                 return false;
5569
5570         ichan.CalValid = 0;
5571
5572         for (i = 0; i < init_cal_count; i++) {
5573                 ath9k_hw_reset_calibration(ah, currCal);
5574
5575                 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5576                                    AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5577                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5578                                  "%s: Cal %d failed to complete in 100ms.\n",
5579                                  __func__, calData->calType);
5580
5581                         ahp->ah_cal_list = ahp->ah_cal_list_last =
5582                                 ahp->ah_cal_list_curr = NULL;
5583                         return false;
5584                 }
5585
5586                 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5587                                          currCal, &isCalDone);
5588                 if (!isCalDone) {
5589                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5590                                  "%s: Not able to run Init Cal %d.\n",
5591                                  __func__, calData->calType);
5592                 }
5593                 if (currCal->calNext) {
5594                         currCal = currCal->calNext;
5595                         calData = currCal->calData;
5596                 }
5597         }
5598
5599         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5600         return true;
5601 }
5602
5603 static inline bool
5604 ath9k_hw_channel_change(struct ath_hal *ah,
5605                         struct ath9k_channel *chan,
5606                         enum ath9k_ht_macmode macmode)
5607 {
5608         u32 synthDelay, qnum;
5609         struct ath_hal_5416 *ahp = AH5416(ah);
5610
5611         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5612                 if (ath9k_hw_numtxpending(ah, qnum)) {
5613                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5614                                  "%s: Transmit frames pending on queue %d\n",
5615                                  __func__, qnum);
5616                         return false;
5617                 }
5618         }
5619
5620         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5621         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5622                            AR_PHY_RFBUS_GRANT_EN)) {
5623                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
5624                          "%s: Could not kill baseband RX\n", __func__);
5625                 return false;
5626         }
5627
5628         ath9k_hw_set_regs(ah, chan, macmode);
5629
5630         if (AR_SREV_9280_10_OR_LATER(ah)) {
5631                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
5632                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5633                                  "%s: failed to set channel\n", __func__);
5634                         return false;
5635                 }
5636         } else {
5637                 if (!(ath9k_hw_set_channel(ah, chan))) {
5638                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5639                                  "%s: failed to set channel\n", __func__);
5640                         return false;
5641                 }
5642         }
5643
5644         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5645                                  ath9k_regd_get_ctl(ah, chan),
5646                                  ath9k_regd_get_antenna_allowed(ah, chan),
5647                                  chan->maxRegTxPower * 2,
5648                                  min((u32) MAX_RATE_POWER,
5649                                      (u32) ah->ah_powerLimit)) != 0) {
5650                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5651                          "%s: error init'ing transmit power\n", __func__);
5652                 return false;
5653         }
5654
5655         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5656         if (IS_CHAN_CCK(chan))
5657                 synthDelay = (4 * synthDelay) / 22;
5658         else
5659                 synthDelay /= 10;
5660
5661         udelay(synthDelay + BASE_ACTIVATE_DELAY);
5662
5663         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5664
5665         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5666                 ath9k_hw_set_delta_slope(ah, chan);
5667
5668         if (AR_SREV_9280_10_OR_LATER(ah))
5669                 ath9k_hw_9280_spur_mitigate(ah, chan);
5670         else
5671                 ath9k_hw_spur_mitigate(ah, chan);
5672
5673         if (!chan->oneTimeCalsDone)
5674                 chan->oneTimeCalsDone = true;
5675
5676         return true;
5677 }
5678
5679 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
5680                                 struct ath9k_channel *chan)
5681 {
5682         struct ath_hal_5416 *ahp = AH5416(ah);
5683
5684         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
5685                 return false;
5686
5687         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5688                 return false;
5689
5690         ahp->ah_chipFullSleep = false;
5691
5692         ath9k_hw_init_pll(ah, chan);
5693
5694         ath9k_hw_set_rfmode(ah, chan);
5695
5696         return true;
5697 }
5698
5699 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5700 {
5701         u32 regval;
5702
5703         regval = REG_READ(ah, AR_AHB_MODE);
5704         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5705
5706         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5707         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5708
5709         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5710
5711         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5712         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5713
5714         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5715
5716         if (AR_SREV_9285(ah)) {
5717                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5718                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5719         } else {
5720                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5721                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5722         }
5723 }
5724
5725 bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5726 {
5727         REG_WRITE(ah, AR_CR, AR_CR_RXD);
5728         if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5729                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5730                         "%s: dma failed to stop in 10ms\n"
5731                         "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5732                         __func__,
5733                         REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5734                 return false;
5735         } else {
5736                 return true;
5737         }
5738 }
5739
5740 void ath9k_hw_startpcureceive(struct ath_hal *ah)
5741 {
5742         REG_CLR_BIT(ah, AR_DIAG_SW,
5743                     (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5744
5745         ath9k_enable_mib_counters(ah);
5746
5747         ath9k_ani_reset(ah);
5748 }
5749
5750 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5751 {
5752         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5753
5754         ath9k_hw_disable_mib_counters(ah);
5755 }
5756
5757 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5758                                      struct ath9k_channel *chan,
5759                                      enum hal_cal_types calType)
5760 {
5761         struct ath_hal_5416 *ahp = AH5416(ah);
5762         bool retval = false;
5763
5764         switch (calType & ahp->ah_suppCals) {
5765         case IQ_MISMATCH_CAL:
5766                 if (!IS_CHAN_B(chan))
5767                         retval = true;
5768                 break;
5769         case ADC_GAIN_CAL:
5770         case ADC_DC_CAL:
5771                 if (!IS_CHAN_B(chan)
5772                     && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5773                         retval = true;
5774                 break;
5775         }
5776
5777         return retval;
5778 }
5779
5780 static inline bool ath9k_hw_init_cal(struct ath_hal *ah,
5781                                      struct ath9k_channel *chan)
5782 {
5783         struct ath_hal_5416 *ahp = AH5416(ah);
5784         struct ath9k_channel *ichan =
5785                 ath9k_regd_check_channel(ah, chan);
5786
5787         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5788                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5789                   AR_PHY_AGC_CONTROL_CAL);
5790
5791         if (!ath9k_hw_wait
5792             (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5793                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5794                          "%s: offset calibration failed to complete in 1ms; "
5795                          "noisy environment?\n", __func__);
5796                 return false;
5797         }
5798
5799         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5800                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5801                   AR_PHY_AGC_CONTROL_NF);
5802
5803         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5804                 NULL;
5805
5806         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5807                 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5808                         INIT_CAL(&ahp->ah_adcGainCalData);
5809                         INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5810                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5811                                  "%s: enabling ADC Gain Calibration.\n",
5812                                  __func__);
5813                 }
5814                 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5815                         INIT_CAL(&ahp->ah_adcDcCalData);
5816                         INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5817                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5818                                  "%s: enabling ADC DC Calibration.\n",
5819                                  __func__);
5820                 }
5821                 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5822                         INIT_CAL(&ahp->ah_iqCalData);
5823                         INSERT_CAL(ahp, &ahp->ah_iqCalData);
5824                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5825                                  "%s: enabling IQ Calibration.\n",
5826                                  __func__);
5827                 }
5828
5829                 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5830
5831                 if (ahp->ah_cal_list_curr)
5832                         ath9k_hw_reset_calibration(ah,
5833                                                    ahp->ah_cal_list_curr);
5834         }
5835
5836         ichan->CalValid = 0;
5837
5838         return true;
5839 }
5840
5841
5842 bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
5843                     struct ath9k_channel *chan,
5844                     enum ath9k_ht_macmode macmode,
5845                     u8 txchainmask, u8 rxchainmask,
5846                     enum ath9k_ht_extprotspacing extprotspacing,
5847                     bool bChannelChange,
5848                     int *status)
5849 {
5850 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
5851         u32 saveLedState;
5852         struct ath_hal_5416 *ahp = AH5416(ah);
5853         struct ath9k_channel *curchan = ah->ah_curchan;
5854         u32 saveDefAntenna;
5855         u32 macStaId1;
5856         int ecode;
5857         int i, rx_chainmask;
5858
5859         ahp->ah_extprotspacing = extprotspacing;
5860         ahp->ah_txchainmask = txchainmask;
5861         ahp->ah_rxchainmask = rxchainmask;
5862
5863         if (AR_SREV_9280(ah)) {
5864                 ahp->ah_txchainmask &= 0x3;
5865                 ahp->ah_rxchainmask &= 0x3;
5866         }
5867
5868         if (ath9k_hw_check_chan(ah, chan) == NULL) {
5869                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5870                          "%s: invalid channel %u/0x%x; no mapping\n",
5871                          __func__, chan->channel, chan->channelFlags);
5872                 FAIL(-EINVAL);
5873         }
5874
5875         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5876                 return false;
5877
5878         if (curchan)
5879                 ath9k_hw_getnf(ah, curchan);
5880
5881         if (bChannelChange &&
5882             (ahp->ah_chipFullSleep != true) &&
5883             (ah->ah_curchan != NULL) &&
5884             (chan->channel != ah->ah_curchan->channel) &&
5885             ((chan->channelFlags & CHANNEL_ALL) ==
5886              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5887             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5888                                    !IS_CHAN_A_5MHZ_SPACED(ah->
5889                                                           ah_curchan)))) {
5890
5891                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
5892                         ath9k_hw_loadnf(ah, ah->ah_curchan);
5893                         ath9k_hw_start_nfcal(ah);
5894                         return true;
5895                 }
5896         }
5897
5898         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
5899         if (saveDefAntenna == 0)
5900                 saveDefAntenna = 1;
5901
5902         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
5903
5904         saveLedState = REG_READ(ah, AR_CFG_LED) &
5905                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
5906                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
5907
5908         ath9k_hw_mark_phy_inactive(ah);
5909
5910         if (!ath9k_hw_chip_reset(ah, chan)) {
5911                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
5912                          __func__);
5913                 FAIL(-EIO);
5914         }
5915
5916         if (AR_SREV_9280(ah)) {
5917                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5918                             AR_GPIO_JTAG_DISABLE);
5919
5920                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
5921                         if (IS_CHAN_5GHZ(chan))
5922                                 ath9k_hw_set_gpio(ah, 9, 0);
5923                         else
5924                                 ath9k_hw_set_gpio(ah, 9, 1);
5925                 }
5926                 ath9k_hw_cfg_output(ah, 9, ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT);
5927         }
5928
5929         ecode = ath9k_hw_process_ini(ah, chan, macmode);
5930         if (ecode != 0)
5931                 goto bad;
5932
5933         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5934                 ath9k_hw_set_delta_slope(ah, chan);
5935
5936         if (AR_SREV_9280_10_OR_LATER(ah))
5937                 ath9k_hw_9280_spur_mitigate(ah, chan);
5938         else
5939                 ath9k_hw_spur_mitigate(ah, chan);
5940
5941         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
5942                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5943                          "%s: error setting board options\n", __func__);
5944                 FAIL(-EIO);
5945         }
5946
5947         ath9k_hw_decrease_chain_power(ah, chan);
5948
5949         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
5950         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
5951                   | macStaId1
5952                   | AR_STA_ID1_RTS_USE_DEF
5953                   | (ah->ah_config.
5954                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
5955                   | ahp->ah_staId1Defaults);
5956         ath9k_hw_set_operating_mode(ah, opmode);
5957
5958         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
5959         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
5960
5961         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
5962
5963         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
5964         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
5965                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
5966
5967         REG_WRITE(ah, AR_ISR, ~0);
5968
5969         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5970
5971         if (AR_SREV_9280_10_OR_LATER(ah)) {
5972                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
5973                         FAIL(-EIO);
5974         } else {
5975                 if (!(ath9k_hw_set_channel(ah, chan)))
5976                         FAIL(-EIO);
5977         }
5978
5979         for (i = 0; i < AR_NUM_DCU; i++)
5980                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
5981
5982         ahp->ah_intrTxqs = 0;
5983         for (i = 0; i < ah->ah_caps.total_queues; i++)
5984                 ath9k_hw_resettxqueue(ah, i);
5985
5986         ath9k_hw_init_interrupt_masks(ah, opmode);
5987         ath9k_hw_init_qos(ah);
5988
5989         ath9k_hw_init_user_settings(ah);
5990
5991         ah->ah_opmode = opmode;
5992
5993         REG_WRITE(ah, AR_STA_ID1,
5994                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
5995
5996         ath9k_hw_set_dma(ah);
5997
5998         REG_WRITE(ah, AR_OBS, 8);
5999
6000         if (ahp->ah_intrMitigation) {
6001
6002                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
6003                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
6004         }
6005
6006         ath9k_hw_init_bb(ah, chan);
6007
6008         if (!ath9k_hw_init_cal(ah, chan))
6009                 FAIL(-ENODEV);
6010
6011         rx_chainmask = ahp->ah_rxchainmask;
6012         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
6013                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
6014                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
6015         }
6016
6017         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
6018
6019         if (AR_SREV_9100(ah)) {
6020                 u32 mask;
6021                 mask = REG_READ(ah, AR_CFG);
6022                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6023                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6024                                  "%s CFG Byte Swap Set 0x%x\n", __func__,
6025                                  mask);
6026                 } else {
6027                         mask =
6028                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6029                         REG_WRITE(ah, AR_CFG, mask);
6030                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6031                                  "%s Setting CFG 0x%x\n", __func__,
6032                                  REG_READ(ah, AR_CFG));
6033                 }
6034         } else {
6035 #ifdef __BIG_ENDIAN
6036                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
6037 #endif
6038         }
6039
6040         return true;
6041 bad:
6042         if (status)
6043                 *status = ecode;
6044         return false;
6045 #undef FAIL
6046 }
6047
6048 bool ath9k_hw_phy_disable(struct ath_hal *ah)
6049 {
6050         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
6051 }
6052
6053 bool ath9k_hw_disable(struct ath_hal *ah)
6054 {
6055         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
6056                 return false;
6057
6058         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
6059 }
6060
6061 bool
6062 ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
6063                    u8 rxchainmask, bool longcal,
6064                    bool *isCalDone)
6065 {
6066         struct ath_hal_5416 *ahp = AH5416(ah);
6067         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6068         struct ath9k_channel *ichan =
6069                 ath9k_regd_check_channel(ah, chan);
6070
6071         *isCalDone = true;
6072
6073         if (ichan == NULL) {
6074                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
6075                          "%s: invalid channel %u/0x%x; no mapping\n",
6076                          __func__, chan->channel, chan->channelFlags);
6077                 return false;
6078         }
6079
6080         if (currCal &&
6081             (currCal->calState == CAL_RUNNING ||
6082              currCal->calState == CAL_WAITING)) {
6083                 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6084                                          isCalDone);
6085                 if (*isCalDone) {
6086                         ahp->ah_cal_list_curr = currCal = currCal->calNext;
6087
6088                         if (currCal->calState == CAL_WAITING) {
6089                                 *isCalDone = false;
6090                                 ath9k_hw_reset_calibration(ah, currCal);
6091                         }
6092                 }
6093         }
6094
6095         if (longcal) {
6096                 ath9k_hw_getnf(ah, ichan);
6097                 ath9k_hw_loadnf(ah, ah->ah_curchan);
6098                 ath9k_hw_start_nfcal(ah);
6099
6100                 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
6101
6102                         chan->channelFlags |= CHANNEL_CW_INT;
6103                         ichan->channelFlags &= ~CHANNEL_CW_INT;
6104                 }
6105         }
6106
6107         return true;
6108 }
6109
6110 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
6111 {
6112         struct ath_hal_5416 *ahp = AH5416(ah);
6113         int i;
6114
6115         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6116                 ahp->ah_totalPowerMeasI[i] +=
6117                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6118                 ahp->ah_totalPowerMeasQ[i] +=
6119                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6120                 ahp->ah_totalIqCorrMeas[i] +=
6121                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6122                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6123                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6124                          ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6125                          ahp->ah_totalPowerMeasQ[i],
6126                          ahp->ah_totalIqCorrMeas[i]);
6127         }
6128 }
6129
6130 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
6131 {
6132         struct ath_hal_5416 *ahp = AH5416(ah);
6133         int i;
6134
6135         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6136                 ahp->ah_totalAdcIOddPhase[i] +=
6137                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6138                 ahp->ah_totalAdcIEvenPhase[i] +=
6139                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6140                 ahp->ah_totalAdcQOddPhase[i] +=
6141                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6142                 ahp->ah_totalAdcQEvenPhase[i] +=
6143                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6144
6145                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6146                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6147                         "oddq=0x%08x; evenq=0x%08x;\n",
6148                          ahp->ah_CalSamples, i,
6149                          ahp->ah_totalAdcIOddPhase[i],
6150                          ahp->ah_totalAdcIEvenPhase[i],
6151                          ahp->ah_totalAdcQOddPhase[i],
6152                          ahp->ah_totalAdcQEvenPhase[i]);
6153         }
6154 }
6155
6156 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6157 {
6158         struct ath_hal_5416 *ahp = AH5416(ah);
6159         int i;
6160
6161         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6162                 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6163                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6164                 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6165                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6166                 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6167                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6168                 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6169                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6170
6171                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6172                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6173                         "oddq=0x%08x; evenq=0x%08x;\n",
6174                          ahp->ah_CalSamples, i,
6175                          ahp->ah_totalAdcDcOffsetIOddPhase[i],
6176                          ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6177                          ahp->ah_totalAdcDcOffsetQOddPhase[i],
6178                          ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6179         }
6180 }
6181
6182 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
6183 {
6184         struct ath_hal_5416 *ahp = AH5416(ah);
6185         u32 powerMeasQ, powerMeasI, iqCorrMeas;
6186         u32 qCoffDenom, iCoffDenom;
6187         int32_t qCoff, iCoff;
6188         int iqCorrNeg, i;
6189
6190         for (i = 0; i < numChains; i++) {
6191                 powerMeasI = ahp->ah_totalPowerMeasI[i];
6192                 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6193                 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6194
6195                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6196                          "Starting IQ Cal and Correction for Chain %d\n",
6197                          i);
6198
6199                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6200                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6201                          i, ahp->ah_totalIqCorrMeas[i]);
6202
6203                 iqCorrNeg = 0;
6204
6205
6206                 if (iqCorrMeas > 0x80000000) {
6207                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
6208                         iqCorrNeg = 1;
6209                 }
6210
6211                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6212                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
6213                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6214                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
6215                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
6216                          iqCorrNeg);
6217
6218                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
6219                 qCoffDenom = powerMeasQ / 64;
6220
6221                 if (powerMeasQ != 0) {
6222
6223                         iCoff = iqCorrMeas / iCoffDenom;
6224                         qCoff = powerMeasI / qCoffDenom - 64;
6225                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6226                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
6227                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6228                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
6229
6230
6231                         iCoff = iCoff & 0x3f;
6232                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6233                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6234                         if (iqCorrNeg == 0x0)
6235                                 iCoff = 0x40 - iCoff;
6236
6237                         if (qCoff > 15)
6238                                 qCoff = 15;
6239                         else if (qCoff <= -16)
6240                                 qCoff = 16;
6241
6242                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6243                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
6244                                 i, iCoff, qCoff);
6245
6246                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6247                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6248                                       iCoff);
6249                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6250                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6251                                       qCoff);
6252                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6253                                 "IQ Cal and Correction done for Chain %d\n",
6254                                 i);
6255                 }
6256         }
6257
6258         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
6259                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
6260 }
6261
6262 static void
6263 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
6264 {
6265         struct ath_hal_5416 *ahp = AH5416(ah);
6266         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6267                 qEvenMeasOffset;
6268         u32 qGainMismatch, iGainMismatch, val, i;
6269
6270         for (i = 0; i < numChains; i++) {
6271                 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6272                 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6273                 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6274                 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6275
6276                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6277                          "Starting ADC Gain Cal for Chain %d\n", i);
6278
6279                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6280                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6281                          iOddMeasOffset);
6282                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6283                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6284                          iEvenMeasOffset);
6285                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6286                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6287                          qOddMeasOffset);
6288                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6289                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6290                          qEvenMeasOffset);
6291
6292                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6293                         iGainMismatch =
6294                                 ((iEvenMeasOffset * 32) /
6295                                  iOddMeasOffset) & 0x3f;
6296                         qGainMismatch =
6297                                 ((qOddMeasOffset * 32) /
6298                                  qEvenMeasOffset) & 0x3f;
6299
6300                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6301                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
6302                                  iGainMismatch);
6303                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6304                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
6305                                  qGainMismatch);
6306
6307                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6308                         val &= 0xfffff000;
6309                         val |= (qGainMismatch) | (iGainMismatch << 6);
6310                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6311
6312                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6313                                  "ADC Gain Cal done for Chain %d\n", i);
6314                 }
6315         }
6316
6317         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6318                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6319                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
6320 }
6321
6322 static void
6323 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
6324 {
6325         struct ath_hal_5416 *ahp = AH5416(ah);
6326         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
6327         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6328         const struct hal_percal_data *calData =
6329                 ahp->ah_cal_list_curr->calData;
6330         u32 numSamples =
6331                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6332
6333         for (i = 0; i < numChains; i++) {
6334                 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6335                 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6336                 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6337                 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6338
6339                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6340                          "Starting ADC DC Offset Cal for Chain %d\n", i);
6341
6342                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6343                          "Chn %d pwr_meas_odd_i = %d\n", i,
6344                          iOddMeasOffset);
6345                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6346                          "Chn %d pwr_meas_even_i = %d\n", i,
6347                          iEvenMeasOffset);
6348                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6349                          "Chn %d pwr_meas_odd_q = %d\n", i,
6350                          qOddMeasOffset);
6351                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6352                          "Chn %d pwr_meas_even_q = %d\n", i,
6353                          qEvenMeasOffset);
6354
6355                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6356                                numSamples) & 0x1ff;
6357                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6358                                numSamples) & 0x1ff;
6359
6360                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6361                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6362                          iDcMismatch);
6363                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6364                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6365                          qDcMismatch);
6366
6367                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6368                 val &= 0xc0000fff;
6369                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6370                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6371
6372                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6373                          "ADC DC Offset Cal done for Chain %d\n", i);
6374         }
6375
6376         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6377                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6378                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6379 }
6380
6381 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
6382 {
6383         struct ath_hal_5416 *ahp = AH5416(ah);
6384         struct ath9k_channel *chan = ah->ah_curchan;
6385
6386         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6387
6388         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
6389                                  ath9k_regd_get_ctl(ah, chan),
6390                                  ath9k_regd_get_antenna_allowed(ah,
6391                                                                 chan),
6392                                  chan->maxRegTxPower * 2,
6393                                  min((u32) MAX_RATE_POWER,
6394                                      (u32) ah->ah_powerLimit)) != 0)
6395                 return false;
6396
6397         return true;
6398 }
6399
6400 void
6401 ath9k_hw_get_channel_centers(struct ath_hal *ah,
6402                              struct ath9k_channel *chan,
6403                              struct chan_centers *centers)
6404 {
6405         int8_t extoff;
6406         struct ath_hal_5416 *ahp = AH5416(ah);
6407
6408         if (!IS_CHAN_HT40(chan)) {
6409                 centers->ctl_center = centers->ext_center =
6410                         centers->synth_center = chan->channel;
6411                 return;
6412         }
6413
6414         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
6415             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
6416                 centers->synth_center =
6417                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6418                 extoff = 1;
6419         } else {
6420                 centers->synth_center =
6421                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6422                 extoff = -1;
6423         }
6424
6425         centers->ctl_center = centers->synth_center - (extoff *
6426                 HT40_CHANNEL_CENTER_SHIFT);
6427         centers->ext_center = centers->synth_center + (extoff *
6428                 ((ahp->
6429                 ah_extprotspacing
6430                 ==
6431                 ATH9K_HT_EXTPROTSPACING_20)
6432                 ?
6433                 HT40_CHANNEL_CENTER_SHIFT
6434                 : 15));
6435
6436 }
6437
6438 void
6439 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
6440                         bool *isCalDone)
6441 {
6442         struct ath_hal_5416 *ahp = AH5416(ah);
6443         struct ath9k_channel *ichan =
6444                 ath9k_regd_check_channel(ah, chan);
6445         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6446
6447         *isCalDone = true;
6448
6449         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6450                 return;
6451
6452         if (currCal == NULL)
6453                 return;
6454
6455         if (ichan == NULL) {
6456                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6457                          "%s: invalid channel %u/0x%x; no mapping\n",
6458                          __func__, chan->channel, chan->channelFlags);
6459                 return;
6460         }
6461
6462
6463         if (currCal->calState != CAL_DONE) {
6464                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6465                          "%s: Calibration state incorrect, %d\n",
6466                          __func__, currCal->calState);
6467                 return;
6468         }
6469
6470
6471         if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
6472                 return;
6473
6474         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6475                  "%s: Resetting Cal %d state for channel %u/0x%x\n",
6476                  __func__, currCal->calData->calType, chan->channel,
6477                  chan->channelFlags);
6478
6479         ichan->CalValid &= ~currCal->calData->calType;
6480         currCal->calState = CAL_WAITING;
6481
6482         *isCalDone = false;
6483 }
6484
6485 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
6486 {
6487         struct ath_hal_5416 *ahp = AH5416(ah);
6488
6489         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
6490 }
6491
6492 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
6493 {
6494         struct ath_hal_5416 *ahp = AH5416(ah);
6495
6496         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
6497         return true;
6498 }
6499
6500 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
6501 {
6502         struct ath_hal_5416 *ahp = AH5416(ah);
6503
6504         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
6505 }
6506
6507 bool
6508 ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
6509 {
6510         struct ath_hal_5416 *ahp = AH5416(ah);
6511
6512         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
6513
6514         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
6515         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
6516
6517         return true;
6518 }
6519
6520 #ifdef CONFIG_ATH9K_RFKILL
6521 static void ath9k_enable_rfkill(struct ath_hal *ah)
6522 {
6523         struct ath_hal_5416 *ahp = AH5416(ah);
6524
6525         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
6526                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
6527
6528         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
6529                     AR_GPIO_INPUT_MUX2_RFSILENT);
6530
6531         ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect);
6532         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
6533
6534         if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) {
6535
6536                 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6537                                        !ahp->ah_gpioBit);
6538         } else {
6539                 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6540                                        ahp->ah_gpioBit);
6541         }
6542 }
6543 #endif
6544
6545 void
6546 ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
6547                        u16 assocId)
6548 {
6549         struct ath_hal_5416 *ahp = AH5416(ah);
6550
6551         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
6552         ahp->ah_assocId = assocId;
6553
6554         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
6555         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
6556                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6557 }
6558
6559 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
6560 {
6561         u64 tsf;
6562
6563         tsf = REG_READ(ah, AR_TSF_U32);
6564         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6565         return tsf;
6566 }
6567
6568 void ath9k_hw_reset_tsf(struct ath_hal *ah)
6569 {
6570         int count;
6571
6572         count = 0;
6573         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
6574                 count++;
6575                 if (count > 10) {
6576                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6577                          "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6578                                  __func__);
6579                         break;
6580                 }
6581                 udelay(10);
6582         }
6583         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
6584 }
6585
6586 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
6587 {
6588         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6589 }
6590
6591 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
6592 {
6593         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6594 }
6595
6596 bool
6597 ath9k_hw_setantennaswitch(struct ath_hal *ah,
6598                           enum ath9k_ant_setting settings,
6599                           struct ath9k_channel *chan,
6600                           u8 *tx_chainmask,
6601                           u8 *rx_chainmask,
6602                           u8 *antenna_cfgd)
6603 {
6604         struct ath_hal_5416 *ahp = AH5416(ah);
6605         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
6606
6607         if (AR_SREV_9280(ah)) {
6608                 if (!tx_chainmask_cfg) {
6609
6610                         tx_chainmask_cfg = *tx_chainmask;
6611                         rx_chainmask_cfg = *rx_chainmask;
6612                 }
6613
6614                 switch (settings) {
6615                 case ATH9K_ANT_FIXED_A:
6616                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6617                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6618                         *antenna_cfgd = true;
6619                         break;
6620                 case ATH9K_ANT_FIXED_B:
6621                         if (ah->ah_caps.tx_chainmask >
6622                             ATH9K_ANTENNA1_CHAINMASK) {
6623                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6624                         }
6625                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6626                         *antenna_cfgd = true;
6627                         break;
6628                 case ATH9K_ANT_VARIABLE:
6629                         *tx_chainmask = tx_chainmask_cfg;
6630                         *rx_chainmask = rx_chainmask_cfg;
6631                         *antenna_cfgd = true;
6632                         break;
6633                 default:
6634                         break;
6635                 }
6636         } else {
6637                 ahp->ah_diversityControl = settings;
6638         }
6639
6640         return true;
6641 }
6642
6643 void ath9k_hw_setopmode(struct ath_hal *ah)
6644 {
6645         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6646 }
6647
6648 bool
6649 ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
6650                        u32 capability, u32 *result)
6651 {
6652         struct ath_hal_5416 *ahp = AH5416(ah);
6653         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6654
6655         switch (type) {
6656         case ATH9K_CAP_CIPHER:
6657                 switch (capability) {
6658                 case ATH9K_CIPHER_AES_CCM:
6659                 case ATH9K_CIPHER_AES_OCB:
6660                 case ATH9K_CIPHER_TKIP:
6661                 case ATH9K_CIPHER_WEP:
6662                 case ATH9K_CIPHER_MIC:
6663                 case ATH9K_CIPHER_CLR:
6664                         return true;
6665                 default:
6666                         return false;
6667                 }
6668         case ATH9K_CAP_TKIP_MIC:
6669                 switch (capability) {
6670                 case 0:
6671                         return true;
6672                 case 1:
6673                         return (ahp->ah_staId1Defaults &
6674                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6675                         false;
6676                 }
6677         case ATH9K_CAP_TKIP_SPLIT:
6678                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6679                         false : true;
6680         case ATH9K_CAP_WME_TKIPMIC:
6681                 return 0;
6682         case ATH9K_CAP_PHYCOUNTERS:
6683                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6684         case ATH9K_CAP_DIVERSITY:
6685                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6686                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6687                         true : false;
6688         case ATH9K_CAP_PHYDIAG:
6689                 return true;
6690         case ATH9K_CAP_MCAST_KEYSRCH:
6691                 switch (capability) {
6692                 case 0:
6693                         return true;
6694                 case 1:
6695                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6696                                 return false;
6697                         } else {
6698                                 return (ahp->ah_staId1Defaults &
6699                                         AR_STA_ID1_MCAST_KSRCH) ? true :
6700                                         false;
6701                         }
6702                 }
6703                 return false;
6704         case ATH9K_CAP_TSF_ADJUST:
6705                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6706                         true : false;
6707         case ATH9K_CAP_RFSILENT:
6708                 if (capability == 3)
6709                         return false;
6710         case ATH9K_CAP_ANT_CFG_2GHZ:
6711                 *result = pCap->num_antcfg_2ghz;
6712                 return true;
6713         case ATH9K_CAP_ANT_CFG_5GHZ:
6714                 *result = pCap->num_antcfg_5ghz;
6715                 return true;
6716         case ATH9K_CAP_TXPOW:
6717                 switch (capability) {
6718                 case 0:
6719                         return 0;
6720                 case 1:
6721                         *result = ah->ah_powerLimit;
6722                         return 0;
6723                 case 2:
6724                         *result = ah->ah_maxPowerLevel;
6725                         return 0;
6726                 case 3:
6727                         *result = ah->ah_tpScale;
6728                         return 0;
6729                 }
6730                 return false;
6731         default:
6732                 return false;
6733         }
6734 }
6735
6736 int
6737 ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
6738 {
6739         struct ath_hal_5416 *ahp = AH5416(ah);
6740         struct ath9k_channel *chan = ah->ah_curchan;
6741         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6742         u16 ant_config;
6743         u32 halNumAntConfig;
6744
6745         halNumAntConfig =
6746                 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6747                 num_antcfg_5ghz;
6748
6749         if (cfg < halNumAntConfig) {
6750                 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
6751                                                      cfg, &ant_config)) {
6752                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6753                         return 0;
6754                 }
6755         }
6756
6757         return -EINVAL;
6758 }
6759
6760 bool ath9k_hw_intrpend(struct ath_hal *ah)
6761 {
6762         u32 host_isr;
6763
6764         if (AR_SREV_9100(ah))
6765                 return true;
6766
6767         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
6768         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
6769                 return true;
6770
6771         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
6772         if ((host_isr & AR_INTR_SYNC_DEFAULT)
6773             && (host_isr != AR_INTR_SPURIOUS))
6774                 return true;
6775
6776         return false;
6777 }
6778
6779 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6780 {
6781         u32 isr = 0;
6782         u32 mask2 = 0;
6783         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6784         u32 sync_cause = 0;
6785         bool fatal_int = false;
6786
6787         if (!AR_SREV_9100(ah)) {
6788                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
6789                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
6790                             == AR_RTC_STATUS_ON) {
6791                                 isr = REG_READ(ah, AR_ISR);
6792                         }
6793                 }
6794
6795                 sync_cause =
6796                         REG_READ(ah,
6797                                  AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6798
6799                 *masked = 0;
6800
6801                 if (!isr && !sync_cause)
6802                         return false;
6803         } else {
6804                 *masked = 0;
6805                 isr = REG_READ(ah, AR_ISR);
6806         }
6807
6808         if (isr) {
6809                 struct ath_hal_5416 *ahp = AH5416(ah);
6810
6811                 if (isr & AR_ISR_BCNMISC) {
6812                         u32 isr2;
6813                         isr2 = REG_READ(ah, AR_ISR_S2);
6814                         if (isr2 & AR_ISR_S2_TIM)
6815                                 mask2 |= ATH9K_INT_TIM;
6816                         if (isr2 & AR_ISR_S2_DTIM)
6817                                 mask2 |= ATH9K_INT_DTIM;
6818                         if (isr2 & AR_ISR_S2_DTIMSYNC)
6819                                 mask2 |= ATH9K_INT_DTIMSYNC;
6820                         if (isr2 & (AR_ISR_S2_CABEND))
6821                                 mask2 |= ATH9K_INT_CABEND;
6822                         if (isr2 & AR_ISR_S2_GTT)
6823                                 mask2 |= ATH9K_INT_GTT;
6824                         if (isr2 & AR_ISR_S2_CST)
6825                                 mask2 |= ATH9K_INT_CST;
6826                 }
6827
6828                 isr = REG_READ(ah, AR_ISR_RAC);
6829                 if (isr == 0xffffffff) {
6830                         *masked = 0;
6831                         return false;
6832                 }
6833
6834                 *masked = isr & ATH9K_INT_COMMON;
6835
6836                 if (ahp->ah_intrMitigation) {
6837
6838                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6839                                 *masked |= ATH9K_INT_RX;
6840                 }
6841
6842                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
6843                         *masked |= ATH9K_INT_RX;
6844                 if (isr &
6845                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
6846                      AR_ISR_TXEOL)) {
6847                         u32 s0_s, s1_s;
6848
6849                         *masked |= ATH9K_INT_TX;
6850
6851                         s0_s = REG_READ(ah, AR_ISR_S0_S);
6852                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
6853                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
6854
6855                         s1_s = REG_READ(ah, AR_ISR_S1_S);
6856                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
6857                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
6858                 }
6859
6860                 if (isr & AR_ISR_RXORN) {
6861                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6862                                  "%s: receive FIFO overrun interrupt\n",
6863                                  __func__);
6864                 }
6865
6866                 if (!AR_SREV_9100(ah)) {
6867                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6868                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
6869                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
6870                                         *masked |= ATH9K_INT_TIM_TIMER;
6871                         }
6872                 }
6873
6874                 *masked |= mask2;
6875         }
6876         if (AR_SREV_9100(ah))
6877                 return true;
6878         if (sync_cause) {
6879                 fatal_int =
6880                         (sync_cause &
6881                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
6882                         ? true : false;
6883
6884                 if (fatal_int) {
6885                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6886                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6887                                          "%s: received PCI FATAL interrupt\n",
6888                                          __func__);
6889                         }
6890                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6891                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6892                                          "%s: received PCI PERR interrupt\n",
6893                                          __func__);
6894                         }
6895                 }
6896                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6897                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6898                                  "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6899                                  __func__);
6900                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6901                         REG_WRITE(ah, AR_RC, 0);
6902                         *masked |= ATH9K_INT_FATAL;
6903                 }
6904                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6905                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6906                                  "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6907                                  __func__);
6908                 }
6909
6910                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6911                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6912         }
6913         return true;
6914 }
6915
6916 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
6917 {
6918         return AH5416(ah)->ah_maskReg;
6919 }
6920
6921 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6922 {
6923         struct ath_hal_5416 *ahp = AH5416(ah);
6924         u32 omask = ahp->ah_maskReg;
6925         u32 mask, mask2;
6926         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6927
6928         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6929                  omask, ints);
6930
6931         if (omask & ATH9K_INT_GLOBAL) {
6932                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
6933                          __func__);
6934                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6935                 (void) REG_READ(ah, AR_IER);
6936                 if (!AR_SREV_9100(ah)) {
6937                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
6938                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
6939
6940                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
6941                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
6942                 }
6943         }
6944
6945         mask = ints & ATH9K_INT_COMMON;
6946         mask2 = 0;
6947
6948         if (ints & ATH9K_INT_TX) {
6949                 if (ahp->ah_txOkInterruptMask)
6950                         mask |= AR_IMR_TXOK;
6951                 if (ahp->ah_txDescInterruptMask)
6952                         mask |= AR_IMR_TXDESC;
6953                 if (ahp->ah_txErrInterruptMask)
6954                         mask |= AR_IMR_TXERR;
6955                 if (ahp->ah_txEolInterruptMask)
6956                         mask |= AR_IMR_TXEOL;
6957         }
6958         if (ints & ATH9K_INT_RX) {
6959                 mask |= AR_IMR_RXERR;
6960                 if (ahp->ah_intrMitigation)
6961                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6962                 else
6963                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6964                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
6965                         mask |= AR_IMR_GENTMR;
6966         }
6967
6968         if (ints & (ATH9K_INT_BMISC)) {
6969                 mask |= AR_IMR_BCNMISC;
6970                 if (ints & ATH9K_INT_TIM)
6971                         mask2 |= AR_IMR_S2_TIM;
6972                 if (ints & ATH9K_INT_DTIM)
6973                         mask2 |= AR_IMR_S2_DTIM;
6974                 if (ints & ATH9K_INT_DTIMSYNC)
6975                         mask2 |= AR_IMR_S2_DTIMSYNC;
6976                 if (ints & ATH9K_INT_CABEND)
6977                         mask2 |= (AR_IMR_S2_CABEND);
6978         }
6979
6980         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
6981                 mask |= AR_IMR_BCNMISC;
6982                 if (ints & ATH9K_INT_GTT)
6983                         mask2 |= AR_IMR_S2_GTT;
6984                 if (ints & ATH9K_INT_CST)
6985                         mask2 |= AR_IMR_S2_CST;
6986         }
6987
6988         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
6989                  mask);
6990         REG_WRITE(ah, AR_IMR, mask);
6991         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
6992                                            AR_IMR_S2_DTIM |
6993                                            AR_IMR_S2_DTIMSYNC |
6994                                            AR_IMR_S2_CABEND |
6995                                            AR_IMR_S2_CABTO |
6996                                            AR_IMR_S2_TSFOOR |
6997                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
6998         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
6999         ahp->ah_maskReg = ints;
7000
7001         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
7002                 if (ints & ATH9K_INT_TIM_TIMER)
7003                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7004                 else
7005                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7006         }
7007
7008         if (ints & ATH9K_INT_GLOBAL) {
7009                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
7010                          __func__);
7011                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
7012                 if (!AR_SREV_9100(ah)) {
7013                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
7014                                   AR_INTR_MAC_IRQ);
7015                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
7016
7017
7018                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
7019                                   AR_INTR_SYNC_DEFAULT);
7020                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
7021                                   AR_INTR_SYNC_DEFAULT);
7022                 }
7023                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
7024                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
7025         }
7026
7027         return omask;
7028 }
7029
7030 void
7031 ath9k_hw_beaconinit(struct ath_hal *ah,
7032                     u32 next_beacon, u32 beacon_period)
7033 {
7034         struct ath_hal_5416 *ahp = AH5416(ah);
7035         int flags = 0;
7036
7037         ahp->ah_beaconInterval = beacon_period;
7038
7039         switch (ah->ah_opmode) {
7040         case ATH9K_M_STA:
7041         case ATH9K_M_MONITOR:
7042                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7043                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7044                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7045                 flags |= AR_TBTT_TIMER_EN;
7046                 break;
7047         case ATH9K_M_IBSS:
7048                 REG_SET_BIT(ah, AR_TXCFG,
7049                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7050                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
7051                           TU_TO_USEC(next_beacon +
7052                                      (ahp->ah_atimWindow ? ahp->
7053                                       ah_atimWindow : 1)));
7054                 flags |= AR_NDP_TIMER_EN;
7055         case ATH9K_M_HOSTAP:
7056                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7057                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7058                           TU_TO_USEC(next_beacon -
7059                                      ah->ah_config.
7060                                      dma_beacon_response_time));
7061                 REG_WRITE(ah, AR_NEXT_SWBA,
7062                           TU_TO_USEC(next_beacon -
7063                                      ah->ah_config.
7064                                      sw_beacon_response_time));
7065                 flags |=
7066                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7067                 break;
7068         }
7069
7070         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7071         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7072         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
7073         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
7074
7075         beacon_period &= ~ATH9K_BEACON_ENA;
7076         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
7077                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
7078                 ath9k_hw_reset_tsf(ah);
7079         }
7080
7081         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7082 }
7083
7084 void
7085 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7086                                const struct ath9k_beacon_state *bs)
7087 {
7088         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7089         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7090
7091         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7092
7093         REG_WRITE(ah, AR_BEACON_PERIOD,
7094                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7095         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
7096                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7097
7098         REG_RMW_FIELD(ah, AR_RSSI_THR,
7099                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
7100
7101         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
7102
7103         if (bs->bs_sleepduration > beaconintval)
7104                 beaconintval = bs->bs_sleepduration;
7105
7106         dtimperiod = bs->bs_dtimperiod;
7107         if (bs->bs_sleepduration > dtimperiod)
7108                 dtimperiod = bs->bs_sleepduration;
7109
7110         if (beaconintval == dtimperiod)
7111                 nextTbtt = bs->bs_nextdtim;
7112         else
7113                 nextTbtt = bs->bs_nexttbtt;
7114
7115         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
7116                  bs->bs_nextdtim);
7117         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
7118                  nextTbtt);
7119         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
7120                  beaconintval);
7121         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7122                  dtimperiod);
7123
7124         REG_WRITE(ah, AR_NEXT_DTIM,
7125                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
7126         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
7127
7128         REG_WRITE(ah, AR_SLEEP1,
7129                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7130                   | AR_SLEEP1_ASSUME_DTIM);
7131
7132         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
7133                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7134         else
7135                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
7136
7137         REG_WRITE(ah, AR_SLEEP2,
7138                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
7139
7140         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
7141         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
7142
7143         REG_SET_BIT(ah, AR_TIMER_MODE,
7144                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
7145                     AR_DTIM_TIMER_EN);
7146
7147 }
7148
7149 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
7150 {
7151         if (entry < ah->ah_caps.keycache_size) {
7152                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7153                 if (val & AR_KEYTABLE_VALID)
7154                         return true;
7155         }
7156         return false;
7157 }
7158
7159 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
7160 {
7161         u32 keyType;
7162
7163         if (entry >= ah->ah_caps.keycache_size) {
7164                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7165                          "%s: entry %u out of range\n", __func__, entry);
7166                 return false;
7167         }
7168         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7169
7170         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
7171         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7172         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7173         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7174         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7175         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7176         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7177         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7178
7179         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7180                 u16 micentry = entry + 64;
7181
7182                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
7183                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7184                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7185                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7186
7187         }
7188
7189         if (ah->ah_curchan == NULL)
7190                 return true;
7191
7192         return true;
7193 }
7194
7195 bool
7196 ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
7197                    const u8 *mac)
7198 {
7199         u32 macHi, macLo;
7200
7201         if (entry >= ah->ah_caps.keycache_size) {
7202                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7203                          "%s: entry %u out of range\n", __func__, entry);
7204                 return false;
7205         }
7206
7207         if (mac != NULL) {
7208                 macHi = (mac[5] << 8) | mac[4];
7209                 macLo = (mac[3] << 24) | (mac[2] << 16)
7210                         | (mac[1] << 8) | mac[0];
7211                 macLo >>= 1;
7212                 macLo |= (macHi & 1) << 31;
7213                 macHi >>= 1;
7214         } else {
7215                 macLo = macHi = 0;
7216         }
7217         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7218         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7219
7220         return true;
7221 }
7222
7223 bool
7224 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7225                             const struct ath9k_keyval *k,
7226                             const u8 *mac, int xorKey)
7227 {
7228         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7229         u32 key0, key1, key2, key3, key4;
7230         u32 keyType;
7231         u32 xorMask = xorKey ?
7232                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7233                  | ATH9K_KEY_XOR) : 0;
7234         struct ath_hal_5416 *ahp = AH5416(ah);
7235
7236         if (entry >= pCap->keycache_size) {
7237                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7238                          "%s: entry %u out of range\n", __func__, entry);
7239                 return false;
7240         }
7241         switch (k->kv_type) {
7242         case ATH9K_CIPHER_AES_OCB:
7243                 keyType = AR_KEYTABLE_TYPE_AES;
7244                 break;
7245         case ATH9K_CIPHER_AES_CCM:
7246                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
7247                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7248                                  "%s: AES-CCM not supported by "
7249                                  "mac rev 0x%x\n", __func__,
7250                                  ah->ah_macRev);
7251                         return false;
7252                 }
7253                 keyType = AR_KEYTABLE_TYPE_CCM;
7254                 break;
7255         case ATH9K_CIPHER_TKIP:
7256                 keyType = AR_KEYTABLE_TYPE_TKIP;
7257                 if (ATH9K_IS_MIC_ENABLED(ah)
7258                     && entry + 64 >= pCap->keycache_size) {
7259                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7260                                  "%s: entry %u inappropriate for TKIP\n",
7261                                  __func__, entry);
7262                         return false;
7263                 }
7264                 break;
7265         case ATH9K_CIPHER_WEP:
7266                 if (k->kv_len < 40 / NBBY) {
7267                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7268                                  "%s: WEP key length %u too small\n",
7269                                  __func__, k->kv_len);
7270                         return false;
7271                 }
7272                 if (k->kv_len <= 40 / NBBY)
7273                         keyType = AR_KEYTABLE_TYPE_40;
7274                 else if (k->kv_len <= 104 / NBBY)
7275                         keyType = AR_KEYTABLE_TYPE_104;
7276                 else
7277                         keyType = AR_KEYTABLE_TYPE_128;
7278                 break;
7279         case ATH9K_CIPHER_CLR:
7280                 keyType = AR_KEYTABLE_TYPE_CLR;
7281                 break;
7282         default:
7283                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7284                          "%s: cipher %u not supported\n", __func__,
7285                          k->kv_type);
7286                 return false;
7287         }
7288
7289         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
7290         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
7291         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
7292         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
7293         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
7294         if (k->kv_len <= 104 / NBBY)
7295                 key4 &= 0xff;
7296
7297         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7298                 u16 micentry = entry + 64;
7299
7300                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7301                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7302                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7303                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7304                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7305                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7306                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7307
7308                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7309                         u32 mic0, mic1, mic2, mic3, mic4;
7310
7311                         mic0 = get_unaligned_le32(k->kv_mic + 0);
7312                         mic2 = get_unaligned_le32(k->kv_mic + 4);
7313                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
7314                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
7315                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
7316                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7317                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7318                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7319                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7320                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7321                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7322                                   AR_KEYTABLE_TYPE_CLR);
7323
7324                 } else {
7325                         u32 mic0, mic2;
7326
7327                         mic0 = get_unaligned_le32(k->kv_mic + 0);
7328                         mic2 = get_unaligned_le32(k->kv_mic + 4);
7329                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7330                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7331                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7332                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7333                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7334                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7335                                   AR_KEYTABLE_TYPE_CLR);
7336                 }
7337                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7338                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7339                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7340                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7341         } else {
7342                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7343                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7344                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7345                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7346                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7347                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7348
7349                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7350         }
7351
7352         if (ah->ah_curchan == NULL)
7353                 return true;
7354
7355         return true;
7356 }
7357
7358 bool
7359 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
7360 {
7361         struct ath_hal_5416 *ahp = AH5416(ah);
7362         u32 txcfg, curLevel, newLevel;
7363         enum ath9k_int omask;
7364
7365         if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7366                 return false;
7367
7368         omask = ath9k_hw_set_interrupts(ah,
7369                                         ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
7370
7371         txcfg = REG_READ(ah, AR_TXCFG);
7372         curLevel = MS(txcfg, AR_FTRIG);
7373         newLevel = curLevel;
7374         if (bIncTrigLevel) {
7375                 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7376                         newLevel++;
7377         } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7378                 newLevel--;
7379         if (newLevel != curLevel)
7380                 REG_WRITE(ah, AR_TXCFG,
7381                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7382
7383         ath9k_hw_set_interrupts(ah, omask);
7384
7385         ah->ah_txTrigLevel = newLevel;
7386
7387         return newLevel != curLevel;
7388 }
7389
7390 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
7391                             const struct ath9k_tx_queue_info *qinfo)
7392 {
7393         u32 cw;
7394         struct ath_hal_5416 *ahp = AH5416(ah);
7395         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7396         struct ath9k_tx_queue_info *qi;
7397
7398         if (q >= pCap->total_queues) {
7399                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7400                          __func__, q);
7401                 return false;
7402         }
7403
7404         qi = &ahp->ah_txq[q];
7405         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7406                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7407                          __func__);
7408                 return false;
7409         }
7410
7411         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
7412
7413         qi->tqi_ver = qinfo->tqi_ver;
7414         qi->tqi_subtype = qinfo->tqi_subtype;
7415         qi->tqi_qflags = qinfo->tqi_qflags;
7416         qi->tqi_priority = qinfo->tqi_priority;
7417         if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
7418                 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
7419         else
7420                 qi->tqi_aifs = INIT_AIFS;
7421         if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
7422                 cw = min(qinfo->tqi_cwmin, 1024U);
7423                 qi->tqi_cwmin = 1;
7424                 while (qi->tqi_cwmin < cw)
7425                         qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7426         } else
7427                 qi->tqi_cwmin = qinfo->tqi_cwmin;
7428         if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
7429                 cw = min(qinfo->tqi_cwmax, 1024U);
7430                 qi->tqi_cwmax = 1;
7431                 while (qi->tqi_cwmax < cw)
7432                         qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7433         } else
7434                 qi->tqi_cwmax = INIT_CWMAX;
7435
7436         if (qinfo->tqi_shretry != 0)
7437                 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
7438         else
7439                 qi->tqi_shretry = INIT_SH_RETRY;
7440         if (qinfo->tqi_lgretry != 0)
7441                 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
7442         else
7443                 qi->tqi_lgretry = INIT_LG_RETRY;
7444         qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
7445         qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
7446         qi->tqi_burstTime = qinfo->tqi_burstTime;
7447         qi->tqi_readyTime = qinfo->tqi_readyTime;
7448
7449         switch (qinfo->tqi_subtype) {
7450         case ATH9K_WME_UPSD:
7451                 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
7452                         qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
7453                 break;
7454         default:
7455                 break;
7456         }
7457         return true;
7458 }
7459
7460 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
7461                             struct ath9k_tx_queue_info *qinfo)
7462 {
7463         struct ath_hal_5416 *ahp = AH5416(ah);
7464         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7465         struct ath9k_tx_queue_info *qi;
7466
7467         if (q >= pCap->total_queues) {
7468                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7469                          __func__, q);
7470                 return false;
7471         }
7472
7473         qi = &ahp->ah_txq[q];
7474         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7475                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7476                          __func__);
7477                 return false;
7478         }
7479
7480         qinfo->tqi_qflags = qi->tqi_qflags;
7481         qinfo->tqi_ver = qi->tqi_ver;
7482         qinfo->tqi_subtype = qi->tqi_subtype;
7483         qinfo->tqi_qflags = qi->tqi_qflags;
7484         qinfo->tqi_priority = qi->tqi_priority;
7485         qinfo->tqi_aifs = qi->tqi_aifs;
7486         qinfo->tqi_cwmin = qi->tqi_cwmin;
7487         qinfo->tqi_cwmax = qi->tqi_cwmax;
7488         qinfo->tqi_shretry = qi->tqi_shretry;
7489         qinfo->tqi_lgretry = qi->tqi_lgretry;
7490         qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7491         qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7492         qinfo->tqi_burstTime = qi->tqi_burstTime;
7493         qinfo->tqi_readyTime = qi->tqi_readyTime;
7494
7495         return true;
7496 }
7497
7498 int
7499 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
7500                       const struct ath9k_tx_queue_info *qinfo)
7501 {
7502         struct ath_hal_5416 *ahp = AH5416(ah);
7503         struct ath9k_tx_queue_info *qi;
7504         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7505         int q;
7506
7507         switch (type) {
7508         case ATH9K_TX_QUEUE_BEACON:
7509                 q = pCap->total_queues - 1;
7510                 break;
7511         case ATH9K_TX_QUEUE_CAB:
7512                 q = pCap->total_queues - 2;
7513                 break;
7514         case ATH9K_TX_QUEUE_PSPOLL:
7515                 q = 1;
7516                 break;
7517         case ATH9K_TX_QUEUE_UAPSD:
7518                 q = pCap->total_queues - 3;
7519                 break;
7520         case ATH9K_TX_QUEUE_DATA:
7521                 for (q = 0; q < pCap->total_queues; q++)
7522                         if (ahp->ah_txq[q].tqi_type ==
7523                             ATH9K_TX_QUEUE_INACTIVE)
7524                                 break;
7525                 if (q == pCap->total_queues) {
7526                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7527                                  "%s: no available tx queue\n", __func__);
7528                         return -1;
7529                 }
7530                 break;
7531         default:
7532                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
7533                          __func__, type);
7534                 return -1;
7535         }
7536
7537         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
7538
7539         qi = &ahp->ah_txq[q];
7540         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
7541                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7542                          "%s: tx queue %u already active\n", __func__, q);
7543                 return -1;
7544         }
7545         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
7546         qi->tqi_type = type;
7547         if (qinfo == NULL) {
7548                 qi->tqi_qflags =
7549                         TXQ_FLAG_TXOKINT_ENABLE
7550                         | TXQ_FLAG_TXERRINT_ENABLE
7551                         | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7552                 qi->tqi_aifs = INIT_AIFS;
7553                 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
7554                 qi->tqi_cwmax = INIT_CWMAX;
7555                 qi->tqi_shretry = INIT_SH_RETRY;
7556                 qi->tqi_lgretry = INIT_LG_RETRY;
7557                 qi->tqi_physCompBuf = 0;
7558         } else {
7559                 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
7560                 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
7561         }
7562
7563         return q;
7564 }
7565
7566 static void
7567 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7568                             struct ath9k_tx_queue_info *qi)
7569 {
7570         struct ath_hal_5416 *ahp = AH5416(ah);
7571
7572         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
7573                  "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7574                  __func__, ahp->ah_txOkInterruptMask,
7575                  ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7576                  ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7577
7578         REG_WRITE(ah, AR_IMR_S0,
7579                   SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7580                   | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
7581         REG_WRITE(ah, AR_IMR_S1,
7582                   SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7583                   | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
7584         REG_RMW_FIELD(ah, AR_IMR_S2,
7585                       AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7586 }
7587
7588 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
7589 {
7590         struct ath_hal_5416 *ahp = AH5416(ah);
7591         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7592         struct ath9k_tx_queue_info *qi;
7593
7594         if (q >= pCap->total_queues) {
7595                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7596                          __func__, q);
7597                 return false;
7598         }
7599         qi = &ahp->ah_txq[q];
7600         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7601                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7602                          __func__, q);
7603                 return false;
7604         }
7605
7606         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
7607                 __func__, q);
7608
7609         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7610         ahp->ah_txOkInterruptMask &= ~(1 << q);
7611         ahp->ah_txErrInterruptMask &= ~(1 << q);
7612         ahp->ah_txDescInterruptMask &= ~(1 << q);
7613         ahp->ah_txEolInterruptMask &= ~(1 << q);
7614         ahp->ah_txUrnInterruptMask &= ~(1 << q);
7615         ath9k_hw_set_txq_interrupts(ah, qi);
7616
7617         return true;
7618 }
7619
7620 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
7621 {
7622         struct ath_hal_5416 *ahp = AH5416(ah);
7623         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7624         struct ath9k_channel *chan = ah->ah_curchan;
7625         struct ath9k_tx_queue_info *qi;
7626         u32 cwMin, chanCwMin, value;
7627
7628         if (q >= pCap->total_queues) {
7629                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7630                          __func__, q);
7631                 return false;
7632         }
7633         qi = &ahp->ah_txq[q];
7634         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7635                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7636                          __func__, q);
7637                 return true;
7638         }
7639
7640         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
7641
7642         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
7643                 if (chan && IS_CHAN_B(chan))
7644                         chanCwMin = INIT_CWMIN_11B;
7645                 else
7646                         chanCwMin = INIT_CWMIN;
7647
7648                 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
7649         } else
7650                 cwMin = qi->tqi_cwmin;
7651
7652         REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN)
7653                   | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
7654                   | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
7655
7656         REG_WRITE(ah, AR_DRETRY_LIMIT(q),
7657                   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
7658                   | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
7659                   | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
7660                 );
7661
7662         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7663         REG_WRITE(ah, AR_DMISC(q),
7664                   AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7665
7666         if (qi->tqi_cbrPeriod) {
7667                 REG_WRITE(ah, AR_QCBRCFG(q),
7668                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7669                           | SM(qi->tqi_cbrOverflowLimit,
7670                                AR_Q_CBRCFG_OVF_THRESH));
7671                 REG_WRITE(ah, AR_QMISC(q),
7672                           REG_READ(ah,
7673                                    AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7674                                         tqi_cbrOverflowLimit
7675                                         ?
7676                                         AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7677                                         :
7678                                         0));
7679         }
7680         if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
7681                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7682                           SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7683                           AR_Q_RDYTIMECFG_EN);
7684         }
7685
7686         REG_WRITE(ah, AR_DCHNTIME(q),
7687                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7688                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7689
7690         if (qi->tqi_burstTime
7691             && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7692                 REG_WRITE(ah, AR_QMISC(q),
7693                           REG_READ(ah,
7694                                    AR_QMISC(q)) |
7695                           AR_Q_MISC_RDYTIME_EXP_POLICY);
7696
7697         }
7698
7699         if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7700                 REG_WRITE(ah, AR_DMISC(q),
7701                           REG_READ(ah, AR_DMISC(q)) |
7702                           AR_D_MISC_POST_FR_BKOFF_DIS);
7703         }
7704         if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7705                 REG_WRITE(ah, AR_DMISC(q),
7706                           REG_READ(ah, AR_DMISC(q)) |
7707                           AR_D_MISC_FRAG_BKOFF_EN);
7708         }
7709         switch (qi->tqi_type) {
7710         case ATH9K_TX_QUEUE_BEACON:
7711                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7712                           | AR_Q_MISC_FSP_DBA_GATED
7713                           | AR_Q_MISC_BEACON_USE
7714                           | AR_Q_MISC_CBR_INCR_DIS1);
7715
7716                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7717                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7718                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7719                           | AR_D_MISC_BEACON_USE
7720                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7721                 break;
7722         case ATH9K_TX_QUEUE_CAB:
7723                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7724                           | AR_Q_MISC_FSP_DBA_GATED
7725                           | AR_Q_MISC_CBR_INCR_DIS1
7726                           | AR_Q_MISC_CBR_INCR_DIS0);
7727                 value = (qi->tqi_readyTime
7728                          - (ah->ah_config.sw_beacon_response_time -
7729                             ah->ah_config.dma_beacon_response_time)
7730                          -
7731                          ah->ah_config.additional_swba_backoff) *
7732                         1024;
7733                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7734                           value | AR_Q_RDYTIMECFG_EN);
7735                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7736                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7737                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7738                 break;
7739         case ATH9K_TX_QUEUE_PSPOLL:
7740                 REG_WRITE(ah, AR_QMISC(q),
7741                           REG_READ(ah,
7742                                    AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7743                 break;
7744         case ATH9K_TX_QUEUE_UAPSD:
7745                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7746                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7747                 break;
7748         default:
7749                 break;
7750         }
7751
7752         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7753                 REG_WRITE(ah, AR_DMISC(q),
7754                           REG_READ(ah, AR_DMISC(q)) |
7755                           SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7756                              AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7757                           AR_D_MISC_POST_FR_BKOFF_DIS);
7758         }
7759
7760         if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7761                 ahp->ah_txOkInterruptMask |= 1 << q;
7762         else
7763                 ahp->ah_txOkInterruptMask &= ~(1 << q);
7764         if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7765                 ahp->ah_txErrInterruptMask |= 1 << q;
7766         else
7767                 ahp->ah_txErrInterruptMask &= ~(1 << q);
7768         if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7769                 ahp->ah_txDescInterruptMask |= 1 << q;
7770         else
7771                 ahp->ah_txDescInterruptMask &= ~(1 << q);
7772         if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7773                 ahp->ah_txEolInterruptMask |= 1 << q;
7774         else
7775                 ahp->ah_txEolInterruptMask &= ~(1 << q);
7776         if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7777                 ahp->ah_txUrnInterruptMask |= 1 << q;
7778         else
7779                 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7780         ath9k_hw_set_txq_interrupts(ah, qi);
7781
7782         return true;
7783 }
7784
7785 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs)
7786 {
7787         struct ath_hal_5416 *ahp = AH5416(ah);
7788         *txqs &= ahp->ah_intrTxqs;
7789         ahp->ah_intrTxqs &= ~(*txqs);
7790 }
7791
7792 bool
7793 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7794                     u32 segLen, bool firstSeg,
7795                     bool lastSeg, const struct ath_desc *ds0)
7796 {
7797         struct ar5416_desc *ads = AR5416DESC(ds);
7798
7799         if (firstSeg) {
7800                 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7801         } else if (lastSeg) {
7802                 ads->ds_ctl0 = 0;
7803                 ads->ds_ctl1 = segLen;
7804                 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7805                 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7806         } else {
7807                 ads->ds_ctl0 = 0;
7808                 ads->ds_ctl1 = segLen | AR_TxMore;
7809                 ads->ds_ctl2 = 0;
7810                 ads->ds_ctl3 = 0;
7811         }
7812         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7813         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7814         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7815         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7816         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7817         return true;
7818 }
7819
7820 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7821 {
7822         struct ar5416_desc *ads = AR5416DESC(ds);
7823
7824         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7825         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7826         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7827         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7828         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7829 }
7830
7831 int
7832 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7833 {
7834         struct ar5416_desc *ads = AR5416DESC(ds);
7835
7836         if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7837                 return -EINPROGRESS;
7838
7839         ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7840         ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7841         ds->ds_txstat.ts_status = 0;
7842         ds->ds_txstat.ts_flags = 0;
7843
7844         if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7845                 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
7846         if (ads->ds_txstatus1 & AR_Filtered)
7847                 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
7848         if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7849                 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
7850         if (ads->ds_txstatus9 & AR_TxOpExceeded)
7851                 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
7852         if (ads->ds_txstatus1 & AR_TxTimerExpired)
7853                 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
7854
7855         if (ads->ds_txstatus1 & AR_DescCfgErr)
7856                 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
7857         if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7858                 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
7859                 ath9k_hw_updatetxtriglevel(ah, true);
7860         }
7861         if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7862                 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
7863                 ath9k_hw_updatetxtriglevel(ah, true);
7864         }
7865         if (ads->ds_txstatus0 & AR_TxBaStatus) {
7866                 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
7867                 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7868                 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7869         }
7870
7871         ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
7872         switch (ds->ds_txstat.ts_rateindex) {
7873         case 0:
7874                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
7875                 break;
7876         case 1:
7877                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
7878                 break;
7879         case 2:
7880                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
7881                 break;
7882         case 3:
7883                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7884                 break;
7885         }
7886
7887         ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7888         ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7889         ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7890         ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7891         ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7892         ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7893         ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7894         ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7895         ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7896         ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7897         ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7898         ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7899         ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7900         ds->ds_txstat.ts_antenna = 1;
7901
7902         return 0;
7903 }
7904
7905 void
7906 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7907                        u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
7908                        u32 keyIx, enum ath9k_key_type keyType, u32 flags)
7909 {
7910         struct ar5416_desc *ads = AR5416DESC(ds);
7911         struct ath_hal_5416 *ahp = AH5416(ah);
7912
7913         txPower += ahp->ah_txPowerIndexOffset;
7914         if (txPower > 63)
7915                 txPower = 63;
7916
7917         ads->ds_ctl0 = (pktLen & AR_FrameLen)
7918                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7919                 | SM(txPower, AR_XmitPower)
7920                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
7921                 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7922                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7923                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7924
7925         ads->ds_ctl1 =
7926                 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7927                 | SM(type, AR_FrameType)
7928                 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
7929                 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7930                 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7931
7932         ads->ds_ctl6 = SM(keyType, AR_EncrType);
7933
7934         if (AR_SREV_9285(ah)) {
7935
7936                 ads->ds_ctl8 = 0;
7937                 ads->ds_ctl9 = 0;
7938                 ads->ds_ctl10 = 0;
7939                 ads->ds_ctl11 = 0;
7940         }
7941 }
7942
7943 void
7944 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
7945                              struct ath_desc *lastds,
7946                              u32 durUpdateEn, u32 rtsctsRate,
7947                              u32 rtsctsDuration,
7948                              struct ath9k_11n_rate_series series[],
7949                              u32 nseries, u32 flags)
7950 {
7951         struct ar5416_desc *ads = AR5416DESC(ds);
7952         struct ar5416_desc *last_ads = AR5416DESC(lastds);
7953         u32 ds_ctl0;
7954
7955         (void) nseries;
7956         (void) rtsctsDuration;
7957
7958         if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
7959                 ds_ctl0 = ads->ds_ctl0;
7960
7961                 if (flags & ATH9K_TXDESC_RTSENA) {
7962                         ds_ctl0 &= ~AR_CTSEnable;
7963                         ds_ctl0 |= AR_RTSEnable;
7964                 } else {
7965                         ds_ctl0 &= ~AR_RTSEnable;
7966                         ds_ctl0 |= AR_CTSEnable;
7967                 }
7968
7969                 ads->ds_ctl0 = ds_ctl0;
7970         } else {
7971                 ads->ds_ctl0 =
7972                         (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
7973         }
7974
7975         ads->ds_ctl2 = set11nTries(series, 0)
7976                 | set11nTries(series, 1)
7977                 | set11nTries(series, 2)
7978                 | set11nTries(series, 3)
7979                 | (durUpdateEn ? AR_DurUpdateEna : 0)
7980                 | SM(0, AR_BurstDur);
7981
7982         ads->ds_ctl3 = set11nRate(series, 0)
7983                 | set11nRate(series, 1)
7984                 | set11nRate(series, 2)
7985                 | set11nRate(series, 3);
7986
7987         ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
7988                 | set11nPktDurRTSCTS(series, 1);
7989
7990         ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
7991                 | set11nPktDurRTSCTS(series, 3);
7992
7993         ads->ds_ctl7 = set11nRateFlags(series, 0)
7994                 | set11nRateFlags(series, 1)
7995                 | set11nRateFlags(series, 2)
7996                 | set11nRateFlags(series, 3)
7997                 | SM(rtsctsRate, AR_RTSCTSRate);
7998         last_ads->ds_ctl2 = ads->ds_ctl2;
7999         last_ads->ds_ctl3 = ads->ds_ctl3;
8000 }
8001
8002 void
8003 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
8004                            u32 aggrLen)
8005 {
8006         struct ar5416_desc *ads = AR5416DESC(ds);
8007
8008         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8009
8010         ads->ds_ctl6 &= ~AR_AggrLen;
8011         ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
8012 }
8013
8014 void
8015 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
8016                             u32 numDelims)
8017 {
8018         struct ar5416_desc *ads = AR5416DESC(ds);
8019         unsigned int ctl6;
8020
8021         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8022
8023         ctl6 = ads->ds_ctl6;
8024         ctl6 &= ~AR_PadDelim;
8025         ctl6 |= SM(numDelims, AR_PadDelim);
8026         ads->ds_ctl6 = ctl6;
8027 }
8028
8029 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
8030 {
8031         struct ar5416_desc *ads = AR5416DESC(ds);
8032
8033         ads->ds_ctl1 |= AR_IsAggr;
8034         ads->ds_ctl1 &= ~AR_MoreAggr;
8035         ads->ds_ctl6 &= ~AR_PadDelim;
8036 }
8037
8038 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
8039 {
8040         struct ar5416_desc *ads = AR5416DESC(ds);
8041
8042         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
8043 }
8044
8045 void
8046 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8047                               u32 burstDuration)
8048 {
8049         struct ar5416_desc *ads = AR5416DESC(ds);
8050
8051         ads->ds_ctl2 &= ~AR_BurstDur;
8052         ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
8053 }
8054
8055 void
8056 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
8057                                 u32 vmf)
8058 {
8059         struct ar5416_desc *ads = AR5416DESC(ds);
8060
8061         if (vmf)
8062                 ads->ds_ctl0 |= AR_VirtMoreFrag;
8063         else
8064                 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8065 }
8066
8067 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp)
8068 {
8069         REG_WRITE(ah, AR_RXDP, rxdp);
8070 }
8071
8072 void ath9k_hw_rxena(struct ath_hal *ah)
8073 {
8074         REG_WRITE(ah, AR_CR, AR_CR_RXE);
8075 }
8076
8077 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
8078 {
8079         if (set) {
8080
8081                 REG_SET_BIT(ah, AR_DIAG_SW,
8082                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8083
8084                 if (!ath9k_hw_wait
8085                     (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8086                         u32 reg;
8087
8088                         REG_CLR_BIT(ah, AR_DIAG_SW,
8089                                     (AR_DIAG_RX_DIS |
8090                                      AR_DIAG_RX_ABORT));
8091
8092                         reg = REG_READ(ah, AR_OBS_BUS_1);
8093                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
8094                                 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
8095                                 __func__, reg);
8096
8097                         return false;
8098                 }
8099         } else {
8100                 REG_CLR_BIT(ah, AR_DIAG_SW,
8101                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8102         }
8103
8104         return true;
8105 }
8106
8107 void
8108 ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
8109                         u32 filter1)
8110 {
8111         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8112         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8113 }
8114
8115 bool
8116 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8117                      u32 size, u32 flags)
8118 {
8119         struct ar5416_desc *ads = AR5416DESC(ds);
8120         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
8121
8122         ads->ds_ctl1 = size & AR_BufLen;
8123         if (flags & ATH9K_RXDESC_INTREQ)
8124                 ads->ds_ctl1 |= AR_RxIntrReq;
8125
8126         ads->ds_rxstatus8 &= ~AR_RxDone;
8127         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8128                 memset(&(ads->u), 0, sizeof(ads->u));
8129         return true;
8130 }
8131
8132 int
8133 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8134                     u32 pa, struct ath_desc *nds, u64 tsf)
8135 {
8136         struct ar5416_desc ads;
8137         struct ar5416_desc *adsp = AR5416DESC(ds);
8138
8139         if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8140                 return -EINPROGRESS;
8141
8142         ads.u.rx = adsp->u.rx;
8143
8144         ds->ds_rxstat.rs_status = 0;
8145         ds->ds_rxstat.rs_flags = 0;
8146
8147         ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
8148         ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
8149
8150         ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
8151         ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
8152         ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
8153         ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8154         ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8155         ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8156         ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8157         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8158                 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8159         else
8160                 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
8161
8162         ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8163         ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8164
8165         ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8166         ds->ds_rxstat.rs_moreaggr =
8167                 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8168         ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8169         ds->ds_rxstat.rs_flags =
8170                 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8171         ds->ds_rxstat.rs_flags |=
8172                 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
8173
8174         if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8175                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
8176         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8177                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
8178         if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8179                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
8180
8181         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8182
8183                 if (ads.ds_rxstatus8 & AR_CRCErr)
8184                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
8185                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8186                         u32 phyerr;
8187
8188                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
8189                         phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8190                         ds->ds_rxstat.rs_phyerr = phyerr;
8191                 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8192                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
8193                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8194                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
8195         }
8196
8197         return 0;
8198 }
8199
8200 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
8201                                       struct ath9k_rate_table *rt)
8202 {
8203         int i;
8204
8205         if (rt->rateCodeToIndex[0] != 0)
8206                 return;
8207         for (i = 0; i < 256; i++)
8208                 rt->rateCodeToIndex[i] = (u8) -1;
8209         for (i = 0; i < rt->rateCount; i++) {
8210                 u8 code = rt->info[i].rateCode;
8211                 u8 cix = rt->info[i].controlRate;
8212
8213                 rt->rateCodeToIndex[code] = i;
8214                 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8215
8216                 rt->info[i].lpAckDuration =
8217                         ath9k_hw_computetxtime(ah, rt,
8218                                                WLAN_CTRL_FRAME_SIZE,
8219                                                cix,
8220                                                false);
8221                 rt->info[i].spAckDuration =
8222                         ath9k_hw_computetxtime(ah, rt,
8223                                                WLAN_CTRL_FRAME_SIZE,
8224                                                cix,
8225                                                true);
8226         }
8227 }
8228
8229 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
8230                                                    u32 mode)
8231 {
8232         struct ath9k_rate_table *rt;
8233         switch (mode) {
8234         case ATH9K_MODE_11A:
8235                 rt = &ar5416_11a_table;
8236                 break;
8237         case ATH9K_MODE_11B:
8238                 rt = &ar5416_11b_table;
8239                 break;
8240         case ATH9K_MODE_11G:
8241                 rt = &ar5416_11g_table;
8242                 break;
8243         case ATH9K_MODE_11NG_HT20:
8244         case ATH9K_MODE_11NG_HT40PLUS:
8245         case ATH9K_MODE_11NG_HT40MINUS:
8246                 rt = &ar5416_11ng_table;
8247                 break;
8248         case ATH9K_MODE_11NA_HT20:
8249         case ATH9K_MODE_11NA_HT40PLUS:
8250         case ATH9K_MODE_11NA_HT40MINUS:
8251                 rt = &ar5416_11na_table;
8252                 break;
8253         default:
8254                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8255                          __func__, mode);
8256                 return NULL;
8257         }
8258         ath9k_hw_setup_rate_table(ah, rt);
8259         return rt;
8260 }
8261
8262 static const char *ath9k_hw_devname(u16 devid)
8263 {
8264         switch (devid) {
8265         case AR5416_DEVID_PCI:
8266         case AR5416_DEVID_PCIE:
8267                 return "Atheros 5416";
8268         case AR9160_DEVID_PCI:
8269                 return "Atheros 9160";
8270         case AR9280_DEVID_PCI:
8271         case AR9280_DEVID_PCIE:
8272                 return "Atheros 9280";
8273         }
8274         return NULL;
8275 }
8276
8277 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
8278 {
8279         return vendorid == ATHEROS_VENDOR_ID ?
8280                 ath9k_hw_devname(devid) : NULL;
8281 }
8282
8283 struct ath_hal *ath9k_hw_attach(u16 devid,
8284                                 struct ath_softc *sc,
8285                                 void __iomem *mem,
8286                                 int *error)
8287 {
8288         struct ath_hal *ah = NULL;
8289
8290         switch (devid) {
8291         case AR5416_DEVID_PCI:
8292         case AR5416_DEVID_PCIE:
8293         case AR9160_DEVID_PCI:
8294         case AR9280_DEVID_PCI:
8295         case AR9280_DEVID_PCIE:
8296                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
8297                 break;
8298         default:
8299                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
8300                          "devid=0x%x not supported.\n", devid);
8301                 ah = NULL;
8302                 *error = -ENXIO;
8303                 break;
8304         }
8305         if (ah != NULL) {
8306                 ah->ah_devid = ah->ah_devid;
8307                 ah->ah_subvendorid = ah->ah_subvendorid;
8308                 ah->ah_macVersion = ah->ah_macVersion;
8309                 ah->ah_macRev = ah->ah_macRev;
8310                 ah->ah_phyRev = ah->ah_phyRev;
8311                 ah->ah_analog5GhzRev = ah->ah_analog5GhzRev;
8312                 ah->ah_analog2GhzRev = ah->ah_analog2GhzRev;
8313         }
8314         return ah;
8315 }
8316
8317 u16
8318 ath9k_hw_computetxtime(struct ath_hal *ah,
8319                        const struct ath9k_rate_table *rates,
8320                        u32 frameLen, u16 rateix,
8321                        bool shortPreamble)
8322 {
8323         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
8324         u32 kbps;
8325
8326         kbps = rates->info[rateix].rateKbps;
8327
8328         if (kbps == 0)
8329                 return 0;
8330         switch (rates->info[rateix].phy) {
8331
8332         case PHY_CCK:
8333                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8334                 if (shortPreamble && rates->info[rateix].shortPreamble)
8335                         phyTime >>= 1;
8336                 numBits = frameLen << 3;
8337                 txTime = CCK_SIFS_TIME + phyTime
8338                         + ((numBits * 1000) / kbps);
8339                 break;
8340         case PHY_OFDM:
8341                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8342                         bitsPerSymbol =
8343                                 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8344
8345                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8346                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8347                         txTime = OFDM_SIFS_TIME_QUARTER
8348                                 + OFDM_PREAMBLE_TIME_QUARTER
8349                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8350                 } else if (ah->ah_curchan &&
8351                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8352                         bitsPerSymbol =
8353                                 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8354
8355                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8356                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8357                         txTime = OFDM_SIFS_TIME_HALF +
8358                                 OFDM_PREAMBLE_TIME_HALF
8359                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8360                 } else {
8361                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8362
8363                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8364                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8365                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8366                                 + (numSymbols * OFDM_SYMBOL_TIME);
8367                 }
8368                 break;
8369
8370         default:
8371                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
8372                          "%s: unknown phy %u (rate ix %u)\n", __func__,
8373                          rates->info[rateix].phy, rateix);
8374                 txTime = 0;
8375                 break;
8376         }
8377         return txTime;
8378 }
8379
8380 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
8381 {
8382         if (flags & CHANNEL_2GHZ) {
8383                 if (freq == 2484)
8384                         return 14;
8385                 if (freq < 2484)
8386                         return (freq - 2407) / 5;
8387                 else
8388                         return 15 + ((freq - 2512) / 20);
8389         } else if (flags & CHANNEL_5GHZ) {
8390                 if (ath9k_regd_is_public_safety_sku(ah) &&
8391                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8392                         return ((freq * 10) +
8393                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8394                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8395                         return (freq - 4000) / 5;
8396                 } else {
8397                         return (freq - 5000) / 5;
8398                 }
8399         } else {
8400                 if (freq == 2484)
8401                         return 14;
8402                 if (freq < 2484)
8403                         return (freq - 2407) / 5;
8404                 if (freq < 5000) {
8405                         if (ath9k_regd_is_public_safety_sku(ah)
8406                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8407                                 return ((freq * 10) +
8408                                         (((freq % 5) ==
8409                                           2) ? 5 : 0) - 49400) / 5;
8410                         } else if (freq > 4900) {
8411                                 return (freq - 4000) / 5;
8412                         } else {
8413                                 return 15 + ((freq - 2512) / 20);
8414                         }
8415                 }
8416                 return (freq - 5000) / 5;
8417         }
8418 }
8419
8420 int16_t
8421 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
8422 {
8423         struct ath9k_channel *ichan;
8424
8425         ichan = ath9k_regd_check_channel(ah, chan);
8426         if (ichan == NULL) {
8427                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8428                          "%s: invalid channel %u/0x%x; no mapping\n",
8429                          __func__, chan->channel, chan->channelFlags);
8430                 return 0;
8431         }
8432         if (ichan->rawNoiseFloor == 0) {
8433                 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8434                 return NOISE_FLOOR[mode];
8435         } else
8436                 return ichan->rawNoiseFloor;
8437 }
8438
8439 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
8440 {
8441         struct ath_hal_5416 *ahp = AH5416(ah);
8442
8443         if (setting)
8444                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8445         else
8446                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8447         return true;
8448 }
8449
8450 bool ath9k_hw_phycounters(struct ath_hal *ah)
8451 {
8452         struct ath_hal_5416 *ahp = AH5416(ah);
8453
8454         return ahp->ah_hasHwPhyCounters ? true : false;
8455 }
8456
8457 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q)
8458 {
8459         return REG_READ(ah, AR_QTXDP(q));
8460 }
8461
8462 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
8463                        u32 txdp)
8464 {
8465         REG_WRITE(ah, AR_QTXDP(q), txdp);
8466
8467         return true;
8468 }
8469
8470 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
8471 {
8472         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
8473
8474         REG_WRITE(ah, AR_Q_TXE, 1 << q);
8475
8476         return true;
8477 }
8478
8479 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
8480 {
8481         u32 npend;
8482
8483         npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
8484         if (npend == 0) {
8485
8486                 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
8487                         npend = 1;
8488         }
8489         return npend;
8490 }
8491
8492 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
8493 {
8494         u32 wait;
8495
8496         REG_WRITE(ah, AR_Q_TXD, 1 << q);
8497
8498         for (wait = 1000; wait != 0; wait--) {
8499                 if (ath9k_hw_numtxpending(ah, q) == 0)
8500                         break;
8501                 udelay(100);
8502         }
8503
8504         if (ath9k_hw_numtxpending(ah, q)) {
8505                 u32 tsfLow, j;
8506
8507                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8508                          "%s: Num of pending TX Frames %d on Q %d\n",
8509                          __func__, ath9k_hw_numtxpending(ah, q), q);
8510
8511                 for (j = 0; j < 2; j++) {
8512                         tsfLow = REG_READ(ah, AR_TSF_L32);
8513                         REG_WRITE(ah, AR_QUIET2,
8514                                   SM(10, AR_QUIET2_QUIET_DUR));
8515                         REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8516                         REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8517                         REG_SET_BIT(ah, AR_TIMER_MODE,
8518                                        AR_QUIET_TIMER_EN);
8519
8520                         if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
8521                             (tsfLow >> 10)) {
8522                                 break;
8523                         }
8524                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8525                                 "%s: TSF have moved while trying to set "
8526                                 "quiet time TSF: 0x%08x\n",
8527                                 __func__, tsfLow);
8528                 }
8529
8530                 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8531
8532                 udelay(200);
8533                 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
8534
8535                 wait = 1000;
8536
8537                 while (ath9k_hw_numtxpending(ah, q)) {
8538                         if ((--wait) == 0) {
8539                                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
8540                                         "%s: Failed to stop Tx DMA in 100 "
8541                                         "msec after killing last frame\n",
8542                                         __func__);
8543                                 break;
8544                         }
8545                         udelay(100);
8546                 }
8547
8548                 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8549         }
8550
8551         REG_WRITE(ah, AR_Q_TXD, 0);
8552         return wait != 0;
8553 }