drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->ah_curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->ah_curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val)
  88 {
  89         int i;
  90
  91         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
  92                 if ((REG_READ(ah, reg) & mask) == val)
  93                         return true;
  94
  95                 udelay(AH_TIME_QUANTUM);
  96         }
  97
  98         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
  99                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 100                 reg, REG_READ(ah, reg), mask, val);
 101
 102         return false;
 103 }
 104
 105 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 106 {
 107         u32 retval;
 108         int i;
 109
 110         for (i = 0, retval = 0; i < n; i++) {
 111                 retval = (retval << 1) | (val & 1);
 112                 val >>= 1;
 113         }
 114         return retval;
 115 }
 116
 117 bool ath9k_get_channel_edges(struct ath_hw *ah,
 118                              u16 flags, u16 *low,
 119                              u16 *high)
 120 {
 121         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 122
 123         if (flags & CHANNEL_5GHZ) {
 124                 *low = pCap->low_5ghz_chan;
 125                 *high = pCap->high_5ghz_chan;
 126                 return true;
 127         }
 128         if ((flags & CHANNEL_2GHZ)) {
 129                 *low = pCap->low_2ghz_chan;
 130                 *high = pCap->high_2ghz_chan;
 131                 return true;
 132         }
 133         return false;
 134 }
 135
 136 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 137                            struct ath_rate_table *rates,
 138                            u32 frameLen, u16 rateix,
 139                            bool shortPreamble)
 140 {
 141         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 142         u32 kbps;
 143
 144         kbps = rates->info[rateix].ratekbps;
 145
 146         if (kbps == 0)
 147                 return 0;
 148
 149         switch (rates->info[rateix].phy) {
 150         case WLAN_RC_PHY_CCK:
 151                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 152                 if (shortPreamble && rates->info[rateix].short_preamble)
 153                         phyTime >>= 1;
 154                 numBits = frameLen << 3;
 155                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 156                 break;
 157         case WLAN_RC_PHY_OFDM:
 158                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 159                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 160                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 161                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 162                         txTime = OFDM_SIFS_TIME_QUARTER
 163                                 + OFDM_PREAMBLE_TIME_QUARTER
 164                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 165                 } else if (ah->ah_curchan &&
 166                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 167                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 168                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 169                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 170                         txTime = OFDM_SIFS_TIME_HALF +
 171                                 OFDM_PREAMBLE_TIME_HALF
 172                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 173                 } else {
 174                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 175                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 176                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 177                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 178                                 + (numSymbols * OFDM_SYMBOL_TIME);
 179                 }
 180                 break;
 181         default:
 182                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 183                         "Unknown phy %u (rate ix %u)\n",
 184                         rates->info[rateix].phy, rateix);
 185                 txTime = 0;
 186                 break;
 187         }
 188
 189         return txTime;
 190 }
 191
 192 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 193                                   struct ath9k_channel *chan,
 194                                   struct chan_centers *centers)
 195 {
 196         int8_t extoff;
 197
 198         if (!IS_CHAN_HT40(chan)) {
 199                 centers->ctl_center = centers->ext_center =
 200                         centers->synth_center = chan->channel;
 201                 return;
 202         }
 203
 204         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 205             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 206                 centers->synth_center =
 207                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 208                 extoff = 1;
 209         } else {
 210                 centers->synth_center =
 211                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 212                 extoff = -1;
 213         }
 214
 215         centers->ctl_center =
 216                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 217         centers->ext_center =
 218                 centers->synth_center + (extoff *
 219                          ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 220                           HT40_CHANNEL_CENTER_SHIFT : 15));
 221 }
 222
 223 /******************/
 224 /* Chip Revisions */
 225 /******************/
 226
 227 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 228 {
 229         u32 val;
 230
 231         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 232
 233         if (val == 0xFF) {
 234                 val = REG_READ(ah, AR_SREV);
 235                 ah->hw_version.macVersion =
 236                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 237                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 238                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 239         } else {
 240                 if (!AR_SREV_9100(ah))
 241                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 242
 243                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 244
 245                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 246                         ah->ah_isPciExpress = true;
 247         }
 248 }
 249
 250 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 251 {
 252         u32 val;
 253         int i;
 254
 255         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 256
 257         for (i = 0; i < 8; i++)
 258                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 259         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 260         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 261
 262         return ath9k_hw_reverse_bits(val, 8);
 263 }
 264
 265 /************************************/
 266 /* HW Attach, Detach, Init Routines */
 267 /************************************/
 268
 269 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 270 {
 271         if (AR_SREV_9100(ah))
 272                 return;
 273
 274         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 275         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 283
 284         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 285 }
 286
 287 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 288 {
 289         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 290         u32 regHold[2];
 291         u32 patternData[4] = { 0x55555555,
 292                                0xaaaaaaaa,
 293                                0x66666666,
 294                                0x99999999 };
 295         int i, j;
 296
 297         for (i = 0; i < 2; i++) {
 298                 u32 addr = regAddr[i];
 299                 u32 wrData, rdData;
 300
 301                 regHold[i] = REG_READ(ah, addr);
 302                 for (j = 0; j < 0x100; j++) {
 303                         wrData = (j << 16) | j;
 304                         REG_WRITE(ah, addr, wrData);
 305                         rdData = REG_READ(ah, addr);
 306                         if (rdData != wrData) {
 307                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 308                                         "address test failed "
 309                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 310                                         addr, wrData, rdData);
 311                                 return false;
 312                         }
 313                 }
 314                 for (j = 0; j < 4; j++) {
 315                         wrData = patternData[j];
 316                         REG_WRITE(ah, addr, wrData);
 317                         rdData = REG_READ(ah, addr);
 318                         if (wrData != rdData) {
 319                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 320                                         "address test failed "
 321                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 322                                         addr, wrData, rdData);
 323                                 return false;
 324                         }
 325                 }
 326                 REG_WRITE(ah, regAddr[i], regHold[i]);
 327         }
 328         udelay(100);
 329
 330         return true;
 331 }
 332
 333 static const char *ath9k_hw_devname(u16 devid)
 334 {
 335         switch (devid) {
 336         case AR5416_DEVID_PCI:
 337                 return "Atheros 5416";
 338         case AR5416_DEVID_PCIE:
 339                 return "Atheros 5418";
 340         case AR9160_DEVID_PCI:
 341                 return "Atheros 9160";
 342         case AR5416_AR9100_DEVID:
 343                 return "Atheros 9100";
 344         case AR9280_DEVID_PCI:
 345         case AR9280_DEVID_PCIE:
 346                 return "Atheros 9280";
 347         case AR9285_DEVID_PCIE:
 348                 return "Atheros 9285";
 349         }
 350
 351         return NULL;
 352 }
 353
 354 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 355 {
 356         int i;
 357
 358         ah->ah_config.dma_beacon_response_time = 2;
 359         ah->ah_config.sw_beacon_response_time = 10;
 360         ah->ah_config.additional_swba_backoff = 0;
 361         ah->ah_config.ack_6mb = 0x0;
 362         ah->ah_config.cwm_ignore_extcca = 0;
 363         ah->ah_config.pcie_powersave_enable = 0;
 364         ah->ah_config.pcie_l1skp_enable = 0;
 365         ah->ah_config.pcie_clock_req = 0;
 366         ah->ah_config.pcie_power_reset = 0x100;
 367         ah->ah_config.pcie_restore = 0;
 368         ah->ah_config.pcie_waen = 0;
 369         ah->ah_config.analog_shiftreg = 1;
 370         ah->ah_config.ht_enable = 1;
 371         ah->ah_config.ofdm_trig_low = 200;
 372         ah->ah_config.ofdm_trig_high = 500;
 373         ah->ah_config.cck_trig_high = 200;
 374         ah->ah_config.cck_trig_low = 100;
 375         ah->ah_config.enable_ani = 1;
 376         ah->ah_config.noise_immunity_level = 4;
 377         ah->ah_config.ofdm_weaksignal_det = 1;
 378         ah->ah_config.cck_weaksignal_thr = 0;
 379         ah->ah_config.spur_immunity_level = 2;
 380         ah->ah_config.firstep_level = 0;
 381         ah->ah_config.rssi_thr_high = 40;
 382         ah->ah_config.rssi_thr_low = 7;
 383         ah->ah_config.diversity_control = 0;
 384         ah->ah_config.antenna_switch_swap = 0;
 385
 386         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 387                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 388                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 389         }
 390
 391         ah->ah_config.intr_mitigation = 1;
 392 }
 393
 394 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 395                                         int *status)
 396 {
 397         struct ath_hw *ah;
 398
 399         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 400         if (ah == NULL) {
 401                 DPRINTF(sc, ATH_DBG_FATAL,
 402                         "Cannot allocate memory for state block\n");
 403                 *status = -ENOMEM;
 404                 return NULL;
 405         }
 406
 407         ah->ah_sc = sc;
 408         ah->hw_version.magic = AR5416_MAGIC;
 409         ah->regulatory.country_code = CTRY_DEFAULT;
 410         ah->hw_version.devid = devid;
 411         ah->hw_version.subvendorid = 0;
 412
 413         ah->ah_flags = 0;
 414         if ((devid == AR5416_AR9100_DEVID))
 415                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 416         if (!AR_SREV_9100(ah))
 417                 ah->ah_flags = AH_USE_EEPROM;
 418
 419         ah->regulatory.power_limit = MAX_RATE_POWER;
 420         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 421         ah->ah_atimWindow = 0;
 422         ah->ah_diversityControl = ah->ah_config.diversity_control;
 423         ah->ah_antennaSwitchSwap =
 424                 ah->ah_config.antenna_switch_swap;
 425         ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 426         ah->ah_beaconInterval = 100;
 427         ah->ah_enable32kHzClock = DONT_USE_32KHZ;
 428         ah->ah_slottime = (u32) -1;
 429         ah->ah_acktimeout = (u32) -1;
 430         ah->ah_ctstimeout = (u32) -1;
 431         ah->ah_globaltxtimeout = (u32) -1;
 432
 433         ah->ah_gBeaconRate = 0;
 434
 435         return ah;
 436 }
 437
 438 static int ath9k_hw_rfattach(struct ath_hw *ah)
 439 {
 440         bool rfStatus = false;
 441         int ecode = 0;
 442
 443         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 444         if (!rfStatus) {
 445                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 446                         "RF setup failed, status %u\n", ecode);
 447                 return ecode;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 454 {
 455         u32 val;
 456
 457         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 458
 459         val = ath9k_hw_get_radiorev(ah);
 460         switch (val & AR_RADIO_SREV_MAJOR) {
 461         case 0:
 462                 val = AR_RAD5133_SREV_MAJOR;
 463                 break;
 464         case AR_RAD5133_SREV_MAJOR:
 465         case AR_RAD5122_SREV_MAJOR:
 466         case AR_RAD2133_SREV_MAJOR:
 467         case AR_RAD2122_SREV_MAJOR:
 468                 break;
 469         default:
 470                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 471                         "5G Radio Chip Rev 0x%02X is not "
 472                         "supported by this driver\n",
 473                         ah->hw_version.analog5GhzRev);
 474                 return -EOPNOTSUPP;
 475         }
 476
 477         ah->hw_version.analog5GhzRev = val;
 478
 479         return 0;
 480 }
 481
 482 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 483 {
 484         u32 sum;
 485         int i;
 486         u16 eeval;
 487
 488         sum = 0;
 489         for (i = 0; i < 3; i++) {
 490                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 491                 sum += eeval;
 492                 ah->macaddr[2 * i] = eeval >> 8;
 493                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 494         }
 495         if (sum == 0 || sum == 0xffff * 3) {
 496                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 497                         "mac address read failed: %pM\n",
 498                         ah->macaddr);
 499                 return -EADDRNOTAVAIL;
 500         }
 501
 502         return 0;
 503 }
 504
 505 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 506 {
 507         u32 rxgain_type;
 508
 509         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 510                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 511
 512                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 513                         INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
 514                         ar9280Modes_backoff_13db_rxgain_9280_2,
 515                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 516                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 517                         INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
 518                         ar9280Modes_backoff_23db_rxgain_9280_2,
 519                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 520                 else
 521                         INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
 522                         ar9280Modes_original_rxgain_9280_2,
 523                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 524         } else {
 525                 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
 526                         ar9280Modes_original_rxgain_9280_2,
 527                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 528         }
 529 }
 530
 531 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 532 {
 533         u32 txgain_type;
 534
 535         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 536                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 537
 538                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 539                         INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
 540                         ar9280Modes_high_power_tx_gain_9280_2,
 541                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 542                 else
 543                         INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
 544                         ar9280Modes_original_tx_gain_9280_2,
 545                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 546         } else {
 547                 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
 548                 ar9280Modes_original_tx_gain_9280_2,
 549                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 550         }
 551 }
 552
 553 static int ath9k_hw_post_attach(struct ath_hw *ah)
 554 {
 555         int ecode;
 556
 557         if (!ath9k_hw_chip_test(ah)) {
 558                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 559                         "hardware self-test failed\n");
 560                 return -ENODEV;
 561         }
 562
 563         ecode = ath9k_hw_rf_claim(ah);
 564         if (ecode != 0)
 565                 return ecode;
 566
 567         ecode = ath9k_hw_eeprom_attach(ah);
 568         if (ecode != 0)
 569                 return ecode;
 570         ecode = ath9k_hw_rfattach(ah);
 571         if (ecode != 0)
 572                 return ecode;
 573
 574         if (!AR_SREV_9100(ah)) {
 575                 ath9k_hw_ani_setup(ah);
 576                 ath9k_hw_ani_attach(ah);
 577         }
 578
 579         return 0;
 580 }
 581
 582 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 583                                          int *status)
 584 {
 585         struct ath_hw *ah;
 586         int ecode;
 587         u32 i, j;
 588
 589         ah = ath9k_hw_newstate(devid, sc, status);
 590         if (ah == NULL)
 591                 return NULL;
 592
 593         ath9k_hw_set_defaults(ah);
 594
 595         if (ah->ah_config.intr_mitigation != 0)
 596                 ah->ah_intrMitigation = true;
 597
 598         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 599                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 600                 ecode = -EIO;
 601                 goto bad;
 602         }
 603
 604         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 605                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 606                 ecode = -EIO;
 607                 goto bad;
 608         }
 609
 610         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 611                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
 612                         ah->ah_config.serialize_regmode =
 613                                 SER_REG_MODE_ON;
 614                 } else {
 615                         ah->ah_config.serialize_regmode =
 616                                 SER_REG_MODE_OFF;
 617                 }
 618         }
 619
 620         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 621                 ah->ah_config.serialize_regmode);
 622
 623         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 624             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 625             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 626             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 627                 DPRINTF(sc, ATH_DBG_RESET,
 628                         "Mac Chip Rev 0x%02x.%x is not supported by "
 629                         "this driver\n", ah->hw_version.macVersion,
 630                         ah->hw_version.macRev);
 631                 ecode = -EOPNOTSUPP;
 632                 goto bad;
 633         }
 634
 635         if (AR_SREV_9100(ah)) {
 636                 ah->ah_iqCalData.calData = &iq_cal_multi_sample;
 637                 ah->ah_suppCals = IQ_MISMATCH_CAL;
 638                 ah->ah_isPciExpress = false;
 639         }
 640         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 641
 642         if (AR_SREV_9160_10_OR_LATER(ah)) {
 643                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 644                         ah->ah_iqCalData.calData = &iq_cal_single_sample;
 645                         ah->ah_adcGainCalData.calData =
 646                                 &adc_gain_cal_single_sample;
 647                         ah->ah_adcDcCalData.calData =
 648                                 &adc_dc_cal_single_sample;
 649                         ah->ah_adcDcCalInitData.calData =
 650                                 &adc_init_dc_cal;
 651                 } else {
 652                         ah->ah_iqCalData.calData = &iq_cal_multi_sample;
 653                         ah->ah_adcGainCalData.calData =
 654                                 &adc_gain_cal_multi_sample;
 655                         ah->ah_adcDcCalData.calData =
 656                                 &adc_dc_cal_multi_sample;
 657                         ah->ah_adcDcCalInitData.calData =
 658                                 &adc_init_dc_cal;
 659                 }
 660                 ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 661         }
 662
 663         if (AR_SREV_9160(ah)) {
 664                 ah->ah_config.enable_ani = 1;
 665                 ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 666                                         ATH9K_ANI_FIRSTEP_LEVEL);
 667         } else {
 668                 ah->ah_ani_function = ATH9K_ANI_ALL;
 669                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 670                         ah->ah_ani_function &=  ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 671                 }
 672         }
 673
 674         DPRINTF(sc, ATH_DBG_RESET,
 675                 "This Mac Chip Rev 0x%02x.%x is \n",
 676                 ah->hw_version.macVersion, ah->hw_version.macRev);
 677
 678         if (AR_SREV_9285_12_OR_LATER(ah)) {
 679                 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2,
 680                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 681                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2,
 682                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 683
 684                 if (ah->ah_config.pcie_clock_req) {
 685                         INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
 686                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 687                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 688                 } else {
 689                         INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
 690                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 691                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 692                                   2);
 693                 }
 694         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 695                 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285,
 696                                ARRAY_SIZE(ar9285Modes_9285), 6);
 697                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285,
 698                                ARRAY_SIZE(ar9285Common_9285), 2);
 699
 700                 if (ah->ah_config.pcie_clock_req) {
 701                         INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
 702                         ar9285PciePhy_clkreq_off_L1_9285,
 703                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 704                 } else {
 705                         INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
 706                         ar9285PciePhy_clkreq_always_on_L1_9285,
 707                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 708                 }
 709         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 710                 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2,
 711                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 712                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2,
 713                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 714
 715                 if (ah->ah_config.pcie_clock_req) {
 716                         INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
 717                                ar9280PciePhy_clkreq_off_L1_9280,
 718                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 719                 } else {
 720                         INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
 721                                ar9280PciePhy_clkreq_always_on_L1_9280,
 722                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 723                 }
 724                 INIT_INI_ARRAY(&ah->ah_iniModesAdditional,
 725                                ar9280Modes_fast_clock_9280_2,
 726                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 727         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 728                 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280,
 729                                ARRAY_SIZE(ar9280Modes_9280), 6);
 730                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280,
 731                                ARRAY_SIZE(ar9280Common_9280), 2);
 732         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 733                 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160,
 734                                ARRAY_SIZE(ar5416Modes_9160), 6);
 735                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160,
 736                                ARRAY_SIZE(ar5416Common_9160), 2);
 737                 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160,
 738                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 739                 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 740                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 741                 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160,
 742                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 743                 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160,
 744                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 745                 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160,
 746                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 747                 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160,
 748                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 749                 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 750                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 751                 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160,
 752                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 753                 if (AR_SREV_9160_11(ah)) {
 754                         INIT_INI_ARRAY(&ah->ah_iniAddac,
 755                                        ar5416Addac_91601_1,
 756                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 757                 } else {
 758                         INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160,
 759                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 760                 }
 761         } else if (AR_SREV_9100_OR_LATER(ah)) {
 762                 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100,
 763                                ARRAY_SIZE(ar5416Modes_9100), 6);
 764                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100,
 765                                ARRAY_SIZE(ar5416Common_9100), 2);
 766                 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100,
 767                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 768                 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 769                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 770                 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100,
 771                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 772                 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100,
 773                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 774                 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100,
 775                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 776                 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100,
 777                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 778                 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 779                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 780                 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100,
 781                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 782                 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100,
 783                                ARRAY_SIZE(ar5416Addac_9100), 2);
 784         } else {
 785                 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes,
 786                                ARRAY_SIZE(ar5416Modes), 6);
 787                 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common,
 788                                ARRAY_SIZE(ar5416Common), 2);
 789                 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0,
 790                                ARRAY_SIZE(ar5416Bank0), 2);
 791                 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain,
 792                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 793                 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1,
 794                                ARRAY_SIZE(ar5416Bank1), 2);
 795                 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2,
 796                                ARRAY_SIZE(ar5416Bank2), 2);
 797                 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3,
 798                                ARRAY_SIZE(ar5416Bank3), 3);
 799                 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6,
 800                                ARRAY_SIZE(ar5416Bank6), 3);
 801                 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC,
 802                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 803                 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7,
 804                                ARRAY_SIZE(ar5416Bank7), 2);
 805                 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac,
 806                                ARRAY_SIZE(ar5416Addac), 2);
 807         }
 808
 809         if (ah->ah_isPciExpress)
 810                 ath9k_hw_configpcipowersave(ah, 0);
 811         else
 812                 ath9k_hw_disablepcie(ah);
 813
 814         ecode = ath9k_hw_post_attach(ah);
 815         if (ecode != 0)
 816                 goto bad;
 817
 818         /* rxgain table */
 819         if (AR_SREV_9280_20(ah))
 820                 ath9k_hw_init_rxgain_ini(ah);
 821
 822         /* txgain table */
 823         if (AR_SREV_9280_20(ah))
 824                 ath9k_hw_init_txgain_ini(ah);
 825
 826         if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 827                 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) {
 828                         u32 reg = INI_RA(&ah->ah_iniModes, i, 0);
 829
 830                         for (j = 1; j < ah->ah_iniModes.ia_columns; j++) {
 831                                 u32 val = INI_RA(&ah->ah_iniModes, i, j);
 832
 833                                 INI_RA(&ah->ah_iniModes, i, j) =
 834                                         ath9k_hw_ini_fixup(ah,
 835                                                            &ah->ah_eeprom.def,
 836                                                            reg, val);
 837                         }
 838                 }
 839         }
 840
 841         if (!ath9k_hw_fill_cap_info(ah)) {
 842                 DPRINTF(sc, ATH_DBG_RESET,
 843                         "failed ath9k_hw_fill_cap_info\n");
 844                 ecode = -EINVAL;
 845                 goto bad;
 846         }
 847
 848         ecode = ath9k_hw_init_macaddr(ah);
 849         if (ecode != 0) {
 850                 DPRINTF(sc, ATH_DBG_RESET,
 851                         "failed initializing mac address\n");
 852                 goto bad;
 853         }
 854
 855         if (AR_SREV_9285(ah))
 856                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 857         else
 858                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 859
 860         ath9k_init_nfcal_hist_buffer(ah);
 861
 862         return ah;
 863 bad:
 864         if (ah)
 865                 ath9k_hw_detach(ah);
 866         if (status)
 867                 *status = ecode;
 868
 869         return NULL;
 870 }
 871
 872 static void ath9k_hw_init_bb(struct ath_hw *ah,
 873                              struct ath9k_channel *chan)
 874 {
 875         u32 synthDelay;
 876
 877         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 878         if (IS_CHAN_B(chan))
 879                 synthDelay = (4 * synthDelay) / 22;
 880         else
 881                 synthDelay /= 10;
 882
 883         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 884
 885         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 886 }
 887
 888 static void ath9k_hw_init_qos(struct ath_hw *ah)
 889 {
 890         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 891         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 892
 893         REG_WRITE(ah, AR_QOS_NO_ACK,
 894                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 895                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 896                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 897
 898         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 899         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 900         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 901         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 902         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 903 }
 904
 905 static void ath9k_hw_init_pll(struct ath_hw *ah,
 906                               struct ath9k_channel *chan)
 907 {
 908         u32 pll;
 909
 910         if (AR_SREV_9100(ah)) {
 911                 if (chan && IS_CHAN_5GHZ(chan))
 912                         pll = 0x1450;
 913                 else
 914                         pll = 0x1458;
 915         } else {
 916                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 917                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 918
 919                         if (chan && IS_CHAN_HALF_RATE(chan))
 920                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 921                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 922                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 923
 924                         if (chan && IS_CHAN_5GHZ(chan)) {
 925                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 926
 927
 928                                 if (AR_SREV_9280_20(ah)) {
 929                                         if (((chan->channel % 20) == 0)
 930                                             || ((chan->channel % 10) == 0))
 931                                                 pll = 0x2850;
 932                                         else
 933                                                 pll = 0x142c;
 934                                 }
 935                         } else {
 936                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 937                         }
 938
 939                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 940
 941                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 942
 943                         if (chan && IS_CHAN_HALF_RATE(chan))
 944                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 945                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 946                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 947
 948                         if (chan && IS_CHAN_5GHZ(chan))
 949                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 950                         else
 951                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 952                 } else {
 953                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 954
 955                         if (chan && IS_CHAN_HALF_RATE(chan))
 956                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 957                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 958                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 959
 960                         if (chan && IS_CHAN_5GHZ(chan))
 961                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 962                         else
 963                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 964                 }
 965         }
 966         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 967
 968         udelay(RTC_PLL_SETTLE_DELAY);
 969
 970         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 971 }
 972
 973 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
 974 {
 975         int rx_chainmask, tx_chainmask;
 976
 977         rx_chainmask = ah->ah_rxchainmask;
 978         tx_chainmask = ah->ah_txchainmask;
 979
 980         switch (rx_chainmask) {
 981         case 0x5:
 982                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 983                             AR_PHY_SWAP_ALT_CHAIN);
 984         case 0x3:
 985                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
 986                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 987                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 988                         break;
 989                 }
 990         case 0x1:
 991         case 0x2:
 992         case 0x7:
 993                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 994                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 995                 break;
 996         default:
 997                 break;
 998         }
 999
1000         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1001         if (tx_chainmask == 0x5) {
1002                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1003                             AR_PHY_SWAP_ALT_CHAIN);
1004         }
1005         if (AR_SREV_9100(ah))
1006                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1007                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1008 }
1009
1010 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1011                                           enum nl80211_iftype opmode)
1012 {
1013         ah->ah_maskReg = AR_IMR_TXERR |
1014                 AR_IMR_TXURN |
1015                 AR_IMR_RXERR |
1016                 AR_IMR_RXORN |
1017                 AR_IMR_BCNMISC;
1018
1019         if (ah->ah_intrMitigation)
1020                 ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1021         else
1022                 ah->ah_maskReg |= AR_IMR_RXOK;
1023
1024         ah->ah_maskReg |= AR_IMR_TXOK;
1025
1026         if (opmode == NL80211_IFTYPE_AP)
1027                 ah->ah_maskReg |= AR_IMR_MIB;
1028
1029         REG_WRITE(ah, AR_IMR, ah->ah_maskReg);
1030         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1031
1032         if (!AR_SREV_9100(ah)) {
1033                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1034                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1035                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1036         }
1037 }
1038
1039 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1040 {
1041         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1042                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1043                 ah->ah_acktimeout = (u32) -1;
1044                 return false;
1045         } else {
1046                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1047                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1048                 ah->ah_acktimeout = us;
1049                 return true;
1050         }
1051 }
1052
1053 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1054 {
1055         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1056                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1057                 ah->ah_ctstimeout = (u32) -1;
1058                 return false;
1059         } else {
1060                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1061                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1062                 ah->ah_ctstimeout = us;
1063                 return true;
1064         }
1065 }
1066
1067 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1068 {
1069         if (tu > 0xFFFF) {
1070                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1071                         "bad global tx timeout %u\n", tu);
1072                 ah->ah_globaltxtimeout = (u32) -1;
1073                 return false;
1074         } else {
1075                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1076                 ah->ah_globaltxtimeout = tu;
1077                 return true;
1078         }
1079 }
1080
1081 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1082 {
1083         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n",
1084                 ah->ah_miscMode);
1085
1086         if (ah->ah_miscMode != 0)
1087                 REG_WRITE(ah, AR_PCU_MISC,
1088                           REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode);
1089         if (ah->ah_slottime != (u32) -1)
1090                 ath9k_hw_setslottime(ah, ah->ah_slottime);
1091         if (ah->ah_acktimeout != (u32) -1)
1092                 ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout);
1093         if (ah->ah_ctstimeout != (u32) -1)
1094                 ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout);
1095         if (ah->ah_globaltxtimeout != (u32) -1)
1096                 ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout);
1097 }
1098
1099 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1100 {
1101         return vendorid == ATHEROS_VENDOR_ID ?
1102                 ath9k_hw_devname(devid) : NULL;
1103 }
1104
1105 void ath9k_hw_detach(struct ath_hw *ah)
1106 {
1107         if (!AR_SREV_9100(ah))
1108                 ath9k_hw_ani_detach(ah);
1109
1110         ath9k_hw_rfdetach(ah);
1111         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1112         kfree(ah);
1113 }
1114
1115 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1116 {
1117         struct ath_hw *ah = NULL;
1118
1119         switch (devid) {
1120         case AR5416_DEVID_PCI:
1121         case AR5416_DEVID_PCIE:
1122         case AR5416_AR9100_DEVID:
1123         case AR9160_DEVID_PCI:
1124         case AR9280_DEVID_PCI:
1125         case AR9280_DEVID_PCIE:
1126         case AR9285_DEVID_PCIE:
1127                 ah = ath9k_hw_do_attach(devid, sc, error);
1128                 break;
1129         default:
1130                 *error = -ENXIO;
1131                 break;
1132         }
1133
1134         return ah;
1135 }
1136
1137 /*******/
1138 /* INI */
1139 /*******/
1140
1141 static void ath9k_hw_override_ini(struct ath_hw *ah,
1142                                   struct ath9k_channel *chan)
1143 {
1144         /*
1145          * Set the RX_ABORT and RX_DIS and clear if off only after
1146          * RXE is set for MAC. This prevents frames with corrupted
1147          * descriptor status.
1148          */
1149         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1150
1151
1152         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1153             AR_SREV_9280_10_OR_LATER(ah))
1154                 return;
1155
1156         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1157 }
1158
1159 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1160                               struct ar5416_eeprom_def *pEepData,
1161                               u32 reg, u32 value)
1162 {
1163         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1164
1165         switch (ah->hw_version.devid) {
1166         case AR9280_DEVID_PCI:
1167                 if (reg == 0x7894) {
1168                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1169                                 "ini VAL: %x  EEPROM: %x\n", value,
1170                                 (pBase->version & 0xff));
1171
1172                         if ((pBase->version & 0xff) > 0x0a) {
1173                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1174                                         "PWDCLKIND: %d\n",
1175                                         pBase->pwdclkind);
1176                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1177                                 value |= AR_AN_TOP2_PWDCLKIND &
1178                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1179                         } else {
1180                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1181                                         "PWDCLKIND Earlier Rev\n");
1182                         }
1183
1184                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1185                                 "final ini VAL: %x\n", value);
1186                 }
1187                 break;
1188         }
1189
1190         return value;
1191 }
1192
1193 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1194                               struct ar5416_eeprom_def *pEepData,
1195                               u32 reg, u32 value)
1196 {
1197         if (ah->ah_eep_map == EEP_MAP_4KBITS)
1198                 return value;
1199         else
1200                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1201 }
1202
1203 static int ath9k_hw_process_ini(struct ath_hw *ah,
1204                                 struct ath9k_channel *chan,
1205                                 enum ath9k_ht_macmode macmode)
1206 {
1207         int i, regWrites = 0;
1208         struct ieee80211_channel *channel = chan->chan;
1209         u32 modesIndex, freqIndex;
1210         int status;
1211
1212         switch (chan->chanmode) {
1213         case CHANNEL_A:
1214         case CHANNEL_A_HT20:
1215                 modesIndex = 1;
1216                 freqIndex = 1;
1217                 break;
1218         case CHANNEL_A_HT40PLUS:
1219         case CHANNEL_A_HT40MINUS:
1220                 modesIndex = 2;
1221                 freqIndex = 1;
1222                 break;
1223         case CHANNEL_G:
1224         case CHANNEL_G_HT20:
1225         case CHANNEL_B:
1226                 modesIndex = 4;
1227                 freqIndex = 2;
1228                 break;
1229         case CHANNEL_G_HT40PLUS:
1230         case CHANNEL_G_HT40MINUS:
1231                 modesIndex = 3;
1232                 freqIndex = 2;
1233                 break;
1234
1235         default:
1236                 return -EINVAL;
1237         }
1238
1239         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1240         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1241         ath9k_hw_set_addac(ah, chan);
1242
1243         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1244                 REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites);
1245         } else {
1246                 struct ar5416IniArray temp;
1247                 u32 addacSize =
1248                         sizeof(u32) * ah->ah_iniAddac.ia_rows *
1249                         ah->ah_iniAddac.ia_columns;
1250
1251                 memcpy(ah->ah_addac5416_21,
1252                        ah->ah_iniAddac.ia_array, addacSize);
1253
1254                 (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0;
1255
1256                 temp.ia_array = ah->ah_addac5416_21;
1257                 temp.ia_columns = ah->ah_iniAddac.ia_columns;
1258                 temp.ia_rows = ah->ah_iniAddac.ia_rows;
1259                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1260         }
1261
1262         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1263
1264         for (i = 0; i < ah->ah_iniModes.ia_rows; i++) {
1265                 u32 reg = INI_RA(&ah->ah_iniModes, i, 0);
1266                 u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex);
1267
1268                 REG_WRITE(ah, reg, val);
1269
1270                 if (reg >= 0x7800 && reg < 0x78a0
1271                     && ah->ah_config.analog_shiftreg) {
1272                         udelay(100);
1273                 }
1274
1275                 DO_DELAY(regWrites);
1276         }
1277
1278         if (AR_SREV_9280(ah))
1279                 REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites);
1280
1281         if (AR_SREV_9280(ah))
1282                 REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites);
1283
1284         for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) {
1285                 u32 reg = INI_RA(&ah->ah_iniCommon, i, 0);
1286                 u32 val = INI_RA(&ah->ah_iniCommon, i, 1);
1287
1288                 REG_WRITE(ah, reg, val);
1289
1290                 if (reg >= 0x7800 && reg < 0x78a0
1291                     && ah->ah_config.analog_shiftreg) {
1292                         udelay(100);
1293                 }
1294
1295                 DO_DELAY(regWrites);
1296         }
1297
1298         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1299
1300         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1301                 REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex,
1302                                 regWrites);
1303         }
1304
1305         ath9k_hw_override_ini(ah, chan);
1306         ath9k_hw_set_regs(ah, chan, macmode);
1307         ath9k_hw_init_chain_masks(ah);
1308
1309         status = ath9k_hw_set_txpower(ah, chan,
1310                                       ath9k_regd_get_ctl(ah, chan),
1311                                       channel->max_antenna_gain * 2,
1312                                       channel->max_power * 2,
1313                                       min((u32) MAX_RATE_POWER,
1314                                           (u32) ah->regulatory.power_limit));
1315         if (status != 0) {
1316                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1317                         "error init'ing transmit power\n");
1318                 return -EIO;
1319         }
1320
1321         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1322                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1323                         "ar5416SetRfRegs failed\n");
1324                 return -EIO;
1325         }
1326
1327         return 0;
1328 }
1329
1330 /****************************************/
1331 /* Reset and Channel Switching Routines */
1332 /****************************************/
1333
1334 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1335 {
1336         u32 rfMode = 0;
1337
1338         if (chan == NULL)
1339                 return;
1340
1341         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1342                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1343
1344         if (!AR_SREV_9280_10_OR_LATER(ah))
1345                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1346                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1347
1348         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1349                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1350
1351         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1352 }
1353
1354 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1355 {
1356         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1357 }
1358
1359 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1360 {
1361         u32 regval;
1362
1363         regval = REG_READ(ah, AR_AHB_MODE);
1364         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1365
1366         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1367         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1368
1369         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1370
1371         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1372         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1373
1374         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1375
1376         if (AR_SREV_9285(ah)) {
1377                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1378                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1379         } else {
1380                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1381                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1382         }
1383 }
1384
1385 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1386 {
1387         u32 val;
1388
1389         val = REG_READ(ah, AR_STA_ID1);
1390         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1391         switch (opmode) {
1392         case NL80211_IFTYPE_AP:
1393                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1394                           | AR_STA_ID1_KSRCH_MODE);
1395                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1396                 break;
1397         case NL80211_IFTYPE_ADHOC:
1398                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1399                           | AR_STA_ID1_KSRCH_MODE);
1400                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1401                 break;
1402         case NL80211_IFTYPE_STATION:
1403         case NL80211_IFTYPE_MONITOR:
1404                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1405                 break;
1406         }
1407 }
1408
1409 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1410                                                  u32 coef_scaled,
1411                                                  u32 *coef_mantissa,
1412                                                  u32 *coef_exponent)
1413 {
1414         u32 coef_exp, coef_man;
1415
1416         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1417                 if ((coef_scaled >> coef_exp) & 0x1)
1418                         break;
1419
1420         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1421
1422         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1423
1424         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1425         *coef_exponent = coef_exp - 16;
1426 }
1427
1428 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1429                                      struct ath9k_channel *chan)
1430 {
1431         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1432         u32 clockMhzScaled = 0x64000000;
1433         struct chan_centers centers;
1434
1435         if (IS_CHAN_HALF_RATE(chan))
1436                 clockMhzScaled = clockMhzScaled >> 1;
1437         else if (IS_CHAN_QUARTER_RATE(chan))
1438                 clockMhzScaled = clockMhzScaled >> 2;
1439
1440         ath9k_hw_get_channel_centers(ah, chan, &centers);
1441         coef_scaled = clockMhzScaled / centers.synth_center;
1442
1443         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1444                                       &ds_coef_exp);
1445
1446         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1447                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1448         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1449                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1450
1451         coef_scaled = (9 * coef_scaled) / 10;
1452
1453         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1454                                       &ds_coef_exp);
1455
1456         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1457                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1458         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1459                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1460 }
1461
1462 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1463 {
1464         u32 rst_flags;
1465         u32 tmpReg;
1466
1467         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1468                   AR_RTC_FORCE_WAKE_ON_INT);
1469
1470         if (AR_SREV_9100(ah)) {
1471                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1472                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1473         } else {
1474                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1475                 if (tmpReg &
1476                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1477                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1478                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1479                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1480                 } else {
1481                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1482                 }
1483
1484                 rst_flags = AR_RTC_RC_MAC_WARM;
1485                 if (type == ATH9K_RESET_COLD)
1486                         rst_flags |= AR_RTC_RC_MAC_COLD;
1487         }
1488
1489         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1490         udelay(50);
1491
1492         REG_WRITE(ah, AR_RTC_RC, 0);
1493         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1494                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1495                         "RTC stuck in MAC reset\n");
1496                 return false;
1497         }
1498
1499         if (!AR_SREV_9100(ah))
1500                 REG_WRITE(ah, AR_RC, 0);
1501
1502         ath9k_hw_init_pll(ah, NULL);
1503
1504         if (AR_SREV_9100(ah))
1505                 udelay(50);
1506
1507         return true;
1508 }
1509
1510 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1511 {
1512         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1513                   AR_RTC_FORCE_WAKE_ON_INT);
1514
1515         REG_WRITE(ah, AR_RTC_RESET, 0);
1516         REG_WRITE(ah, AR_RTC_RESET, 1);
1517
1518         if (!ath9k_hw_wait(ah,
1519                            AR_RTC_STATUS,
1520                            AR_RTC_STATUS_M,
1521                            AR_RTC_STATUS_ON)) {
1522                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1523                 return false;
1524         }
1525
1526         ath9k_hw_read_revisions(ah);
1527
1528         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1529 }
1530
1531 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1532 {
1533         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1534                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1535
1536         switch (type) {
1537         case ATH9K_RESET_POWER_ON:
1538                 return ath9k_hw_set_reset_power_on(ah);
1539                 break;
1540         case ATH9K_RESET_WARM:
1541         case ATH9K_RESET_COLD:
1542                 return ath9k_hw_set_reset(ah, type);
1543                 break;
1544         default:
1545                 return false;
1546         }
1547 }
1548
1549 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1550                               enum ath9k_ht_macmode macmode)
1551 {
1552         u32 phymode;
1553         u32 enableDacFifo = 0;
1554
1555         if (AR_SREV_9285_10_OR_LATER(ah))
1556                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1557                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1558
1559         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1560                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1561
1562         if (IS_CHAN_HT40(chan)) {
1563                 phymode |= AR_PHY_FC_DYN2040_EN;
1564
1565                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1566                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1567                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1568
1569                 if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1570                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1571         }
1572         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1573
1574         ath9k_hw_set11nmac2040(ah, macmode);
1575
1576         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1577         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1578 }
1579
1580 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1581                                 struct ath9k_channel *chan)
1582 {
1583         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1584                 return false;
1585
1586         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1587                 return false;
1588
1589         ah->ah_chipFullSleep = false;
1590         ath9k_hw_init_pll(ah, chan);
1591         ath9k_hw_set_rfmode(ah, chan);
1592
1593         return true;
1594 }
1595
1596 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1597                                     struct ath9k_channel *chan,
1598                                     enum ath9k_ht_macmode macmode)
1599 {
1600         struct ieee80211_channel *channel = chan->chan;
1601         u32 synthDelay, qnum;
1602
1603         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1604                 if (ath9k_hw_numtxpending(ah, qnum)) {
1605                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1606                                 "Transmit frames pending on queue %d\n", qnum);
1607                         return false;
1608                 }
1609         }
1610
1611         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1612         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1613                            AR_PHY_RFBUS_GRANT_EN)) {
1614                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1615                         "Could not kill baseband RX\n");
1616                 return false;
1617         }
1618
1619         ath9k_hw_set_regs(ah, chan, macmode);
1620
1621         if (AR_SREV_9280_10_OR_LATER(ah)) {
1622                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1623                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1624                                 "failed to set channel\n");
1625                         return false;
1626                 }
1627         } else {
1628                 if (!(ath9k_hw_set_channel(ah, chan))) {
1629                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1630                                 "failed to set channel\n");
1631                         return false;
1632                 }
1633         }
1634
1635         if (ath9k_hw_set_txpower(ah, chan,
1636                                  ath9k_regd_get_ctl(ah, chan),
1637                                  channel->max_antenna_gain * 2,
1638                                  channel->max_power * 2,
1639                                  min((u32) MAX_RATE_POWER,
1640                                      (u32) ah->regulatory.power_limit)) != 0) {
1641                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1642                         "error init'ing transmit power\n");
1643                 return false;
1644         }
1645
1646         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1647         if (IS_CHAN_B(chan))
1648                 synthDelay = (4 * synthDelay) / 22;
1649         else
1650                 synthDelay /= 10;
1651
1652         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1653
1654         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1655
1656         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1657                 ath9k_hw_set_delta_slope(ah, chan);
1658
1659         if (AR_SREV_9280_10_OR_LATER(ah))
1660                 ath9k_hw_9280_spur_mitigate(ah, chan);
1661         else
1662                 ath9k_hw_spur_mitigate(ah, chan);
1663
1664         if (!chan->oneTimeCalsDone)
1665                 chan->oneTimeCalsDone = true;
1666
1667         return true;
1668 }
1669
1670 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1671 {
1672         int bb_spur = AR_NO_SPUR;
1673         int freq;
1674         int bin, cur_bin;
1675         int bb_spur_off, spur_subchannel_sd;
1676         int spur_freq_sd;
1677         int spur_delta_phase;
1678         int denominator;
1679         int upper, lower, cur_vit_mask;
1680         int tmp, newVal;
1681         int i;
1682         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1683                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1684         };
1685         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1686                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1687         };
1688         int inc[4] = { 0, 100, 0, 0 };
1689         struct chan_centers centers;
1690
1691         int8_t mask_m[123];
1692         int8_t mask_p[123];
1693         int8_t mask_amt;
1694         int tmp_mask;
1695         int cur_bb_spur;
1696         bool is2GHz = IS_CHAN_2GHZ(chan);
1697
1698         memset(&mask_m, 0, sizeof(int8_t) * 123);
1699         memset(&mask_p, 0, sizeof(int8_t) * 123);
1700
1701         ath9k_hw_get_channel_centers(ah, chan, &centers);
1702         freq = centers.synth_center;
1703
1704         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1705         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1706                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1707
1708                 if (is2GHz)
1709                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1710                 else
1711                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1712
1713                 if (AR_NO_SPUR == cur_bb_spur)
1714                         break;
1715                 cur_bb_spur = cur_bb_spur - freq;
1716
1717                 if (IS_CHAN_HT40(chan)) {
1718                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1719                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1720                                 bb_spur = cur_bb_spur;
1721                                 break;
1722                         }
1723                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1724                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1725                         bb_spur = cur_bb_spur;
1726                         break;
1727                 }
1728         }
1729
1730         if (AR_NO_SPUR == bb_spur) {
1731                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1732                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1733                 return;
1734         } else {
1735                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1736                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1737         }
1738
1739         bin = bb_spur * 320;
1740
1741         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1742
1743         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1744                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1745                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1746                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1747         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1748
1749         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1750                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1751                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1752                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1753                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1754         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1755
1756         if (IS_CHAN_HT40(chan)) {
1757                 if (bb_spur < 0) {
1758                         spur_subchannel_sd = 1;
1759                         bb_spur_off = bb_spur + 10;
1760                 } else {
1761                         spur_subchannel_sd = 0;
1762                         bb_spur_off = bb_spur - 10;
1763                 }
1764         } else {
1765                 spur_subchannel_sd = 0;
1766                 bb_spur_off = bb_spur;
1767         }
1768
1769         if (IS_CHAN_HT40(chan))
1770                 spur_delta_phase =
1771                         ((bb_spur * 262144) /
1772                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1773         else
1774                 spur_delta_phase =
1775                         ((bb_spur * 524288) /
1776                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1777
1778         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1779         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1780
1781         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1782                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1783                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1784         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1785
1786         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1787         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1788
1789         cur_bin = -6000;
1790         upper = bin + 100;
1791         lower = bin - 100;
1792
1793         for (i = 0; i < 4; i++) {
1794                 int pilot_mask = 0;
1795                 int chan_mask = 0;
1796                 int bp = 0;
1797                 for (bp = 0; bp < 30; bp++) {
1798                         if ((cur_bin > lower) && (cur_bin < upper)) {
1799                                 pilot_mask = pilot_mask | 0x1 << bp;
1800                                 chan_mask = chan_mask | 0x1 << bp;
1801                         }
1802                         cur_bin += 100;
1803                 }
1804                 cur_bin += inc[i];
1805                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1806                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1807         }
1808
1809         cur_vit_mask = 6100;
1810         upper = bin + 120;
1811         lower = bin - 120;
1812
1813         for (i = 0; i < 123; i++) {
1814                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1815
1816                         /* workaround for gcc bug #37014 */
1817                         volatile int tmp_v = abs(cur_vit_mask - bin);
1818
1819                         if (tmp_v < 75)
1820                                 mask_amt = 1;
1821                         else
1822                                 mask_amt = 0;
1823                         if (cur_vit_mask < 0)
1824                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1825                         else
1826                                 mask_p[cur_vit_mask / 100] = mask_amt;
1827                 }
1828                 cur_vit_mask -= 100;
1829         }
1830
1831         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1832                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1833                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1834                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1835                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1836                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1837                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1838                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1839         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1840         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1841
1842         tmp_mask = (mask_m[31] << 28)
1843                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1844                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1845                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1846                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1847                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1848                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1849                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1850         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1851         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1852
1853         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1854                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1855                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1856                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1857                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1858                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1859                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1860                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1861         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1862         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1863
1864         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1865                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1866                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1867                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1868                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1869                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1870                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1871                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1872         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1873         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1874
1875         tmp_mask = (mask_p[15] << 28)
1876                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1877                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1878                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1879                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1880                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1881                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1882                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1883         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1884         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1885
1886         tmp_mask = (mask_p[30] << 28)
1887                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1888                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1889                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1890                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1891                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1892                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1893                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1894         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1895         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1896
1897         tmp_mask = (mask_p[45] << 28)
1898                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1899                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1900                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1901                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1902                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1903                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1904                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1905         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1906         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1907
1908         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1909                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1910                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1911                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1912                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1913                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1914                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1915                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1916         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1917         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1918 }
1919
1920 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1921 {
1922         int bb_spur = AR_NO_SPUR;
1923         int bin, cur_bin;
1924         int spur_freq_sd;
1925         int spur_delta_phase;
1926         int denominator;
1927         int upper, lower, cur_vit_mask;
1928         int tmp, new;
1929         int i;
1930         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1931                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1932         };
1933         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1934                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1935         };
1936         int inc[4] = { 0, 100, 0, 0 };
1937
1938         int8_t mask_m[123];
1939         int8_t mask_p[123];
1940         int8_t mask_amt;
1941         int tmp_mask;
1942         int cur_bb_spur;
1943         bool is2GHz = IS_CHAN_2GHZ(chan);
1944
1945         memset(&mask_m, 0, sizeof(int8_t) * 123);
1946         memset(&mask_p, 0, sizeof(int8_t) * 123);
1947
1948         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1949                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1950                 if (AR_NO_SPUR == cur_bb_spur)
1951                         break;
1952                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1953                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1954                         bb_spur = cur_bb_spur;
1955                         break;
1956                 }
1957         }
1958
1959         if (AR_NO_SPUR == bb_spur)
1960                 return;
1961
1962         bin = bb_spur * 32;
1963
1964         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1965         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1966                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1967                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1968                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1969
1970         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1971
1972         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1973                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1974                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1975                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1976                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1977         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1978
1979         spur_delta_phase = ((bb_spur * 524288) / 100) &
1980                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1981
1982         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1983         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1984
1985         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1986                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1987                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1988         REG_WRITE(ah, AR_PHY_TIMING11, new);
1989
1990         cur_bin = -6000;
1991         upper = bin + 100;
1992         lower = bin - 100;
1993
1994         for (i = 0; i < 4; i++) {
1995                 int pilot_mask = 0;
1996                 int chan_mask = 0;
1997                 int bp = 0;
1998                 for (bp = 0; bp < 30; bp++) {
1999                         if ((cur_bin > lower) && (cur_bin < upper)) {
2000                                 pilot_mask = pilot_mask | 0x1 << bp;
2001                                 chan_mask = chan_mask | 0x1 << bp;
2002                         }
2003                         cur_bin += 100;
2004                 }
2005                 cur_bin += inc[i];
2006                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2007                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2008         }
2009
2010         cur_vit_mask = 6100;
2011         upper = bin + 120;
2012         lower = bin - 120;
2013
2014         for (i = 0; i < 123; i++) {
2015                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2016
2017                         /* workaround for gcc bug #37014 */
2018                         volatile int tmp_v = abs(cur_vit_mask - bin);
2019
2020                         if (tmp_v < 75)
2021                                 mask_amt = 1;
2022                         else
2023                                 mask_amt = 0;
2024                         if (cur_vit_mask < 0)
2025                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2026                         else
2027                                 mask_p[cur_vit_mask / 100] = mask_amt;
2028                 }
2029                 cur_vit_mask -= 100;
2030         }
2031
2032         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2033                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2034                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2035                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2036                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2037                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2038                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2039                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2040         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2041         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2042
2043         tmp_mask = (mask_m[31] << 28)
2044                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2045                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2046                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2047                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2048                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2049                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2050                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2051         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2052         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2053
2054         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2055                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2056                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2057                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2058                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2059                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2060                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2061                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2062         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2063         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2064
2065         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2066                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2067                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2068                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2069                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2070                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2071                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2072                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2073         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2074         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2075
2076         tmp_mask = (mask_p[15] << 28)
2077                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2078                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2079                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2080                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2081                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2082                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2083                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2084         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2085         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2086
2087         tmp_mask = (mask_p[30] << 28)
2088                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2089                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2090                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2091                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2092                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2093                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2094                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2095         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2096         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2097
2098         tmp_mask = (mask_p[45] << 28)
2099                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2100                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2101                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2102                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2103                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2104                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2105                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2106         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2107         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2108
2109         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2110                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2111                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2112                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2113                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2114                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2115                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2116                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2117         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2118         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2119 }
2120
2121 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2122                     bool bChannelChange)
2123 {
2124         u32 saveLedState;
2125         struct ath_softc *sc = ah->ah_sc;
2126         struct ath9k_channel *curchan = ah->ah_curchan;
2127         u32 saveDefAntenna;
2128         u32 macStaId1;
2129         int i, rx_chainmask, r;
2130
2131         ah->ah_extprotspacing = sc->ht_extprotspacing;
2132         ah->ah_txchainmask = sc->tx_chainmask;
2133         ah->ah_rxchainmask = sc->rx_chainmask;
2134
2135         if (AR_SREV_9285(ah)) {
2136                 ah->ah_txchainmask &= 0x1;
2137                 ah->ah_rxchainmask &= 0x1;
2138         } else if (AR_SREV_9280(ah)) {
2139                 ah->ah_txchainmask &= 0x3;
2140                 ah->ah_rxchainmask &= 0x3;
2141         }
2142
2143         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2144                 return -EIO;
2145
2146         if (curchan)
2147                 ath9k_hw_getnf(ah, curchan);
2148
2149         if (bChannelChange &&
2150             (ah->ah_chipFullSleep != true) &&
2151             (ah->ah_curchan != NULL) &&
2152             (chan->channel != ah->ah_curchan->channel) &&
2153             ((chan->channelFlags & CHANNEL_ALL) ==
2154              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2155             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2156                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2157
2158                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2159                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2160                         ath9k_hw_start_nfcal(ah);
2161                         return 0;
2162                 }
2163         }
2164
2165         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2166         if (saveDefAntenna == 0)
2167                 saveDefAntenna = 1;
2168
2169         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2170
2171         saveLedState = REG_READ(ah, AR_CFG_LED) &
2172                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2173                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2174
2175         ath9k_hw_mark_phy_inactive(ah);
2176
2177         if (!ath9k_hw_chip_reset(ah, chan)) {
2178                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2179                 return -EINVAL;
2180         }
2181
2182         if (AR_SREV_9280_10_OR_LATER(ah))
2183                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2184
2185         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2186         if (r)
2187                 return r;
2188
2189         /* Setup MFP options for CCMP */
2190         if (AR_SREV_9280_20_OR_LATER(ah)) {
2191                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2192                  * frames when constructing CCMP AAD. */
2193                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2194                               0xc7ff);
2195                 ah->sw_mgmt_crypto = false;
2196         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2197                 /* Disable hardware crypto for management frames */
2198                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2199                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2200                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2201                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2202                 ah->sw_mgmt_crypto = true;
2203         } else
2204                 ah->sw_mgmt_crypto = true;
2205
2206         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2207                 ath9k_hw_set_delta_slope(ah, chan);
2208
2209         if (AR_SREV_9280_10_OR_LATER(ah))
2210                 ath9k_hw_9280_spur_mitigate(ah, chan);
2211         else
2212                 ath9k_hw_spur_mitigate(ah, chan);
2213
2214         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2215                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2216                         "error setting board options\n");
2217                 return -EIO;
2218         }
2219
2220         ath9k_hw_decrease_chain_power(ah, chan);
2221
2222         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2223         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2224                   | macStaId1
2225                   | AR_STA_ID1_RTS_USE_DEF
2226                   | (ah->ah_config.
2227                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2228                   | ah->ah_staId1Defaults);
2229         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2230
2231         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2232         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2233
2234         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2235
2236         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2237         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2238                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2239
2240         REG_WRITE(ah, AR_ISR, ~0);
2241
2242         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2243
2244         if (AR_SREV_9280_10_OR_LATER(ah)) {
2245                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2246                         return -EIO;
2247         } else {
2248                 if (!(ath9k_hw_set_channel(ah, chan)))
2249                         return -EIO;
2250         }
2251
2252         for (i = 0; i < AR_NUM_DCU; i++)
2253                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2254
2255         ah->ah_intrTxqs = 0;
2256         for (i = 0; i < ah->ah_caps.total_queues; i++)
2257                 ath9k_hw_resettxqueue(ah, i);
2258
2259         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2260         ath9k_hw_init_qos(ah);
2261
2262 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2263         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2264                 ath9k_enable_rfkill(ah);
2265 #endif
2266         ath9k_hw_init_user_settings(ah);
2267
2268         REG_WRITE(ah, AR_STA_ID1,
2269                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2270
2271         ath9k_hw_set_dma(ah);
2272
2273         REG_WRITE(ah, AR_OBS, 8);
2274
2275         if (ah->ah_intrMitigation) {
2276
2277                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2278                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2279         }
2280
2281         ath9k_hw_init_bb(ah, chan);
2282
2283         if (!ath9k_hw_init_cal(ah, chan))
2284                 return -EIO;;
2285
2286         rx_chainmask = ah->ah_rxchainmask;
2287         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2288                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2289                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2290         }
2291
2292         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2293
2294         if (AR_SREV_9100(ah)) {
2295                 u32 mask;
2296                 mask = REG_READ(ah, AR_CFG);
2297                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2298                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2299                                 "CFG Byte Swap Set 0x%x\n", mask);
2300                 } else {
2301                         mask =
2302                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2303                         REG_WRITE(ah, AR_CFG, mask);
2304                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2305                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2306                 }
2307         } else {
2308 #ifdef __BIG_ENDIAN
2309                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2310 #endif
2311         }
2312
2313         return 0;
2314 }
2315
2316 /************************/
2317 /* Key Cache Management */
2318 /************************/
2319
2320 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2321 {
2322         u32 keyType;
2323
2324         if (entry >= ah->ah_caps.keycache_size) {
2325                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2326                         "entry %u out of range\n", entry);
2327                 return false;
2328         }
2329
2330         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2331
2332         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2333         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2334         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2335         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2336         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2337         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2338         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2339         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2340
2341         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2342                 u16 micentry = entry + 64;
2343
2344                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2345                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2346                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2347                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2348
2349         }
2350
2351         if (ah->ah_curchan == NULL)
2352                 return true;
2353
2354         return true;
2355 }
2356
2357 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2358 {
2359         u32 macHi, macLo;
2360
2361         if (entry >= ah->ah_caps.keycache_size) {
2362                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2363                         "entry %u out of range\n", entry);
2364                 return false;
2365         }
2366
2367         if (mac != NULL) {
2368                 macHi = (mac[5] << 8) | mac[4];
2369                 macLo = (mac[3] << 24) |
2370                         (mac[2] << 16) |
2371                         (mac[1] << 8) |
2372                         mac[0];
2373                 macLo >>= 1;
2374                 macLo |= (macHi & 1) << 31;
2375                 macHi >>= 1;
2376         } else {
2377                 macLo = macHi = 0;
2378         }
2379         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2380         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2381
2382         return true;
2383 }
2384
2385 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2386                                  const struct ath9k_keyval *k,
2387                                  const u8 *mac, int xorKey)
2388 {
2389         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2390         u32 key0, key1, key2, key3, key4;
2391         u32 keyType;
2392         u32 xorMask = xorKey ?
2393                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2394                  | ATH9K_KEY_XOR) : 0;
2395
2396         if (entry >= pCap->keycache_size) {
2397                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2398                         "entry %u out of range\n", entry);
2399                 return false;
2400         }
2401
2402         switch (k->kv_type) {
2403         case ATH9K_CIPHER_AES_OCB:
2404                 keyType = AR_KEYTABLE_TYPE_AES;
2405                 break;
2406         case ATH9K_CIPHER_AES_CCM:
2407                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2408                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2409                                 "AES-CCM not supported by mac rev 0x%x\n",
2410                                 ah->hw_version.macRev);
2411                         return false;
2412                 }
2413                 keyType = AR_KEYTABLE_TYPE_CCM;
2414                 break;
2415         case ATH9K_CIPHER_TKIP:
2416                 keyType = AR_KEYTABLE_TYPE_TKIP;
2417                 if (ATH9K_IS_MIC_ENABLED(ah)
2418                     && entry + 64 >= pCap->keycache_size) {
2419                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2420                                 "entry %u inappropriate for TKIP\n", entry);
2421                         return false;
2422                 }
2423                 break;
2424         case ATH9K_CIPHER_WEP:
2425                 if (k->kv_len < LEN_WEP40) {
2426                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2427                                 "WEP key length %u too small\n", k->kv_len);
2428                         return false;
2429                 }
2430                 if (k->kv_len <= LEN_WEP40)
2431                         keyType = AR_KEYTABLE_TYPE_40;
2432                 else if (k->kv_len <= LEN_WEP104)
2433                         keyType = AR_KEYTABLE_TYPE_104;
2434                 else
2435                         keyType = AR_KEYTABLE_TYPE_128;
2436                 break;
2437         case ATH9K_CIPHER_CLR:
2438                 keyType = AR_KEYTABLE_TYPE_CLR;
2439                 break;
2440         default:
2441                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2442                         "cipher %u not supported\n", k->kv_type);
2443                 return false;
2444         }
2445
2446         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2447         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2448         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2449         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2450         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2451         if (k->kv_len <= LEN_WEP104)
2452                 key4 &= 0xff;
2453
2454         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2455                 u16 micentry = entry + 64;
2456
2457                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2458                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2459                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2460                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2461                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2462                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2463                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2464
2465                 if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2466                         u32 mic0, mic1, mic2, mic3, mic4;
2467
2468                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2469                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2470                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2471                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2472                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2473                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2474                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2475                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2476                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2477                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2478                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2479                                   AR_KEYTABLE_TYPE_CLR);
2480
2481                 } else {
2482                         u32 mic0, mic2;
2483
2484                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2485                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2486                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2487                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2488                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2489                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2490                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2491                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2492                                   AR_KEYTABLE_TYPE_CLR);
2493                 }
2494                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2495                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2496                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2497                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2498         } else {
2499                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2500                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2501                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2502                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2503                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2504                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2505
2506                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2507         }
2508
2509         if (ah->ah_curchan == NULL)
2510                 return true;
2511
2512         return true;
2513 }
2514
2515 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2516 {
2517         if (entry < ah->ah_caps.keycache_size) {
2518                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2519                 if (val & AR_KEYTABLE_VALID)
2520                         return true;
2521         }
2522         return false;
2523 }
2524
2525 /******************************/
2526 /* Power Management (Chipset) */
2527 /******************************/
2528
2529 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2530 {
2531         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2532         if (setChip) {
2533                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2534                             AR_RTC_FORCE_WAKE_EN);
2535                 if (!AR_SREV_9100(ah))
2536                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2537
2538                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2539                             AR_RTC_RESET_EN);
2540         }
2541 }
2542
2543 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2544 {
2545         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2546         if (setChip) {
2547                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2548
2549                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2550                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2551                                   AR_RTC_FORCE_WAKE_ON_INT);
2552                 } else {
2553                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2554                                     AR_RTC_FORCE_WAKE_EN);
2555                 }
2556         }
2557 }
2558
2559 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2560 {
2561         u32 val;
2562         int i;
2563
2564         if (setChip) {
2565                 if ((REG_READ(ah, AR_RTC_STATUS) &
2566                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2567                         if (ath9k_hw_set_reset_reg(ah,
2568                                            ATH9K_RESET_POWER_ON) != true) {
2569                                 return false;
2570                         }
2571                 }
2572                 if (AR_SREV_9100(ah))
2573                         REG_SET_BIT(ah, AR_RTC_RESET,
2574                                     AR_RTC_RESET_EN);
2575
2576                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2577                             AR_RTC_FORCE_WAKE_EN);
2578                 udelay(50);
2579
2580                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2581                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2582                         if (val == AR_RTC_STATUS_ON)
2583                                 break;
2584                         udelay(50);
2585                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2586                                     AR_RTC_FORCE_WAKE_EN);
2587                 }
2588                 if (i == 0) {
2589                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2590                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2591                         return false;
2592                 }
2593         }
2594
2595         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2596
2597         return true;
2598 }
2599
2600 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2601 {
2602         int status = true, setChip = true;
2603         static const char *modes[] = {
2604                 "AWAKE",
2605                 "FULL-SLEEP",
2606                 "NETWORK SLEEP",
2607                 "UNDEFINED"
2608         };
2609
2610         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2611                 modes[ah->ah_power_mode], modes[mode],
2612                 setChip ? "set chip " : "");
2613
2614         switch (mode) {
2615         case ATH9K_PM_AWAKE:
2616                 status = ath9k_hw_set_power_awake(ah, setChip);
2617                 break;
2618         case ATH9K_PM_FULL_SLEEP:
2619                 ath9k_set_power_sleep(ah, setChip);
2620                 ah->ah_chipFullSleep = true;
2621                 break;
2622         case ATH9K_PM_NETWORK_SLEEP:
2623                 ath9k_set_power_network_sleep(ah, setChip);
2624                 break;
2625         default:
2626                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2627                         "Unknown power mode %u\n", mode);
2628                 return false;
2629         }
2630         ah->ah_power_mode = mode;
2631
2632         return status;
2633 }
2634
2635 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2636 {
2637         u8 i;
2638
2639         if (ah->ah_isPciExpress != true)
2640                 return;
2641
2642         if (ah->ah_config.pcie_powersave_enable == 2)
2643                 return;
2644
2645         if (restore)
2646                 return;
2647
2648         if (AR_SREV_9280_20_OR_LATER(ah)) {
2649                 for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) {
2650                         REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0),
2651                                   INI_RA(&ah->ah_iniPcieSerdes, i, 1));
2652                 }
2653                 udelay(1000);
2654         } else if (AR_SREV_9280(ah) &&
2655                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2656                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2657                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2658
2659                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2660                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2661                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2662
2663                 if (ah->ah_config.pcie_clock_req)
2664                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2665                 else
2666                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2667
2668                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2669                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2670                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2671
2672                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2673
2674                 udelay(1000);
2675         } else {
2676                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2677                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2678                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2679                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2680                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2681                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2682                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2683                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2684                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2685                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2686         }
2687
2688         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2689
2690         if (ah->ah_config.pcie_waen) {
2691                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2692         } else {
2693                 if (AR_SREV_9285(ah))
2694                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2695                 else if (AR_SREV_9280(ah))
2696                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2697                 else
2698                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2699         }
2700 }
2701
2702 /**********************/
2703 /* Interrupt Handling */
2704 /**********************/
2705
2706 bool ath9k_hw_intrpend(struct ath_hw *ah)
2707 {
2708         u32 host_isr;
2709
2710         if (AR_SREV_9100(ah))
2711                 return true;
2712
2713         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2714         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2715                 return true;
2716
2717         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2718         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2719             && (host_isr != AR_INTR_SPURIOUS))
2720                 return true;
2721
2722         return false;
2723 }
2724
2725 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2726 {
2727         u32 isr = 0;
2728         u32 mask2 = 0;
2729         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2730         u32 sync_cause = 0;
2731         bool fatal_int = false;
2732
2733         if (!AR_SREV_9100(ah)) {
2734                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2735                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2736                             == AR_RTC_STATUS_ON) {
2737                                 isr = REG_READ(ah, AR_ISR);
2738                         }
2739                 }
2740
2741                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2742                         AR_INTR_SYNC_DEFAULT;
2743
2744                 *masked = 0;
2745
2746                 if (!isr && !sync_cause)
2747                         return false;
2748         } else {
2749                 *masked = 0;
2750                 isr = REG_READ(ah, AR_ISR);
2751         }
2752
2753         if (isr) {
2754                 if (isr & AR_ISR_BCNMISC) {
2755                         u32 isr2;
2756                         isr2 = REG_READ(ah, AR_ISR_S2);
2757                         if (isr2 & AR_ISR_S2_TIM)
2758                                 mask2 |= ATH9K_INT_TIM;
2759                         if (isr2 & AR_ISR_S2_DTIM)
2760                                 mask2 |= ATH9K_INT_DTIM;
2761                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2762                                 mask2 |= ATH9K_INT_DTIMSYNC;
2763                         if (isr2 & (AR_ISR_S2_CABEND))
2764                                 mask2 |= ATH9K_INT_CABEND;
2765                         if (isr2 & AR_ISR_S2_GTT)
2766                                 mask2 |= ATH9K_INT_GTT;
2767                         if (isr2 & AR_ISR_S2_CST)
2768                                 mask2 |= ATH9K_INT_CST;
2769                 }
2770
2771                 isr = REG_READ(ah, AR_ISR_RAC);
2772                 if (isr == 0xffffffff) {
2773                         *masked = 0;
2774                         return false;
2775                 }
2776
2777                 *masked = isr & ATH9K_INT_COMMON;
2778
2779                 if (ah->ah_intrMitigation) {
2780                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2781                                 *masked |= ATH9K_INT_RX;
2782                 }
2783
2784                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2785                         *masked |= ATH9K_INT_RX;
2786                 if (isr &
2787                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2788                      AR_ISR_TXEOL)) {
2789                         u32 s0_s, s1_s;
2790
2791                         *masked |= ATH9K_INT_TX;
2792
2793                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2794                         ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2795                         ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2796
2797                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2798                         ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2799                         ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2800                 }
2801
2802                 if (isr & AR_ISR_RXORN) {
2803                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2804                                 "receive FIFO overrun interrupt\n");
2805                 }
2806
2807                 if (!AR_SREV_9100(ah)) {
2808                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2809                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2810                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2811                                         *masked |= ATH9K_INT_TIM_TIMER;
2812                         }
2813                 }
2814
2815                 *masked |= mask2;
2816         }
2817
2818         if (AR_SREV_9100(ah))
2819                 return true;
2820
2821         if (sync_cause) {
2822                 fatal_int =
2823                         (sync_cause &
2824                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2825                         ? true : false;
2826
2827                 if (fatal_int) {
2828                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2829                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2830                                         "received PCI FATAL interrupt\n");
2831                         }
2832                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2833                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2834                                         "received PCI PERR interrupt\n");
2835                         }
2836                 }
2837                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2838                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2839                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2840                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2841                         REG_WRITE(ah, AR_RC, 0);
2842                         *masked |= ATH9K_INT_FATAL;
2843                 }
2844                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2845                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2846                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2847                 }
2848
2849                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2850                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2851         }
2852
2853         return true;
2854 }
2855
2856 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2857 {
2858         return ah->ah_maskReg;
2859 }
2860
2861 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2862 {
2863         u32 omask = ah->ah_maskReg;
2864         u32 mask, mask2;
2865         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2866
2867         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2868
2869         if (omask & ATH9K_INT_GLOBAL) {
2870                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2871                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2872                 (void) REG_READ(ah, AR_IER);
2873                 if (!AR_SREV_9100(ah)) {
2874                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2875                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2876
2877                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2878                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2879                 }
2880         }
2881
2882         mask = ints & ATH9K_INT_COMMON;
2883         mask2 = 0;
2884
2885         if (ints & ATH9K_INT_TX) {
2886                 if (ah->ah_txOkInterruptMask)
2887                         mask |= AR_IMR_TXOK;
2888                 if (ah->ah_txDescInterruptMask)
2889                         mask |= AR_IMR_TXDESC;
2890                 if (ah->ah_txErrInterruptMask)
2891                         mask |= AR_IMR_TXERR;
2892                 if (ah->ah_txEolInterruptMask)
2893                         mask |= AR_IMR_TXEOL;
2894         }
2895         if (ints & ATH9K_INT_RX) {
2896                 mask |= AR_IMR_RXERR;
2897                 if (ah->ah_intrMitigation)
2898                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2899                 else
2900                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2901                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2902                         mask |= AR_IMR_GENTMR;
2903         }
2904
2905         if (ints & (ATH9K_INT_BMISC)) {
2906                 mask |= AR_IMR_BCNMISC;
2907                 if (ints & ATH9K_INT_TIM)
2908                         mask2 |= AR_IMR_S2_TIM;
2909                 if (ints & ATH9K_INT_DTIM)
2910                         mask2 |= AR_IMR_S2_DTIM;
2911                 if (ints & ATH9K_INT_DTIMSYNC)
2912                         mask2 |= AR_IMR_S2_DTIMSYNC;
2913                 if (ints & ATH9K_INT_CABEND)
2914                         mask2 |= (AR_IMR_S2_CABEND);
2915         }
2916
2917         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2918                 mask |= AR_IMR_BCNMISC;
2919                 if (ints & ATH9K_INT_GTT)
2920                         mask2 |= AR_IMR_S2_GTT;
2921                 if (ints & ATH9K_INT_CST)
2922                         mask2 |= AR_IMR_S2_CST;
2923         }
2924
2925         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2926         REG_WRITE(ah, AR_IMR, mask);
2927         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2928                                            AR_IMR_S2_DTIM |
2929                                            AR_IMR_S2_DTIMSYNC |
2930                                            AR_IMR_S2_CABEND |
2931                                            AR_IMR_S2_CABTO |
2932                                            AR_IMR_S2_TSFOOR |
2933                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2934         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2935         ah->ah_maskReg = ints;
2936
2937         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2938                 if (ints & ATH9K_INT_TIM_TIMER)
2939                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2940                 else
2941                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2942         }
2943
2944         if (ints & ATH9K_INT_GLOBAL) {
2945                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
2946                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2947                 if (!AR_SREV_9100(ah)) {
2948                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2949                                   AR_INTR_MAC_IRQ);
2950                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2951
2952
2953                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2954                                   AR_INTR_SYNC_DEFAULT);
2955                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2956                                   AR_INTR_SYNC_DEFAULT);
2957                 }
2958                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2959                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2960         }
2961
2962         return omask;
2963 }
2964
2965 /*******************/
2966 /* Beacon Handling */
2967 /*******************/
2968
2969 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2970 {
2971         int flags = 0;
2972
2973         ah->ah_beaconInterval = beacon_period;
2974
2975         switch (ah->ah_opmode) {
2976         case NL80211_IFTYPE_STATION:
2977         case NL80211_IFTYPE_MONITOR:
2978                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2979                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2980                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2981                 flags |= AR_TBTT_TIMER_EN;
2982                 break;
2983         case NL80211_IFTYPE_ADHOC:
2984                 REG_SET_BIT(ah, AR_TXCFG,
2985                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2986                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2987                           TU_TO_USEC(next_beacon +
2988                                      (ah->ah_atimWindow ? ah->
2989                                       ah_atimWindow : 1)));
2990                 flags |= AR_NDP_TIMER_EN;
2991         case NL80211_IFTYPE_AP:
2992                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2993                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2994                           TU_TO_USEC(next_beacon -
2995                                      ah->ah_config.
2996                                      dma_beacon_response_time));
2997                 REG_WRITE(ah, AR_NEXT_SWBA,
2998                           TU_TO_USEC(next_beacon -
2999                                      ah->ah_config.
3000                                      sw_beacon_response_time));
3001                 flags |=
3002                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3003                 break;
3004         default:
3005                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3006                         "%s: unsupported opmode: %d\n",
3007                         __func__, ah->ah_opmode);
3008                 return;
3009                 break;
3010         }
3011
3012         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3013         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3014         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3015         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3016
3017         beacon_period &= ~ATH9K_BEACON_ENA;
3018         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3019                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3020                 ath9k_hw_reset_tsf(ah);
3021         }
3022
3023         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3024 }
3025
3026 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3027                                     const struct ath9k_beacon_state *bs)
3028 {
3029         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3030         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3031
3032         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3033
3034         REG_WRITE(ah, AR_BEACON_PERIOD,
3035                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3036         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3037                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3038
3039         REG_RMW_FIELD(ah, AR_RSSI_THR,
3040                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3041
3042         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3043
3044         if (bs->bs_sleepduration > beaconintval)
3045                 beaconintval = bs->bs_sleepduration;
3046
3047         dtimperiod = bs->bs_dtimperiod;
3048         if (bs->bs_sleepduration > dtimperiod)
3049                 dtimperiod = bs->bs_sleepduration;
3050
3051         if (beaconintval == dtimperiod)
3052                 nextTbtt = bs->bs_nextdtim;
3053         else
3054                 nextTbtt = bs->bs_nexttbtt;
3055
3056         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3057         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3058         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3059         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3060
3061         REG_WRITE(ah, AR_NEXT_DTIM,
3062                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3063         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3064
3065         REG_WRITE(ah, AR_SLEEP1,
3066                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3067                   | AR_SLEEP1_ASSUME_DTIM);
3068
3069         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3070                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3071         else
3072                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3073
3074         REG_WRITE(ah, AR_SLEEP2,
3075                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3076
3077         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3078         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3079
3080         REG_SET_BIT(ah, AR_TIMER_MODE,
3081                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3082                     AR_DTIM_TIMER_EN);
3083
3084 }
3085
3086 /*******************/
3087 /* HW Capabilities */
3088 /*******************/
3089
3090 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3091 {
3092         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3093         u16 capField = 0, eeval;
3094
3095         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3096
3097         ah->regulatory.current_rd = eeval;
3098
3099         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3100         ah->regulatory.current_rd_ext = eeval;
3101
3102         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3103
3104         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3105             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3106                 if (ah->regulatory.current_rd == 0x64 ||
3107                     ah->regulatory.current_rd == 0x65)
3108                         ah->regulatory.current_rd += 5;
3109                 else if (ah->regulatory.current_rd == 0x41)
3110                         ah->regulatory.current_rd = 0x43;
3111                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3112                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3113         }
3114
3115         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3116         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3117
3118         if (eeval & AR5416_OPFLAGS_11A) {
3119                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3120                 if (ah->ah_config.ht_enable) {
3121                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3122                                 set_bit(ATH9K_MODE_11NA_HT20,
3123                                         pCap->wireless_modes);
3124                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3125                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3126                                         pCap->wireless_modes);
3127                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3128                                         pCap->wireless_modes);
3129                         }
3130                 }
3131         }
3132
3133         if (eeval & AR5416_OPFLAGS_11G) {
3134                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3135                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3136                 if (ah->ah_config.ht_enable) {
3137                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3138                                 set_bit(ATH9K_MODE_11NG_HT20,
3139                                         pCap->wireless_modes);
3140                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3141                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3142                                         pCap->wireless_modes);
3143                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3144                                         pCap->wireless_modes);
3145                         }
3146                 }
3147         }
3148
3149         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3150         if ((ah->ah_isPciExpress)
3151             || (eeval & AR5416_OPFLAGS_11A)) {
3152                 pCap->rx_chainmask =
3153                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3154         } else {
3155                 pCap->rx_chainmask =
3156                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3157         }
3158
3159         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3160                 ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3161
3162         pCap->low_2ghz_chan = 2312;
3163         pCap->high_2ghz_chan = 2732;
3164
3165         pCap->low_5ghz_chan = 4920;
3166         pCap->high_5ghz_chan = 6100;
3167
3168         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3169         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3170         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3171
3172         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3173         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3174         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3175
3176         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3177
3178         if (ah->ah_config.ht_enable)
3179                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3180         else
3181                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3182
3183         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3184         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3185         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3186         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3187
3188         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3189                 pCap->total_queues =
3190                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3191         else
3192                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3193
3194         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3195                 pCap->keycache_size =
3196                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3197         else
3198                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3199
3200         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3201         pCap->num_mr_retries = 4;
3202         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3203
3204         if (AR_SREV_9285_10_OR_LATER(ah))
3205                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3206         else if (AR_SREV_9280_10_OR_LATER(ah))
3207                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3208         else
3209                 pCap->num_gpio_pins = AR_NUM_GPIO;
3210
3211         if (AR_SREV_9280_10_OR_LATER(ah)) {
3212                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3213                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3214         } else {
3215                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3216                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3217         }
3218
3219         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3220                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3221                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3222         } else {
3223                 pCap->rts_aggr_limit = (8 * 1024);
3224         }
3225
3226         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3227
3228 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3229         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3230         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3231                 ah->ah_rfkill_gpio =
3232                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3233                 ah->ah_rfkill_polarity =
3234                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3235
3236                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3237         }
3238 #endif
3239
3240         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3241             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3242             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3243             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3244             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3245                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3246         else
3247                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3248
3249         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3250                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3251         else
3252                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3253
3254         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3255                 pCap->reg_cap =
3256                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3257                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3258                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3259                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3260         } else {
3261                 pCap->reg_cap =
3262                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3263                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3264         }
3265
3266         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3267
3268         pCap->num_antcfg_5ghz =
3269                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3270         pCap->num_antcfg_2ghz =
3271                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3272
3273         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3274                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3275                 ah->ah_btactive_gpio = 6;
3276                 ah->ah_wlanactive_gpio = 5;
3277         }
3278
3279         return true;
3280 }
3281
3282 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3283                             u32 capability, u32 *result)
3284 {
3285         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3286
3287         switch (type) {
3288         case ATH9K_CAP_CIPHER:
3289                 switch (capability) {
3290                 case ATH9K_CIPHER_AES_CCM:
3291                 case ATH9K_CIPHER_AES_OCB:
3292                 case ATH9K_CIPHER_TKIP:
3293                 case ATH9K_CIPHER_WEP:
3294                 case ATH9K_CIPHER_MIC:
3295                 case ATH9K_CIPHER_CLR:
3296                         return true;
3297                 default:
3298                         return false;
3299                 }
3300         case ATH9K_CAP_TKIP_MIC:
3301                 switch (capability) {
3302                 case 0:
3303                         return true;
3304                 case 1:
3305                         return (ah->ah_staId1Defaults &
3306                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3307                         false;
3308                 }
3309         case ATH9K_CAP_TKIP_SPLIT:
3310                 return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3311                         false : true;
3312         case ATH9K_CAP_WME_TKIPMIC:
3313                 return 0;
3314         case ATH9K_CAP_PHYCOUNTERS:
3315                 return ah->ah_hasHwPhyCounters ? 0 : -ENXIO;
3316         case ATH9K_CAP_DIVERSITY:
3317                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3318                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3319                         true : false;
3320         case ATH9K_CAP_PHYDIAG:
3321                 return true;
3322         case ATH9K_CAP_MCAST_KEYSRCH:
3323                 switch (capability) {
3324                 case 0:
3325                         return true;
3326                 case 1:
3327                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3328                                 return false;
3329                         } else {
3330                                 return (ah->ah_staId1Defaults &
3331                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3332                                         false;
3333                         }
3334                 }
3335                 return false;
3336         case ATH9K_CAP_TSF_ADJUST:
3337                 return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3338                         true : false;
3339         case ATH9K_CAP_RFSILENT:
3340                 if (capability == 3)
3341                         return false;
3342         case ATH9K_CAP_ANT_CFG_2GHZ:
3343                 *result = pCap->num_antcfg_2ghz;
3344                 return true;
3345         case ATH9K_CAP_ANT_CFG_5GHZ:
3346                 *result = pCap->num_antcfg_5ghz;
3347                 return true;
3348         case ATH9K_CAP_TXPOW:
3349                 switch (capability) {
3350                 case 0:
3351                         return 0;
3352                 case 1:
3353                         *result = ah->regulatory.power_limit;
3354                         return 0;
3355                 case 2:
3356                         *result = ah->regulatory.max_power_level;
3357                         return 0;
3358                 case 3:
3359                         *result = ah->regulatory.tp_scale;
3360                         return 0;
3361                 }
3362                 return false;
3363         default:
3364                 return false;
3365         }
3366 }
3367
3368 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3369                             u32 capability, u32 setting, int *status)
3370 {
3371         u32 v;
3372
3373         switch (type) {
3374         case ATH9K_CAP_TKIP_MIC:
3375                 if (setting)
3376                         ah->ah_staId1Defaults |=
3377                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3378                 else
3379                         ah->ah_staId1Defaults &=
3380                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3381                 return true;
3382         case ATH9K_CAP_DIVERSITY:
3383                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3384                 if (setting)
3385                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3386                 else
3387                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3388                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3389                 return true;
3390         case ATH9K_CAP_MCAST_KEYSRCH:
3391                 if (setting)
3392                         ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3393                 else
3394                         ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3395                 return true;
3396         case ATH9K_CAP_TSF_ADJUST:
3397                 if (setting)
3398                         ah->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3399                 else
3400                         ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3401                 return true;
3402         default:
3403                 return false;
3404         }
3405 }
3406
3407 /****************************/
3408 /* GPIO / RFKILL / Antennae */
3409 /****************************/
3410
3411 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3412                                          u32 gpio, u32 type)
3413 {
3414         int addr;
3415         u32 gpio_shift, tmp;
3416
3417         if (gpio > 11)
3418                 addr = AR_GPIO_OUTPUT_MUX3;
3419         else if (gpio > 5)
3420                 addr = AR_GPIO_OUTPUT_MUX2;
3421         else
3422                 addr = AR_GPIO_OUTPUT_MUX1;
3423
3424         gpio_shift = (gpio % 6) * 5;
3425
3426         if (AR_SREV_9280_20_OR_LATER(ah)
3427             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3428                 REG_RMW(ah, addr, (type << gpio_shift),
3429                         (0x1f << gpio_shift));
3430         } else {
3431                 tmp = REG_READ(ah, addr);
3432                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3433                 tmp &= ~(0x1f << gpio_shift);
3434                 tmp |= (type << gpio_shift);
3435                 REG_WRITE(ah, addr, tmp);
3436         }
3437 }
3438
3439 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3440 {
3441         u32 gpio_shift;
3442
3443         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3444
3445         gpio_shift = gpio << 1;
3446
3447         REG_RMW(ah,
3448                 AR_GPIO_OE_OUT,
3449                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3450                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3451 }
3452
3453 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3454 {
3455 #define MS_REG_READ(x, y) \
3456         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3457
3458         if (gpio >= ah->ah_caps.num_gpio_pins)
3459                 return 0xffffffff;
3460
3461         if (AR_SREV_9285_10_OR_LATER(ah))
3462                 return MS_REG_READ(AR9285, gpio) != 0;
3463         else if (AR_SREV_9280_10_OR_LATER(ah))
3464                 return MS_REG_READ(AR928X, gpio) != 0;
3465         else
3466                 return MS_REG_READ(AR, gpio) != 0;
3467 }
3468
3469 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3470                          u32 ah_signal_type)
3471 {
3472         u32 gpio_shift;
3473
3474         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3475
3476         gpio_shift = 2 * gpio;
3477
3478         REG_RMW(ah,
3479                 AR_GPIO_OE_OUT,
3480                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3481                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3482 }
3483
3484 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3485 {
3486         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3487                 AR_GPIO_BIT(gpio));
3488 }
3489
3490 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3491 void ath9k_enable_rfkill(struct ath_hw *ah)
3492 {
3493         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3494                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3495
3496         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3497                     AR_GPIO_INPUT_MUX2_RFSILENT);
3498
3499         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3500         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3501 }
3502 #endif
3503
3504 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3505 {
3506         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3507 }
3508
3509 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3510 {
3511         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3512 }
3513
3514 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3515                                enum ath9k_ant_setting settings,
3516                                struct ath9k_channel *chan,
3517                                u8 *tx_chainmask,
3518                                u8 *rx_chainmask,
3519                                u8 *antenna_cfgd)
3520 {
3521         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3522
3523         if (AR_SREV_9280(ah)) {
3524                 if (!tx_chainmask_cfg) {
3525
3526                         tx_chainmask_cfg = *tx_chainmask;
3527                         rx_chainmask_cfg = *rx_chainmask;
3528                 }
3529
3530                 switch (settings) {
3531                 case ATH9K_ANT_FIXED_A:
3532                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3533                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3534                         *antenna_cfgd = true;
3535                         break;
3536                 case ATH9K_ANT_FIXED_B:
3537                         if (ah->ah_caps.tx_chainmask >
3538                             ATH9K_ANTENNA1_CHAINMASK) {
3539                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3540                         }
3541                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3542                         *antenna_cfgd = true;
3543                         break;
3544                 case ATH9K_ANT_VARIABLE:
3545                         *tx_chainmask = tx_chainmask_cfg;
3546                         *rx_chainmask = rx_chainmask_cfg;
3547                         *antenna_cfgd = true;
3548                         break;
3549                 default:
3550                         break;
3551                 }
3552         } else {
3553                 ah->ah_diversityControl = settings;
3554         }
3555
3556         return true;
3557 }
3558
3559 /*********************/
3560 /* General Operation */
3561 /*********************/
3562
3563 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3564 {
3565         u32 bits = REG_READ(ah, AR_RX_FILTER);
3566         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3567
3568         if (phybits & AR_PHY_ERR_RADAR)
3569                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3570         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3571                 bits |= ATH9K_RX_FILTER_PHYERR;
3572
3573         return bits;
3574 }
3575
3576 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3577 {
3578         u32 phybits;
3579
3580         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3581         phybits = 0;
3582         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3583                 phybits |= AR_PHY_ERR_RADAR;
3584         if (bits & ATH9K_RX_FILTER_PHYERR)
3585                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3586         REG_WRITE(ah, AR_PHY_ERR, phybits);
3587
3588         if (phybits)
3589                 REG_WRITE(ah, AR_RXCFG,
3590                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3591         else
3592                 REG_WRITE(ah, AR_RXCFG,
3593                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3594 }
3595
3596 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3597 {
3598         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3599 }
3600
3601 bool ath9k_hw_disable(struct ath_hw *ah)
3602 {
3603         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3604                 return false;
3605
3606         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3607 }
3608
3609 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3610 {
3611         struct ath9k_channel *chan = ah->ah_curchan;
3612         struct ieee80211_channel *channel = chan->chan;
3613
3614         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3615
3616         if (ath9k_hw_set_txpower(ah, chan,
3617                                  ath9k_regd_get_ctl(ah, chan),
3618                                  channel->max_antenna_gain * 2,
3619                                  channel->max_power * 2,
3620                                  min((u32) MAX_RATE_POWER,
3621                                      (u32) ah->regulatory.power_limit)) != 0)
3622                 return false;
3623
3624         return true;
3625 }
3626
3627 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3628 {
3629         memcpy(ah->macaddr, mac, ETH_ALEN);
3630 }
3631
3632 void ath9k_hw_setopmode(struct ath_hw *ah)
3633 {
3634         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3635 }
3636
3637 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3638 {
3639         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3640         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3641 }
3642
3643 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3644 {
3645         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3646         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3647 }
3648
3649 void ath9k_hw_write_associd(struct ath_softc *sc)
3650 {
3651         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3652         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3653                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3654 }
3655
3656 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3657 {
3658         u64 tsf;
3659
3660         tsf = REG_READ(ah, AR_TSF_U32);
3661         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3662
3663         return tsf;
3664 }
3665
3666 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3667 {
3668         REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3669         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3670         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3671 }
3672
3673 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3674 {
3675         int count;
3676
3677         count = 0;
3678         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3679                 count++;
3680                 if (count > 10) {
3681                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3682                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3683                         break;
3684                 }
3685                 udelay(10);
3686         }
3687         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3688 }
3689
3690 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3691 {
3692         if (setting)
3693                 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3694         else
3695                 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3696
3697         return true;
3698 }
3699
3700 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3701 {
3702         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3703                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3704                 ah->ah_slottime = (u32) -1;
3705                 return false;
3706         } else {
3707                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3708                 ah->ah_slottime = us;
3709                 return true;
3710         }
3711 }
3712
3713 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3714 {
3715         u32 macmode;
3716
3717         if (mode == ATH9K_HT_MACMODE_2040 &&
3718             !ah->ah_config.cwm_ignore_extcca)
3719                 macmode = AR_2040_JOINED_RX_CLEAR;
3720         else
3721                 macmode = 0;
3722
3723         REG_WRITE(ah, AR_2040_MODE, macmode);
3724 }
3725
3726 /***************************/
3727 /*  Bluetooth Coexistence  */
3728 /***************************/
3729
3730 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3731 {
3732         /* connect bt_active to baseband */
3733         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3734                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3735                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3736
3737         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3738                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3739
3740         /* Set input mux for bt_active to gpio pin */
3741         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3742                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3743                         ah->ah_btactive_gpio);
3744
3745         /* Configure the desired gpio port for input */
3746         ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3747
3748         /* Configure the desired GPIO port for TX_FRAME output */
3749         ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3750                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3751 }