drivers/net/wireless/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef EEPROM_H
  18 #define EEPROM_H
  19
  20 #define AH_USE_EEPROM   0x1
  21
  22 #ifdef __BIG_ENDIAN
  23 #define AR5416_EEPROM_MAGIC 0x5aa5
  24 #else
  25 #define AR5416_EEPROM_MAGIC 0xa55a
  26 #endif
  27
  28 #define CTRY_DEBUG   0x1ff
  29 #define CTRY_DEFAULT 0
  30
  31 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  32 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  33 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  34 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  35 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  36 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  37 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  38 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  39 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  40
  41 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  42 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  43 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  44 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  46 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  47
  48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  50
  51 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  52 #define AR5416_EEPROM_S             2
  53 #define AR5416_EEPROM_OFFSET        0x2000
  54 #define AR5416_EEPROM_MAX           0xae0
  55
  56 #define AR5416_EEPROM_START_ADDR \
  57         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  58
  59 #define SD_NO_CTL               0xE0
  60 #define NO_CTL                  0xff
  61 #define CTL_MODE_M              7
  62 #define CTL_11A                 0
  63 #define CTL_11B                 1
  64 #define CTL_11G                 2
  65 #define CTL_2GHT20              5
  66 #define CTL_5GHT20              6
  67 #define CTL_2GHT40              7
  68 #define CTL_5GHT40              8
  69
  70 #define EXT_ADDITIVE (0x8000)
  71 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  72 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  73 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  74
  75 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  76 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  77
  78 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  79 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  80
  81 /*
  82  * For AR9285 and later chipsets, the following bits are not being programmed
  83  * in EEPROM and so need to be enabled always.
  84  *
  85  * Bit 0: en_fcc_mid
  86  * Bit 1: en_jap_mid
  87  * Bit 2: en_fcc_dfs_ht40
  88  * Bit 3: en_jap_ht40
  89  * Bit 4: en_jap_dfs_ht40
  90  */
  91 #define AR9285_RDEXT_DEFAULT    0x1F
  92
  93 #define AR_EEPROM_MAC(i)        (0x1d+(i))
  94 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
  95 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  96 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
  97
  98 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
  99                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 100
 101 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 102 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 103 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 104 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 105
 106 #define EEP_RFSILENT_ENABLED        0x0001
 107 #define EEP_RFSILENT_ENABLED_S      0
 108 #define EEP_RFSILENT_POLARITY       0x0002
 109 #define EEP_RFSILENT_POLARITY_S     1
 110 #define EEP_RFSILENT_GPIO_SEL       0x001c
 111 #define EEP_RFSILENT_GPIO_SEL_S     2
 112
 113 #define AR5416_OPFLAGS_11A           0x01
 114 #define AR5416_OPFLAGS_11G           0x02
 115 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 116 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 117 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 118 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 119
 120 #define AR5416_EEP_NO_BACK_VER       0x1
 121 #define AR5416_EEP_VER               0xE
 122 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 123 #define AR5416_EEP_MINOR_VER_2       0x2
 124 #define AR5416_EEP_MINOR_VER_3       0x3
 125 #define AR5416_EEP_MINOR_VER_7       0x7
 126 #define AR5416_EEP_MINOR_VER_9       0x9
 127 #define AR5416_EEP_MINOR_VER_16      0x10
 128 #define AR5416_EEP_MINOR_VER_17      0x11
 129 #define AR5416_EEP_MINOR_VER_19      0x13
 130 #define AR5416_EEP_MINOR_VER_20      0x14
 131 #define AR5416_EEP_MINOR_VER_22      0x16
 132
 133 #define AR5416_NUM_5G_CAL_PIERS         8
 134 #define AR5416_NUM_2G_CAL_PIERS         4
 135 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 136 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 137 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 138 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 139 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 140 #define AR5416_NUM_CTLS                 24
 141 #define AR5416_NUM_BAND_EDGES           8
 142 #define AR5416_NUM_PD_GAINS             4
 143 #define AR5416_PD_GAINS_IN_MASK         4
 144 #define AR5416_PD_GAIN_ICEPTS           5
 145 #define AR5416_EEPROM_MODAL_SPURS       5
 146 #define AR5416_MAX_RATE_POWER           63
 147 #define AR5416_NUM_PDADC_VALUES         128
 148 #define AR5416_BCHAN_UNUSED             0xFF
 149 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 150 #define AR5416_MAX_CHAINS               3
 151 #define AR5416_PWR_TABLE_OFFSET         -5
 152
 153 /* Rx gain type values */
 154 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 155 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 156 #define AR5416_EEP_RXGAIN_ORIG             2
 157
 158 /* Tx gain type values */
 159 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 160 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 161
 162 #define AR5416_EEP4K_START_LOC                64
 163 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 164 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 165 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 166 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 167 #define AR5416_EEP4K_NUM_CTLS                 12
 168 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 169 #define AR5416_EEP4K_NUM_PD_GAINS             2
 170 #define AR5416_EEP4K_PD_GAINS_IN_MASK         4
 171 #define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 172 #define AR5416_EEP4K_MAX_CHAINS               1
 173
 174 #define AR9280_TX_GAIN_TABLE_SIZE 22
 175
 176 enum eeprom_param {
 177         EEP_NFTHRESH_5,
 178         EEP_NFTHRESH_2,
 179         EEP_MAC_MSW,
 180         EEP_MAC_MID,
 181         EEP_MAC_LSW,
 182         EEP_REG_0,
 183         EEP_REG_1,
 184         EEP_OP_CAP,
 185         EEP_OP_MODE,
 186         EEP_RF_SILENT,
 187         EEP_OB_5,
 188         EEP_DB_5,
 189         EEP_OB_2,
 190         EEP_DB_2,
 191         EEP_MINOR_REV,
 192         EEP_TX_MASK,
 193         EEP_RX_MASK,
 194         EEP_RXGAIN_TYPE,
 195         EEP_TXGAIN_TYPE,
 196         EEP_OL_PWRCTRL,
 197         EEP_RC_CHAIN_MASK,
 198         EEP_DAC_HPWR_5G,
 199         EEP_FRAC_N_5G
 200 };
 201
 202 enum ar5416_rates {
 203         rate6mb, rate9mb, rate12mb, rate18mb,
 204         rate24mb, rate36mb, rate48mb, rate54mb,
 205         rate1l, rate2l, rate2s, rate5_5l,
 206         rate5_5s, rate11l, rate11s, rateXr,
 207         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 208         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 209         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 210         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 211         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 212         Ar5416RateSize
 213 };
 214
 215 enum ath9k_hal_freq_band {
 216         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 217         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 218 };
 219
 220 struct base_eep_header {
 221         u16 length;
 222         u16 checksum;
 223         u16 version;
 224         u8 opCapFlags;
 225         u8 eepMisc;
 226         u16 regDmn[2];
 227         u8 macAddr[6];
 228         u8 rxMask;
 229         u8 txMask;
 230         u16 rfSilent;
 231         u16 blueToothOptions;
 232         u16 deviceCap;
 233         u32 binBuildNumber;
 234         u8 deviceType;
 235         u8 pwdclkind;
 236         u8 futureBase_1[2];
 237         u8 rxGainType;
 238         u8 dacHiPwrMode_5G;
 239         u8 openLoopPwrCntl;
 240         u8 dacLpMode;
 241         u8 txGainType;
 242         u8 rcChainMask;
 243         u8 desiredScaleCCK;
 244         u8 power_table_offset;
 245         u8 frac_n_5g;
 246         u8 futureBase_3[21];
 247 } __packed;
 248
 249 struct base_eep_header_4k {
 250         u16 length;
 251         u16 checksum;
 252         u16 version;
 253         u8 opCapFlags;
 254         u8 eepMisc;
 255         u16 regDmn[2];
 256         u8 macAddr[6];
 257         u8 rxMask;
 258         u8 txMask;
 259         u16 rfSilent;
 260         u16 blueToothOptions;
 261         u16 deviceCap;
 262         u32 binBuildNumber;
 263         u8 deviceType;
 264         u8 futureBase[1];
 265 } __packed;
 266
 267
 268 struct spur_chan {
 269         u16 spurChan;
 270         u8 spurRangeLow;
 271         u8 spurRangeHigh;
 272 } __packed;
 273
 274 struct modal_eep_header {
 275         u32 antCtrlChain[AR5416_MAX_CHAINS];
 276         u32 antCtrlCommon;
 277         u8 antennaGainCh[AR5416_MAX_CHAINS];
 278         u8 switchSettling;
 279         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 280         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 281         u8 adcDesiredSize;
 282         u8 pgaDesiredSize;
 283         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 284         u8 txEndToXpaOff;
 285         u8 txEndToRxOn;
 286         u8 txFrameToXpaOn;
 287         u8 thresh62;
 288         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 289         u8 xpdGain;
 290         u8 xpd;
 291         u8 iqCalICh[AR5416_MAX_CHAINS];
 292         u8 iqCalQCh[AR5416_MAX_CHAINS];
 293         u8 pdGainOverlap;
 294         u8 ob;
 295         u8 db;
 296         u8 xpaBiasLvl;
 297         u8 pwrDecreaseFor2Chain;
 298         u8 pwrDecreaseFor3Chain;
 299         u8 txFrameToDataStart;
 300         u8 txFrameToPaOn;
 301         u8 ht40PowerIncForPdadc;
 302         u8 bswAtten[AR5416_MAX_CHAINS];
 303         u8 bswMargin[AR5416_MAX_CHAINS];
 304         u8 swSettleHt40;
 305         u8 xatten2Db[AR5416_MAX_CHAINS];
 306         u8 xatten2Margin[AR5416_MAX_CHAINS];
 307         u8 ob_ch1;
 308         u8 db_ch1;
 309         u8 useAnt1:1,
 310             force_xpaon:1,
 311             local_bias:1,
 312             femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
 313         u8 miscBits;
 314         u16 xpaBiasLvlFreq[3];
 315         u8 futureModal[6];
 316
 317         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 318 } __packed;
 319
 320 struct calDataPerFreqOpLoop {
 321         u8 pwrPdg[2][5];
 322         u8 vpdPdg[2][5];
 323         u8 pcdac[2][5];
 324         u8 empty[2][5];
 325 } __packed;
 326
 327 struct modal_eep_4k_header {
 328         u32  antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 329         u32  antCtrlCommon;
 330         u8   antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 331         u8   switchSettling;
 332         u8   txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 333         u8   rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 334         u8   adcDesiredSize;
 335         u8   pgaDesiredSize;
 336         u8   xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 337         u8   txEndToXpaOff;
 338         u8   txEndToRxOn;
 339         u8   txFrameToXpaOn;
 340         u8   thresh62;
 341         u8   noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 342         u8   xpdGain;
 343         u8   xpd;
 344         u8   iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 345         u8   iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 346         u8   pdGainOverlap;
 347         u8   ob_01;
 348         u8   db1_01;
 349         u8   xpaBiasLvl;
 350         u8   txFrameToDataStart;
 351         u8   txFrameToPaOn;
 352         u8   ht40PowerIncForPdadc;
 353         u8   bswAtten[AR5416_EEP4K_MAX_CHAINS];
 354         u8   bswMargin[AR5416_EEP4K_MAX_CHAINS];
 355         u8   swSettleHt40;
 356         u8   xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 357         u8   xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 358         u8   db2_01;
 359         u8   version;
 360         u16  ob_234;
 361         u16  db1_234;
 362         u16  db2_234;
 363         u8   futureModal[4];
 364
 365         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 366 } __packed;
 367
 368
 369 struct cal_data_per_freq {
 370         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 371         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 372 } __packed;
 373
 374 struct cal_data_per_freq_4k {
 375         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 376         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 377 } __packed;
 378
 379 struct cal_target_power_leg {
 380         u8 bChannel;
 381         u8 tPow2x[4];
 382 } __packed;
 383
 384 struct cal_target_power_ht {
 385         u8 bChannel;
 386         u8 tPow2x[8];
 387 } __packed;
 388
 389
 390 #ifdef __BIG_ENDIAN_BITFIELD
 391 struct cal_ctl_edges {
 392         u8 bChannel;
 393         u8 flag:2, tPower:6;
 394 } __packed;
 395 #else
 396 struct cal_ctl_edges {
 397         u8 bChannel;
 398         u8 tPower:6, flag:2;
 399 } __packed;
 400 #endif
 401
 402 struct cal_ctl_data {
 403         struct cal_ctl_edges
 404         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 405 } __packed;
 406
 407 struct cal_ctl_data_4k {
 408         struct cal_ctl_edges
 409         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 410 } __packed;
 411
 412 struct ar5416_eeprom_def {
 413         struct base_eep_header baseEepHeader;
 414         u8 custData[64];
 415         struct modal_eep_header modalHeader[2];
 416         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 417         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 418         struct cal_data_per_freq
 419          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 420         struct cal_data_per_freq
 421          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 422         struct cal_target_power_leg
 423          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 424         struct cal_target_power_ht
 425          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 426         struct cal_target_power_ht
 427          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 428         struct cal_target_power_leg
 429          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 430         struct cal_target_power_leg
 431          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 432         struct cal_target_power_ht
 433          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 434         struct cal_target_power_ht
 435          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 436         u8 ctlIndex[AR5416_NUM_CTLS];
 437         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 438         u8 padding;
 439 } __packed;
 440
 441 struct ar5416_eeprom_4k {
 442         struct base_eep_header_4k baseEepHeader;
 443         u8 custData[20];
 444         struct modal_eep_4k_header modalHeader;
 445         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 446         struct cal_data_per_freq_4k
 447         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 448         struct cal_target_power_leg
 449         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 450         struct cal_target_power_leg
 451         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 452         struct cal_target_power_ht
 453         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 454         struct cal_target_power_ht
 455         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 456         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 457         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 458         u8 padding;
 459 } __packed;
 460
 461 enum reg_ext_bitmap {
 462         REG_EXT_JAPAN_MIDBAND = 1,
 463         REG_EXT_FCC_DFS_HT40 = 2,
 464         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 465         REG_EXT_JAPAN_DFS_HT40 = 4
 466 };
 467
 468 struct ath9k_country_entry {
 469         u16 countryCode;
 470         u16 regDmnEnum;
 471         u16 regDmn5G;
 472         u16 regDmn2G;
 473         u8 isMultidomain;
 474         u8 iso[3];
 475 };
 476
 477 enum ath9k_eep_map {
 478         EEP_MAP_DEFAULT = 0x0,
 479         EEP_MAP_4KBITS,
 480         EEP_MAP_MAX
 481 };
 482
 483 struct eeprom_ops {
 484         int (*check_eeprom)(struct ath_hw *hw);
 485         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 486         bool (*fill_eeprom)(struct ath_hw *hw);
 487         int (*get_eeprom_ver)(struct ath_hw *hw);
 488         int (*get_eeprom_rev)(struct ath_hw *hw);
 489         u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
 490         u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
 491                                       struct ath9k_channel *chan);
 492         bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 493         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 494         int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 495                            u16 cfgCtl, u8 twiceAntennaReduction,
 496                            u8 twiceMaxRegulatoryPower, u8 powerLimit);
 497         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 498 };
 499
 500 #define ar5416_get_ntxchains(_txchainmask)                      \
 501         (((_txchainmask >> 2) & 1) +                            \
 502          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 503
 504 int ath9k_hw_eeprom_attach(struct ath_hw *ah);
 505
 506 #endif /* EEPROM_H */