2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
145 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
152 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
161 if (txq != sc->tx.txq_map[q])
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
174 static struct ath_atx_tid *
175 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
177 struct ieee80211_hdr *hdr;
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
188 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
193 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
197 skb = __skb_dequeue(&tid->retry_q);
199 skb = __skb_dequeue(&tid->buf_q);
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
210 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
216 struct ath_frame_info *fi;
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
239 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
241 struct ath_txq *txq = tid->ac->txq;
244 struct list_head bf_head;
245 struct ath_tx_status ts;
246 struct ath_frame_info *fi;
247 bool sendbar = false;
249 INIT_LIST_HEAD(&bf_head);
251 memset(&ts, 0, sizeof(ts));
253 while ((skb = __skb_dequeue(&tid->retry_q))) {
254 fi = get_frame_info(skb);
257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
262 if (fi->baw_tracked) {
263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
272 ath_txq_unlock(sc, txq);
273 ath_send_bar(tid, tid->seq_start);
274 ath_txq_lock(sc, txq);
278 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
286 __clear_bit(cindex, tid->tx_buf);
288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
291 if (tid->bar_index >= 0)
296 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
303 index = ATH_BA_INDEX(tid->seq_start, seqno);
304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
305 __set_bit(cindex, tid->tx_buf);
308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
315 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
321 struct list_head bf_head;
322 struct ath_tx_status ts;
323 struct ath_frame_info *fi;
325 memset(&ts, 0, sizeof(ts));
326 INIT_LIST_HEAD(&bf_head);
328 while ((skb = ath_tid_dequeue(tid))) {
329 fi = get_frame_info(skb);
333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
337 list_add_tail(&bf->list, &bf_head);
338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
342 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
343 struct sk_buff *skb, int count)
345 struct ath_frame_info *fi = get_frame_info(skb);
346 struct ath_buf *bf = fi->bf;
347 struct ieee80211_hdr *hdr;
348 int prev = fi->retries;
350 TX_STAT_INC(txq->axq_qnum, a_retries);
351 fi->retries += count;
356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
362 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
364 struct ath_buf *bf = NULL;
366 spin_lock_bh(&sc->tx.txbuflock);
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
369 spin_unlock_bh(&sc->tx.txbuflock);
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
376 spin_unlock_bh(&sc->tx.txbuflock);
381 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
388 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
392 tbf = ath_tx_get_buffer(sc);
396 ATH_TXBUF_RESET(tbf);
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
401 tbf->bf_state = bf->bf_state;
402 tbf->bf_state.stale = false;
407 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
408 struct ath_tx_status *ts, int txok,
409 int *nframes, int *nbad)
411 struct ath_frame_info *fi;
413 u32 ba[WME_BA_BMP_SIZE >> 5];
420 isaggr = bf_isaggr(bf);
422 seq_st = ts->ts_seqnum;
423 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
427 fi = get_frame_info(bf->bf_mpdu);
428 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
431 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
439 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
440 struct ath_buf *bf, struct list_head *bf_q,
441 struct ath_tx_status *ts, int txok)
443 struct ath_node *an = NULL;
445 struct ieee80211_sta *sta;
446 struct ieee80211_hw *hw = sc->hw;
447 struct ieee80211_hdr *hdr;
448 struct ieee80211_tx_info *tx_info;
449 struct ath_atx_tid *tid = NULL;
450 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
451 struct list_head bf_head;
452 struct sk_buff_head bf_pending;
453 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
454 u32 ba[WME_BA_BMP_SIZE >> 5];
455 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
456 bool rc_update = true, isba;
457 struct ieee80211_tx_rate rates[4];
458 struct ath_frame_info *fi;
460 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
465 hdr = (struct ieee80211_hdr *)skb->data;
467 tx_info = IEEE80211_SKB_CB(skb);
469 memcpy(rates, bf->rates, sizeof(rates));
471 retries = ts->ts_longretry + 1;
472 for (i = 0; i < ts->ts_rateindex; i++)
473 retries += rates[i].count;
477 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
481 INIT_LIST_HEAD(&bf_head);
483 bf_next = bf->bf_next;
485 if (!bf->bf_state.stale || bf_next != NULL)
486 list_move_tail(&bf->list, &bf_head);
488 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
495 an = (struct ath_node *)sta->drv_priv;
496 tid = ath_get_skb_tid(sc, an, skb);
497 seq_first = tid->seq_start;
498 isba = ts->ts_flags & ATH9K_TX_BA;
501 * The hardware occasionally sends a tx status for the wrong TID.
502 * In this case, the BA status cannot be considered valid and all
503 * subframes need to be retransmitted
505 * Only BlockAcks have a TID and therefore normal Acks cannot be
508 if (isba && tid->tidno != ts->tid)
511 isaggr = bf_isaggr(bf);
512 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
514 if (isaggr && txok) {
515 if (ts->ts_flags & ATH9K_TX_BA) {
516 seq_st = ts->ts_seqnum;
517 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
520 * AR5416 can become deaf/mute when BA
521 * issue happens. Chip needs to be reset.
522 * But AP code may have sychronization issues
523 * when perform internal reset in this routine.
524 * Only enable reset in STA mode for now.
526 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
531 __skb_queue_head_init(&bf_pending);
533 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
535 u16 seqno = bf->bf_state.seqno;
537 txfail = txpending = sendbar = 0;
538 bf_next = bf->bf_next;
541 tx_info = IEEE80211_SKB_CB(skb);
542 fi = get_frame_info(skb);
544 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
547 * Outside of the current BlockAck window,
548 * maybe part of a previous session
551 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
552 /* transmit completion, subframe is
553 * acked by block ack */
555 } else if (!isaggr && txok) {
556 /* transmit completion */
560 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
561 if (txok || !an->sleeping)
562 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
569 bar_index = max_t(int, bar_index,
570 ATH_BA_INDEX(seq_first, seqno));
574 * Make sure the last desc is reclaimed if it
575 * not a holding desc.
577 INIT_LIST_HEAD(&bf_head);
578 if (bf_next != NULL || !bf_last->bf_state.stale)
579 list_move_tail(&bf->list, &bf_head);
583 * complete the acked-ones/xretried ones; update
586 ath_tx_update_baw(sc, tid, seqno);
588 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
589 memcpy(tx_info->control.rates, rates, sizeof(rates));
590 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
594 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
597 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
598 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
599 ieee80211_sta_eosp(sta);
601 /* retry the un-acked ones */
602 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
605 tbf = ath_clone_txbuf(sc, bf_last);
607 * Update tx baw and complete the
608 * frame with failed status if we
612 ath_tx_update_baw(sc, tid, seqno);
614 ath_tx_complete_buf(sc, bf, txq,
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
628 __skb_queue_tail(&bf_pending, skb);
634 /* prepend un-acked frames to the beginning of the pending frame queue */
635 if (!skb_queue_empty(&bf_pending)) {
637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
641 ath_tx_queue_tid(txq, tid);
643 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
644 tid->ac->clear_ps_filter = true;
648 if (bar_index >= 0) {
649 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
651 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
652 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
654 ath_txq_unlock(sc, txq);
655 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
656 ath_txq_lock(sc, txq);
662 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
665 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
671 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
672 struct ath_tx_status *ts, struct ath_buf *bf,
673 struct list_head *bf_head)
675 struct ieee80211_tx_info *info;
678 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
679 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
680 txq->axq_tx_inprogress = false;
683 if (bf_is_ampdu_not_probing(bf))
684 txq->axq_ampdu_depth--;
686 if (!bf_isampdu(bf)) {
688 info = IEEE80211_SKB_CB(bf->bf_mpdu);
689 memcpy(info->control.rates, bf->rates,
690 sizeof(info->control.rates));
691 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
693 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
695 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
698 ath_txq_schedule(sc, txq);
701 static bool ath_lookup_legacy(struct ath_buf *bf)
704 struct ieee80211_tx_info *tx_info;
705 struct ieee80211_tx_rate *rates;
709 tx_info = IEEE80211_SKB_CB(skb);
710 rates = tx_info->control.rates;
712 for (i = 0; i < 4; i++) {
713 if (!rates[i].count || rates[i].idx < 0)
716 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
723 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
724 struct ath_atx_tid *tid)
727 struct ieee80211_tx_info *tx_info;
728 struct ieee80211_tx_rate *rates;
729 u32 max_4ms_framelen, frmlen;
730 u16 aggr_limit, bt_aggr_limit, legacy = 0;
731 int q = tid->ac->txq->mac80211_qnum;
735 tx_info = IEEE80211_SKB_CB(skb);
739 * Find the lowest frame length among the rate series that will have a
740 * 4ms (or TXOP limited) transmit duration.
742 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
744 for (i = 0; i < 4; i++) {
750 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
755 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
760 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
763 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
764 max_4ms_framelen = min(max_4ms_framelen, frmlen);
768 * limit aggregate size by the minimum rate if rate selected is
769 * not a probe rate, if rate selected is a probe rate then
770 * avoid aggregation of this packet.
772 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
775 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
778 * Override the default aggregation limit for BTCOEX.
780 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
782 aggr_limit = bt_aggr_limit;
785 * h/w can accept aggregates up to 16 bit lengths (65535).
786 * The IE, however can hold up to 65536, which shows up here
787 * as zero. Ignore 65536 since we are constrained by hw.
789 if (tid->an->maxampdu)
790 aggr_limit = min(aggr_limit, tid->an->maxampdu);
796 * Returns the number of delimiters to be added to
797 * meet the minimum required mpdudensity.
799 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
800 struct ath_buf *bf, u16 frmlen,
803 #define FIRST_DESC_NDELIMS 60
804 u32 nsymbits, nsymbols;
807 int width, streams, half_gi, ndelim, mindelim;
808 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
810 /* Select standard number of delimiters based on frame length alone */
811 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
814 * If encryption enabled, hardware requires some more padding between
816 * TODO - this could be improved to be dependent on the rate.
817 * The hardware can keep up at lower rates, but not higher rates
819 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
820 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
821 ndelim += ATH_AGGR_ENCRYPTDELIM;
824 * Add delimiter when using RTS/CTS with aggregation
825 * and non enterprise AR9003 card
827 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
828 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
829 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
832 * Convert desired mpdu density from microeconds to bytes based
833 * on highest rate in rate series (i.e. first rate) to determine
834 * required minimum length for subframe. Take into account
835 * whether high rate is 20 or 40Mhz and half or full GI.
837 * If there is no mpdu density restriction, no further calculation
841 if (tid->an->mpdudensity == 0)
844 rix = bf->rates[0].idx;
845 flags = bf->rates[0].flags;
846 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
847 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
850 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
852 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
857 streams = HT_RC_2_STREAMS(rix);
858 nsymbits = bits_per_symbol[rix % 8][width] * streams;
859 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
861 if (frmlen < minlen) {
862 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
863 ndelim = max(mindelim, ndelim);
869 static struct ath_buf *
870 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
871 struct ath_atx_tid *tid, struct sk_buff_head **q)
873 struct ieee80211_tx_info *tx_info;
874 struct ath_frame_info *fi;
881 if (skb_queue_empty(*q))
888 fi = get_frame_info(skb);
891 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
893 bf->bf_state.stale = false;
896 __skb_unlink(skb, *q);
897 ath_txq_skb_done(sc, txq, skb);
898 ieee80211_free_txskb(sc->hw, skb);
905 tx_info = IEEE80211_SKB_CB(skb);
906 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
907 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
908 bf->bf_state.bf_type = 0;
912 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
913 seqno = bf->bf_state.seqno;
915 /* do not step over block-ack window */
916 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
919 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
920 struct ath_tx_status ts = {};
921 struct list_head bf_head;
923 INIT_LIST_HEAD(&bf_head);
924 list_add(&bf->list, &bf_head);
925 __skb_unlink(skb, *q);
926 ath_tx_update_baw(sc, tid, seqno);
927 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
938 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
939 struct ath_atx_tid *tid, struct list_head *bf_q,
940 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
943 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
944 struct ath_buf *bf = bf_first, *bf_prev = NULL;
945 int nframes = 0, ndelim;
946 u16 aggr_limit = 0, al = 0, bpad = 0,
947 al_delta, h_baw = tid->baw_size / 2;
948 struct ieee80211_tx_info *tx_info;
949 struct ath_frame_info *fi;
954 aggr_limit = ath_lookup_rate(sc, bf, tid);
958 fi = get_frame_info(skb);
960 /* do not exceed aggregation limit */
961 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
963 if (aggr_limit < al + bpad + al_delta ||
964 ath_lookup_legacy(bf) || nframes >= h_baw)
967 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
968 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
969 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
973 /* add padding for previous frame to aggregation length */
974 al += bpad + al_delta;
977 * Get the delimiters needed to meet the MPDU
978 * density for this node.
980 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
982 bpad = PADBYTES(al_delta) + (ndelim << 2);
987 /* link buffers of this frame to the aggregate */
988 if (!fi->baw_tracked)
989 ath_tx_addto_baw(sc, tid, bf);
990 bf->bf_state.ndelim = ndelim;
992 __skb_unlink(skb, tid_q);
993 list_add_tail(&bf->list, bf_q);
995 bf_prev->bf_next = bf;
999 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1004 } while (ath_tid_has_buffered(tid));
1007 bf->bf_lastbf = bf_prev;
1009 if (bf == bf_prev) {
1010 al = get_frame_info(bf->bf_mpdu)->framelen;
1011 bf->bf_state.bf_type = BUF_AMPDU;
1013 TX_STAT_INC(txq->axq_qnum, a_aggr);
1024 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1025 * width - 0 for 20 MHz, 1 for 40 MHz
1026 * half_gi - to use 4us v/s 3.6 us for symbol time
1028 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1029 int width, int half_gi, bool shortPreamble)
1031 u32 nbits, nsymbits, duration, nsymbols;
1034 /* find number of symbols: PLCP + data */
1035 streams = HT_RC_2_STREAMS(rix);
1036 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1037 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1038 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1041 duration = SYMBOL_TIME(nsymbols);
1043 duration = SYMBOL_TIME_HALFGI(nsymbols);
1045 /* addup duration for legacy/ht training and signal fields */
1046 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1051 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1053 int streams = HT_RC_2_STREAMS(mcs);
1057 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1058 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1059 bits -= OFDM_PLCP_BITS;
1061 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1068 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1070 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1073 /* 4ms is the default (and maximum) duration */
1074 if (!txop || txop > 4096)
1077 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1078 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1079 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1080 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1081 for (mcs = 0; mcs < 32; mcs++) {
1082 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1083 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1084 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1085 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1089 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1090 struct ath_tx_info *info, int len, bool rts)
1092 struct ath_hw *ah = sc->sc_ah;
1093 struct sk_buff *skb;
1094 struct ieee80211_tx_info *tx_info;
1095 struct ieee80211_tx_rate *rates;
1096 const struct ieee80211_rate *rate;
1097 struct ieee80211_hdr *hdr;
1098 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1099 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1104 tx_info = IEEE80211_SKB_CB(skb);
1106 hdr = (struct ieee80211_hdr *)skb->data;
1108 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1109 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1110 info->rtscts_rate = fi->rtscts_rate;
1112 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1113 bool is_40, is_sgi, is_sp;
1116 if (!rates[i].count || (rates[i].idx < 0))
1120 info->rates[i].Tries = rates[i].count;
1123 * Handle RTS threshold for unaggregated HT frames.
1125 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1126 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1127 unlikely(rts_thresh != (u32) -1)) {
1128 if (!rts_thresh || (len > rts_thresh))
1132 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1133 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1134 info->flags |= ATH9K_TXDESC_RTSENA;
1135 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1136 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1137 info->flags |= ATH9K_TXDESC_CTSENA;
1140 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1141 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1142 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1143 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1145 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1146 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1147 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1149 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1151 info->rates[i].Rate = rix | 0x80;
1152 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1153 ah->txchainmask, info->rates[i].Rate);
1154 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1155 is_40, is_sgi, is_sp);
1156 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1157 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1162 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1163 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1164 !(rate->flags & IEEE80211_RATE_ERP_G))
1165 phy = WLAN_RC_PHY_CCK;
1167 phy = WLAN_RC_PHY_OFDM;
1169 info->rates[i].Rate = rate->hw_value;
1170 if (rate->hw_value_short) {
1171 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1172 info->rates[i].Rate |= rate->hw_value_short;
1177 if (bf->bf_state.bfs_paprd)
1178 info->rates[i].ChSel = ah->txchainmask;
1180 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1181 ah->txchainmask, info->rates[i].Rate);
1183 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1184 phy, rate->bitrate * 100, len, rix, is_sp);
1187 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1188 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1189 info->flags &= ~ATH9K_TXDESC_RTSENA;
1191 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1192 if (info->flags & ATH9K_TXDESC_RTSENA)
1193 info->flags &= ~ATH9K_TXDESC_CTSENA;
1196 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1198 struct ieee80211_hdr *hdr;
1199 enum ath9k_pkt_type htype;
1202 hdr = (struct ieee80211_hdr *)skb->data;
1203 fc = hdr->frame_control;
1205 if (ieee80211_is_beacon(fc))
1206 htype = ATH9K_PKT_TYPE_BEACON;
1207 else if (ieee80211_is_probe_resp(fc))
1208 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1209 else if (ieee80211_is_atim(fc))
1210 htype = ATH9K_PKT_TYPE_ATIM;
1211 else if (ieee80211_is_pspoll(fc))
1212 htype = ATH9K_PKT_TYPE_PSPOLL;
1214 htype = ATH9K_PKT_TYPE_NORMAL;
1219 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1220 struct ath_txq *txq, int len)
1222 struct ath_hw *ah = sc->sc_ah;
1223 struct ath_buf *bf_first = NULL;
1224 struct ath_tx_info info;
1225 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1228 memset(&info, 0, sizeof(info));
1229 info.is_first = true;
1230 info.is_last = true;
1231 info.txpower = MAX_RATE_POWER;
1232 info.qcu = txq->axq_qnum;
1235 struct sk_buff *skb = bf->bf_mpdu;
1236 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1237 struct ath_frame_info *fi = get_frame_info(skb);
1238 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1240 info.type = get_hw_packet_type(skb);
1242 info.link = bf->bf_next->bf_daddr;
1244 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1249 if (!sc->tx99_state)
1250 info.flags = ATH9K_TXDESC_INTREQ;
1251 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1252 txq == sc->tx.uapsdq)
1253 info.flags |= ATH9K_TXDESC_CLRDMASK;
1255 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1256 info.flags |= ATH9K_TXDESC_NOACK;
1257 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1258 info.flags |= ATH9K_TXDESC_LDPC;
1260 if (bf->bf_state.bfs_paprd)
1261 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1262 ATH9K_TXDESC_PAPRD_S;
1265 * mac80211 doesn't handle RTS threshold for HT because
1266 * the decision has to be taken based on AMPDU length
1267 * and aggregation is done entirely inside ath9k.
1268 * Set the RTS/CTS flag for the first subframe based
1271 if (aggr && (bf == bf_first) &&
1272 unlikely(rts_thresh != (u32) -1)) {
1274 * "len" is the size of the entire AMPDU.
1276 if (!rts_thresh || (len > rts_thresh))
1283 ath_buf_set_rate(sc, bf, &info, len, rts);
1286 info.buf_addr[0] = bf->bf_buf_addr;
1287 info.buf_len[0] = skb->len;
1288 info.pkt_len = fi->framelen;
1289 info.keyix = fi->keyix;
1290 info.keytype = fi->keytype;
1294 info.aggr = AGGR_BUF_FIRST;
1295 else if (bf == bf_first->bf_lastbf)
1296 info.aggr = AGGR_BUF_LAST;
1298 info.aggr = AGGR_BUF_MIDDLE;
1300 info.ndelim = bf->bf_state.ndelim;
1301 info.aggr_len = len;
1304 if (bf == bf_first->bf_lastbf)
1307 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1313 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1314 struct ath_atx_tid *tid, struct list_head *bf_q,
1315 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1317 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1318 struct sk_buff *skb;
1322 struct ieee80211_tx_info *tx_info;
1326 __skb_unlink(skb, tid_q);
1327 list_add_tail(&bf->list, bf_q);
1329 bf_prev->bf_next = bf;
1335 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1339 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1340 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1343 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1347 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1348 struct ath_atx_tid *tid, bool *stop)
1351 struct ieee80211_tx_info *tx_info;
1352 struct sk_buff_head *tid_q;
1353 struct list_head bf_q;
1355 bool aggr, last = true;
1357 if (!ath_tid_has_buffered(tid))
1360 INIT_LIST_HEAD(&bf_q);
1362 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1366 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1367 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1368 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1369 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1374 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1376 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1379 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1381 if (list_empty(&bf_q))
1384 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1385 tid->ac->clear_ps_filter = false;
1386 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1389 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1390 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1394 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1397 struct ath_atx_tid *txtid;
1398 struct ath_txq *txq;
1399 struct ath_node *an;
1402 an = (struct ath_node *)sta->drv_priv;
1403 txtid = ATH_AN_2_TID(an, tid);
1404 txq = txtid->ac->txq;
1406 ath_txq_lock(sc, txq);
1408 /* update ampdu factor/density, they may have changed. This may happen
1409 * in HT IBSS when a beacon with HT-info is received after the station
1410 * has already been added.
1412 if (sta->ht_cap.ht_supported) {
1413 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1414 sta->ht_cap.ampdu_factor);
1415 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1416 an->mpdudensity = density;
1419 /* force sequence number allocation for pending frames */
1420 ath_tx_tid_change_state(sc, txtid);
1422 txtid->active = true;
1423 txtid->paused = true;
1424 *ssn = txtid->seq_start = txtid->seq_next;
1425 txtid->bar_index = -1;
1427 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1428 txtid->baw_head = txtid->baw_tail = 0;
1430 ath_txq_unlock_complete(sc, txq);
1435 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1437 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1438 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1439 struct ath_txq *txq = txtid->ac->txq;
1441 ath_txq_lock(sc, txq);
1442 txtid->active = false;
1443 txtid->paused = false;
1444 ath_tx_flush_tid(sc, txtid);
1445 ath_tx_tid_change_state(sc, txtid);
1446 ath_txq_unlock_complete(sc, txq);
1449 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1450 struct ath_node *an)
1452 struct ath_atx_tid *tid;
1453 struct ath_atx_ac *ac;
1454 struct ath_txq *txq;
1458 for (tidno = 0, tid = &an->tid[tidno];
1459 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1467 ath_txq_lock(sc, txq);
1469 buffered = ath_tid_has_buffered(tid);
1472 list_del(&tid->list);
1476 list_del(&ac->list);
1479 ath_txq_unlock(sc, txq);
1481 ieee80211_sta_set_buffered(sta, tidno, buffered);
1485 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1487 struct ath_atx_tid *tid;
1488 struct ath_atx_ac *ac;
1489 struct ath_txq *txq;
1492 for (tidno = 0, tid = &an->tid[tidno];
1493 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1498 ath_txq_lock(sc, txq);
1499 ac->clear_ps_filter = true;
1501 if (!tid->paused && ath_tid_has_buffered(tid)) {
1502 ath_tx_queue_tid(txq, tid);
1503 ath_txq_schedule(sc, txq);
1506 ath_txq_unlock_complete(sc, txq);
1510 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1513 struct ath_atx_tid *tid;
1514 struct ath_node *an;
1515 struct ath_txq *txq;
1517 an = (struct ath_node *)sta->drv_priv;
1518 tid = ATH_AN_2_TID(an, tidno);
1521 ath_txq_lock(sc, txq);
1523 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1524 tid->paused = false;
1526 if (ath_tid_has_buffered(tid)) {
1527 ath_tx_queue_tid(txq, tid);
1528 ath_txq_schedule(sc, txq);
1531 ath_txq_unlock_complete(sc, txq);
1534 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1535 struct ieee80211_sta *sta,
1536 u16 tids, int nframes,
1537 enum ieee80211_frame_release_type reason,
1540 struct ath_softc *sc = hw->priv;
1541 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1542 struct ath_txq *txq = sc->tx.uapsdq;
1543 struct ieee80211_tx_info *info;
1544 struct list_head bf_q;
1545 struct ath_buf *bf_tail = NULL, *bf;
1546 struct sk_buff_head *tid_q;
1550 INIT_LIST_HEAD(&bf_q);
1551 for (i = 0; tids && nframes; i++, tids >>= 1) {
1552 struct ath_atx_tid *tid;
1557 tid = ATH_AN_2_TID(an, i);
1561 ath_txq_lock(sc, tid->ac->txq);
1562 while (nframes > 0) {
1563 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1567 __skb_unlink(bf->bf_mpdu, tid_q);
1568 list_add_tail(&bf->list, &bf_q);
1569 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1570 if (bf_isampdu(bf)) {
1571 ath_tx_addto_baw(sc, tid, bf);
1572 bf->bf_state.bf_type &= ~BUF_AGGR;
1575 bf_tail->bf_next = bf;
1580 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1582 if (an->sta && !ath_tid_has_buffered(tid))
1583 ieee80211_sta_set_buffered(an->sta, i, false);
1585 ath_txq_unlock_complete(sc, tid->ac->txq);
1588 if (list_empty(&bf_q))
1591 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1592 info->flags |= IEEE80211_TX_STATUS_EOSP;
1594 bf = list_first_entry(&bf_q, struct ath_buf, list);
1595 ath_txq_lock(sc, txq);
1596 ath_tx_fill_desc(sc, bf, txq, 0);
1597 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1598 ath_txq_unlock(sc, txq);
1601 /********************/
1602 /* Queue Management */
1603 /********************/
1605 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1607 struct ath_hw *ah = sc->sc_ah;
1608 struct ath9k_tx_queue_info qi;
1609 static const int subtype_txq_to_hwq[] = {
1610 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1611 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1612 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1613 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1617 memset(&qi, 0, sizeof(qi));
1618 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1619 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1620 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1621 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1622 qi.tqi_physCompBuf = 0;
1625 * Enable interrupts only for EOL and DESC conditions.
1626 * We mark tx descriptors to receive a DESC interrupt
1627 * when a tx queue gets deep; otherwise waiting for the
1628 * EOL to reap descriptors. Note that this is done to
1629 * reduce interrupt load and this only defers reaping
1630 * descriptors, never transmitting frames. Aside from
1631 * reducing interrupts this also permits more concurrency.
1632 * The only potential downside is if the tx queue backs
1633 * up in which case the top half of the kernel may backup
1634 * due to a lack of tx descriptors.
1636 * The UAPSD queue is an exception, since we take a desc-
1637 * based intr on the EOSP frames.
1639 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1640 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1642 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1643 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1645 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1646 TXQ_FLAG_TXDESCINT_ENABLE;
1648 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1649 if (axq_qnum == -1) {
1651 * NB: don't print a message, this happens
1652 * normally on parts with too few tx queues
1656 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1657 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1659 txq->axq_qnum = axq_qnum;
1660 txq->mac80211_qnum = -1;
1661 txq->axq_link = NULL;
1662 __skb_queue_head_init(&txq->complete_q);
1663 INIT_LIST_HEAD(&txq->axq_q);
1664 INIT_LIST_HEAD(&txq->axq_acq);
1665 spin_lock_init(&txq->axq_lock);
1667 txq->axq_ampdu_depth = 0;
1668 txq->axq_tx_inprogress = false;
1669 sc->tx.txqsetup |= 1<<axq_qnum;
1671 txq->txq_headidx = txq->txq_tailidx = 0;
1672 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1673 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1675 return &sc->tx.txq[axq_qnum];
1678 int ath_txq_update(struct ath_softc *sc, int qnum,
1679 struct ath9k_tx_queue_info *qinfo)
1681 struct ath_hw *ah = sc->sc_ah;
1683 struct ath9k_tx_queue_info qi;
1685 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1687 ath9k_hw_get_txq_props(ah, qnum, &qi);
1688 qi.tqi_aifs = qinfo->tqi_aifs;
1689 qi.tqi_cwmin = qinfo->tqi_cwmin;
1690 qi.tqi_cwmax = qinfo->tqi_cwmax;
1691 qi.tqi_burstTime = qinfo->tqi_burstTime;
1692 qi.tqi_readyTime = qinfo->tqi_readyTime;
1694 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1695 ath_err(ath9k_hw_common(sc->sc_ah),
1696 "Unable to update hardware queue %u!\n", qnum);
1699 ath9k_hw_resettxqueue(ah, qnum);
1705 int ath_cabq_update(struct ath_softc *sc)
1707 struct ath9k_tx_queue_info qi;
1708 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1709 int qnum = sc->beacon.cabq->axq_qnum;
1711 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1713 qi.tqi_readyTime = (cur_conf->beacon_interval *
1714 ATH_CABQ_READY_TIME) / 100;
1715 ath_txq_update(sc, qnum, &qi);
1720 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1721 struct list_head *list)
1723 struct ath_buf *bf, *lastbf;
1724 struct list_head bf_head;
1725 struct ath_tx_status ts;
1727 memset(&ts, 0, sizeof(ts));
1728 ts.ts_status = ATH9K_TX_FLUSH;
1729 INIT_LIST_HEAD(&bf_head);
1731 while (!list_empty(list)) {
1732 bf = list_first_entry(list, struct ath_buf, list);
1734 if (bf->bf_state.stale) {
1735 list_del(&bf->list);
1737 ath_tx_return_buffer(sc, bf);
1741 lastbf = bf->bf_lastbf;
1742 list_cut_position(&bf_head, list, &lastbf->list);
1743 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1748 * Drain a given TX queue (could be Beacon or Data)
1750 * This assumes output has been stopped and
1751 * we do not need to block ath_tx_tasklet.
1753 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1755 ath_txq_lock(sc, txq);
1757 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1758 int idx = txq->txq_tailidx;
1760 while (!list_empty(&txq->txq_fifo[idx])) {
1761 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1763 INCR(idx, ATH_TXFIFO_DEPTH);
1765 txq->txq_tailidx = idx;
1768 txq->axq_link = NULL;
1769 txq->axq_tx_inprogress = false;
1770 ath_drain_txq_list(sc, txq, &txq->axq_q);
1772 ath_txq_unlock_complete(sc, txq);
1775 bool ath_drain_all_txq(struct ath_softc *sc)
1777 struct ath_hw *ah = sc->sc_ah;
1778 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1779 struct ath_txq *txq;
1783 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1786 ath9k_hw_abort_tx_dma(ah);
1788 /* Check if any queue remains active */
1789 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1790 if (!ATH_TXQ_SETUP(sc, i))
1793 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1798 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1800 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1801 if (!ATH_TXQ_SETUP(sc, i))
1805 * The caller will resume queues with ieee80211_wake_queues.
1806 * Mark the queue as not stopped to prevent ath_tx_complete
1807 * from waking the queue too early.
1809 txq = &sc->tx.txq[i];
1810 txq->stopped = false;
1811 ath_draintxq(sc, txq);
1817 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1819 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1820 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1823 /* For each axq_acq entry, for each tid, try to schedule packets
1824 * for transmit until ampdu_depth has reached min Q depth.
1826 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1828 struct ath_atx_ac *ac, *last_ac;
1829 struct ath_atx_tid *tid, *last_tid;
1832 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1833 list_empty(&txq->axq_acq))
1838 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1839 while (!list_empty(&txq->axq_acq)) {
1842 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1843 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1844 list_del(&ac->list);
1847 while (!list_empty(&ac->tid_q)) {
1849 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1851 list_del(&tid->list);
1857 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1861 * add tid to round-robin queue if more frames
1862 * are pending for the tid
1864 if (ath_tid_has_buffered(tid))
1865 ath_tx_queue_tid(txq, tid);
1867 if (stop || tid == last_tid)
1871 if (!list_empty(&ac->tid_q) && !ac->sched) {
1873 list_add_tail(&ac->list, &txq->axq_acq);
1879 if (ac == last_ac) {
1884 last_ac = list_entry(txq->axq_acq.prev,
1885 struct ath_atx_ac, list);
1897 * Insert a chain of ath_buf (descriptors) on a txq and
1898 * assume the descriptors are already chained together by caller.
1900 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1901 struct list_head *head, bool internal)
1903 struct ath_hw *ah = sc->sc_ah;
1904 struct ath_common *common = ath9k_hw_common(ah);
1905 struct ath_buf *bf, *bf_last;
1906 bool puttxbuf = false;
1910 * Insert the frame on the outbound list and
1911 * pass it on to the hardware.
1914 if (list_empty(head))
1917 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1918 bf = list_first_entry(head, struct ath_buf, list);
1919 bf_last = list_entry(head->prev, struct ath_buf, list);
1921 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1922 txq->axq_qnum, txq->axq_depth);
1924 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1925 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1926 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1929 list_splice_tail_init(head, &txq->axq_q);
1931 if (txq->axq_link) {
1932 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1933 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1934 txq->axq_qnum, txq->axq_link,
1935 ito64(bf->bf_daddr), bf->bf_desc);
1939 txq->axq_link = bf_last->bf_desc;
1943 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1944 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1945 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1946 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1949 if (!edma || sc->tx99_state) {
1950 TX_STAT_INC(txq->axq_qnum, txstart);
1951 ath9k_hw_txstart(ah, txq->axq_qnum);
1957 if (bf_is_ampdu_not_probing(bf))
1958 txq->axq_ampdu_depth++;
1960 bf_last = bf->bf_lastbf;
1961 bf = bf_last->bf_next;
1962 bf_last->bf_next = NULL;
1967 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1968 struct ath_atx_tid *tid, struct sk_buff *skb)
1970 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1971 struct ath_frame_info *fi = get_frame_info(skb);
1972 struct list_head bf_head;
1973 struct ath_buf *bf = fi->bf;
1975 INIT_LIST_HEAD(&bf_head);
1976 list_add_tail(&bf->list, &bf_head);
1977 bf->bf_state.bf_type = 0;
1978 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
1979 bf->bf_state.bf_type = BUF_AMPDU;
1980 ath_tx_addto_baw(sc, tid, bf);
1985 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1986 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1987 TX_STAT_INC(txq->axq_qnum, queued);
1990 static void setup_frame_info(struct ieee80211_hw *hw,
1991 struct ieee80211_sta *sta,
1992 struct sk_buff *skb,
1995 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1996 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1997 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1998 const struct ieee80211_rate *rate;
1999 struct ath_frame_info *fi = get_frame_info(skb);
2000 struct ath_node *an = NULL;
2001 enum ath9k_key_type keytype;
2002 bool short_preamble = false;
2005 * We check if Short Preamble is needed for the CTS rate by
2006 * checking the BSS's global flag.
2007 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2009 if (tx_info->control.vif &&
2010 tx_info->control.vif->bss_conf.use_short_preamble)
2011 short_preamble = true;
2013 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2014 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2017 an = (struct ath_node *) sta->drv_priv;
2019 memset(fi, 0, sizeof(*fi));
2021 fi->keyix = hw_key->hw_key_idx;
2022 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2023 fi->keyix = an->ps_key;
2025 fi->keyix = ATH9K_TXKEYIX_INVALID;
2026 fi->keytype = keytype;
2027 fi->framelen = framelen;
2031 fi->rtscts_rate = rate->hw_value;
2033 fi->rtscts_rate |= rate->hw_value_short;
2036 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2038 struct ath_hw *ah = sc->sc_ah;
2039 struct ath9k_channel *curchan = ah->curchan;
2041 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2042 (chainmask == 0x7) && (rate < 0x90))
2044 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2052 * Assign a descriptor (and sequence number if necessary,
2053 * and map buffer for DMA. Frees skb on error
2055 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2056 struct ath_txq *txq,
2057 struct ath_atx_tid *tid,
2058 struct sk_buff *skb)
2060 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2061 struct ath_frame_info *fi = get_frame_info(skb);
2062 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2067 bf = ath_tx_get_buffer(sc);
2069 ath_dbg(common, XMIT, "TX buffers are full\n");
2073 ATH_TXBUF_RESET(bf);
2076 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2077 seqno = tid->seq_next;
2078 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2081 hdr->seq_ctrl |= cpu_to_le16(fragno);
2083 if (!ieee80211_has_morefrags(hdr->frame_control))
2084 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2086 bf->bf_state.seqno = seqno;
2091 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2092 skb->len, DMA_TO_DEVICE);
2093 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2095 bf->bf_buf_addr = 0;
2096 ath_err(ath9k_hw_common(sc->sc_ah),
2097 "dma_mapping_error() on TX\n");
2098 ath_tx_return_buffer(sc, bf);
2107 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2108 struct ath_tx_control *txctl)
2110 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2111 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2112 struct ieee80211_sta *sta = txctl->sta;
2113 struct ieee80211_vif *vif = info->control.vif;
2114 struct ath_vif *avp;
2115 struct ath_softc *sc = hw->priv;
2116 int frmlen = skb->len + FCS_LEN;
2117 int padpos, padsize;
2119 /* NOTE: sta can be NULL according to net/mac80211.h */
2121 txctl->an = (struct ath_node *)sta->drv_priv;
2122 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2123 avp = (void *)vif->drv_priv;
2124 txctl->an = &avp->mcast_node;
2127 if (info->control.hw_key)
2128 frmlen += info->control.hw_key->icv_len;
2131 * As a temporary workaround, assign seq# here; this will likely need
2132 * to be cleaned up to work better with Beacon transmission and virtual
2135 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2136 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2137 sc->tx.seq_no += 0x10;
2138 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2139 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2142 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2143 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2144 !ieee80211_is_data(hdr->frame_control))
2145 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2147 /* Add the padding after the header if this is not already done */
2148 padpos = ieee80211_hdrlen(hdr->frame_control);
2149 padsize = padpos & 3;
2150 if (padsize && skb->len > padpos) {
2151 if (skb_headroom(skb) < padsize)
2154 skb_push(skb, padsize);
2155 memmove(skb->data, skb->data + padsize, padpos);
2158 setup_frame_info(hw, sta, skb, frmlen);
2163 /* Upon failure caller should free skb */
2164 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2165 struct ath_tx_control *txctl)
2167 struct ieee80211_hdr *hdr;
2168 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2169 struct ieee80211_sta *sta = txctl->sta;
2170 struct ieee80211_vif *vif = info->control.vif;
2171 struct ath_softc *sc = hw->priv;
2172 struct ath_txq *txq = txctl->txq;
2173 struct ath_atx_tid *tid = NULL;
2178 ret = ath_tx_prepare(hw, skb, txctl);
2182 hdr = (struct ieee80211_hdr *) skb->data;
2184 * At this point, the vif, hw_key and sta pointers in the tx control
2185 * info are no longer valid (overwritten by the ath_frame_info data.
2188 q = skb_get_queue_mapping(skb);
2190 ath_txq_lock(sc, txq);
2191 if (txq == sc->tx.txq_map[q] &&
2192 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2194 ieee80211_stop_queue(sc->hw, q);
2195 txq->stopped = true;
2198 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2199 ath_txq_unlock(sc, txq);
2200 txq = sc->tx.uapsdq;
2201 ath_txq_lock(sc, txq);
2202 } else if (txctl->an &&
2203 ieee80211_is_data_present(hdr->frame_control)) {
2204 tid = ath_get_skb_tid(sc, txctl->an, skb);
2206 WARN_ON(tid->ac->txq != txctl->txq);
2208 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2209 tid->ac->clear_ps_filter = true;
2212 * Add this frame to software queue for scheduling later
2215 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2216 __skb_queue_tail(&tid->buf_q, skb);
2217 if (!txctl->an->sleeping)
2218 ath_tx_queue_tid(txq, tid);
2220 ath_txq_schedule(sc, txq);
2224 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2226 ath_txq_skb_done(sc, txq, skb);
2228 dev_kfree_skb_any(skb);
2230 ieee80211_free_txskb(sc->hw, skb);
2234 bf->bf_state.bfs_paprd = txctl->paprd;
2237 bf->bf_state.bfs_paprd_timestamp = jiffies;
2239 ath_set_rates(vif, sta, bf);
2240 ath_tx_send_normal(sc, txq, tid, skb);
2243 ath_txq_unlock(sc, txq);
2248 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2249 struct sk_buff *skb)
2251 struct ath_softc *sc = hw->priv;
2252 struct ath_tx_control txctl = {
2253 .txq = sc->beacon.cabq
2255 struct ath_tx_info info = {};
2256 struct ieee80211_hdr *hdr;
2257 struct ath_buf *bf_tail = NULL;
2264 sc->cur_beacon_conf.beacon_interval * 1000 *
2265 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2268 struct ath_frame_info *fi = get_frame_info(skb);
2270 if (ath_tx_prepare(hw, skb, &txctl))
2273 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2278 ath_set_rates(vif, NULL, bf);
2279 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2280 duration += info.rates[0].PktDuration;
2282 bf_tail->bf_next = bf;
2284 list_add_tail(&bf->list, &bf_q);
2288 if (duration > max_duration)
2291 skb = ieee80211_get_buffered_bc(hw, vif);
2295 ieee80211_free_txskb(hw, skb);
2297 if (list_empty(&bf_q))
2300 bf = list_first_entry(&bf_q, struct ath_buf, list);
2301 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2303 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2304 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2305 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2306 sizeof(*hdr), DMA_TO_DEVICE);
2309 ath_txq_lock(sc, txctl.txq);
2310 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2311 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2312 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2313 ath_txq_unlock(sc, txctl.txq);
2320 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2321 int tx_flags, struct ath_txq *txq)
2323 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2324 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2325 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2326 int padpos, padsize;
2327 unsigned long flags;
2329 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2331 if (sc->sc_ah->caldata)
2332 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2334 if (!(tx_flags & ATH_TX_ERROR))
2335 /* Frame was ACKed */
2336 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2338 padpos = ieee80211_hdrlen(hdr->frame_control);
2339 padsize = padpos & 3;
2340 if (padsize && skb->len>padpos+padsize) {
2342 * Remove MAC header padding before giving the frame back to
2345 memmove(skb->data + padsize, skb->data, padpos);
2346 skb_pull(skb, padsize);
2349 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2350 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2351 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2353 "Going back to sleep after having received TX status (0x%lx)\n",
2354 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2356 PS_WAIT_FOR_PSPOLL_DATA |
2357 PS_WAIT_FOR_TX_ACK));
2359 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2361 __skb_queue_tail(&txq->complete_q, skb);
2362 ath_txq_skb_done(sc, txq, skb);
2365 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2366 struct ath_txq *txq, struct list_head *bf_q,
2367 struct ath_tx_status *ts, int txok)
2369 struct sk_buff *skb = bf->bf_mpdu;
2370 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2371 unsigned long flags;
2375 tx_flags |= ATH_TX_ERROR;
2377 if (ts->ts_status & ATH9K_TXERR_FILT)
2378 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2380 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2381 bf->bf_buf_addr = 0;
2383 goto skip_tx_complete;
2385 if (bf->bf_state.bfs_paprd) {
2386 if (time_after(jiffies,
2387 bf->bf_state.bfs_paprd_timestamp +
2388 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2389 dev_kfree_skb_any(skb);
2391 complete(&sc->paprd_complete);
2393 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2394 ath_tx_complete(sc, skb, tx_flags, txq);
2397 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2398 * accidentally reference it later.
2403 * Return the list of ath_buf of this mpdu to free queue
2405 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2406 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2407 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2410 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2411 struct ath_tx_status *ts, int nframes, int nbad,
2414 struct sk_buff *skb = bf->bf_mpdu;
2415 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2416 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2417 struct ieee80211_hw *hw = sc->hw;
2418 struct ath_hw *ah = sc->sc_ah;
2422 tx_info->status.ack_signal = ts->ts_rssi;
2424 tx_rateindex = ts->ts_rateindex;
2425 WARN_ON(tx_rateindex >= hw->max_rates);
2427 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2428 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2430 BUG_ON(nbad > nframes);
2432 tx_info->status.ampdu_len = nframes;
2433 tx_info->status.ampdu_ack_len = nframes - nbad;
2435 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2436 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2438 * If an underrun error is seen assume it as an excessive
2439 * retry only if max frame trigger level has been reached
2440 * (2 KB for single stream, and 4 KB for dual stream).
2441 * Adjust the long retry as if the frame was tried
2442 * hw->max_rate_tries times to affect how rate control updates
2443 * PER for the failed rate.
2444 * In case of congestion on the bus penalizing this type of
2445 * underruns should help hardware actually transmit new frames
2446 * successfully by eventually preferring slower rates.
2447 * This itself should also alleviate congestion on the bus.
2449 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2450 ATH9K_TX_DELIM_UNDERRUN)) &&
2451 ieee80211_is_data(hdr->frame_control) &&
2452 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2453 tx_info->status.rates[tx_rateindex].count =
2457 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2458 tx_info->status.rates[i].count = 0;
2459 tx_info->status.rates[i].idx = -1;
2462 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2465 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2467 struct ath_hw *ah = sc->sc_ah;
2468 struct ath_common *common = ath9k_hw_common(ah);
2469 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2470 struct list_head bf_head;
2471 struct ath_desc *ds;
2472 struct ath_tx_status ts;
2475 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2476 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2479 ath_txq_lock(sc, txq);
2481 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2484 if (list_empty(&txq->axq_q)) {
2485 txq->axq_link = NULL;
2486 ath_txq_schedule(sc, txq);
2489 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2492 * There is a race condition that a BH gets scheduled
2493 * after sw writes TxE and before hw re-load the last
2494 * descriptor to get the newly chained one.
2495 * Software must keep the last DONE descriptor as a
2496 * holding descriptor - software does so by marking
2497 * it with the STALE flag.
2500 if (bf->bf_state.stale) {
2502 if (list_is_last(&bf_held->list, &txq->axq_q))
2505 bf = list_entry(bf_held->list.next, struct ath_buf,
2509 lastbf = bf->bf_lastbf;
2510 ds = lastbf->bf_desc;
2512 memset(&ts, 0, sizeof(ts));
2513 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2514 if (status == -EINPROGRESS)
2517 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2520 * Remove ath_buf's of the same transmit unit from txq,
2521 * however leave the last descriptor back as the holding
2522 * descriptor for hw.
2524 lastbf->bf_state.stale = true;
2525 INIT_LIST_HEAD(&bf_head);
2526 if (!list_is_singular(&lastbf->list))
2527 list_cut_position(&bf_head,
2528 &txq->axq_q, lastbf->list.prev);
2531 list_del(&bf_held->list);
2532 ath_tx_return_buffer(sc, bf_held);
2535 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2537 ath_txq_unlock_complete(sc, txq);
2540 void ath_tx_tasklet(struct ath_softc *sc)
2542 struct ath_hw *ah = sc->sc_ah;
2543 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2546 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2547 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2548 ath_tx_processq(sc, &sc->tx.txq[i]);
2552 void ath_tx_edma_tasklet(struct ath_softc *sc)
2554 struct ath_tx_status ts;
2555 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2556 struct ath_hw *ah = sc->sc_ah;
2557 struct ath_txq *txq;
2558 struct ath_buf *bf, *lastbf;
2559 struct list_head bf_head;
2560 struct list_head *fifo_list;
2564 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2567 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2568 if (status == -EINPROGRESS)
2570 if (status == -EIO) {
2571 ath_dbg(common, XMIT, "Error processing tx status\n");
2575 /* Process beacon completions separately */
2576 if (ts.qid == sc->beacon.beaconq) {
2577 sc->beacon.tx_processed = true;
2578 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2580 ath9k_csa_is_finished(sc);
2584 txq = &sc->tx.txq[ts.qid];
2586 ath_txq_lock(sc, txq);
2588 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2590 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2591 if (list_empty(fifo_list)) {
2592 ath_txq_unlock(sc, txq);
2596 bf = list_first_entry(fifo_list, struct ath_buf, list);
2597 if (bf->bf_state.stale) {
2598 list_del(&bf->list);
2599 ath_tx_return_buffer(sc, bf);
2600 bf = list_first_entry(fifo_list, struct ath_buf, list);
2603 lastbf = bf->bf_lastbf;
2605 INIT_LIST_HEAD(&bf_head);
2606 if (list_is_last(&lastbf->list, fifo_list)) {
2607 list_splice_tail_init(fifo_list, &bf_head);
2608 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2610 if (!list_empty(&txq->axq_q)) {
2611 struct list_head bf_q;
2613 INIT_LIST_HEAD(&bf_q);
2614 txq->axq_link = NULL;
2615 list_splice_tail_init(&txq->axq_q, &bf_q);
2616 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2619 lastbf->bf_state.stale = true;
2621 list_cut_position(&bf_head, fifo_list,
2625 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2626 ath_txq_unlock_complete(sc, txq);
2634 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2636 struct ath_descdma *dd = &sc->txsdma;
2637 u8 txs_len = sc->sc_ah->caps.txs_len;
2639 dd->dd_desc_len = size * txs_len;
2640 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2641 &dd->dd_desc_paddr, GFP_KERNEL);
2648 static int ath_tx_edma_init(struct ath_softc *sc)
2652 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2654 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2655 sc->txsdma.dd_desc_paddr,
2656 ATH_TXSTATUS_RING_SIZE);
2661 int ath_tx_init(struct ath_softc *sc, int nbufs)
2663 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2666 spin_lock_init(&sc->tx.txbuflock);
2668 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2672 "Failed to allocate tx descriptors: %d\n", error);
2676 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2677 "beacon", ATH_BCBUF, 1, 1);
2680 "Failed to allocate beacon descriptors: %d\n", error);
2684 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2686 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2687 error = ath_tx_edma_init(sc);
2692 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2694 struct ath_atx_tid *tid;
2695 struct ath_atx_ac *ac;
2698 for (tidno = 0, tid = &an->tid[tidno];
2699 tidno < IEEE80211_NUM_TIDS;
2703 tid->seq_start = tid->seq_next = 0;
2704 tid->baw_size = WME_MAX_BA;
2705 tid->baw_head = tid->baw_tail = 0;
2707 tid->paused = false;
2708 tid->active = false;
2709 __skb_queue_head_init(&tid->buf_q);
2710 __skb_queue_head_init(&tid->retry_q);
2711 acno = TID_TO_WME_AC(tidno);
2712 tid->ac = &an->ac[acno];
2715 for (acno = 0, ac = &an->ac[acno];
2716 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2718 ac->clear_ps_filter = true;
2719 ac->txq = sc->tx.txq_map[acno];
2720 INIT_LIST_HEAD(&ac->tid_q);
2724 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2726 struct ath_atx_ac *ac;
2727 struct ath_atx_tid *tid;
2728 struct ath_txq *txq;
2731 for (tidno = 0, tid = &an->tid[tidno];
2732 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2737 ath_txq_lock(sc, txq);
2740 list_del(&tid->list);
2745 list_del(&ac->list);
2746 tid->ac->sched = false;
2749 ath_tid_drain(sc, txq, tid);
2750 tid->active = false;
2752 ath_txq_unlock(sc, txq);
2756 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2757 struct ath_tx_control *txctl)
2759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2760 struct ath_frame_info *fi = get_frame_info(skb);
2761 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2763 int padpos, padsize;
2765 padpos = ieee80211_hdrlen(hdr->frame_control);
2766 padsize = padpos & 3;
2768 if (padsize && skb->len > padpos) {
2769 if (skb_headroom(skb) < padsize) {
2770 ath_dbg(common, XMIT,
2771 "tx99 padding failed\n");
2775 skb_push(skb, padsize);
2776 memmove(skb->data, skb->data + padsize, padpos);
2779 fi->keyix = ATH9K_TXKEYIX_INVALID;
2780 fi->framelen = skb->len + FCS_LEN;
2781 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2783 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2785 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2789 ath_set_rates(sc->tx99_vif, NULL, bf);
2791 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2792 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2794 ath_tx_send_normal(sc, txctl->txq, NULL, skb);