2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 /* Common between single chip and non single-chip solutions */
21 void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
23 /* Single chip radio settings */
24 int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
25 void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
27 /* Routines below are for non single-chip solutions */
28 int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
29 void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
31 int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32 void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
34 bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
35 struct ath9k_channel *chan,
38 void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
39 struct ath9k_channel *chan);
41 #define AR_PHY_BASE 0x9800
42 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
44 #define AR_PHY_TEST 0x9800
45 #define PHY_AGC_CLR 0x10000000
46 #define RFSILENT_BB 0x00002000
48 #define AR_PHY_TURBO 0x9804
49 #define AR_PHY_FC_TURBO_MODE 0x00000001
50 #define AR_PHY_FC_TURBO_SHORT 0x00000002
51 #define AR_PHY_FC_DYN2040_EN 0x00000004
52 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
53 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
54 /* For 25 MHz channel spacing -- not used but supported by hw */
55 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
56 #define AR_PHY_FC_HT_EN 0x00000040
57 #define AR_PHY_FC_SHORT_GI_40 0x00000080
58 #define AR_PHY_FC_WALSH 0x00000100
59 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
60 #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
62 #define AR_PHY_TEST2 0x9808
64 #define AR_PHY_TIMING2 0x9810
65 #define AR_PHY_TIMING3 0x9814
66 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
67 #define AR_PHY_TIMING3_DSC_MAN_S 17
68 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
69 #define AR_PHY_TIMING3_DSC_EXP_S 13
71 #define AR_PHY_CHIP_ID 0x9818
72 #define AR_PHY_CHIP_ID_REV_0 0x80
73 #define AR_PHY_CHIP_ID_REV_1 0x81
74 #define AR_PHY_CHIP_ID_9160_REV_0 0xb0
76 #define AR_PHY_ACTIVE 0x981C
77 #define AR_PHY_ACTIVE_EN 0x00000001
78 #define AR_PHY_ACTIVE_DIS 0x00000000
80 #define AR_PHY_RF_CTL2 0x9824
81 #define AR_PHY_TX_END_DATA_START 0x000000FF
82 #define AR_PHY_TX_END_DATA_START_S 0
83 #define AR_PHY_TX_END_PA_ON 0x0000FF00
84 #define AR_PHY_TX_END_PA_ON_S 8
86 #define AR_PHY_RF_CTL3 0x9828
87 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
88 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
90 #define AR_PHY_ADC_CTL 0x982C
91 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
92 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
93 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
94 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
95 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
96 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
97 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
99 #define AR_PHY_ADC_SERIAL_CTL 0x9830
100 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
101 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
103 #define AR_PHY_RF_CTL4 0x9834
104 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
105 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
106 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
107 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
108 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
109 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
110 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
111 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
113 #define AR_PHY_TSTDAC_CONST 0x983c
115 #define AR_PHY_SETTLING 0x9844
116 #define AR_PHY_SETTLING_SWITCH 0x00003F80
117 #define AR_PHY_SETTLING_SWITCH_S 7
119 #define AR_PHY_RXGAIN 0x9848
120 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
121 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
122 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
123 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
124 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
125 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
126 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
127 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
129 #define AR_PHY_DESIRED_SZ 0x9850
130 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
131 #define AR_PHY_DESIRED_SZ_ADC_S 0
132 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
133 #define AR_PHY_DESIRED_SZ_PGA_S 8
134 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
135 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
137 #define AR_PHY_FIND_SIG 0x9858
138 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
139 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
140 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
141 #define AR_PHY_FIND_SIG_FIRPWR_S 18
143 #define AR_PHY_AGC_CTL1 0x985C
144 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
145 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
146 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
147 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
149 #define AR_PHY_AGC_CONTROL 0x9860
150 #define AR_PHY_AGC_CONTROL_CAL 0x00000001
151 #define AR_PHY_AGC_CONTROL_NF 0x00000002
152 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
153 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
154 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
156 #define AR_PHY_CCA 0x9864
157 #define AR_PHY_MINCCA_PWR 0x0FF80000
158 #define AR_PHY_MINCCA_PWR_S 19
159 #define AR_PHY_CCA_THRESH62 0x0007F000
160 #define AR_PHY_CCA_THRESH62_S 12
161 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
162 #define AR9280_PHY_MINCCA_PWR_S 20
163 #define AR9280_PHY_CCA_THRESH62 0x000FF000
164 #define AR9280_PHY_CCA_THRESH62_S 12
166 #define AR_PHY_SFCORR_LOW 0x986C
167 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
168 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
169 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
170 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
171 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
172 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
173 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
175 #define AR_PHY_SFCORR 0x9868
176 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
177 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
178 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
179 #define AR_PHY_SFCORR_M1_THRESH_S 17
180 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
181 #define AR_PHY_SFCORR_M2_THRESH_S 24
183 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870
184 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874
185 #define AR_PHY_SYNTH_CONTROL 0x9874
186 #define AR_PHY_SLEEP_SCAL 0x9878
188 #define AR_PHY_PLL_CTL 0x987c
189 #define AR_PHY_PLL_CTL_40 0xaa
190 #define AR_PHY_PLL_CTL_40_5413 0x04
191 #define AR_PHY_PLL_CTL_44 0xab
192 #define AR_PHY_PLL_CTL_44_2133 0xeb
193 #define AR_PHY_PLL_CTL_40_2133 0xea
195 #define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
196 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
197 #define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
198 #define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
199 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
200 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
201 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
202 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
203 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
204 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
205 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
206 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
207 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
208 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
210 #define AR_PHY_RX_DELAY 0x9914
211 #define AR_PHY_SEARCH_START_DELAY 0x9918
212 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
214 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
215 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
216 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
217 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
218 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
219 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
220 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
221 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
222 #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
224 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
225 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
226 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
227 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
229 #define AR_PHY_TIMING5 0x9924
230 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
231 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
233 #define AR_PHY_POWER_TX_RATE1 0x9934
234 #define AR_PHY_POWER_TX_RATE2 0x9938
235 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
236 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
238 #define AR_PHY_FRAME_CTL 0x9944
239 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
240 #define AR_PHY_FRAME_CTL_TX_CLIP_S 3
242 #define AR_PHY_TXPWRADJ 0x994C
243 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
244 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
245 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
246 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
248 #define AR_PHY_RADAR_EXT 0x9940
249 #define AR_PHY_RADAR_EXT_ENA 0x00004000
251 #define AR_PHY_RADAR_0 0x9954
252 #define AR_PHY_RADAR_0_ENA 0x00000001
253 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
254 #define AR_PHY_RADAR_0_INBAND 0x0000003e
255 #define AR_PHY_RADAR_0_INBAND_S 1
256 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0
257 #define AR_PHY_RADAR_0_PRSSI_S 6
258 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000
259 #define AR_PHY_RADAR_0_HEIGHT_S 12
260 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000
261 #define AR_PHY_RADAR_0_RRSSI_S 18
262 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000
263 #define AR_PHY_RADAR_0_FIRPWR_S 24
265 #define AR_PHY_RADAR_1 0x9958
266 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
267 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
268 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
269 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
270 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
271 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
272 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
273 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
274 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
275 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
276 #define AR_PHY_RADAR_1_MAXLEN_S 0
278 #define AR_PHY_SWITCH_CHAIN_0 0x9960
279 #define AR_PHY_SWITCH_COM 0x9964
281 #define AR_PHY_SIGMA_DELTA 0x996C
282 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
283 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
284 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
285 #define AR_PHY_SIGMA_DELTA_FILT2_S 3
286 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
287 #define AR_PHY_SIGMA_DELTA_FILT1_S 8
288 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
289 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
291 #define AR_PHY_RESTART 0x9970
292 #define AR_PHY_RESTART_DIV_GC 0x001C0000
293 #define AR_PHY_RESTART_DIV_GC_S 18
295 #define AR_PHY_RFBUS_REQ 0x997C
296 #define AR_PHY_RFBUS_REQ_EN 0x00000001
298 #define AR_PHY_TIMING7 0x9980
299 #define AR_PHY_TIMING8 0x9984
300 #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
301 #define AR_PHY_TIMING8_PILOT_MASK_2_S 0
303 #define AR_PHY_BIN_MASK2_1 0x9988
304 #define AR_PHY_BIN_MASK2_2 0x998c
305 #define AR_PHY_BIN_MASK2_3 0x9990
306 #define AR_PHY_BIN_MASK2_4 0x9994
308 #define AR_PHY_BIN_MASK_1 0x9900
309 #define AR_PHY_BIN_MASK_2 0x9904
310 #define AR_PHY_BIN_MASK_3 0x9908
312 #define AR_PHY_MASK_CTL 0x990c
314 #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
315 #define AR_PHY_BIN_MASK2_4_MASK_4_S 0
317 #define AR_PHY_TIMING9 0x9998
318 #define AR_PHY_TIMING10 0x999c
319 #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
320 #define AR_PHY_TIMING10_PILOT_MASK_2_S 0
322 #define AR_PHY_TIMING11 0x99a0
323 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
324 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
325 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
326 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
327 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
328 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
330 #define AR_PHY_RX_CHAINMASK 0x99a4
331 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
332 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
333 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
335 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
336 #define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
337 #define AR_PHY_9285_ANT_DIV_CTL 0x01000000
338 #define AR_PHY_9285_ANT_DIV_CTL_S 24
339 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
340 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
341 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
342 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
343 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
344 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
345 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
346 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
347 #define AR_PHY_9285_ANT_DIV_LNA1 2
348 #define AR_PHY_9285_ANT_DIV_LNA2 1
349 #define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
350 #define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
351 #define AR_PHY_9285_ANT_DIV_GAINTB_0 0
352 #define AR_PHY_9285_ANT_DIV_GAINTB_1 1
354 #define AR_PHY_EXT_CCA0 0x99b8
355 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
356 #define AR_PHY_EXT_CCA0_THRESH62_S 0
358 #define AR_PHY_EXT_CCA 0x99bc
359 #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
360 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
361 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
362 #define AR_PHY_EXT_CCA_THRESH62_S 16
363 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
364 #define AR_PHY_EXT_MINCCA_PWR_S 23
365 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
366 #define AR9280_PHY_EXT_MINCCA_PWR_S 16
368 #define AR_PHY_SFCORR_EXT 0x99c0
369 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
370 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
371 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
372 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
373 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
374 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
375 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
376 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
377 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
379 #define AR_PHY_HALFGI 0x99D0
380 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
381 #define AR_PHY_HALFGI_DSC_MAN_S 4
382 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F
383 #define AR_PHY_HALFGI_DSC_EXP_S 0
385 #define AR_PHY_CHAN_INFO_MEMORY 0x99DC
386 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
388 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
390 #define AR_PHY_M_SLEEP 0x99f0
391 #define AR_PHY_REFCLKDLY 0x99f4
392 #define AR_PHY_REFCLKPD 0x99f8
394 #define AR_PHY_CALMODE 0x99f0
396 #define AR_PHY_CALMODE_IQ 0x00000000
397 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
398 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
399 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
401 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
402 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
403 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
404 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
406 #define AR_PHY_CURRENT_RSSI 0x9c1c
407 #define AR9280_PHY_CURRENT_RSSI 0x9c3c
409 #define AR_PHY_RFBUS_GRANT 0x9C20
410 #define AR_PHY_RFBUS_GRANT_EN 0x00000001
412 #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
413 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
415 #define AR_PHY_CHAN_INFO_GAIN 0x9CFC
417 #define AR_PHY_MODE 0xA200
418 #define AR_PHY_MODE_ASYNCFIFO 0x80
419 #define AR_PHY_MODE_AR2133 0x08
420 #define AR_PHY_MODE_AR5111 0x00
421 #define AR_PHY_MODE_AR5112 0x08
422 #define AR_PHY_MODE_DYNAMIC 0x04
423 #define AR_PHY_MODE_RF2GHZ 0x02
424 #define AR_PHY_MODE_RF5GHZ 0x00
425 #define AR_PHY_MODE_CCK 0x01
426 #define AR_PHY_MODE_OFDM 0x00
427 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
429 #define AR_PHY_CCK_TX_CTRL 0xA204
430 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
431 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
432 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
434 #define AR_PHY_CCK_DETECT 0xA208
435 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
436 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
437 /* [12:6] settling time for antenna switch */
438 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
439 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
440 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
441 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
443 #define AR_PHY_GAIN_2GHZ 0xA20C
444 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
445 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
446 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
447 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
448 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
449 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
451 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
452 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
453 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
454 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
455 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
456 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
457 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
458 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
460 #define AR_PHY_CCK_RXCTRL4 0xA21C
461 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
462 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
464 #define AR_PHY_DAG_CTRLCCK 0xA228
465 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
466 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
467 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
469 #define AR_PHY_FORCE_CLKEN_CCK 0xA22C
470 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
472 #define AR_PHY_POWER_TX_RATE3 0xA234
473 #define AR_PHY_POWER_TX_RATE4 0xA238
475 #define AR_PHY_SCRM_SEQ_XR 0xA23C
476 #define AR_PHY_HEADER_DETECT_XR 0xA240
477 #define AR_PHY_CHIRP_DETECTED_XR 0xA244
478 #define AR_PHY_BLUETOOTH 0xA254
480 #define AR_PHY_TPCRG1 0xA258
481 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
482 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
484 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
485 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
486 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
487 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
488 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
489 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
491 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
492 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
494 #define AR_PHY_TX_PWRCTRL4 0xa264
495 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
496 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
497 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
498 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
500 #define AR_PHY_TX_PWRCTRL6_0 0xa270
501 #define AR_PHY_TX_PWRCTRL6_1 0xb270
502 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
503 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
505 #define AR_PHY_TX_PWRCTRL7 0xa274
506 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
507 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
509 #define AR_PHY_TX_PWRCTRL9 0xa27C
510 #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
511 #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
512 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
513 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
515 #define AR_PHY_TX_GAIN_TBL1 0xa300
516 #define AR_PHY_TX_GAIN 0x0007F000
517 #define AR_PHY_TX_GAIN_S 12
519 #define AR_PHY_CH0_TX_PWRCTRL11 0xa398
520 #define AR_PHY_CH1_TX_PWRCTRL11 0xb398
521 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
522 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
524 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
525 #define AR_PHY_MASK2_M_31_45 0xa3a4
526 #define AR_PHY_MASK2_M_16_30 0xa3a8
527 #define AR_PHY_MASK2_M_00_15 0xa3ac
528 #define AR_PHY_MASK2_P_15_01 0xa3b8
529 #define AR_PHY_MASK2_P_30_16 0xa3bc
530 #define AR_PHY_MASK2_P_45_31 0xa3c0
531 #define AR_PHY_MASK2_P_61_45 0xa3c4
532 #define AR_PHY_SPUR_REG 0x994c
534 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
535 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
537 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
538 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
539 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
540 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
541 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
542 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
544 #define AR_PHY_PILOT_MASK_01_30 0xa3b0
545 #define AR_PHY_PILOT_MASK_31_60 0xa3b4
547 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4
548 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8
550 #define AR_PHY_ANALOG_SWAP 0xa268
551 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
553 #define AR_PHY_TPCRG5 0xA26C
554 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
555 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
556 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
557 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
558 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
559 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
560 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
561 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
562 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
563 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
565 /* Carrier leak calibration control, do it after AGC calibration */
566 #define AR_PHY_CL_CAL_CTL 0xA358
567 #define AR_PHY_CL_CAL_ENABLE 0x00000002
568 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
570 #define AR_PHY_POWER_TX_RATE5 0xA38C
571 #define AR_PHY_POWER_TX_RATE6 0xA390
573 #define AR_PHY_CAL_CHAINMASK 0xA39C
575 #define AR_PHY_POWER_TX_SUB 0xA3C8
576 #define AR_PHY_POWER_TX_RATE7 0xA3CC
577 #define AR_PHY_POWER_TX_RATE8 0xA3D0
578 #define AR_PHY_POWER_TX_RATE9 0xA3D4
580 #define AR_PHY_XPA_CFG 0xA3D8
581 #define AR_PHY_FORCE_XPA_CFG 0x000000001
582 #define AR_PHY_FORCE_XPA_CFG_S 0
584 #define AR_PHY_CH1_CCA 0xa864
585 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
586 #define AR_PHY_CH1_MINCCA_PWR_S 19
587 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
588 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
590 #define AR_PHY_CH2_CCA 0xb864
591 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
592 #define AR_PHY_CH2_MINCCA_PWR_S 19
594 #define AR_PHY_CH1_EXT_CCA 0xa9bc
595 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
596 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
597 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
598 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
600 #define AR_PHY_CH2_EXT_CCA 0xb9bc
601 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
602 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
604 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
606 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
607 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
612 #define ATH9K_IS_MIC_ENABLED(ah) \
613 ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
615 #define ANTSWAP_AB 0x0001
616 #define REDUCE_CHAIN_0 0x00000050
617 #define REDUCE_CHAIN_1 0x00000051
619 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
621 for (i = 0; i < (_iniarray)->ia_rows; i++) \
622 (_bank)[i] = INI_RA((_iniarray), i, _col);; \