drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static char *dev_info = "ath9k";
  22
  23 MODULE_AUTHOR("Atheros Communications");
  24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  26 MODULE_LICENSE("Dual BSD/GPL");
  27
  28 static int modparam_nohwcrypt;
  29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  31
  32 /* We use the hw_value as an index into our private channel structure */
  33
  34 #define CHAN2G(_freq, _idx)  { \
  35         .center_freq = (_freq), \
  36         .hw_value = (_idx), \
  37         .max_power = 20, \
  38 }
  39
  40 #define CHAN5G(_freq, _idx) { \
  41         .band = IEEE80211_BAND_5GHZ, \
  42         .center_freq = (_freq), \
  43         .hw_value = (_idx), \
  44         .max_power = 20, \
  45 }
  46
  47 /* Some 2 GHz radios are actually tunable on 2312-2732
  48  * on 5 MHz steps, we support the channels which we know
  49  * we have calibration data for all cards though to make
  50  * this static */
  51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  52         CHAN2G(2412, 0), /* Channel 1 */
  53         CHAN2G(2417, 1), /* Channel 2 */
  54         CHAN2G(2422, 2), /* Channel 3 */
  55         CHAN2G(2427, 3), /* Channel 4 */
  56         CHAN2G(2432, 4), /* Channel 5 */
  57         CHAN2G(2437, 5), /* Channel 6 */
  58         CHAN2G(2442, 6), /* Channel 7 */
  59         CHAN2G(2447, 7), /* Channel 8 */
  60         CHAN2G(2452, 8), /* Channel 9 */
  61         CHAN2G(2457, 9), /* Channel 10 */
  62         CHAN2G(2462, 10), /* Channel 11 */
  63         CHAN2G(2467, 11), /* Channel 12 */
  64         CHAN2G(2472, 12), /* Channel 13 */
  65         CHAN2G(2484, 13), /* Channel 14 */
  66 };
  67
  68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  69  * on 5 MHz steps, we support the channels which we know
  70  * we have calibration data for all cards though to make
  71  * this static */
  72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  73         /* _We_ call this UNII 1 */
  74         CHAN5G(5180, 14), /* Channel 36 */
  75         CHAN5G(5200, 15), /* Channel 40 */
  76         CHAN5G(5220, 16), /* Channel 44 */
  77         CHAN5G(5240, 17), /* Channel 48 */
  78         /* _We_ call this UNII 2 */
  79         CHAN5G(5260, 18), /* Channel 52 */
  80         CHAN5G(5280, 19), /* Channel 56 */
  81         CHAN5G(5300, 20), /* Channel 60 */
  82         CHAN5G(5320, 21), /* Channel 64 */
  83         /* _We_ call this "Middle band" */
  84         CHAN5G(5500, 22), /* Channel 100 */
  85         CHAN5G(5520, 23), /* Channel 104 */
  86         CHAN5G(5540, 24), /* Channel 108 */
  87         CHAN5G(5560, 25), /* Channel 112 */
  88         CHAN5G(5580, 26), /* Channel 116 */
  89         CHAN5G(5600, 27), /* Channel 120 */
  90         CHAN5G(5620, 28), /* Channel 124 */
  91         CHAN5G(5640, 29), /* Channel 128 */
  92         CHAN5G(5660, 30), /* Channel 132 */
  93         CHAN5G(5680, 31), /* Channel 136 */
  94         CHAN5G(5700, 32), /* Channel 140 */
  95         /* _We_ call this UNII 3 */
  96         CHAN5G(5745, 33), /* Channel 149 */
  97         CHAN5G(5765, 34), /* Channel 153 */
  98         CHAN5G(5785, 35), /* Channel 157 */
  99         CHAN5G(5805, 36), /* Channel 161 */
 100         CHAN5G(5825, 37), /* Channel 165 */
 101 };
 102
 103 static void ath_cache_conf_rate(struct ath_softc *sc,
 104                                 struct ieee80211_conf *conf)
 105 {
 106         switch (conf->channel->band) {
 107         case IEEE80211_BAND_2GHZ:
 108                 if (conf_is_ht20(conf))
 109                         sc->cur_rate_table =
 110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 111                 else if (conf_is_ht40_minus(conf))
 112                         sc->cur_rate_table =
 113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 114                 else if (conf_is_ht40_plus(conf))
 115                         sc->cur_rate_table =
 116                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 117                 else
 118                         sc->cur_rate_table =
 119                           sc->hw_rate_table[ATH9K_MODE_11G];
 120                 break;
 121         case IEEE80211_BAND_5GHZ:
 122                 if (conf_is_ht20(conf))
 123                         sc->cur_rate_table =
 124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 125                 else if (conf_is_ht40_minus(conf))
 126                         sc->cur_rate_table =
 127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 128                 else if (conf_is_ht40_plus(conf))
 129                         sc->cur_rate_table =
 130                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 131                 else
 132                         sc->cur_rate_table =
 133                           sc->hw_rate_table[ATH9K_MODE_11A];
 134                 break;
 135         default:
 136                 BUG_ON(1);
 137                 break;
 138         }
 139 }
 140
 141 static void ath_update_txpow(struct ath_softc *sc)
 142 {
 143         struct ath_hw *ah = sc->sc_ah;
 144         u32 txpow;
 145
 146         if (sc->curtxpow != sc->config.txpowlimit) {
 147                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 148                 /* read back in case value is clamped */
 149                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 150                 sc->curtxpow = txpow;
 151         }
 152 }
 153
 154 static u8 parse_mpdudensity(u8 mpdudensity)
 155 {
 156         /*
 157          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 158          *   0 for no restriction
 159          *   1 for 1/4 us
 160          *   2 for 1/2 us
 161          *   3 for 1 us
 162          *   4 for 2 us
 163          *   5 for 4 us
 164          *   6 for 8 us
 165          *   7 for 16 us
 166          */
 167         switch (mpdudensity) {
 168         case 0:
 169                 return 0;
 170         case 1:
 171         case 2:
 172         case 3:
 173                 /* Our lower layer calculations limit our precision to
 174                    1 microsecond */
 175                 return 1;
 176         case 4:
 177                 return 2;
 178         case 5:
 179                 return 4;
 180         case 6:
 181                 return 8;
 182         case 7:
 183                 return 16;
 184         default:
 185                 return 0;
 186         }
 187 }
 188
 189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 190 {
 191         const struct ath_rate_table *rate_table = NULL;
 192         struct ieee80211_supported_band *sband;
 193         struct ieee80211_rate *rate;
 194         int i, maxrates;
 195
 196         switch (band) {
 197         case IEEE80211_BAND_2GHZ:
 198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 199                 break;
 200         case IEEE80211_BAND_5GHZ:
 201                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 202                 break;
 203         default:
 204                 break;
 205         }
 206
 207         if (rate_table == NULL)
 208                 return;
 209
 210         sband = &sc->sbands[band];
 211         rate = sc->rates[band];
 212
 213         if (rate_table->rate_cnt > ATH_RATE_MAX)
 214                 maxrates = ATH_RATE_MAX;
 215         else
 216                 maxrates = rate_table->rate_cnt;
 217
 218         for (i = 0; i < maxrates; i++) {
 219                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 220                 rate[i].hw_value = rate_table->info[i].ratecode;
 221                 if (rate_table->info[i].short_preamble) {
 222                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 223                                 rate_table->info[i].short_preamble;
 224                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 225                 }
 226                 sband->n_bitrates++;
 227
 228                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
 229                           "Rate: %2dMbps, ratecode: %2d\n",
 230                           rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
 235                                                 struct ieee80211_hw *hw)
 236 {
 237         struct ieee80211_channel *curchan = hw->conf.channel;
 238         struct ath9k_channel *channel;
 239         u8 chan_idx;
 240
 241         chan_idx = curchan->hw_value;
 242         channel = &sc->sc_ah->channels[chan_idx];
 243         ath9k_update_ichannel(sc, hw, channel);
 244         return channel;
 245 }
 246
 247 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 248 {
 249         unsigned long flags;
 250         bool ret;
 251
 252         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 253         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 254         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 255
 256         return ret;
 257 }
 258
 259 void ath9k_ps_wakeup(struct ath_softc *sc)
 260 {
 261         unsigned long flags;
 262
 263         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 264         if (++sc->ps_usecount != 1)
 265                 goto unlock;
 266
 267         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 268
 269  unlock:
 270         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 271 }
 272
 273 void ath9k_ps_restore(struct ath_softc *sc)
 274 {
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 278         if (--sc->ps_usecount != 0)
 279                 goto unlock;
 280
 281         if (sc->ps_enabled &&
 282             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 283                               SC_OP_WAIT_FOR_CAB |
 284                               SC_OP_WAIT_FOR_PSPOLL_DATA |
 285                               SC_OP_WAIT_FOR_TX_ACK)))
 286                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 287
 288  unlock:
 289         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 290 }
 291
 292 /*
 293  * Set/change channels.  If the channel is really being changed, it's done
 294  * by reseting the chip.  To accomplish this we must first cleanup any pending
 295  * DMA, then restart stuff.
 296 */
 297 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 298                     struct ath9k_channel *hchan)
 299 {
 300         struct ath_hw *ah = sc->sc_ah;
 301         struct ath_common *common = ath9k_hw_common(ah);
 302         bool fastcc = true, stopped;
 303         struct ieee80211_channel *channel = hw->conf.channel;
 304         int r;
 305
 306         if (sc->sc_flags & SC_OP_INVALID)
 307                 return -EIO;
 308
 309         ath9k_ps_wakeup(sc);
 310
 311         /*
 312          * This is only performed if the channel settings have
 313          * actually changed.
 314          *
 315          * To switch channels clear any pending DMA operations;
 316          * wait long enough for the RX fifo to drain, reset the
 317          * hardware at the new frequency, and then re-enable
 318          * the relevant bits of the h/w.
 319          */
 320         ath9k_hw_set_interrupts(ah, 0);
 321         ath_drain_all_txq(sc, false);
 322         stopped = ath_stoprecv(sc);
 323
 324         /* XXX: do not flush receive queue here. We don't want
 325          * to flush data frames already in queue because of
 326          * changing channel. */
 327
 328         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 329                 fastcc = false;
 330
 331         ath_print(common, ATH_DBG_CONFIG,
 332                   "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 333                   sc->sc_ah->curchan->channel,
 334                   channel->center_freq, sc->tx_chan_width);
 335
 336         spin_lock_bh(&sc->sc_resetlock);
 337
 338         r = ath9k_hw_reset(ah, hchan, fastcc);
 339         if (r) {
 340                 ath_print(common, ATH_DBG_FATAL,
 341                           "Unable to reset channel (%u Mhz) "
 342                           "reset status %d\n",
 343                           channel->center_freq, r);
 344                 spin_unlock_bh(&sc->sc_resetlock);
 345                 goto ps_restore;
 346         }
 347         spin_unlock_bh(&sc->sc_resetlock);
 348
 349         sc->sc_flags &= ~SC_OP_FULL_RESET;
 350
 351         if (ath_startrecv(sc) != 0) {
 352                 ath_print(common, ATH_DBG_FATAL,
 353                           "Unable to restart recv logic\n");
 354                 r = -EIO;
 355                 goto ps_restore;
 356         }
 357
 358         ath_cache_conf_rate(sc, &hw->conf);
 359         ath_update_txpow(sc);
 360         ath9k_hw_set_interrupts(ah, sc->imask);
 361
 362  ps_restore:
 363         ath9k_ps_restore(sc);
 364         return r;
 365 }
 366
 367 /*
 368  *  This routine performs the periodic noise floor calibration function
 369  *  that is used to adjust and optimize the chip performance.  This
 370  *  takes environmental changes (location, temperature) into account.
 371  *  When the task is complete, it reschedules itself depending on the
 372  *  appropriate interval that was calculated.
 373  */
 374 static void ath_ani_calibrate(unsigned long data)
 375 {
 376         struct ath_softc *sc = (struct ath_softc *)data;
 377         struct ath_hw *ah = sc->sc_ah;
 378         struct ath_common *common = ath9k_hw_common(ah);
 379         bool longcal = false;
 380         bool shortcal = false;
 381         bool aniflag = false;
 382         unsigned int timestamp = jiffies_to_msecs(jiffies);
 383         u32 cal_interval, short_cal_interval;
 384
 385         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 386                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 387
 388         /*
 389         * don't calibrate when we're scanning.
 390         * we are most likely not on our home channel.
 391         */
 392         spin_lock(&sc->ani_lock);
 393         if (sc->sc_flags & SC_OP_SCANNING)
 394                 goto set_timer;
 395
 396         /* Only calibrate if awake */
 397         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 398                 goto set_timer;
 399
 400         ath9k_ps_wakeup(sc);
 401
 402         /* Long calibration runs independently of short calibration. */
 403         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 404                 longcal = true;
 405                 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 406                 sc->ani.longcal_timer = timestamp;
 407         }
 408
 409         /* Short calibration applies only while caldone is false */
 410         if (!sc->ani.caldone) {
 411                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 412                         shortcal = true;
 413                         ath_print(common, ATH_DBG_ANI,
 414                                   "shortcal @%lu\n", jiffies);
 415                         sc->ani.shortcal_timer = timestamp;
 416                         sc->ani.resetcal_timer = timestamp;
 417                 }
 418         } else {
 419                 if ((timestamp - sc->ani.resetcal_timer) >=
 420                     ATH_RESTART_CALINTERVAL) {
 421                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 422                         if (sc->ani.caldone)
 423                                 sc->ani.resetcal_timer = timestamp;
 424                 }
 425         }
 426
 427         /* Verify whether we must check ANI */
 428         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 429                 aniflag = true;
 430                 sc->ani.checkani_timer = timestamp;
 431         }
 432
 433         /* Skip all processing if there's nothing to do. */
 434         if (longcal || shortcal || aniflag) {
 435                 /* Call ANI routine if necessary */
 436                 if (aniflag)
 437                         ath9k_hw_ani_monitor(ah, ah->curchan);
 438
 439                 /* Perform calibration if necessary */
 440                 if (longcal || shortcal) {
 441                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 442                                                      sc->rx_chainmask, longcal);
 443
 444                         if (longcal)
 445                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 446                                                                      ah->curchan);
 447
 448                         ath_print(common, ATH_DBG_ANI,
 449                                   " calibrate chan %u/%x nf: %d\n",
 450                                   ah->curchan->channel,
 451                                   ah->curchan->channelFlags,
 452                                   sc->ani.noise_floor);
 453                 }
 454         }
 455
 456         ath9k_ps_restore(sc);
 457
 458 set_timer:
 459         spin_unlock(&sc->ani_lock);
 460         /*
 461         * Set timer interval based on previous results.
 462         * The interval must be the shortest necessary to satisfy ANI,
 463         * short calibration and long calibration.
 464         */
 465         cal_interval = ATH_LONG_CALINTERVAL;
 466         if (sc->sc_ah->config.enable_ani)
 467                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 468         if (!sc->ani.caldone)
 469                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 470
 471         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 472 }
 473
 474 static void ath_start_ani(struct ath_softc *sc)
 475 {
 476         unsigned long timestamp = jiffies_to_msecs(jiffies);
 477
 478         sc->ani.longcal_timer = timestamp;
 479         sc->ani.shortcal_timer = timestamp;
 480         sc->ani.checkani_timer = timestamp;
 481
 482         mod_timer(&sc->ani.timer,
 483                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 484 }
 485
 486 /*
 487  * Update tx/rx chainmask. For legacy association,
 488  * hard code chainmask to 1x1, for 11n association, use
 489  * the chainmask configuration, for bt coexistence, use
 490  * the chainmask configuration even in legacy mode.
 491  */
 492 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 493 {
 494         struct ath_hw *ah = sc->sc_ah;
 495
 496         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
 497             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 498                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 499                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 500         } else {
 501                 sc->tx_chainmask = 1;
 502                 sc->rx_chainmask = 1;
 503         }
 504
 505         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 506                   "tx chmask: %d, rx chmask: %d\n",
 507                   sc->tx_chainmask, sc->rx_chainmask);
 508 }
 509
 510 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 511 {
 512         struct ath_node *an;
 513
 514         an = (struct ath_node *)sta->drv_priv;
 515
 516         if (sc->sc_flags & SC_OP_TXAGGR) {
 517                 ath_tx_node_init(sc, an);
 518                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 519                                      sta->ht_cap.ampdu_factor);
 520                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 521                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 522         }
 523 }
 524
 525 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 526 {
 527         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 528
 529         if (sc->sc_flags & SC_OP_TXAGGR)
 530                 ath_tx_node_cleanup(sc, an);
 531 }
 532
 533 static void ath9k_tasklet(unsigned long data)
 534 {
 535         struct ath_softc *sc = (struct ath_softc *)data;
 536         struct ath_hw *ah = sc->sc_ah;
 537         struct ath_common *common = ath9k_hw_common(ah);
 538
 539         u32 status = sc->intrstatus;
 540
 541         ath9k_ps_wakeup(sc);
 542
 543         if (status & ATH9K_INT_FATAL) {
 544                 ath_reset(sc, false);
 545                 ath9k_ps_restore(sc);
 546                 return;
 547         }
 548
 549         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 550                 spin_lock_bh(&sc->rx.rxflushlock);
 551                 ath_rx_tasklet(sc, 0);
 552                 spin_unlock_bh(&sc->rx.rxflushlock);
 553         }
 554
 555         if (status & ATH9K_INT_TX)
 556                 ath_tx_tasklet(sc);
 557
 558         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 559                 /*
 560                  * TSF sync does not look correct; remain awake to sync with
 561                  * the next Beacon.
 562                  */
 563                 ath_print(common, ATH_DBG_PS,
 564                           "TSFOOR - Sync with next Beacon\n");
 565                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 566         }
 567
 568         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 569                 if (status & ATH9K_INT_GENTIMER)
 570                         ath_gen_timer_isr(sc->sc_ah);
 571
 572         /* re-enable hardware interrupt */
 573         ath9k_hw_set_interrupts(ah, sc->imask);
 574         ath9k_ps_restore(sc);
 575 }
 576
 577 irqreturn_t ath_isr(int irq, void *dev)
 578 {
 579 #define SCHED_INTR (                            \
 580                 ATH9K_INT_FATAL |               \
 581                 ATH9K_INT_RXORN |               \
 582                 ATH9K_INT_RXEOL |               \
 583                 ATH9K_INT_RX |                  \
 584                 ATH9K_INT_TX |                  \
 585                 ATH9K_INT_BMISS |               \
 586                 ATH9K_INT_CST |                 \
 587                 ATH9K_INT_TSFOOR |              \
 588                 ATH9K_INT_GENTIMER)
 589
 590         struct ath_softc *sc = dev;
 591         struct ath_hw *ah = sc->sc_ah;
 592         enum ath9k_int status;
 593         bool sched = false;
 594
 595         /*
 596          * The hardware is not ready/present, don't
 597          * touch anything. Note this can happen early
 598          * on if the IRQ is shared.
 599          */
 600         if (sc->sc_flags & SC_OP_INVALID)
 601                 return IRQ_NONE;
 602
 603
 604         /* shared irq, not for us */
 605
 606         if (!ath9k_hw_intrpend(ah))
 607                 return IRQ_NONE;
 608
 609         /*
 610          * Figure out the reason(s) for the interrupt.  Note
 611          * that the hal returns a pseudo-ISR that may include
 612          * bits we haven't explicitly enabled so we mask the
 613          * value to insure we only process bits we requested.
 614          */
 615         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 616         status &= sc->imask;    /* discard unasked-for bits */
 617
 618         /*
 619          * If there are no status bits set, then this interrupt was not
 620          * for me (should have been caught above).
 621          */
 622         if (!status)
 623                 return IRQ_NONE;
 624
 625         /* Cache the status */
 626         sc->intrstatus = status;
 627
 628         if (status & SCHED_INTR)
 629                 sched = true;
 630
 631         /*
 632          * If a FATAL or RXORN interrupt is received, we have to reset the
 633          * chip immediately.
 634          */
 635         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 636                 goto chip_reset;
 637
 638         if (status & ATH9K_INT_SWBA)
 639                 tasklet_schedule(&sc->bcon_tasklet);
 640
 641         if (status & ATH9K_INT_TXURN)
 642                 ath9k_hw_updatetxtriglevel(ah, true);
 643
 644         if (status & ATH9K_INT_MIB) {
 645                 /*
 646                  * Disable interrupts until we service the MIB
 647                  * interrupt; otherwise it will continue to
 648                  * fire.
 649                  */
 650                 ath9k_hw_set_interrupts(ah, 0);
 651                 /*
 652                  * Let the hal handle the event. We assume
 653                  * it will clear whatever condition caused
 654                  * the interrupt.
 655                  */
 656                 ath9k_hw_procmibevent(ah);
 657                 ath9k_hw_set_interrupts(ah, sc->imask);
 658         }
 659
 660         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 661                 if (status & ATH9K_INT_TIM_TIMER) {
 662                         /* Clear RxAbort bit so that we can
 663                          * receive frames */
 664                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 665                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 666                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 667                 }
 668
 669 chip_reset:
 670
 671         ath_debug_stat_interrupt(sc, status);
 672
 673         if (sched) {
 674                 /* turn off every interrupt except SWBA */
 675                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 676                 tasklet_schedule(&sc->intr_tq);
 677         }
 678
 679         return IRQ_HANDLED;
 680
 681 #undef SCHED_INTR
 682 }
 683
 684 static u32 ath_get_extchanmode(struct ath_softc *sc,
 685                                struct ieee80211_channel *chan,
 686                                enum nl80211_channel_type channel_type)
 687 {
 688         u32 chanmode = 0;
 689
 690         switch (chan->band) {
 691         case IEEE80211_BAND_2GHZ:
 692                 switch(channel_type) {
 693                 case NL80211_CHAN_NO_HT:
 694                 case NL80211_CHAN_HT20:
 695                         chanmode = CHANNEL_G_HT20;
 696                         break;
 697                 case NL80211_CHAN_HT40PLUS:
 698                         chanmode = CHANNEL_G_HT40PLUS;
 699                         break;
 700                 case NL80211_CHAN_HT40MINUS:
 701                         chanmode = CHANNEL_G_HT40MINUS;
 702                         break;
 703                 }
 704                 break;
 705         case IEEE80211_BAND_5GHZ:
 706                 switch(channel_type) {
 707                 case NL80211_CHAN_NO_HT:
 708                 case NL80211_CHAN_HT20:
 709                         chanmode = CHANNEL_A_HT20;
 710                         break;
 711                 case NL80211_CHAN_HT40PLUS:
 712                         chanmode = CHANNEL_A_HT40PLUS;
 713                         break;
 714                 case NL80211_CHAN_HT40MINUS:
 715                         chanmode = CHANNEL_A_HT40MINUS;
 716                         break;
 717                 }
 718                 break;
 719         default:
 720                 break;
 721         }
 722
 723         return chanmode;
 724 }
 725
 726 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 727                            struct ath9k_keyval *hk, const u8 *addr,
 728                            bool authenticator)
 729 {
 730         const u8 *key_rxmic;
 731         const u8 *key_txmic;
 732
 733         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 734         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 735
 736         if (addr == NULL) {
 737                 /*
 738                  * Group key installation - only two key cache entries are used
 739                  * regardless of splitmic capability since group key is only
 740                  * used either for TX or RX.
 741                  */
 742                 if (authenticator) {
 743                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 744                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 745                 } else {
 746                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 747                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 748                 }
 749                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 750         }
 751         if (!sc->splitmic) {
 752                 /* TX and RX keys share the same key cache entry. */
 753                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 754                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 755                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 756         }
 757
 758         /* Separate key cache entries for TX and RX */
 759
 760         /* TX key goes at first index, RX key at +32. */
 761         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 762         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 763                 /* TX MIC entry failed. No need to proceed further */
 764                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
 765                           "Setting TX MIC Key Failed\n");
 766                 return 0;
 767         }
 768
 769         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 770         /* XXX delete tx key on failure? */
 771         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 772 }
 773
 774 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 775 {
 776         int i;
 777
 778         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 779                 if (test_bit(i, sc->keymap) ||
 780                     test_bit(i + 64, sc->keymap))
 781                         continue; /* At least one part of TKIP key allocated */
 782                 if (sc->splitmic &&
 783                     (test_bit(i + 32, sc->keymap) ||
 784                      test_bit(i + 64 + 32, sc->keymap)))
 785                         continue; /* At least one part of TKIP key allocated */
 786
 787                 /* Found a free slot for a TKIP key */
 788                 return i;
 789         }
 790         return -1;
 791 }
 792
 793 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 794 {
 795         int i;
 796
 797         /* First, try to find slots that would not be available for TKIP. */
 798         if (sc->splitmic) {
 799                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 800                         if (!test_bit(i, sc->keymap) &&
 801                             (test_bit(i + 32, sc->keymap) ||
 802                              test_bit(i + 64, sc->keymap) ||
 803                              test_bit(i + 64 + 32, sc->keymap)))
 804                                 return i;
 805                         if (!test_bit(i + 32, sc->keymap) &&
 806                             (test_bit(i, sc->keymap) ||
 807                              test_bit(i + 64, sc->keymap) ||
 808                              test_bit(i + 64 + 32, sc->keymap)))
 809                                 return i + 32;
 810                         if (!test_bit(i + 64, sc->keymap) &&
 811                             (test_bit(i , sc->keymap) ||
 812                              test_bit(i + 32, sc->keymap) ||
 813                              test_bit(i + 64 + 32, sc->keymap)))
 814                                 return i + 64;
 815                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 816                             (test_bit(i, sc->keymap) ||
 817                              test_bit(i + 32, sc->keymap) ||
 818                              test_bit(i + 64, sc->keymap)))
 819                                 return i + 64 + 32;
 820                 }
 821         } else {
 822                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 823                         if (!test_bit(i, sc->keymap) &&
 824                             test_bit(i + 64, sc->keymap))
 825                                 return i;
 826                         if (test_bit(i, sc->keymap) &&
 827                             !test_bit(i + 64, sc->keymap))
 828                                 return i + 64;
 829                 }
 830         }
 831
 832         /* No partially used TKIP slots, pick any available slot */
 833         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 834                 /* Do not allow slots that could be needed for TKIP group keys
 835                  * to be used. This limitation could be removed if we know that
 836                  * TKIP will not be used. */
 837                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 838                         continue;
 839                 if (sc->splitmic) {
 840                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 841                                 continue;
 842                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 843                                 continue;
 844                 }
 845
 846                 if (!test_bit(i, sc->keymap))
 847                         return i; /* Found a free slot for a key */
 848         }
 849
 850         /* No free slot found */
 851         return -1;
 852 }
 853
 854 static int ath_key_config(struct ath_softc *sc,
 855                           struct ieee80211_vif *vif,
 856                           struct ieee80211_sta *sta,
 857                           struct ieee80211_key_conf *key)
 858 {
 859         struct ath9k_keyval hk;
 860         const u8 *mac = NULL;
 861         int ret = 0;
 862         int idx;
 863
 864         memset(&hk, 0, sizeof(hk));
 865
 866         switch (key->alg) {
 867         case ALG_WEP:
 868                 hk.kv_type = ATH9K_CIPHER_WEP;
 869                 break;
 870         case ALG_TKIP:
 871                 hk.kv_type = ATH9K_CIPHER_TKIP;
 872                 break;
 873         case ALG_CCMP:
 874                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 875                 break;
 876         default:
 877                 return -EOPNOTSUPP;
 878         }
 879
 880         hk.kv_len = key->keylen;
 881         memcpy(hk.kv_val, key->key, key->keylen);
 882
 883         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 884                 /* For now, use the default keys for broadcast keys. This may
 885                  * need to change with virtual interfaces. */
 886                 idx = key->keyidx;
 887         } else if (key->keyidx) {
 888                 if (WARN_ON(!sta))
 889                         return -EOPNOTSUPP;
 890                 mac = sta->addr;
 891
 892                 if (vif->type != NL80211_IFTYPE_AP) {
 893                         /* Only keyidx 0 should be used with unicast key, but
 894                          * allow this for client mode for now. */
 895                         idx = key->keyidx;
 896                 } else
 897                         return -EIO;
 898         } else {
 899                 if (WARN_ON(!sta))
 900                         return -EOPNOTSUPP;
 901                 mac = sta->addr;
 902
 903                 if (key->alg == ALG_TKIP)
 904                         idx = ath_reserve_key_cache_slot_tkip(sc);
 905                 else
 906                         idx = ath_reserve_key_cache_slot(sc);
 907                 if (idx < 0)
 908                         return -ENOSPC; /* no free key cache entries */
 909         }
 910
 911         if (key->alg == ALG_TKIP)
 912                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 913                                       vif->type == NL80211_IFTYPE_AP);
 914         else
 915                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 916
 917         if (!ret)
 918                 return -EIO;
 919
 920         set_bit(idx, sc->keymap);
 921         if (key->alg == ALG_TKIP) {
 922                 set_bit(idx + 64, sc->keymap);
 923                 if (sc->splitmic) {
 924                         set_bit(idx + 32, sc->keymap);
 925                         set_bit(idx + 64 + 32, sc->keymap);
 926                 }
 927         }
 928
 929         return idx;
 930 }
 931
 932 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 933 {
 934         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 935         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 936                 return;
 937
 938         clear_bit(key->hw_key_idx, sc->keymap);
 939         if (key->alg != ALG_TKIP)
 940                 return;
 941
 942         clear_bit(key->hw_key_idx + 64, sc->keymap);
 943         if (sc->splitmic) {
 944                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 945                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 946         }
 947 }
 948
 949 static void setup_ht_cap(struct ath_softc *sc,
 950                          struct ieee80211_sta_ht_cap *ht_info)
 951 {
 952         u8 tx_streams, rx_streams;
 953
 954         ht_info->ht_supported = true;
 955         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 956                        IEEE80211_HT_CAP_SM_PS |
 957                        IEEE80211_HT_CAP_SGI_40 |
 958                        IEEE80211_HT_CAP_DSSSCCK40;
 959
 960         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 961         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 962
 963         /* set up supported mcs set */
 964         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 965         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
 966         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
 967
 968         if (tx_streams != rx_streams) {
 969                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
 970                           "TX streams %d, RX streams: %d\n",
 971                           tx_streams, rx_streams);
 972                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 973                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 974                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 975         }
 976
 977         ht_info->mcs.rx_mask[0] = 0xff;
 978         if (rx_streams >= 2)
 979                 ht_info->mcs.rx_mask[1] = 0xff;
 980
 981         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 982 }
 983
 984 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 985                                  struct ieee80211_vif *vif,
 986                                  struct ieee80211_bss_conf *bss_conf)
 987 {
 988         struct ath_hw *ah = sc->sc_ah;
 989         struct ath_common *common = ath9k_hw_common(ah);
 990
 991         if (bss_conf->assoc) {
 992                 ath_print(common, ATH_DBG_CONFIG,
 993                           "Bss Info ASSOC %d, bssid: %pM\n",
 994                            bss_conf->aid, common->curbssid);
 995
 996                 /* New association, store aid */
 997                 common->curaid = bss_conf->aid;
 998                 ath9k_hw_write_associd(ah);
 999
1000                 /*
1001                  * Request a re-configuration of Beacon related timers
1002                  * on the receipt of the first Beacon frame (i.e.,
1003                  * after time sync with the AP).
1004                  */
1005                 sc->sc_flags |= SC_OP_BEACON_SYNC;
1006
1007                 /* Configure the beacon */
1008                 ath_beacon_config(sc, vif);
1009
1010                 /* Reset rssi stats */
1011                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1012
1013                 ath_start_ani(sc);
1014         } else {
1015                 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1016                 common->curaid = 0;
1017                 /* Stop ANI */
1018                 del_timer_sync(&sc->ani.timer);
1019         }
1020 }
1021
1022 /********************************/
1023 /*       LED functions          */
1024 /********************************/
1025
1026 static void ath_led_blink_work(struct work_struct *work)
1027 {
1028         struct ath_softc *sc = container_of(work, struct ath_softc,
1029                                             ath_led_blink_work.work);
1030
1031         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1032                 return;
1033
1034         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1035             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1036                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1037         else
1038                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1039                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1040
1041         ieee80211_queue_delayed_work(sc->hw,
1042                                      &sc->ath_led_blink_work,
1043                                      (sc->sc_flags & SC_OP_LED_ON) ?
1044                                         msecs_to_jiffies(sc->led_off_duration) :
1045                                         msecs_to_jiffies(sc->led_on_duration));
1046
1047         sc->led_on_duration = sc->led_on_cnt ?
1048                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1049                         ATH_LED_ON_DURATION_IDLE;
1050         sc->led_off_duration = sc->led_off_cnt ?
1051                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1052                         ATH_LED_OFF_DURATION_IDLE;
1053         sc->led_on_cnt = sc->led_off_cnt = 0;
1054         if (sc->sc_flags & SC_OP_LED_ON)
1055                 sc->sc_flags &= ~SC_OP_LED_ON;
1056         else
1057                 sc->sc_flags |= SC_OP_LED_ON;
1058 }
1059
1060 static void ath_led_brightness(struct led_classdev *led_cdev,
1061                                enum led_brightness brightness)
1062 {
1063         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1064         struct ath_softc *sc = led->sc;
1065
1066         switch (brightness) {
1067         case LED_OFF:
1068                 if (led->led_type == ATH_LED_ASSOC ||
1069                     led->led_type == ATH_LED_RADIO) {
1070                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1071                                 (led->led_type == ATH_LED_RADIO));
1072                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1073                         if (led->led_type == ATH_LED_RADIO)
1074                                 sc->sc_flags &= ~SC_OP_LED_ON;
1075                 } else {
1076                         sc->led_off_cnt++;
1077                 }
1078                 break;
1079         case LED_FULL:
1080                 if (led->led_type == ATH_LED_ASSOC) {
1081                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1082                         ieee80211_queue_delayed_work(sc->hw,
1083                                                      &sc->ath_led_blink_work, 0);
1084                 } else if (led->led_type == ATH_LED_RADIO) {
1085                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1086                         sc->sc_flags |= SC_OP_LED_ON;
1087                 } else {
1088                         sc->led_on_cnt++;
1089                 }
1090                 break;
1091         default:
1092                 break;
1093         }
1094 }
1095
1096 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1097                             char *trigger)
1098 {
1099         int ret;
1100
1101         led->sc = sc;
1102         led->led_cdev.name = led->name;
1103         led->led_cdev.default_trigger = trigger;
1104         led->led_cdev.brightness_set = ath_led_brightness;
1105
1106         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1107         if (ret)
1108                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1109                           "Failed to register led:%s", led->name);
1110         else
1111                 led->registered = 1;
1112         return ret;
1113 }
1114
1115 static void ath_unregister_led(struct ath_led *led)
1116 {
1117         if (led->registered) {
1118                 led_classdev_unregister(&led->led_cdev);
1119                 led->registered = 0;
1120         }
1121 }
1122
1123 static void ath_deinit_leds(struct ath_softc *sc)
1124 {
1125         ath_unregister_led(&sc->assoc_led);
1126         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1127         ath_unregister_led(&sc->tx_led);
1128         ath_unregister_led(&sc->rx_led);
1129         ath_unregister_led(&sc->radio_led);
1130         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1131 }
1132
1133 static void ath_init_leds(struct ath_softc *sc)
1134 {
1135         char *trigger;
1136         int ret;
1137
1138         if (AR_SREV_9287(sc->sc_ah))
1139                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1140         else
1141                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1142
1143         /* Configure gpio 1 for output */
1144         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1145                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1146         /* LED off, active low */
1147         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1148
1149         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1150
1151         trigger = ieee80211_get_radio_led_name(sc->hw);
1152         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1153                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1154         ret = ath_register_led(sc, &sc->radio_led, trigger);
1155         sc->radio_led.led_type = ATH_LED_RADIO;
1156         if (ret)
1157                 goto fail;
1158
1159         trigger = ieee80211_get_assoc_led_name(sc->hw);
1160         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1161                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1162         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1163         sc->assoc_led.led_type = ATH_LED_ASSOC;
1164         if (ret)
1165                 goto fail;
1166
1167         trigger = ieee80211_get_tx_led_name(sc->hw);
1168         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1169                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1170         ret = ath_register_led(sc, &sc->tx_led, trigger);
1171         sc->tx_led.led_type = ATH_LED_TX;
1172         if (ret)
1173                 goto fail;
1174
1175         trigger = ieee80211_get_rx_led_name(sc->hw);
1176         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1177                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1178         ret = ath_register_led(sc, &sc->rx_led, trigger);
1179         sc->rx_led.led_type = ATH_LED_RX;
1180         if (ret)
1181                 goto fail;
1182
1183         return;
1184
1185 fail:
1186         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1187         ath_deinit_leds(sc);
1188 }
1189
1190 void ath_radio_enable(struct ath_softc *sc)
1191 {
1192         struct ath_hw *ah = sc->sc_ah;
1193         struct ath_common *common = ath9k_hw_common(ah);
1194         struct ieee80211_channel *channel = sc->hw->conf.channel;
1195         int r;
1196
1197         ath9k_ps_wakeup(sc);
1198         ath9k_hw_configpcipowersave(ah, 0, 0);
1199
1200         if (!ah->curchan)
1201                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1202
1203         spin_lock_bh(&sc->sc_resetlock);
1204         r = ath9k_hw_reset(ah, ah->curchan, false);
1205         if (r) {
1206                 ath_print(common, ATH_DBG_FATAL,
1207                           "Unable to reset channel %u (%uMhz) ",
1208                           "reset status %d\n",
1209                           channel->center_freq, r);
1210         }
1211         spin_unlock_bh(&sc->sc_resetlock);
1212
1213         ath_update_txpow(sc);
1214         if (ath_startrecv(sc) != 0) {
1215                 ath_print(common, ATH_DBG_FATAL,
1216                           "Unable to restart recv logic\n");
1217                 return;
1218         }
1219
1220         if (sc->sc_flags & SC_OP_BEACONS)
1221                 ath_beacon_config(sc, NULL);    /* restart beacons */
1222
1223         /* Re-Enable  interrupts */
1224         ath9k_hw_set_interrupts(ah, sc->imask);
1225
1226         /* Enable LED */
1227         ath9k_hw_cfg_output(ah, ah->led_pin,
1228                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1229         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1230
1231         ieee80211_wake_queues(sc->hw);
1232         ath9k_ps_restore(sc);
1233 }
1234
1235 void ath_radio_disable(struct ath_softc *sc)
1236 {
1237         struct ath_hw *ah = sc->sc_ah;
1238         struct ieee80211_channel *channel = sc->hw->conf.channel;
1239         int r;
1240
1241         ath9k_ps_wakeup(sc);
1242         ieee80211_stop_queues(sc->hw);
1243
1244         /* Disable LED */
1245         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1246         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1247
1248         /* Disable interrupts */
1249         ath9k_hw_set_interrupts(ah, 0);
1250
1251         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1252         ath_stoprecv(sc);               /* turn off frame recv */
1253         ath_flushrecv(sc);              /* flush recv queue */
1254
1255         if (!ah->curchan)
1256                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1257
1258         spin_lock_bh(&sc->sc_resetlock);
1259         r = ath9k_hw_reset(ah, ah->curchan, false);
1260         if (r) {
1261                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1262                           "Unable to reset channel %u (%uMhz) "
1263                           "reset status %d\n",
1264                           channel->center_freq, r);
1265         }
1266         spin_unlock_bh(&sc->sc_resetlock);
1267
1268         ath9k_hw_phy_disable(ah);
1269         ath9k_hw_configpcipowersave(ah, 1, 1);
1270         ath9k_ps_restore(sc);
1271         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1272 }
1273
1274 /*******************/
1275 /*      Rfkill     */
1276 /*******************/
1277
1278 static bool ath_is_rfkill_set(struct ath_softc *sc)
1279 {
1280         struct ath_hw *ah = sc->sc_ah;
1281
1282         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1283                                   ah->rfkill_polarity;
1284 }
1285
1286 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1287 {
1288         struct ath_wiphy *aphy = hw->priv;
1289         struct ath_softc *sc = aphy->sc;
1290         bool blocked = !!ath_is_rfkill_set(sc);
1291
1292         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1293 }
1294
1295 static void ath_start_rfkill_poll(struct ath_softc *sc)
1296 {
1297         struct ath_hw *ah = sc->sc_ah;
1298
1299         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1300                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1301 }
1302
1303 void ath_cleanup(struct ath_softc *sc)
1304 {
1305         ath_detach(sc);
1306         free_irq(sc->irq, sc);
1307         ath_bus_cleanup(sc);
1308         kfree(sc->sec_wiphy);
1309         ieee80211_free_hw(sc->hw);
1310 }
1311
1312 void ath_detach(struct ath_softc *sc)
1313 {
1314         struct ieee80211_hw *hw = sc->hw;
1315         struct ath_hw *ah = sc->sc_ah;
1316         int i = 0;
1317
1318         ath9k_ps_wakeup(sc);
1319
1320         dev_dbg(sc->dev, "Detach ATH hw\n");
1321
1322         ath_deinit_leds(sc);
1323         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1324
1325         for (i = 0; i < sc->num_sec_wiphy; i++) {
1326                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1327                 if (aphy == NULL)
1328                         continue;
1329                 sc->sec_wiphy[i] = NULL;
1330                 ieee80211_unregister_hw(aphy->hw);
1331                 ieee80211_free_hw(aphy->hw);
1332         }
1333         ieee80211_unregister_hw(hw);
1334         ath_rx_cleanup(sc);
1335         ath_tx_cleanup(sc);
1336
1337         tasklet_kill(&sc->intr_tq);
1338         tasklet_kill(&sc->bcon_tasklet);
1339
1340         if (!(sc->sc_flags & SC_OP_INVALID))
1341                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1342
1343         /* cleanup tx queues */
1344         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1345                 if (ATH_TXQ_SETUP(sc, i))
1346                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1347
1348         if ((sc->btcoex.no_stomp_timer) &&
1349             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1350                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1351
1352         ath9k_hw_detach(ah);
1353         ath9k_exit_debug(ah);
1354         sc->sc_ah = NULL;
1355 }
1356
1357 static int ath9k_reg_notifier(struct wiphy *wiphy,
1358                               struct regulatory_request *request)
1359 {
1360         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1361         struct ath_wiphy *aphy = hw->priv;
1362         struct ath_softc *sc = aphy->sc;
1363         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1364
1365         return ath_reg_notifier_apply(wiphy, request, reg);
1366 }
1367
1368 /*
1369  * Detects if there is any priority bt traffic
1370  */
1371 static void ath_detect_bt_priority(struct ath_softc *sc)
1372 {
1373         struct ath_btcoex *btcoex = &sc->btcoex;
1374         struct ath_hw *ah = sc->sc_ah;
1375
1376         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1377                 btcoex->bt_priority_cnt++;
1378
1379         if (time_after(jiffies, btcoex->bt_priority_time +
1380                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1381                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1382                         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1383                                   "BT priority traffic detected");
1384                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1385                 } else {
1386                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1387                 }
1388
1389                 btcoex->bt_priority_cnt = 0;
1390                 btcoex->bt_priority_time = jiffies;
1391         }
1392 }
1393
1394 /*
1395  * Configures appropriate weight based on stomp type.
1396  */
1397 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1398                                   enum ath_stomp_type stomp_type)
1399 {
1400         struct ath_hw *ah = sc->sc_ah;
1401
1402         switch (stomp_type) {
1403         case ATH_BTCOEX_STOMP_ALL:
1404                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1405                                            AR_STOMP_ALL_WLAN_WGHT);
1406                 break;
1407         case ATH_BTCOEX_STOMP_LOW:
1408                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1409                                            AR_STOMP_LOW_WLAN_WGHT);
1410                 break;
1411         case ATH_BTCOEX_STOMP_NONE:
1412                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1413                                            AR_STOMP_NONE_WLAN_WGHT);
1414                 break;
1415         default:
1416                 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1417                           "Invalid Stomptype\n");
1418                 break;
1419         }
1420
1421         ath9k_hw_btcoex_enable(ah);
1422 }
1423
1424 static void ath9k_gen_timer_start(struct ath_hw *ah,
1425                                   struct ath_gen_timer *timer,
1426                                   u32 timer_next,
1427                                   u32 timer_period)
1428 {
1429         ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1430
1431         if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
1432                 ath9k_hw_set_interrupts(ah, 0);
1433                 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
1434                 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1435         }
1436 }
1437
1438 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1439 {
1440         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1441
1442         ath9k_hw_gen_timer_stop(ah, timer);
1443
1444         /* if no timer is enabled, turn off interrupt mask */
1445         if (timer_table->timer_mask.val == 0) {
1446                 ath9k_hw_set_interrupts(ah, 0);
1447                 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
1448                 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1449         }
1450 }
1451
1452 /*
1453  * This is the master bt coex timer which runs for every
1454  * 45ms, bt traffic will be given priority during 55% of this
1455  * period while wlan gets remaining 45%
1456  */
1457 static void ath_btcoex_period_timer(unsigned long data)
1458 {
1459         struct ath_softc *sc = (struct ath_softc *) data;
1460         struct ath_hw *ah = sc->sc_ah;
1461         struct ath_btcoex *btcoex = &sc->btcoex;
1462
1463         ath_detect_bt_priority(sc);
1464
1465         spin_lock_bh(&btcoex->btcoex_lock);
1466
1467         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1468
1469         spin_unlock_bh(&btcoex->btcoex_lock);
1470
1471         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1472                 if (btcoex->hw_timer_enabled)
1473                         ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1474
1475                 ath9k_gen_timer_start(ah,
1476                                       btcoex->no_stomp_timer,
1477                                       (ath9k_hw_gettsf32(ah) +
1478                                        btcoex->btcoex_no_stomp),
1479                                        btcoex->btcoex_no_stomp * 10);
1480                 btcoex->hw_timer_enabled = true;
1481         }
1482
1483         mod_timer(&btcoex->period_timer, jiffies +
1484                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1485 }
1486
1487 /*
1488  * Generic tsf based hw timer which configures weight
1489  * registers to time slice between wlan and bt traffic
1490  */
1491 static void ath_btcoex_no_stomp_timer(void *arg)
1492 {
1493         struct ath_softc *sc = (struct ath_softc *)arg;
1494         struct ath_hw *ah = sc->sc_ah;
1495         struct ath_btcoex *btcoex = &sc->btcoex;
1496
1497         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1498                   "no stomp timer running \n");
1499
1500         spin_lock_bh(&btcoex->btcoex_lock);
1501
1502         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1503                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1504          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1505                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1506
1507         spin_unlock_bh(&btcoex->btcoex_lock);
1508 }
1509
1510 static int ath_init_btcoex_timer(struct ath_softc *sc)
1511 {
1512         struct ath_btcoex *btcoex = &sc->btcoex;
1513
1514         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1515         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1516                 btcoex->btcoex_period / 100;
1517
1518         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1519                         (unsigned long) sc);
1520
1521         spin_lock_init(&btcoex->btcoex_lock);
1522
1523         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1524                         ath_btcoex_no_stomp_timer,
1525                         ath_btcoex_no_stomp_timer,
1526                         (void *) sc, AR_FIRST_NDP_TIMER);
1527
1528         if (!btcoex->no_stomp_timer)
1529                 return -ENOMEM;
1530
1531         return 0;
1532 }
1533
1534 /*
1535  * Read and write, they both share the same lock. We do this to serialize
1536  * reads and writes on Atheros 802.11n PCI devices only. This is required
1537  * as the FIFO on these devices can only accept sanely 2 requests. After
1538  * that the device goes bananas. Serializing the reads/writes prevents this
1539  * from happening.
1540  */
1541
1542 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1543 {
1544         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1545
1546         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1547                 unsigned long flags;
1548                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1549                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1550                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1551         } else
1552                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1553 }
1554
1555 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1556 {
1557         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1558         u32 val;
1559
1560         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1561                 unsigned long flags;
1562                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1563                 val = ioread32(ah->ah_sc->mem + reg_offset);
1564                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1565         } else
1566                 val = ioread32(ah->ah_sc->mem + reg_offset);
1567         return val;
1568 }
1569
1570 static struct ath_ops ath9k_common_ops = {
1571         .read = ath9k_ioread32,
1572         .write = ath9k_iowrite32,
1573 };
1574
1575 /*
1576  * Initialize and fill ath_softc, ath_sofct is the
1577  * "Software Carrier" struct. Historically it has existed
1578  * to allow the separation between hardware specific
1579  * variables (now in ath_hw) and driver specific variables.
1580  */
1581 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1582 {
1583         struct ath_hw *ah = NULL;
1584         struct ath_common *common;
1585         int r = 0, i;
1586         int csz = 0;
1587         int qnum;
1588
1589         /* XXX: hardware will not be ready until ath_open() being called */
1590         sc->sc_flags |= SC_OP_INVALID;
1591
1592         spin_lock_init(&sc->wiphy_lock);
1593         spin_lock_init(&sc->sc_resetlock);
1594         spin_lock_init(&sc->sc_serial_rw);
1595         spin_lock_init(&sc->ani_lock);
1596         spin_lock_init(&sc->sc_pm_lock);
1597         mutex_init(&sc->mutex);
1598         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1599         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1600                      (unsigned long)sc);
1601
1602         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1603         if (!ah) {
1604                 r = -ENOMEM;
1605                 goto bad_no_ah;
1606         }
1607
1608         ah->ah_sc = sc;
1609         ah->hw_version.devid = devid;
1610         ah->hw_version.subsysid = subsysid;
1611         sc->sc_ah = ah;
1612
1613         common = ath9k_hw_common(ah);
1614         common->ops = &ath9k_common_ops;
1615         common->ah = ah;
1616         common->hw = sc->hw;
1617
1618         /*
1619          * Cache line size is used to size and align various
1620          * structures used to communicate with the hardware.
1621          */
1622         ath_read_cachesize(sc, &csz);
1623         /* XXX assert csz is non-zero */
1624         common->cachelsz = csz << 2;    /* convert to bytes */
1625
1626         if (ath9k_init_debug(ah) < 0)
1627                 dev_err(sc->dev, "Unable to create debugfs files\n");
1628
1629         r = ath9k_hw_init(ah);
1630         if (r) {
1631                 ath_print(common, ATH_DBG_FATAL,
1632                           "Unable to initialize hardware; "
1633                           "initialization status: %d\n", r);
1634                 goto bad;
1635         }
1636
1637         /* Get the hardware key cache size. */
1638         sc->keymax = ah->caps.keycache_size;
1639         if (sc->keymax > ATH_KEYMAX) {
1640                 ath_print(common, ATH_DBG_ANY,
1641                           "Warning, using only %u entries in %u key cache\n",
1642                           ATH_KEYMAX, sc->keymax);
1643                 sc->keymax = ATH_KEYMAX;
1644         }
1645
1646         /*
1647          * Reset the key cache since some parts do not
1648          * reset the contents on initial power up.
1649          */
1650         for (i = 0; i < sc->keymax; i++)
1651                 ath9k_hw_keyreset(ah, (u16) i);
1652
1653         /* default to MONITOR mode */
1654         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1655
1656         /* Setup rate tables */
1657
1658         ath_rate_attach(sc);
1659         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1660         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1661
1662         /*
1663          * Allocate hardware transmit queues: one queue for
1664          * beacon frames and one data queue for each QoS
1665          * priority.  Note that the hal handles reseting
1666          * these queues at the needed time.
1667          */
1668         sc->beacon.beaconq = ath_beaconq_setup(ah);
1669         if (sc->beacon.beaconq == -1) {
1670                 ath_print(common, ATH_DBG_FATAL,
1671                           "Unable to setup a beacon xmit queue\n");
1672                 r = -EIO;
1673                 goto bad2;
1674         }
1675         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1676         if (sc->beacon.cabq == NULL) {
1677                 ath_print(common, ATH_DBG_FATAL,
1678                           "Unable to setup CAB xmit queue\n");
1679                 r = -EIO;
1680                 goto bad2;
1681         }
1682
1683         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1684         ath_cabq_update(sc);
1685
1686         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1687                 sc->tx.hwq_map[i] = -1;
1688
1689         /* Setup data queues */
1690         /* NB: ensure BK queue is the lowest priority h/w queue */
1691         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1692                 ath_print(common, ATH_DBG_FATAL,
1693                           "Unable to setup xmit queue for BK traffic\n");
1694                 r = -EIO;
1695                 goto bad2;
1696         }
1697
1698         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1699                 ath_print(common, ATH_DBG_FATAL,
1700                           "Unable to setup xmit queue for BE traffic\n");
1701                 r = -EIO;
1702                 goto bad2;
1703         }
1704         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1705                 ath_print(common, ATH_DBG_FATAL,
1706                           "Unable to setup xmit queue for VI traffic\n");
1707                 r = -EIO;
1708                 goto bad2;
1709         }
1710         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1711                 ath_print(common, ATH_DBG_FATAL,
1712                           "Unable to setup xmit queue for VO traffic\n");
1713                 r = -EIO;
1714                 goto bad2;
1715         }
1716
1717         /* Initializes the noise floor to a reasonable default value.
1718          * Later on this will be updated during ANI processing. */
1719
1720         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1721         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1722
1723         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1724                                    ATH9K_CIPHER_TKIP, NULL)) {
1725                 /*
1726                  * Whether we should enable h/w TKIP MIC.
1727                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1728                  * report WMM capable, so it's always safe to turn on
1729                  * TKIP MIC in this case.
1730                  */
1731                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1732                                        0, 1, NULL);
1733         }
1734
1735         /*
1736          * Check whether the separate key cache entries
1737          * are required to handle both tx+rx MIC keys.
1738          * With split mic keys the number of stations is limited
1739          * to 27 otherwise 59.
1740          */
1741         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1742                                    ATH9K_CIPHER_TKIP, NULL)
1743             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1744                                       ATH9K_CIPHER_MIC, NULL)
1745             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1746                                       0, NULL))
1747                 sc->splitmic = 1;
1748
1749         /* turn on mcast key search if possible */
1750         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1751                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1752                                              1, NULL);
1753
1754         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1755
1756         /* 11n Capabilities */
1757         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1758                 sc->sc_flags |= SC_OP_TXAGGR;
1759                 sc->sc_flags |= SC_OP_RXAGGR;
1760         }
1761
1762         sc->tx_chainmask = ah->caps.tx_chainmask;
1763         sc->rx_chainmask = ah->caps.rx_chainmask;
1764
1765         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1766         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1767
1768         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1769                 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1770
1771         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1772
1773         /* initialize beacon slots */
1774         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1775                 sc->beacon.bslot[i] = NULL;
1776                 sc->beacon.bslot_aphy[i] = NULL;
1777         }
1778
1779         /* setup channels and rates */
1780
1781         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1782         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1783                 sc->rates[IEEE80211_BAND_2GHZ];
1784         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1785         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1786                 ARRAY_SIZE(ath9k_2ghz_chantable);
1787
1788         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1789                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1790                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1791                         sc->rates[IEEE80211_BAND_5GHZ];
1792                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1793                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1794                         ARRAY_SIZE(ath9k_5ghz_chantable);
1795         }
1796
1797         switch (ah->btcoex_hw.scheme) {
1798         case ATH_BTCOEX_CFG_NONE:
1799                 break;
1800         case ATH_BTCOEX_CFG_2WIRE:
1801                 ath9k_hw_btcoex_init_2wire(ah);
1802                 break;
1803         case ATH_BTCOEX_CFG_3WIRE:
1804                 ath9k_hw_btcoex_init_3wire(ah);
1805                 r = ath_init_btcoex_timer(sc);
1806                 if (r)
1807                         goto bad2;
1808                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1809                 ath9k_hw_init_btcoex_hw(ah, qnum);
1810                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1811                 break;
1812         default:
1813                 WARN_ON(1);
1814                 break;
1815         }
1816
1817         return 0;
1818 bad2:
1819         /* cleanup tx queues */
1820         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1821                 if (ATH_TXQ_SETUP(sc, i))
1822                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1823 bad:
1824         ath9k_hw_detach(ah);
1825 bad_no_ah:
1826         ath9k_exit_debug(sc->sc_ah);
1827         sc->sc_ah = NULL;
1828
1829         return r;
1830 }
1831
1832 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1833 {
1834         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1835                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1836                 IEEE80211_HW_SIGNAL_DBM |
1837                 IEEE80211_HW_AMPDU_AGGREGATION |
1838                 IEEE80211_HW_SUPPORTS_PS |
1839                 IEEE80211_HW_PS_NULLFUNC_STACK |
1840                 IEEE80211_HW_SPECTRUM_MGMT;
1841
1842         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1843                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1844
1845         hw->wiphy->interface_modes =
1846                 BIT(NL80211_IFTYPE_AP) |
1847                 BIT(NL80211_IFTYPE_STATION) |
1848                 BIT(NL80211_IFTYPE_ADHOC) |
1849                 BIT(NL80211_IFTYPE_MESH_POINT);
1850
1851         hw->queues = 4;
1852         hw->max_rates = 4;
1853         hw->channel_change_time = 5000;
1854         hw->max_listen_interval = 10;
1855         /* Hardware supports 10 but we use 4 */
1856         hw->max_rate_tries = 4;
1857         hw->sta_data_size = sizeof(struct ath_node);
1858         hw->vif_data_size = sizeof(struct ath_vif);
1859
1860         hw->rate_control_algorithm = "ath9k_rate_control";
1861
1862         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1863                 &sc->sbands[IEEE80211_BAND_2GHZ];
1864         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1865                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1866                         &sc->sbands[IEEE80211_BAND_5GHZ];
1867 }
1868
1869 /* Device driver core initialization */
1870 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1871 {
1872         struct ieee80211_hw *hw = sc->hw;
1873         struct ath_common *common;
1874         struct ath_hw *ah;
1875         int error = 0, i;
1876         struct ath_regulatory *reg;
1877
1878         dev_dbg(sc->dev, "Attach ATH hw\n");
1879
1880         error = ath_init_softc(devid, sc, subsysid);
1881         if (error != 0)
1882                 return error;
1883
1884         ah = sc->sc_ah;
1885         common = ath9k_hw_common(ah);
1886
1887         /* get mac address from hardware and set in mac80211 */
1888
1889         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1890
1891         ath_set_hw_capab(sc, hw);
1892
1893         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1894                               ath9k_reg_notifier);
1895         if (error)
1896                 return error;
1897
1898         reg = &common->regulatory;
1899
1900         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1901                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1902                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1903                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1904         }
1905
1906         /* initialize tx/rx engine */
1907         error = ath_tx_init(sc, ATH_TXBUF);
1908         if (error != 0)
1909                 goto error_attach;
1910
1911         error = ath_rx_init(sc, ATH_RXBUF);
1912         if (error != 0)
1913                 goto error_attach;
1914
1915         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1916         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1917         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1918
1919         error = ieee80211_register_hw(hw);
1920
1921         if (!ath_is_world_regd(reg)) {
1922                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1923                 if (error)
1924                         goto error_attach;
1925         }
1926
1927         /* Initialize LED control */
1928         ath_init_leds(sc);
1929
1930         ath_start_rfkill_poll(sc);
1931
1932         return 0;
1933
1934 error_attach:
1935         /* cleanup tx queues */
1936         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1937                 if (ATH_TXQ_SETUP(sc, i))
1938                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1939
1940         ath9k_hw_detach(ah);
1941         ath9k_exit_debug(ah);
1942         sc->sc_ah = NULL;
1943
1944         return error;
1945 }
1946
1947 int ath_reset(struct ath_softc *sc, bool retry_tx)
1948 {
1949         struct ath_hw *ah = sc->sc_ah;
1950         struct ath_common *common = ath9k_hw_common(ah);
1951         struct ieee80211_hw *hw = sc->hw;
1952         int r;
1953
1954         ath9k_hw_set_interrupts(ah, 0);
1955         ath_drain_all_txq(sc, retry_tx);
1956         ath_stoprecv(sc);
1957         ath_flushrecv(sc);
1958
1959         spin_lock_bh(&sc->sc_resetlock);
1960         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1961         if (r)
1962                 ath_print(common, ATH_DBG_FATAL,
1963                           "Unable to reset hardware; reset status %d\n", r);
1964         spin_unlock_bh(&sc->sc_resetlock);
1965
1966         if (ath_startrecv(sc) != 0)
1967                 ath_print(common, ATH_DBG_FATAL,
1968                           "Unable to start recv logic\n");
1969
1970         /*
1971          * We may be doing a reset in response to a request
1972          * that changes the channel so update any state that
1973          * might change as a result.
1974          */
1975         ath_cache_conf_rate(sc, &hw->conf);
1976
1977         ath_update_txpow(sc);
1978
1979         if (sc->sc_flags & SC_OP_BEACONS)
1980                 ath_beacon_config(sc, NULL);    /* restart beacons */
1981
1982         ath9k_hw_set_interrupts(ah, sc->imask);
1983
1984         if (retry_tx) {
1985                 int i;
1986                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1987                         if (ATH_TXQ_SETUP(sc, i)) {
1988                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1989                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1990                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1991                         }
1992                 }
1993         }
1994
1995         return r;
1996 }
1997
1998 /*
1999  *  This function will allocate both the DMA descriptor structure, and the
2000  *  buffers it contains.  These are used to contain the descriptors used
2001  *  by the system.
2002 */
2003 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2004                       struct list_head *head, const char *name,
2005                       int nbuf, int ndesc)
2006 {
2007 #define DS2PHYS(_dd, _ds)                                               \
2008         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2009 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2010 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2011         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2012         struct ath_desc *ds;
2013         struct ath_buf *bf;
2014         int i, bsize, error;
2015
2016         ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2017                   name, nbuf, ndesc);
2018
2019         INIT_LIST_HEAD(head);
2020         /* ath_desc must be a multiple of DWORDs */
2021         if ((sizeof(struct ath_desc) % 4) != 0) {
2022                 ath_print(common, ATH_DBG_FATAL,
2023                           "ath_desc not DWORD aligned\n");
2024                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
2025                 error = -ENOMEM;
2026                 goto fail;
2027         }
2028
2029         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2030
2031         /*
2032          * Need additional DMA memory because we can't use
2033          * descriptors that cross the 4K page boundary. Assume
2034          * one skipped descriptor per 4K page.
2035          */
2036         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2037                 u32 ndesc_skipped =
2038                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2039                 u32 dma_len;
2040
2041                 while (ndesc_skipped) {
2042                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
2043                         dd->dd_desc_len += dma_len;
2044
2045                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2046                 };
2047         }
2048
2049         /* allocate descriptors */
2050         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2051                                          &dd->dd_desc_paddr, GFP_KERNEL);
2052         if (dd->dd_desc == NULL) {
2053                 error = -ENOMEM;
2054                 goto fail;
2055         }
2056         ds = dd->dd_desc;
2057         ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2058                   name, ds, (u32) dd->dd_desc_len,
2059                   ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2060
2061         /* allocate buffers */
2062         bsize = sizeof(struct ath_buf) * nbuf;
2063         bf = kzalloc(bsize, GFP_KERNEL);
2064         if (bf == NULL) {
2065                 error = -ENOMEM;
2066                 goto fail2;
2067         }
2068         dd->dd_bufptr = bf;
2069
2070         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2071                 bf->bf_desc = ds;
2072                 bf->bf_daddr = DS2PHYS(dd, ds);
2073
2074                 if (!(sc->sc_ah->caps.hw_caps &
2075                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2076                         /*
2077                          * Skip descriptor addresses which can cause 4KB
2078                          * boundary crossing (addr + length) with a 32 dword
2079                          * descriptor fetch.
2080                          */
2081                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2082                                 ASSERT((caddr_t) bf->bf_desc <
2083                                        ((caddr_t) dd->dd_desc +
2084                                         dd->dd_desc_len));
2085
2086                                 ds += ndesc;
2087                                 bf->bf_desc = ds;
2088                                 bf->bf_daddr = DS2PHYS(dd, ds);
2089                         }
2090                 }
2091                 list_add_tail(&bf->list, head);
2092         }
2093         return 0;
2094 fail2:
2095         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2096                           dd->dd_desc_paddr);
2097 fail:
2098         memset(dd, 0, sizeof(*dd));
2099         return error;
2100 #undef ATH_DESC_4KB_BOUND_CHECK
2101 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2102 #undef DS2PHYS
2103 }
2104
2105 void ath_descdma_cleanup(struct ath_softc *sc,
2106                          struct ath_descdma *dd,
2107                          struct list_head *head)
2108 {
2109         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2110                           dd->dd_desc_paddr);
2111
2112         INIT_LIST_HEAD(head);
2113         kfree(dd->dd_bufptr);
2114         memset(dd, 0, sizeof(*dd));
2115 }
2116
2117 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2118 {
2119         int qnum;
2120
2121         switch (queue) {
2122         case 0:
2123                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2124                 break;
2125         case 1:
2126                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2127                 break;
2128         case 2:
2129                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2130                 break;
2131         case 3:
2132                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2133                 break;
2134         default:
2135                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2136                 break;
2137         }
2138
2139         return qnum;
2140 }
2141
2142 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2143 {
2144         int qnum;
2145
2146         switch (queue) {
2147         case ATH9K_WME_AC_VO:
2148                 qnum = 0;
2149                 break;
2150         case ATH9K_WME_AC_VI:
2151                 qnum = 1;
2152                 break;
2153         case ATH9K_WME_AC_BE:
2154                 qnum = 2;
2155                 break;
2156         case ATH9K_WME_AC_BK:
2157                 qnum = 3;
2158                 break;
2159         default:
2160                 qnum = -1;
2161                 break;
2162         }
2163
2164         return qnum;
2165 }
2166
2167 /* XXX: Remove me once we don't depend on ath9k_channel for all
2168  * this redundant data */
2169 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2170                            struct ath9k_channel *ichan)
2171 {
2172         struct ieee80211_channel *chan = hw->conf.channel;
2173         struct ieee80211_conf *conf = &hw->conf;
2174
2175         ichan->channel = chan->center_freq;
2176         ichan->chan = chan;
2177
2178         if (chan->band == IEEE80211_BAND_2GHZ) {
2179                 ichan->chanmode = CHANNEL_G;
2180                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2181         } else {
2182                 ichan->chanmode = CHANNEL_A;
2183                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2184         }
2185
2186         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2187
2188         if (conf_is_ht(conf)) {
2189                 if (conf_is_ht40(conf))
2190                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2191
2192                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2193                                             conf->channel_type);
2194         }
2195 }
2196
2197 /**********************/
2198 /* mac80211 callbacks */
2199 /**********************/
2200
2201 /*
2202  * (Re)start btcoex timers
2203  */
2204 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2205 {
2206         struct ath_btcoex *btcoex = &sc->btcoex;
2207         struct ath_hw *ah = sc->sc_ah;
2208
2209         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2210                   "Starting btcoex timers");
2211
2212         /* make sure duty cycle timer is also stopped when resuming */
2213         if (btcoex->hw_timer_enabled)
2214                 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2215
2216         btcoex->bt_priority_cnt = 0;
2217         btcoex->bt_priority_time = jiffies;
2218         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2219
2220         mod_timer(&btcoex->period_timer, jiffies);
2221 }
2222
2223 static int ath9k_start(struct ieee80211_hw *hw)
2224 {
2225         struct ath_wiphy *aphy = hw->priv;
2226         struct ath_softc *sc = aphy->sc;
2227         struct ath_hw *ah = sc->sc_ah;
2228         struct ath_common *common = ath9k_hw_common(ah);
2229         struct ieee80211_channel *curchan = hw->conf.channel;
2230         struct ath9k_channel *init_channel;
2231         int r;
2232
2233         ath_print(common, ATH_DBG_CONFIG,
2234                   "Starting driver with initial channel: %d MHz\n",
2235                   curchan->center_freq);
2236
2237         mutex_lock(&sc->mutex);
2238
2239         if (ath9k_wiphy_started(sc)) {
2240                 if (sc->chan_idx == curchan->hw_value) {
2241                         /*
2242                          * Already on the operational channel, the new wiphy
2243                          * can be marked active.
2244                          */
2245                         aphy->state = ATH_WIPHY_ACTIVE;
2246                         ieee80211_wake_queues(hw);
2247                 } else {
2248                         /*
2249                          * Another wiphy is on another channel, start the new
2250                          * wiphy in paused state.
2251                          */
2252                         aphy->state = ATH_WIPHY_PAUSED;
2253                         ieee80211_stop_queues(hw);
2254                 }
2255                 mutex_unlock(&sc->mutex);
2256                 return 0;
2257         }
2258         aphy->state = ATH_WIPHY_ACTIVE;
2259
2260         /* setup initial channel */
2261
2262         sc->chan_idx = curchan->hw_value;
2263
2264         init_channel = ath_get_curchannel(sc, hw);
2265
2266         /* Reset SERDES registers */
2267         ath9k_hw_configpcipowersave(ah, 0, 0);
2268
2269         /*
2270          * The basic interface to setting the hardware in a good
2271          * state is ``reset''.  On return the hardware is known to
2272          * be powered up and with interrupts disabled.  This must
2273          * be followed by initialization of the appropriate bits
2274          * and then setup of the interrupt mask.
2275          */
2276         spin_lock_bh(&sc->sc_resetlock);
2277         r = ath9k_hw_reset(ah, init_channel, false);
2278         if (r) {
2279                 ath_print(common, ATH_DBG_FATAL,
2280                           "Unable to reset hardware; reset status %d "
2281                           "(freq %u MHz)\n", r,
2282                           curchan->center_freq);
2283                 spin_unlock_bh(&sc->sc_resetlock);
2284                 goto mutex_unlock;
2285         }
2286         spin_unlock_bh(&sc->sc_resetlock);
2287
2288         /*
2289          * This is needed only to setup initial state
2290          * but it's best done after a reset.
2291          */
2292         ath_update_txpow(sc);
2293
2294         /*
2295          * Setup the hardware after reset:
2296          * The receive engine is set going.
2297          * Frame transmit is handled entirely
2298          * in the frame output path; there's nothing to do
2299          * here except setup the interrupt mask.
2300          */
2301         if (ath_startrecv(sc) != 0) {
2302                 ath_print(common, ATH_DBG_FATAL,
2303                           "Unable to start recv logic\n");
2304                 r = -EIO;
2305                 goto mutex_unlock;
2306         }
2307
2308         /* Setup our intr mask. */
2309         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2310                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2311                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2312
2313         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2314                 sc->imask |= ATH9K_INT_GTT;
2315
2316         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2317                 sc->imask |= ATH9K_INT_CST;
2318
2319         ath_cache_conf_rate(sc, &hw->conf);
2320
2321         sc->sc_flags &= ~SC_OP_INVALID;
2322
2323         /* Disable BMISS interrupt when we're not associated */
2324         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2325         ath9k_hw_set_interrupts(ah, sc->imask);
2326
2327         ieee80211_wake_queues(hw);
2328
2329         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2330
2331         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2332             !ah->btcoex_hw.enabled) {
2333                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2334                                            AR_STOMP_LOW_WLAN_WGHT);
2335                 ath9k_hw_btcoex_enable(ah);
2336
2337                 if (sc->bus_ops->bt_coex_prep)
2338                         sc->bus_ops->bt_coex_prep(sc);
2339                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2340                         ath9k_btcoex_timer_resume(sc);
2341         }
2342
2343 mutex_unlock:
2344         mutex_unlock(&sc->mutex);
2345
2346         return r;
2347 }
2348
2349 static int ath9k_tx(struct ieee80211_hw *hw,
2350                     struct sk_buff *skb)
2351 {
2352         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2353         struct ath_wiphy *aphy = hw->priv;
2354         struct ath_softc *sc = aphy->sc;
2355         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2356         struct ath_tx_control txctl;
2357         int hdrlen, padsize;
2358
2359         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2360                 ath_print(common, ATH_DBG_XMIT,
2361                           "ath9k: %s: TX in unexpected wiphy state "
2362                           "%d\n", wiphy_name(hw->wiphy), aphy->state);
2363                 goto exit;
2364         }
2365
2366         if (sc->ps_enabled) {
2367                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2368                 /*
2369                  * mac80211 does not set PM field for normal data frames, so we
2370                  * need to update that based on the current PS mode.
2371                  */
2372                 if (ieee80211_is_data(hdr->frame_control) &&
2373                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2374                     !ieee80211_has_pm(hdr->frame_control)) {
2375                         ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2376                                   "while in PS mode\n");
2377                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2378                 }
2379         }
2380
2381         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2382                 /*
2383                  * We are using PS-Poll and mac80211 can request TX while in
2384                  * power save mode. Need to wake up hardware for the TX to be
2385                  * completed and if needed, also for RX of buffered frames.
2386                  */
2387                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2388                 ath9k_ps_wakeup(sc);
2389                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2390                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2391                         ath_print(common, ATH_DBG_PS,
2392                                   "Sending PS-Poll to pick a buffered frame\n");
2393                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2394                 } else {
2395                         ath_print(common, ATH_DBG_PS,
2396                                   "Wake up to complete TX\n");
2397                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2398                 }
2399                 /*
2400                  * The actual restore operation will happen only after
2401                  * the sc_flags bit is cleared. We are just dropping
2402                  * the ps_usecount here.
2403                  */
2404                 ath9k_ps_restore(sc);
2405         }
2406
2407         memset(&txctl, 0, sizeof(struct ath_tx_control));
2408
2409         /*
2410          * As a temporary workaround, assign seq# here; this will likely need
2411          * to be cleaned up to work better with Beacon transmission and virtual
2412          * BSSes.
2413          */
2414         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2415                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2416                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2417                         sc->tx.seq_no += 0x10;
2418                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2419                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2420         }
2421
2422         /* Add the padding after the header if this is not already done */
2423         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2424         if (hdrlen & 3) {
2425                 padsize = hdrlen % 4;
2426                 if (skb_headroom(skb) < padsize)
2427                         return -1;
2428                 skb_push(skb, padsize);
2429                 memmove(skb->data, skb->data + padsize, hdrlen);
2430         }
2431
2432         /* Check if a tx queue is available */
2433
2434         txctl.txq = ath_test_get_txq(sc, skb);
2435         if (!txctl.txq)
2436                 goto exit;
2437
2438         ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2439
2440         if (ath_tx_start(hw, skb, &txctl) != 0) {
2441                 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2442                 goto exit;
2443         }
2444
2445         return 0;
2446 exit:
2447         dev_kfree_skb_any(skb);
2448         return 0;
2449 }
2450
2451 /*
2452  * Pause btcoex timer and bt duty cycle timer
2453  */
2454 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2455 {
2456         struct ath_btcoex *btcoex = &sc->btcoex;
2457         struct ath_hw *ah = sc->sc_ah;
2458
2459         del_timer_sync(&btcoex->period_timer);
2460
2461         if (btcoex->hw_timer_enabled)
2462                 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2463
2464         btcoex->hw_timer_enabled = false;
2465 }
2466
2467 static void ath9k_stop(struct ieee80211_hw *hw)
2468 {
2469         struct ath_wiphy *aphy = hw->priv;
2470         struct ath_softc *sc = aphy->sc;
2471         struct ath_hw *ah = sc->sc_ah;
2472         struct ath_common *common = ath9k_hw_common(ah);
2473
2474         mutex_lock(&sc->mutex);
2475
2476         aphy->state = ATH_WIPHY_INACTIVE;
2477
2478         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2479         cancel_delayed_work_sync(&sc->tx_complete_work);
2480
2481         if (!sc->num_sec_wiphy) {
2482                 cancel_delayed_work_sync(&sc->wiphy_work);
2483                 cancel_work_sync(&sc->chan_work);
2484         }
2485
2486         if (sc->sc_flags & SC_OP_INVALID) {
2487                 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2488                 mutex_unlock(&sc->mutex);
2489                 return;
2490         }
2491
2492         if (ath9k_wiphy_started(sc)) {
2493                 mutex_unlock(&sc->mutex);
2494                 return; /* another wiphy still in use */
2495         }
2496
2497         if (ah->btcoex_hw.enabled) {
2498                 ath9k_hw_btcoex_disable(ah);
2499                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2500                         ath9k_btcoex_timer_pause(sc);
2501         }
2502
2503         /* make sure h/w will not generate any interrupt
2504          * before setting the invalid flag. */
2505         ath9k_hw_set_interrupts(ah, 0);
2506
2507         if (!(sc->sc_flags & SC_OP_INVALID)) {
2508                 ath_drain_all_txq(sc, false);
2509                 ath_stoprecv(sc);
2510                 ath9k_hw_phy_disable(ah);
2511         } else
2512                 sc->rx.rxlink = NULL;
2513
2514         /* disable HAL and put h/w to sleep */
2515         ath9k_hw_disable(ah);
2516         ath9k_hw_configpcipowersave(ah, 1, 1);
2517         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2518
2519         sc->sc_flags |= SC_OP_INVALID;
2520
2521         mutex_unlock(&sc->mutex);
2522
2523         ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2524 }
2525
2526 static int ath9k_add_interface(struct ieee80211_hw *hw,
2527                                struct ieee80211_if_init_conf *conf)
2528 {
2529         struct ath_wiphy *aphy = hw->priv;
2530         struct ath_softc *sc = aphy->sc;
2531         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2532         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2533         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2534         int ret = 0;
2535
2536         mutex_lock(&sc->mutex);
2537
2538         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2539             sc->nvifs > 0) {
2540                 ret = -ENOBUFS;
2541                 goto out;
2542         }
2543
2544         switch (conf->type) {
2545         case NL80211_IFTYPE_STATION:
2546                 ic_opmode = NL80211_IFTYPE_STATION;
2547                 break;
2548         case NL80211_IFTYPE_ADHOC:
2549         case NL80211_IFTYPE_AP:
2550         case NL80211_IFTYPE_MESH_POINT:
2551                 if (sc->nbcnvifs >= ATH_BCBUF) {
2552                         ret = -ENOBUFS;
2553                         goto out;
2554                 }
2555                 ic_opmode = conf->type;
2556                 break;
2557         default:
2558                 ath_print(common, ATH_DBG_FATAL,
2559                         "Interface type %d not yet supported\n", conf->type);
2560                 ret = -EOPNOTSUPP;
2561                 goto out;
2562         }
2563
2564         ath_print(common, ATH_DBG_CONFIG,
2565                   "Attach a VIF of type: %d\n", ic_opmode);
2566
2567         /* Set the VIF opmode */
2568         avp->av_opmode = ic_opmode;
2569         avp->av_bslot = -1;
2570
2571         sc->nvifs++;
2572
2573         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2574                 ath9k_set_bssid_mask(hw);
2575
2576         if (sc->nvifs > 1)
2577                 goto out; /* skip global settings for secondary vif */
2578
2579         if (ic_opmode == NL80211_IFTYPE_AP) {
2580                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2581                 sc->sc_flags |= SC_OP_TSF_RESET;
2582         }
2583
2584         /* Set the device opmode */
2585         sc->sc_ah->opmode = ic_opmode;
2586
2587         /*
2588          * Enable MIB interrupts when there are hardware phy counters.
2589          * Note we only do this (at the moment) for station mode.
2590          */
2591         if ((conf->type == NL80211_IFTYPE_STATION) ||
2592             (conf->type == NL80211_IFTYPE_ADHOC) ||
2593             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2594                 sc->imask |= ATH9K_INT_MIB;
2595                 sc->imask |= ATH9K_INT_TSFOOR;
2596         }
2597
2598         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2599
2600         if (conf->type == NL80211_IFTYPE_AP    ||
2601             conf->type == NL80211_IFTYPE_ADHOC ||
2602             conf->type == NL80211_IFTYPE_MONITOR)
2603                 ath_start_ani(sc);
2604
2605 out:
2606         mutex_unlock(&sc->mutex);
2607         return ret;
2608 }
2609
2610 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2611                                    struct ieee80211_if_init_conf *conf)
2612 {
2613         struct ath_wiphy *aphy = hw->priv;
2614         struct ath_softc *sc = aphy->sc;
2615         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2616         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2617         int i;
2618
2619         ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2620
2621         mutex_lock(&sc->mutex);
2622
2623         /* Stop ANI */
2624         del_timer_sync(&sc->ani.timer);
2625
2626         /* Reclaim beacon resources */
2627         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2628             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2629             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2630                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2631                 ath_beacon_return(sc, avp);
2632         }
2633
2634         sc->sc_flags &= ~SC_OP_BEACONS;
2635
2636         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2637                 if (sc->beacon.bslot[i] == conf->vif) {
2638                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2639                                "slot\n", __func__);
2640                         sc->beacon.bslot[i] = NULL;
2641                         sc->beacon.bslot_aphy[i] = NULL;
2642                 }
2643         }
2644
2645         sc->nvifs--;
2646
2647         mutex_unlock(&sc->mutex);
2648 }
2649
2650 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2651 {
2652         struct ath_wiphy *aphy = hw->priv;
2653         struct ath_softc *sc = aphy->sc;
2654         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2655         struct ieee80211_conf *conf = &hw->conf;
2656         struct ath_hw *ah = sc->sc_ah;
2657         bool all_wiphys_idle = false, disable_radio = false;
2658
2659         mutex_lock(&sc->mutex);
2660
2661         /* Leave this as the first check */
2662         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2663
2664                 spin_lock_bh(&sc->wiphy_lock);
2665                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2666                 spin_unlock_bh(&sc->wiphy_lock);
2667
2668                 if (conf->flags & IEEE80211_CONF_IDLE){
2669                         if (all_wiphys_idle)
2670                                 disable_radio = true;
2671                 }
2672                 else if (all_wiphys_idle) {
2673                         ath_radio_enable(sc);
2674                         ath_print(common, ATH_DBG_CONFIG,
2675                                   "not-idle: enabling radio\n");
2676                 }
2677         }
2678
2679         if (changed & IEEE80211_CONF_CHANGE_PS) {
2680                 if (conf->flags & IEEE80211_CONF_PS) {
2681                         if (!(ah->caps.hw_caps &
2682                               ATH9K_HW_CAP_AUTOSLEEP)) {
2683                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2684                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2685                                         ath9k_hw_set_interrupts(sc->sc_ah,
2686                                                         sc->imask);
2687                                 }
2688                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2689                         }
2690                         sc->ps_enabled = true;
2691                 } else {
2692                         sc->ps_enabled = false;
2693                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2694                         if (!(ah->caps.hw_caps &
2695                               ATH9K_HW_CAP_AUTOSLEEP)) {
2696                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2697                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2698                                                   SC_OP_WAIT_FOR_CAB |
2699                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2700                                                   SC_OP_WAIT_FOR_TX_ACK);
2701                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2702                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2703                                         ath9k_hw_set_interrupts(sc->sc_ah,
2704                                                         sc->imask);
2705                                 }
2706                         }
2707                 }
2708         }
2709
2710         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2711                 struct ieee80211_channel *curchan = hw->conf.channel;
2712                 int pos = curchan->hw_value;
2713
2714                 aphy->chan_idx = pos;
2715                 aphy->chan_is_ht = conf_is_ht(conf);
2716
2717                 if (aphy->state == ATH_WIPHY_SCAN ||
2718                     aphy->state == ATH_WIPHY_ACTIVE)
2719                         ath9k_wiphy_pause_all_forced(sc, aphy);
2720                 else {
2721                         /*
2722                          * Do not change operational channel based on a paused
2723                          * wiphy changes.
2724                          */
2725                         goto skip_chan_change;
2726                 }
2727
2728                 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2729                           curchan->center_freq);
2730
2731                 /* XXX: remove me eventualy */
2732                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2733
2734                 ath_update_chainmask(sc, conf_is_ht(conf));
2735
2736                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2737                         ath_print(common, ATH_DBG_FATAL,
2738                                   "Unable to set channel\n");
2739                         mutex_unlock(&sc->mutex);
2740                         return -EINVAL;
2741                 }
2742         }
2743
2744 skip_chan_change:
2745         if (changed & IEEE80211_CONF_CHANGE_POWER)
2746                 sc->config.txpowlimit = 2 * conf->power_level;
2747
2748         if (disable_radio) {
2749                 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2750                 ath_radio_disable(sc);
2751         }
2752
2753         mutex_unlock(&sc->mutex);
2754
2755         return 0;
2756 }
2757
2758 #define SUPPORTED_FILTERS                       \
2759         (FIF_PROMISC_IN_BSS |                   \
2760         FIF_ALLMULTI |                          \
2761         FIF_CONTROL |                           \
2762         FIF_PSPOLL |                            \
2763         FIF_OTHER_BSS |                         \
2764         FIF_BCN_PRBRESP_PROMISC |               \
2765         FIF_FCSFAIL)
2766
2767 /* FIXME: sc->sc_full_reset ? */
2768 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2769                                    unsigned int changed_flags,
2770                                    unsigned int *total_flags,
2771                                    u64 multicast)
2772 {
2773         struct ath_wiphy *aphy = hw->priv;
2774         struct ath_softc *sc = aphy->sc;
2775         u32 rfilt;
2776
2777         changed_flags &= SUPPORTED_FILTERS;
2778         *total_flags &= SUPPORTED_FILTERS;
2779
2780         sc->rx.rxfilter = *total_flags;
2781         ath9k_ps_wakeup(sc);
2782         rfilt = ath_calcrxfilter(sc);
2783         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2784         ath9k_ps_restore(sc);
2785
2786         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2787                   "Set HW RX filter: 0x%x\n", rfilt);
2788 }
2789
2790 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2791                              struct ieee80211_vif *vif,
2792                              enum sta_notify_cmd cmd,
2793                              struct ieee80211_sta *sta)
2794 {
2795         struct ath_wiphy *aphy = hw->priv;
2796         struct ath_softc *sc = aphy->sc;
2797
2798         switch (cmd) {
2799         case STA_NOTIFY_ADD:
2800                 ath_node_attach(sc, sta);
2801                 break;
2802         case STA_NOTIFY_REMOVE:
2803                 ath_node_detach(sc, sta);
2804                 break;
2805         default:
2806                 break;
2807         }
2808 }
2809
2810 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2811                          const struct ieee80211_tx_queue_params *params)
2812 {
2813         struct ath_wiphy *aphy = hw->priv;
2814         struct ath_softc *sc = aphy->sc;
2815         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2816         struct ath9k_tx_queue_info qi;
2817         int ret = 0, qnum;
2818
2819         if (queue >= WME_NUM_AC)
2820                 return 0;
2821
2822         mutex_lock(&sc->mutex);
2823
2824         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2825
2826         qi.tqi_aifs = params->aifs;
2827         qi.tqi_cwmin = params->cw_min;
2828         qi.tqi_cwmax = params->cw_max;
2829         qi.tqi_burstTime = params->txop;
2830         qnum = ath_get_hal_qnum(queue, sc);
2831
2832         ath_print(common, ATH_DBG_CONFIG,
2833                   "Configure tx [queue/halq] [%d/%d],  "
2834                   "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2835                   queue, qnum, params->aifs, params->cw_min,
2836                   params->cw_max, params->txop);
2837
2838         ret = ath_txq_update(sc, qnum, &qi);
2839         if (ret)
2840                 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2841
2842         mutex_unlock(&sc->mutex);
2843
2844         return ret;
2845 }
2846
2847 static int ath9k_set_key(struct ieee80211_hw *hw,
2848                          enum set_key_cmd cmd,
2849                          struct ieee80211_vif *vif,
2850                          struct ieee80211_sta *sta,
2851                          struct ieee80211_key_conf *key)
2852 {
2853         struct ath_wiphy *aphy = hw->priv;
2854         struct ath_softc *sc = aphy->sc;
2855         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2856         int ret = 0;
2857
2858         if (modparam_nohwcrypt)
2859                 return -ENOSPC;
2860
2861         mutex_lock(&sc->mutex);
2862         ath9k_ps_wakeup(sc);
2863         ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2864
2865         switch (cmd) {
2866         case SET_KEY:
2867                 ret = ath_key_config(sc, vif, sta, key);
2868                 if (ret >= 0) {
2869                         key->hw_key_idx = ret;
2870                         /* push IV and Michael MIC generation to stack */
2871                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2872                         if (key->alg == ALG_TKIP)
2873                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2874                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2875                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2876                         ret = 0;
2877                 }
2878                 break;
2879         case DISABLE_KEY:
2880                 ath_key_delete(sc, key);
2881                 break;
2882         default:
2883                 ret = -EINVAL;
2884         }
2885
2886         ath9k_ps_restore(sc);
2887         mutex_unlock(&sc->mutex);
2888
2889         return ret;
2890 }
2891
2892 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2893                                    struct ieee80211_vif *vif,
2894                                    struct ieee80211_bss_conf *bss_conf,
2895                                    u32 changed)
2896 {
2897         struct ath_wiphy *aphy = hw->priv;
2898         struct ath_softc *sc = aphy->sc;
2899         struct ath_hw *ah = sc->sc_ah;
2900         struct ath_common *common = ath9k_hw_common(ah);
2901         struct ath_vif *avp = (void *)vif->drv_priv;
2902         u32 rfilt = 0;
2903         int error, i;
2904
2905         mutex_lock(&sc->mutex);
2906
2907         /*
2908          * TODO: Need to decide which hw opmode to use for
2909          *       multi-interface cases
2910          * XXX: This belongs into add_interface!
2911          */
2912         if (vif->type == NL80211_IFTYPE_AP &&
2913             ah->opmode != NL80211_IFTYPE_AP) {
2914                 ah->opmode = NL80211_IFTYPE_STATION;
2915                 ath9k_hw_setopmode(ah);
2916                 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2917                 common->curaid = 0;
2918                 ath9k_hw_write_associd(ah);
2919                 /* Request full reset to get hw opmode changed properly */
2920                 sc->sc_flags |= SC_OP_FULL_RESET;
2921         }
2922
2923         if ((changed & BSS_CHANGED_BSSID) &&
2924             !is_zero_ether_addr(bss_conf->bssid)) {
2925                 switch (vif->type) {
2926                 case NL80211_IFTYPE_STATION:
2927                 case NL80211_IFTYPE_ADHOC:
2928                 case NL80211_IFTYPE_MESH_POINT:
2929                         /* Set BSSID */
2930                         memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2931                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2932                         common->curaid = 0;
2933                         ath9k_hw_write_associd(ah);
2934
2935                         /* Set aggregation protection mode parameters */
2936                         sc->config.ath_aggr_prot = 0;
2937
2938                         ath_print(common, ATH_DBG_CONFIG,
2939                                   "RX filter 0x%x bssid %pM aid 0x%x\n",
2940                                   rfilt, common->curbssid, common->curaid);
2941
2942                         /* need to reconfigure the beacon */
2943                         sc->sc_flags &= ~SC_OP_BEACONS ;
2944
2945                         break;
2946                 default:
2947                         break;
2948                 }
2949         }
2950
2951         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2952             (vif->type == NL80211_IFTYPE_AP) ||
2953             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2954                 if ((changed & BSS_CHANGED_BEACON) ||
2955                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2956                      bss_conf->enable_beacon)) {
2957                         /*
2958                          * Allocate and setup the beacon frame.
2959                          *
2960                          * Stop any previous beacon DMA.  This may be
2961                          * necessary, for example, when an ibss merge
2962                          * causes reconfiguration; we may be called
2963                          * with beacon transmission active.
2964                          */
2965                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2966
2967                         error = ath_beacon_alloc(aphy, vif);
2968                         if (!error)
2969                                 ath_beacon_config(sc, vif);
2970                 }
2971         }
2972
2973         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2974         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2975                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2976                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2977                                 ath9k_hw_keysetmac(sc->sc_ah,
2978                                                    (u16)i,
2979                                                    common->curbssid);
2980         }
2981
2982         /* Only legacy IBSS for now */
2983         if (vif->type == NL80211_IFTYPE_ADHOC)
2984                 ath_update_chainmask(sc, 0);
2985
2986         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2987                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2988                           bss_conf->use_short_preamble);
2989                 if (bss_conf->use_short_preamble)
2990                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2991                 else
2992                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2993         }
2994
2995         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2996                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2997                           bss_conf->use_cts_prot);
2998                 if (bss_conf->use_cts_prot &&
2999                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3000                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3001                 else
3002                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3003         }
3004
3005         if (changed & BSS_CHANGED_ASSOC) {
3006                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3007                         bss_conf->assoc);
3008                 ath9k_bss_assoc_info(sc, vif, bss_conf);
3009         }
3010
3011         /*
3012          * The HW TSF has to be reset when the beacon interval changes.
3013          * We set the flag here, and ath_beacon_config_ap() would take this
3014          * into account when it gets called through the subsequent
3015          * config_interface() call - with IFCC_BEACON in the changed field.
3016          */
3017
3018         if (changed & BSS_CHANGED_BEACON_INT) {
3019                 sc->sc_flags |= SC_OP_TSF_RESET;
3020                 sc->beacon_interval = bss_conf->beacon_int;
3021         }
3022
3023         mutex_unlock(&sc->mutex);
3024 }
3025
3026 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3027 {
3028         u64 tsf;
3029         struct ath_wiphy *aphy = hw->priv;
3030         struct ath_softc *sc = aphy->sc;
3031
3032         mutex_lock(&sc->mutex);
3033         tsf = ath9k_hw_gettsf64(sc->sc_ah);
3034         mutex_unlock(&sc->mutex);
3035
3036         return tsf;
3037 }
3038
3039 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3040 {
3041         struct ath_wiphy *aphy = hw->priv;
3042         struct ath_softc *sc = aphy->sc;
3043
3044         mutex_lock(&sc->mutex);
3045         ath9k_hw_settsf64(sc->sc_ah, tsf);
3046         mutex_unlock(&sc->mutex);
3047 }
3048
3049 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3050 {
3051         struct ath_wiphy *aphy = hw->priv;
3052         struct ath_softc *sc = aphy->sc;
3053
3054         mutex_lock(&sc->mutex);
3055
3056         ath9k_ps_wakeup(sc);
3057         ath9k_hw_reset_tsf(sc->sc_ah);
3058         ath9k_ps_restore(sc);
3059
3060         mutex_unlock(&sc->mutex);
3061 }
3062
3063 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3064                               enum ieee80211_ampdu_mlme_action action,
3065                               struct ieee80211_sta *sta,
3066                               u16 tid, u16 *ssn)
3067 {
3068         struct ath_wiphy *aphy = hw->priv;
3069         struct ath_softc *sc = aphy->sc;
3070         int ret = 0;
3071
3072         switch (action) {
3073         case IEEE80211_AMPDU_RX_START:
3074                 if (!(sc->sc_flags & SC_OP_RXAGGR))
3075                         ret = -ENOTSUPP;
3076                 break;
3077         case IEEE80211_AMPDU_RX_STOP:
3078                 break;
3079         case IEEE80211_AMPDU_TX_START:
3080                 ath_tx_aggr_start(sc, sta, tid, ssn);
3081                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3082                 break;
3083         case IEEE80211_AMPDU_TX_STOP:
3084                 ath_tx_aggr_stop(sc, sta, tid);
3085                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3086                 break;
3087         case IEEE80211_AMPDU_TX_OPERATIONAL:
3088                 ath_tx_aggr_resume(sc, sta, tid);
3089                 break;
3090         default:
3091                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3092                           "Unknown AMPDU action\n");
3093         }
3094
3095         return ret;
3096 }
3097
3098 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3099 {
3100         struct ath_wiphy *aphy = hw->priv;
3101         struct ath_softc *sc = aphy->sc;
3102
3103         mutex_lock(&sc->mutex);
3104         if (ath9k_wiphy_scanning(sc)) {
3105                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3106                        "same time\n");
3107                 /*
3108                  * Do not allow the concurrent scanning state for now. This
3109                  * could be improved with scanning control moved into ath9k.
3110                  */
3111                 mutex_unlock(&sc->mutex);
3112                 return;
3113         }
3114
3115         aphy->state = ATH_WIPHY_SCAN;
3116         ath9k_wiphy_pause_all_forced(sc, aphy);
3117
3118         spin_lock_bh(&sc->ani_lock);
3119         sc->sc_flags |= SC_OP_SCANNING;
3120         spin_unlock_bh(&sc->ani_lock);
3121         mutex_unlock(&sc->mutex);
3122 }
3123
3124 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3125 {
3126         struct ath_wiphy *aphy = hw->priv;
3127         struct ath_softc *sc = aphy->sc;
3128
3129         mutex_lock(&sc->mutex);
3130         spin_lock_bh(&sc->ani_lock);
3131         aphy->state = ATH_WIPHY_ACTIVE;
3132         sc->sc_flags &= ~SC_OP_SCANNING;
3133         sc->sc_flags |= SC_OP_FULL_RESET;
3134         spin_unlock_bh(&sc->ani_lock);
3135         ath_beacon_config(sc, NULL);
3136         mutex_unlock(&sc->mutex);
3137 }
3138
3139 struct ieee80211_ops ath9k_ops = {
3140         .tx                 = ath9k_tx,
3141         .start              = ath9k_start,
3142         .stop               = ath9k_stop,
3143         .add_interface      = ath9k_add_interface,
3144         .remove_interface   = ath9k_remove_interface,
3145         .config             = ath9k_config,
3146         .configure_filter   = ath9k_configure_filter,
3147         .sta_notify         = ath9k_sta_notify,
3148         .conf_tx            = ath9k_conf_tx,
3149         .bss_info_changed   = ath9k_bss_info_changed,
3150         .set_key            = ath9k_set_key,
3151         .get_tsf            = ath9k_get_tsf,
3152         .set_tsf            = ath9k_set_tsf,
3153         .reset_tsf          = ath9k_reset_tsf,
3154         .ampdu_action       = ath9k_ampdu_action,
3155         .sw_scan_start      = ath9k_sw_scan_start,
3156         .sw_scan_complete   = ath9k_sw_scan_complete,
3157         .rfkill_poll        = ath9k_rfkill_poll_state,
3158 };
3159
3160 static struct {
3161         u32 version;
3162         const char * name;
3163 } ath_mac_bb_names[] = {
3164         { AR_SREV_VERSION_5416_PCI,     "5416" },
3165         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3166         { AR_SREV_VERSION_9100,         "9100" },
3167         { AR_SREV_VERSION_9160,         "9160" },
3168         { AR_SREV_VERSION_9280,         "9280" },
3169         { AR_SREV_VERSION_9285,         "9285" },
3170         { AR_SREV_VERSION_9287,         "9287" }
3171 };
3172
3173 static struct {
3174         u16 version;
3175         const char * name;
3176 } ath_rf_names[] = {
3177         { 0,                            "5133" },
3178         { AR_RAD5133_SREV_MAJOR,        "5133" },
3179         { AR_RAD5122_SREV_MAJOR,        "5122" },
3180         { AR_RAD2133_SREV_MAJOR,        "2133" },
3181         { AR_RAD2122_SREV_MAJOR,        "2122" }
3182 };
3183
3184 /*
3185  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3186  */
3187 const char *
3188 ath_mac_bb_name(u32 mac_bb_version)
3189 {
3190         int i;
3191
3192         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3193                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3194                         return ath_mac_bb_names[i].name;
3195                 }
3196         }
3197
3198         return "????";
3199 }
3200
3201 /*
3202  * Return the RF name. "????" is returned if the RF is unknown.
3203  */
3204 const char *
3205 ath_rf_name(u16 rf_version)
3206 {
3207         int i;
3208
3209         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3210                 if (ath_rf_names[i].version == rf_version) {
3211                         return ath_rf_names[i].name;
3212                 }
3213         }
3214
3215         return "????";
3216 }
3217
3218 static int __init ath9k_init(void)
3219 {
3220         int error;
3221
3222         /* Register rate control algorithm */
3223         error = ath_rate_control_register();
3224         if (error != 0) {
3225                 printk(KERN_ERR
3226                         "ath9k: Unable to register rate control "
3227                         "algorithm: %d\n",
3228                         error);
3229                 goto err_out;
3230         }
3231
3232         error = ath9k_debug_create_root();
3233         if (error) {
3234                 printk(KERN_ERR
3235                         "ath9k: Unable to create debugfs root: %d\n",
3236                         error);
3237                 goto err_rate_unregister;
3238         }
3239
3240         error = ath_pci_init();
3241         if (error < 0) {
3242                 printk(KERN_ERR
3243                         "ath9k: No PCI devices found, driver not installed.\n");
3244                 error = -ENODEV;
3245                 goto err_remove_root;
3246         }
3247
3248         error = ath_ahb_init();
3249         if (error < 0) {
3250                 error = -ENODEV;
3251                 goto err_pci_exit;
3252         }
3253
3254         return 0;
3255
3256  err_pci_exit:
3257         ath_pci_exit();
3258
3259  err_remove_root:
3260         ath9k_debug_remove_root();
3261  err_rate_unregister:
3262         ath_rate_control_unregister();
3263  err_out:
3264         return error;
3265 }
3266 module_init(ath9k_init);
3267
3268 static void __exit ath9k_exit(void)
3269 {
3270         ath_ahb_exit();
3271         ath_pci_exit();
3272         ath9k_debug_remove_root();
3273         ath_rate_control_unregister();
3274         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3275 }
3276 module_exit(ath9k_exit);