2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
21 MS(ads->ds_rxstatus0, AR_RxRate) : \
22 (ads->ds_rxstatus3 >> 2) & 0xFF)
24 #define set11nTries(_series, _index) \
25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
27 #define set11nRate(_series, _index) \
28 (SM((_series)[_index].Rate, AR_XmitRate##_index))
30 #define set11nPktDurRTSCTS(_series, _index) \
31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
33 AR_RTSCTSQual##_index : 0))
35 #define set11nRateFlags(_series, _index) \
36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
42 #define CCK_SIFS_TIME 10
43 #define CCK_PREAMBLE_BITS 144
44 #define CCK_PLCP_BITS 48
46 #define OFDM_SIFS_TIME 16
47 #define OFDM_PREAMBLE_TIME 20
48 #define OFDM_PLCP_BITS 22
49 #define OFDM_SYMBOL_TIME 4
51 #define OFDM_SIFS_TIME_HALF 32
52 #define OFDM_PREAMBLE_TIME_HALF 40
53 #define OFDM_PLCP_BITS_HALF 22
54 #define OFDM_SYMBOL_TIME_HALF 8
56 #define OFDM_SIFS_TIME_QUARTER 64
57 #define OFDM_PREAMBLE_TIME_QUARTER 80
58 #define OFDM_PLCP_BITS_QUARTER 22
59 #define OFDM_SYMBOL_TIME_QUARTER 16
63 #define INIT_CWMIN_11B 31
64 #define INIT_CWMAX 1023
65 #define INIT_SH_RETRY 10
66 #define INIT_LG_RETRY 10
67 #define INIT_SSH_RETRY 32
68 #define INIT_SLG_RETRY 32
70 #define ATH9K_SLOT_TIME_6 6
71 #define ATH9K_SLOT_TIME_9 9
72 #define ATH9K_SLOT_TIME_20 20
74 #define ATH9K_TXERR_XRETRY 0x01
75 #define ATH9K_TXERR_FILT 0x02
76 #define ATH9K_TXERR_FIFO 0x04
77 #define ATH9K_TXERR_XTXOP 0x08
78 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
79 #define ATH9K_TX_ACKED 0x20
80 #define ATH9K_TXERR_MASK \
81 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
82 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
84 #define ATH9K_TX_BA 0x01
85 #define ATH9K_TX_PWRMGMT 0x02
86 #define ATH9K_TX_DESC_CFG_ERR 0x04
87 #define ATH9K_TX_DATA_UNDERRUN 0x08
88 #define ATH9K_TX_DELIM_UNDERRUN 0x10
89 #define ATH9K_TX_SW_ABORTED 0x40
90 #define ATH9K_TX_SW_FILTERED 0x80
93 #define MIN_TX_FIFO_THRESHOLD 0x1
96 * Single stream device AR9285 and AR9271 require 2 KB
97 * to work around a hardware issue, all other devices
98 * have can use the max 4 KB limit.
100 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
102 struct ath_tx_status {
128 struct ath_rx_status {
153 #define ATH9K_RXERR_CRC 0x01
154 #define ATH9K_RXERR_PHY 0x02
155 #define ATH9K_RXERR_FIFO 0x04
156 #define ATH9K_RXERR_DECRYPT 0x08
157 #define ATH9K_RXERR_MIC 0x10
159 #define ATH9K_RX_MORE 0x01
160 #define ATH9K_RX_MORE_AGGR 0x02
161 #define ATH9K_RX_GI 0x04
162 #define ATH9K_RX_2040 0x08
163 #define ATH9K_RX_DELIM_CRC_PRE 0x10
164 #define ATH9K_RX_DELIM_CRC_POST 0x20
165 #define ATH9K_RX_DECRYPT_BUSY 0x40
167 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
168 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
177 struct ath_tx_status tx;
178 struct ath_rx_status rx;
184 #define ds_txstat ds_us.tx
185 #define ds_rxstat ds_us.rx
186 #define ds_stat ds_us.stats
188 #define ATH9K_TXDESC_CLRDMASK 0x0001
189 #define ATH9K_TXDESC_NOACK 0x0002
190 #define ATH9K_TXDESC_RTSENA 0x0004
191 #define ATH9K_TXDESC_CTSENA 0x0008
192 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
193 * the descriptor its marked on. We take a tx interrupt to reap
194 * descriptors when the h/w hits an EOL condition or
195 * when the descriptor is specifically marked to generate
196 * an interrupt with this flag. Descriptors should be
197 * marked periodically to insure timely replenishing of the
198 * supply needed for sending frames. Defering interrupts
199 * reduces system load and potentially allows more concurrent
200 * work to be done but if done to aggressively can cause
201 * senders to backup. When the hardware queue is left too
202 * large rate control information may also be too out of
203 * date. An Alternative for this is TX interrupt mitigation
204 * but this needs more testing. */
205 #define ATH9K_TXDESC_INTREQ 0x0010
206 #define ATH9K_TXDESC_VEOL 0x0020
207 #define ATH9K_TXDESC_EXT_ONLY 0x0040
208 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
209 #define ATH9K_TXDESC_VMF 0x0100
210 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
211 #define ATH9K_TXDESC_CAB 0x0400
213 #define ATH9K_RXDESC_INTREQ 0x0020
257 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
258 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
260 #define ds_ctl2 u.tx.ctl2
261 #define ds_ctl3 u.tx.ctl3
262 #define ds_ctl4 u.tx.ctl4
263 #define ds_ctl5 u.tx.ctl5
264 #define ds_ctl6 u.tx.ctl6
265 #define ds_ctl7 u.tx.ctl7
266 #define ds_ctl8 u.tx.ctl8
267 #define ds_ctl9 u.tx.ctl9
268 #define ds_ctl10 u.tx.ctl10
269 #define ds_ctl11 u.tx.ctl11
271 #define ds_txstatus0 u.tx.status0
272 #define ds_txstatus1 u.tx.status1
273 #define ds_txstatus2 u.tx.status2
274 #define ds_txstatus3 u.tx.status3
275 #define ds_txstatus4 u.tx.status4
276 #define ds_txstatus5 u.tx.status5
277 #define ds_txstatus6 u.tx.status6
278 #define ds_txstatus7 u.tx.status7
279 #define ds_txstatus8 u.tx.status8
280 #define ds_txstatus9 u.tx.status9
282 #define ds_rxstatus0 u.rx.status0
283 #define ds_rxstatus1 u.rx.status1
284 #define ds_rxstatus2 u.rx.status2
285 #define ds_rxstatus3 u.rx.status3
286 #define ds_rxstatus4 u.rx.status4
287 #define ds_rxstatus5 u.rx.status5
288 #define ds_rxstatus6 u.rx.status6
289 #define ds_rxstatus7 u.rx.status7
290 #define ds_rxstatus8 u.rx.status8
292 #define AR_FrameLen 0x00000fff
293 #define AR_VirtMoreFrag 0x00001000
294 #define AR_TxCtlRsvd00 0x0000e000
295 #define AR_XmitPower 0x003f0000
296 #define AR_XmitPower_S 16
297 #define AR_RTSEnable 0x00400000
298 #define AR_VEOL 0x00800000
299 #define AR_ClrDestMask 0x01000000
300 #define AR_TxCtlRsvd01 0x1e000000
301 #define AR_TxIntrReq 0x20000000
302 #define AR_DestIdxValid 0x40000000
303 #define AR_CTSEnable 0x80000000
305 #define AR_BufLen 0x00000fff
306 #define AR_TxMore 0x00001000
307 #define AR_DestIdx 0x000fe000
308 #define AR_DestIdx_S 13
309 #define AR_FrameType 0x00f00000
310 #define AR_FrameType_S 20
311 #define AR_NoAck 0x01000000
312 #define AR_InsertTS 0x02000000
313 #define AR_CorruptFCS 0x04000000
314 #define AR_ExtOnly 0x08000000
315 #define AR_ExtAndCtl 0x10000000
316 #define AR_MoreAggr 0x20000000
317 #define AR_IsAggr 0x40000000
319 #define AR_BurstDur 0x00007fff
320 #define AR_BurstDur_S 0
321 #define AR_DurUpdateEna 0x00008000
322 #define AR_XmitDataTries0 0x000f0000
323 #define AR_XmitDataTries0_S 16
324 #define AR_XmitDataTries1 0x00f00000
325 #define AR_XmitDataTries1_S 20
326 #define AR_XmitDataTries2 0x0f000000
327 #define AR_XmitDataTries2_S 24
328 #define AR_XmitDataTries3 0xf0000000
329 #define AR_XmitDataTries3_S 28
331 #define AR_XmitRate0 0x000000ff
332 #define AR_XmitRate0_S 0
333 #define AR_XmitRate1 0x0000ff00
334 #define AR_XmitRate1_S 8
335 #define AR_XmitRate2 0x00ff0000
336 #define AR_XmitRate2_S 16
337 #define AR_XmitRate3 0xff000000
338 #define AR_XmitRate3_S 24
340 #define AR_PacketDur0 0x00007fff
341 #define AR_PacketDur0_S 0
342 #define AR_RTSCTSQual0 0x00008000
343 #define AR_PacketDur1 0x7fff0000
344 #define AR_PacketDur1_S 16
345 #define AR_RTSCTSQual1 0x80000000
347 #define AR_PacketDur2 0x00007fff
348 #define AR_PacketDur2_S 0
349 #define AR_RTSCTSQual2 0x00008000
350 #define AR_PacketDur3 0x7fff0000
351 #define AR_PacketDur3_S 16
352 #define AR_RTSCTSQual3 0x80000000
354 #define AR_AggrLen 0x0000ffff
355 #define AR_AggrLen_S 0
356 #define AR_TxCtlRsvd60 0x00030000
357 #define AR_PadDelim 0x03fc0000
358 #define AR_PadDelim_S 18
359 #define AR_EncrType 0x0c000000
360 #define AR_EncrType_S 26
361 #define AR_TxCtlRsvd61 0xf0000000
363 #define AR_2040_0 0x00000001
364 #define AR_GI0 0x00000002
365 #define AR_ChainSel0 0x0000001c
366 #define AR_ChainSel0_S 2
367 #define AR_2040_1 0x00000020
368 #define AR_GI1 0x00000040
369 #define AR_ChainSel1 0x00000380
370 #define AR_ChainSel1_S 7
371 #define AR_2040_2 0x00000400
372 #define AR_GI2 0x00000800
373 #define AR_ChainSel2 0x00007000
374 #define AR_ChainSel2_S 12
375 #define AR_2040_3 0x00008000
376 #define AR_GI3 0x00010000
377 #define AR_ChainSel3 0x000e0000
378 #define AR_ChainSel3_S 17
379 #define AR_RTSCTSRate 0x0ff00000
380 #define AR_RTSCTSRate_S 20
381 #define AR_TxCtlRsvd70 0xf0000000
383 #define AR_TxRSSIAnt00 0x000000ff
384 #define AR_TxRSSIAnt00_S 0
385 #define AR_TxRSSIAnt01 0x0000ff00
386 #define AR_TxRSSIAnt01_S 8
387 #define AR_TxRSSIAnt02 0x00ff0000
388 #define AR_TxRSSIAnt02_S 16
389 #define AR_TxStatusRsvd00 0x3f000000
390 #define AR_TxBaStatus 0x40000000
391 #define AR_TxStatusRsvd01 0x80000000
394 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
395 * transmitted successfully. If clear, no ACK or BA was received to indicate
396 * successful transmission when we were expecting an ACK or BA.
398 #define AR_FrmXmitOK 0x00000001
399 #define AR_ExcessiveRetries 0x00000002
400 #define AR_FIFOUnderrun 0x00000004
401 #define AR_Filtered 0x00000008
402 #define AR_RTSFailCnt 0x000000f0
403 #define AR_RTSFailCnt_S 4
404 #define AR_DataFailCnt 0x00000f00
405 #define AR_DataFailCnt_S 8
406 #define AR_VirtRetryCnt 0x0000f000
407 #define AR_VirtRetryCnt_S 12
408 #define AR_TxDelimUnderrun 0x00010000
409 #define AR_TxDataUnderrun 0x00020000
410 #define AR_DescCfgErr 0x00040000
411 #define AR_TxTimerExpired 0x00080000
412 #define AR_TxStatusRsvd10 0xfff00000
414 #define AR_SendTimestamp ds_txstatus2
415 #define AR_BaBitmapLow ds_txstatus3
416 #define AR_BaBitmapHigh ds_txstatus4
418 #define AR_TxRSSIAnt10 0x000000ff
419 #define AR_TxRSSIAnt10_S 0
420 #define AR_TxRSSIAnt11 0x0000ff00
421 #define AR_TxRSSIAnt11_S 8
422 #define AR_TxRSSIAnt12 0x00ff0000
423 #define AR_TxRSSIAnt12_S 16
424 #define AR_TxRSSICombined 0xff000000
425 #define AR_TxRSSICombined_S 24
427 #define AR_TxEVM0 ds_txstatus5
428 #define AR_TxEVM1 ds_txstatus6
429 #define AR_TxEVM2 ds_txstatus7
431 #define AR_TxDone 0x00000001
432 #define AR_SeqNum 0x00001ffe
433 #define AR_SeqNum_S 1
434 #define AR_TxStatusRsvd80 0x0001e000
435 #define AR_TxOpExceeded 0x00020000
436 #define AR_TxStatusRsvd81 0x001c0000
437 #define AR_FinalTxIdx 0x00600000
438 #define AR_FinalTxIdx_S 21
439 #define AR_TxStatusRsvd82 0x01800000
440 #define AR_PowerMgmt 0x02000000
441 #define AR_TxStatusRsvd83 0xfc000000
443 #define AR_RxCTLRsvd00 0xffffffff
445 #define AR_BufLen 0x00000fff
446 #define AR_RxCtlRsvd00 0x00001000
447 #define AR_RxIntrReq 0x00002000
448 #define AR_RxCtlRsvd01 0xffffc000
450 #define AR_RxRSSIAnt00 0x000000ff
451 #define AR_RxRSSIAnt00_S 0
452 #define AR_RxRSSIAnt01 0x0000ff00
453 #define AR_RxRSSIAnt01_S 8
454 #define AR_RxRSSIAnt02 0x00ff0000
455 #define AR_RxRSSIAnt02_S 16
456 #define AR_RxRate 0xff000000
457 #define AR_RxRate_S 24
458 #define AR_RxStatusRsvd00 0xff000000
460 #define AR_DataLen 0x00000fff
461 #define AR_RxMore 0x00001000
462 #define AR_NumDelim 0x003fc000
463 #define AR_NumDelim_S 14
464 #define AR_RxStatusRsvd10 0xff800000
466 #define AR_RcvTimestamp ds_rxstatus2
468 #define AR_GI 0x00000001
469 #define AR_2040 0x00000002
470 #define AR_Parallel40 0x00000004
471 #define AR_Parallel40_S 2
472 #define AR_RxStatusRsvd30 0x000000f8
473 #define AR_RxAntenna 0xffffff00
474 #define AR_RxAntenna_S 8
476 #define AR_RxRSSIAnt10 0x000000ff
477 #define AR_RxRSSIAnt10_S 0
478 #define AR_RxRSSIAnt11 0x0000ff00
479 #define AR_RxRSSIAnt11_S 8
480 #define AR_RxRSSIAnt12 0x00ff0000
481 #define AR_RxRSSIAnt12_S 16
482 #define AR_RxRSSICombined 0xff000000
483 #define AR_RxRSSICombined_S 24
485 #define AR_RxEVM0 ds_rxstatus4
486 #define AR_RxEVM1 ds_rxstatus5
487 #define AR_RxEVM2 ds_rxstatus6
489 #define AR_RxDone 0x00000001
490 #define AR_RxFrameOK 0x00000002
491 #define AR_CRCErr 0x00000004
492 #define AR_DecryptCRCErr 0x00000008
493 #define AR_PHYErr 0x00000010
494 #define AR_MichaelErr 0x00000020
495 #define AR_PreDelimCRCErr 0x00000040
496 #define AR_RxStatusRsvd70 0x00000080
497 #define AR_RxKeyIdxValid 0x00000100
498 #define AR_KeyIdx 0x0000fe00
499 #define AR_KeyIdx_S 9
500 #define AR_PHYErrCode 0x0000ff00
501 #define AR_PHYErrCode_S 8
502 #define AR_RxMoreAggr 0x00010000
503 #define AR_RxAggr 0x00020000
504 #define AR_PostDelimCRCErr 0x00040000
505 #define AR_RxStatusRsvd71 0x3ff80000
506 #define AR_DecryptBusyErr 0x40000000
507 #define AR_KeyMiss 0x80000000
509 enum ath9k_tx_queue {
510 ATH9K_TX_QUEUE_INACTIVE = 0,
512 ATH9K_TX_QUEUE_BEACON,
514 ATH9K_TX_QUEUE_UAPSD,
515 ATH9K_TX_QUEUE_PSPOLL
518 #define ATH9K_NUM_TX_QUEUES 10
520 enum ath9k_tx_queue_subtype {
528 enum ath9k_tx_queue_flags {
529 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
530 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
531 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
532 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
533 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
534 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
535 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
536 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
537 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
540 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
541 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
543 #define ATH9K_DECOMP_MASK_SIZE 128
544 #define ATH9K_READY_TIME_LO_BOUND 50
545 #define ATH9K_READY_TIME_HI_BOUND 96
547 enum ath9k_pkt_type {
548 ATH9K_PKT_TYPE_NORMAL = 0,
550 ATH9K_PKT_TYPE_PSPOLL,
551 ATH9K_PKT_TYPE_BEACON,
552 ATH9K_PKT_TYPE_PROBE_RESP,
553 ATH9K_PKT_TYPE_CHIRP,
554 ATH9K_PKT_TYPE_GRP_POLL,
557 struct ath9k_tx_queue_info {
559 enum ath9k_tx_queue tqi_type;
560 enum ath9k_tx_queue_subtype tqi_subtype;
561 enum ath9k_tx_queue_flags tqi_qflags;
569 u32 tqi_cbrOverflowLimit;
576 enum ath9k_rx_filter {
577 ATH9K_RX_FILTER_UCAST = 0x00000001,
578 ATH9K_RX_FILTER_MCAST = 0x00000002,
579 ATH9K_RX_FILTER_BCAST = 0x00000004,
580 ATH9K_RX_FILTER_CONTROL = 0x00000008,
581 ATH9K_RX_FILTER_BEACON = 0x00000010,
582 ATH9K_RX_FILTER_PROM = 0x00000020,
583 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
584 ATH9K_RX_FILTER_PHYERR = 0x00000100,
585 ATH9K_RX_FILTER_MYBEACON = 0x00000200,
586 ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
587 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
588 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
589 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
592 #define ATH9K_RATESERIES_RTS_CTS 0x0001
593 #define ATH9K_RATESERIES_2040 0x0002
594 #define ATH9K_RATESERIES_HALFGI 0x0004
596 struct ath9k_11n_rate_series {
604 struct ath9k_keyval {
608 u8 kv_val[16]; /* TK */
609 u8 kv_mic[8]; /* Michael MIC key */
610 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
611 * supports both MIC keys in the same key cache entry;
612 * in that case, kv_mic is the RX key) */
615 enum ath9k_key_type {
616 ATH9K_KEY_TYPE_CLEAR,
623 ATH9K_CIPHER_WEP = 0,
624 ATH9K_CIPHER_AES_OCB = 1,
625 ATH9K_CIPHER_AES_CCM = 2,
626 ATH9K_CIPHER_CKIP = 3,
627 ATH9K_CIPHER_TKIP = 4,
628 ATH9K_CIPHER_CLR = 5,
629 ATH9K_CIPHER_MIC = 127
633 struct ath9k_channel;
635 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
636 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
637 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
638 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
639 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
640 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
641 void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
642 u32 segLen, bool firstSeg,
643 bool lastSeg, const struct ath_desc *ds0);
644 void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
645 int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds);
646 void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
647 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
648 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
649 void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
650 struct ath_desc *lastds,
651 u32 durUpdateEn, u32 rtsctsRate,
653 struct ath9k_11n_rate_series series[],
654 u32 nseries, u32 flags);
655 void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
657 void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
659 void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
660 void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
661 void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
663 void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
665 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
666 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
667 const struct ath9k_tx_queue_info *qinfo);
668 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
669 struct ath9k_tx_queue_info *qinfo);
670 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
671 const struct ath9k_tx_queue_info *qinfo);
672 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
673 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
674 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
675 u32 pa, struct ath_desc *nds, u64 tsf);
676 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
677 u32 size, u32 flags);
678 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
679 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
680 void ath9k_hw_rxena(struct ath_hw *ah);
681 void ath9k_hw_startpcureceive(struct ath_hw *ah);
682 void ath9k_hw_stoppcurecv(struct ath_hw *ah);
683 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
684 int ath9k_hw_beaconq_setup(struct ath_hw *ah);