2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/ath9k_platform.h>
20 #include <linux/module.h>
24 static char *dev_info = "ath9k";
26 MODULE_AUTHOR("Atheros Communications");
27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29 MODULE_LICENSE("Dual BSD/GPL");
31 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
32 module_param_named(debug, ath9k_debug, uint, 0);
33 MODULE_PARM_DESC(debug, "Debugging mask");
35 int ath9k_modparam_nohwcrypt;
36 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
37 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
40 module_param_named(blink, led_blink, int, 0444);
41 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
43 static int ath9k_btcoex_enable;
44 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
45 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
47 bool is_ath9k_unloaded;
48 /* We use the hw_value as an index into our private channel structure */
50 #define CHAN2G(_freq, _idx) { \
51 .band = IEEE80211_BAND_2GHZ, \
52 .center_freq = (_freq), \
57 #define CHAN5G(_freq, _idx) { \
58 .band = IEEE80211_BAND_5GHZ, \
59 .center_freq = (_freq), \
64 /* Some 2 GHz radios are actually tunable on 2312-2732
65 * on 5 MHz steps, we support the channels which we know
66 * we have calibration data for all cards though to make
68 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
69 CHAN2G(2412, 0), /* Channel 1 */
70 CHAN2G(2417, 1), /* Channel 2 */
71 CHAN2G(2422, 2), /* Channel 3 */
72 CHAN2G(2427, 3), /* Channel 4 */
73 CHAN2G(2432, 4), /* Channel 5 */
74 CHAN2G(2437, 5), /* Channel 6 */
75 CHAN2G(2442, 6), /* Channel 7 */
76 CHAN2G(2447, 7), /* Channel 8 */
77 CHAN2G(2452, 8), /* Channel 9 */
78 CHAN2G(2457, 9), /* Channel 10 */
79 CHAN2G(2462, 10), /* Channel 11 */
80 CHAN2G(2467, 11), /* Channel 12 */
81 CHAN2G(2472, 12), /* Channel 13 */
82 CHAN2G(2484, 13), /* Channel 14 */
85 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
86 * on 5 MHz steps, we support the channels which we know
87 * we have calibration data for all cards though to make
89 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
90 /* _We_ call this UNII 1 */
91 CHAN5G(5180, 14), /* Channel 36 */
92 CHAN5G(5200, 15), /* Channel 40 */
93 CHAN5G(5220, 16), /* Channel 44 */
94 CHAN5G(5240, 17), /* Channel 48 */
95 /* _We_ call this UNII 2 */
96 CHAN5G(5260, 18), /* Channel 52 */
97 CHAN5G(5280, 19), /* Channel 56 */
98 CHAN5G(5300, 20), /* Channel 60 */
99 CHAN5G(5320, 21), /* Channel 64 */
100 /* _We_ call this "Middle band" */
101 CHAN5G(5500, 22), /* Channel 100 */
102 CHAN5G(5520, 23), /* Channel 104 */
103 CHAN5G(5540, 24), /* Channel 108 */
104 CHAN5G(5560, 25), /* Channel 112 */
105 CHAN5G(5580, 26), /* Channel 116 */
106 CHAN5G(5600, 27), /* Channel 120 */
107 CHAN5G(5620, 28), /* Channel 124 */
108 CHAN5G(5640, 29), /* Channel 128 */
109 CHAN5G(5660, 30), /* Channel 132 */
110 CHAN5G(5680, 31), /* Channel 136 */
111 CHAN5G(5700, 32), /* Channel 140 */
112 /* _We_ call this UNII 3 */
113 CHAN5G(5745, 33), /* Channel 149 */
114 CHAN5G(5765, 34), /* Channel 153 */
115 CHAN5G(5785, 35), /* Channel 157 */
116 CHAN5G(5805, 36), /* Channel 161 */
117 CHAN5G(5825, 37), /* Channel 165 */
120 /* Atheros hardware rate code addition for short premble */
121 #define SHPCHECK(__hw_rate, __flags) \
122 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
124 #define RATE(_bitrate, _hw_rate, _flags) { \
125 .bitrate = (_bitrate), \
127 .hw_value = (_hw_rate), \
128 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
131 static struct ieee80211_rate ath9k_legacy_rates[] = {
133 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
146 #ifdef CONFIG_MAC80211_LEDS
147 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
148 { .throughput = 0 * 1024, .blink_time = 334 },
149 { .throughput = 1 * 1024, .blink_time = 260 },
150 { .throughput = 5 * 1024, .blink_time = 220 },
151 { .throughput = 10 * 1024, .blink_time = 190 },
152 { .throughput = 20 * 1024, .blink_time = 170 },
153 { .throughput = 50 * 1024, .blink_time = 150 },
154 { .throughput = 70 * 1024, .blink_time = 130 },
155 { .throughput = 100 * 1024, .blink_time = 110 },
156 { .throughput = 200 * 1024, .blink_time = 80 },
157 { .throughput = 300 * 1024, .blink_time = 50 },
161 static void ath9k_deinit_softc(struct ath_softc *sc);
164 * Read and write, they both share the same lock. We do this to serialize
165 * reads and writes on Atheros 802.11n PCI devices only. This is required
166 * as the FIFO on these devices can only accept sanely 2 requests.
169 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
171 struct ath_hw *ah = (struct ath_hw *) hw_priv;
172 struct ath_common *common = ath9k_hw_common(ah);
173 struct ath_softc *sc = (struct ath_softc *) common->priv;
175 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
177 spin_lock_irqsave(&sc->sc_serial_rw, flags);
178 iowrite32(val, sc->mem + reg_offset);
179 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
181 iowrite32(val, sc->mem + reg_offset);
184 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
186 struct ath_hw *ah = (struct ath_hw *) hw_priv;
187 struct ath_common *common = ath9k_hw_common(ah);
188 struct ath_softc *sc = (struct ath_softc *) common->priv;
191 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
193 spin_lock_irqsave(&sc->sc_serial_rw, flags);
194 val = ioread32(sc->mem + reg_offset);
195 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
197 val = ioread32(sc->mem + reg_offset);
201 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
206 val = ioread32(sc->mem + reg_offset);
209 iowrite32(val, sc->mem + reg_offset);
214 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
216 struct ath_hw *ah = (struct ath_hw *) hw_priv;
217 struct ath_common *common = ath9k_hw_common(ah);
218 struct ath_softc *sc = (struct ath_softc *) common->priv;
219 unsigned long uninitialized_var(flags);
222 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
223 spin_lock_irqsave(&sc->sc_serial_rw, flags);
224 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
225 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
227 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
232 /**************************/
234 /**************************/
236 static void setup_ht_cap(struct ath_softc *sc,
237 struct ieee80211_sta_ht_cap *ht_info)
239 struct ath_hw *ah = sc->sc_ah;
240 struct ath_common *common = ath9k_hw_common(ah);
241 u8 tx_streams, rx_streams;
244 ht_info->ht_supported = true;
245 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
246 IEEE80211_HT_CAP_SM_PS |
247 IEEE80211_HT_CAP_SGI_40 |
248 IEEE80211_HT_CAP_DSSSCCK40;
250 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
251 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
253 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
254 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
256 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
257 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
259 if (AR_SREV_9330(ah) || AR_SREV_9485(ah))
261 else if (AR_SREV_9300_20_OR_LATER(ah))
266 if (AR_SREV_9280_20_OR_LATER(ah)) {
267 if (max_streams >= 2)
268 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
269 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
272 /* set up supported mcs set */
273 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
274 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
275 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
277 ath_dbg(common, ATH_DBG_CONFIG,
278 "TX streams %d, RX streams: %d\n",
279 tx_streams, rx_streams);
281 if (tx_streams != rx_streams) {
282 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
283 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
284 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
287 for (i = 0; i < rx_streams; i++)
288 ht_info->mcs.rx_mask[i] = 0xff;
290 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
293 static int ath9k_reg_notifier(struct wiphy *wiphy,
294 struct regulatory_request *request)
296 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
297 struct ath_softc *sc = hw->priv;
298 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
300 return ath_reg_notifier_apply(wiphy, request, reg);
304 * This function will allocate both the DMA descriptor structure, and the
305 * buffers it contains. These are used to contain the descriptors used
308 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
309 struct list_head *head, const char *name,
310 int nbuf, int ndesc, bool is_tx)
312 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
315 int i, bsize, error, desc_len;
317 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
320 INIT_LIST_HEAD(head);
323 desc_len = sc->sc_ah->caps.tx_desc_len;
325 desc_len = sizeof(struct ath_desc);
327 /* ath_desc must be a multiple of DWORDs */
328 if ((desc_len % 4) != 0) {
329 ath_err(common, "ath_desc not DWORD aligned\n");
330 BUG_ON((desc_len % 4) != 0);
335 dd->dd_desc_len = desc_len * nbuf * ndesc;
338 * Need additional DMA memory because we can't use
339 * descriptors that cross the 4K page boundary. Assume
340 * one skipped descriptor per 4K page.
342 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
344 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
347 while (ndesc_skipped) {
348 dma_len = ndesc_skipped * desc_len;
349 dd->dd_desc_len += dma_len;
351 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
355 /* allocate descriptors */
356 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
357 &dd->dd_desc_paddr, GFP_KERNEL);
358 if (dd->dd_desc == NULL) {
362 ds = (u8 *) dd->dd_desc;
363 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
364 name, ds, (u32) dd->dd_desc_len,
365 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
367 /* allocate buffers */
368 bsize = sizeof(struct ath_buf) * nbuf;
369 bf = kzalloc(bsize, GFP_KERNEL);
376 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
378 bf->bf_daddr = DS2PHYS(dd, ds);
380 if (!(sc->sc_ah->caps.hw_caps &
381 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
383 * Skip descriptor addresses which can cause 4KB
384 * boundary crossing (addr + length) with a 32 dword
387 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
388 BUG_ON((caddr_t) bf->bf_desc >=
389 ((caddr_t) dd->dd_desc +
392 ds += (desc_len * ndesc);
394 bf->bf_daddr = DS2PHYS(dd, ds);
397 list_add_tail(&bf->list, head);
401 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
404 memset(dd, 0, sizeof(*dd));
408 static int ath9k_init_btcoex(struct ath_softc *sc)
413 switch (sc->sc_ah->btcoex_hw.scheme) {
414 case ATH_BTCOEX_CFG_NONE:
416 case ATH_BTCOEX_CFG_2WIRE:
417 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
419 case ATH_BTCOEX_CFG_3WIRE:
420 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
421 r = ath_init_btcoex_timer(sc);
424 txq = sc->tx.txq_map[WME_AC_BE];
425 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
426 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
427 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
428 INIT_LIST_HEAD(&sc->btcoex.mci.info);
438 static int ath9k_init_queues(struct ath_softc *sc)
442 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
443 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
445 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
448 for (i = 0; i < WME_NUM_AC; i++) {
449 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
450 sc->tx.txq_map[i]->mac80211_qnum = i;
455 static int ath9k_init_channels_rates(struct ath_softc *sc)
459 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
460 ARRAY_SIZE(ath9k_5ghz_chantable) !=
463 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
464 channels = kmemdup(ath9k_2ghz_chantable,
465 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
469 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
470 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
471 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
472 ARRAY_SIZE(ath9k_2ghz_chantable);
473 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
474 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
475 ARRAY_SIZE(ath9k_legacy_rates);
478 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
479 channels = kmemdup(ath9k_5ghz_chantable,
480 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
482 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
483 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
487 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
488 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
489 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
490 ARRAY_SIZE(ath9k_5ghz_chantable);
491 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
492 ath9k_legacy_rates + 4;
493 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
494 ARRAY_SIZE(ath9k_legacy_rates) - 4;
499 static void ath9k_init_misc(struct ath_softc *sc)
501 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
503 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
505 sc->config.txpowlimit = ATH_TXPOWER_MAX;
507 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
508 sc->sc_flags |= SC_OP_TXAGGR;
509 sc->sc_flags |= SC_OP_RXAGGR;
512 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
514 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
516 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
518 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
519 sc->beacon.bslot[i] = NULL;
521 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
522 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
525 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
526 const struct ath_bus_ops *bus_ops)
528 struct ath9k_platform_data *pdata = sc->dev->platform_data;
529 struct ath_hw *ah = NULL;
530 struct ath_common *common;
534 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
539 ah->hw_version.devid = devid;
540 ah->reg_ops.read = ath9k_ioread32;
541 ah->reg_ops.write = ath9k_iowrite32;
542 ah->reg_ops.rmw = ath9k_reg_rmw;
543 atomic_set(&ah->intr_ref_cnt, -1);
547 ah->ah_flags |= AH_USE_EEPROM;
548 sc->sc_ah->led_pin = -1;
550 sc->sc_ah->gpio_mask = pdata->gpio_mask;
551 sc->sc_ah->gpio_val = pdata->gpio_val;
552 sc->sc_ah->led_pin = pdata->led_pin;
553 ah->is_clk_25mhz = pdata->is_clk_25mhz;
554 ah->get_mac_revision = pdata->get_mac_revision;
555 ah->external_reset = pdata->external_reset;
558 common = ath9k_hw_common(ah);
559 common->ops = &ah->reg_ops;
560 common->bus_ops = bus_ops;
564 common->debug_mask = ath9k_debug;
565 common->btcoex_enabled = ath9k_btcoex_enable == 1;
566 common->disable_ani = false;
567 spin_lock_init(&common->cc_lock);
569 spin_lock_init(&sc->sc_serial_rw);
570 spin_lock_init(&sc->sc_pm_lock);
571 mutex_init(&sc->mutex);
572 #ifdef CONFIG_ATH9K_DEBUGFS
573 spin_lock_init(&sc->nodes_lock);
574 spin_lock_init(&sc->debug.samp_lock);
575 INIT_LIST_HEAD(&sc->nodes);
577 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
578 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
582 * Cache line size is used to size and align various
583 * structures used to communicate with the hardware.
585 ath_read_cachesize(common, &csz);
586 common->cachelsz = csz << 2; /* convert to bytes */
588 /* Initializes the hardware for all supported chipsets */
589 ret = ath9k_hw_init(ah);
593 if (pdata && pdata->macaddr)
594 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
596 ret = ath9k_init_queues(sc);
600 ret = ath9k_init_btcoex(sc);
604 ret = ath9k_init_channels_rates(sc);
608 ath9k_cmn_init_crypto(sc->sc_ah);
614 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
615 if (ATH_TXQ_SETUP(sc, i))
616 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
627 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
629 struct ieee80211_supported_band *sband;
630 struct ieee80211_channel *chan;
631 struct ath_hw *ah = sc->sc_ah;
634 sband = &sc->sbands[band];
635 for (i = 0; i < sband->n_channels; i++) {
636 chan = &sband->channels[i];
637 ah->curchan = &ah->channels[chan->hw_value];
638 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
639 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
643 static void ath9k_init_txpower_limits(struct ath_softc *sc)
645 struct ath_hw *ah = sc->sc_ah;
646 struct ath9k_channel *curchan = ah->curchan;
648 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
649 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
650 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
651 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
653 ah->curchan = curchan;
656 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
658 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
661 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
662 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
663 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
664 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
668 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
670 struct ath_hw *ah = sc->sc_ah;
671 struct ath_common *common = ath9k_hw_common(ah);
673 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
674 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
675 IEEE80211_HW_SIGNAL_DBM |
676 IEEE80211_HW_SUPPORTS_PS |
677 IEEE80211_HW_PS_NULLFUNC_STACK |
678 IEEE80211_HW_SPECTRUM_MGMT |
679 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
681 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
682 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
684 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
685 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
687 hw->wiphy->interface_modes =
688 BIT(NL80211_IFTYPE_P2P_GO) |
689 BIT(NL80211_IFTYPE_P2P_CLIENT) |
690 BIT(NL80211_IFTYPE_AP) |
691 BIT(NL80211_IFTYPE_WDS) |
692 BIT(NL80211_IFTYPE_STATION) |
693 BIT(NL80211_IFTYPE_ADHOC) |
694 BIT(NL80211_IFTYPE_MESH_POINT);
696 if (AR_SREV_5416(sc->sc_ah))
697 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
699 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
700 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
704 hw->channel_change_time = 5000;
705 hw->max_listen_interval = 10;
706 hw->max_rate_tries = 10;
707 hw->sta_data_size = sizeof(struct ath_node);
708 hw->vif_data_size = sizeof(struct ath_vif);
710 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
711 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
713 /* single chain devices with rx diversity */
714 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
715 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
717 sc->ant_rx = hw->wiphy->available_antennas_rx;
718 sc->ant_tx = hw->wiphy->available_antennas_tx;
720 #ifdef CONFIG_ATH9K_RATE_CONTROL
721 hw->rate_control_algorithm = "ath9k_rate_control";
724 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
725 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
726 &sc->sbands[IEEE80211_BAND_2GHZ];
727 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
728 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
729 &sc->sbands[IEEE80211_BAND_5GHZ];
731 ath9k_reload_chainmask_settings(sc);
733 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
736 int ath9k_init_device(u16 devid, struct ath_softc *sc,
737 const struct ath_bus_ops *bus_ops)
739 struct ieee80211_hw *hw = sc->hw;
740 struct ath_common *common;
743 struct ath_regulatory *reg;
745 /* Bring up device */
746 error = ath9k_init_softc(devid, sc, bus_ops);
751 common = ath9k_hw_common(ah);
752 ath9k_set_hw_capab(sc, hw);
754 /* Initialize regulatory */
755 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
760 reg = &common->regulatory;
763 error = ath_tx_init(sc, ATH_TXBUF);
768 error = ath_rx_init(sc, ATH_RXBUF);
772 ath9k_init_txpower_limits(sc);
774 #ifdef CONFIG_MAC80211_LEDS
775 /* must be initialized before ieee80211_register_hw */
776 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
777 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
778 ARRAY_SIZE(ath9k_tpt_blink));
781 /* Register with mac80211 */
782 error = ieee80211_register_hw(hw);
786 error = ath9k_init_debug(ah);
788 ath_err(common, "Unable to create debugfs files\n");
792 /* Handle world regulatory */
793 if (!ath_is_world_regd(reg)) {
794 error = regulatory_hint(hw->wiphy, reg->alpha2);
799 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
800 INIT_WORK(&sc->hw_check_work, ath_hw_check);
801 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
802 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
803 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
806 ath_start_rfkill_poll(sc);
811 ieee80211_unregister_hw(hw);
819 ath9k_deinit_softc(sc);
824 /*****************************/
825 /* De-Initialization */
826 /*****************************/
828 static void ath9k_deinit_softc(struct ath_softc *sc)
832 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
833 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
835 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
836 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
838 if ((sc->btcoex.no_stomp_timer) &&
839 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
840 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
842 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
843 if (ATH_TXQ_SETUP(sc, i))
844 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
846 ath9k_hw_deinit(sc->sc_ah);
852 void ath9k_deinit_device(struct ath_softc *sc)
854 struct ieee80211_hw *hw = sc->hw;
858 wiphy_rfkill_stop_polling(sc->hw->wiphy);
861 ath9k_ps_restore(sc);
863 ieee80211_unregister_hw(hw);
866 ath9k_deinit_softc(sc);
869 void ath_descdma_cleanup(struct ath_softc *sc,
870 struct ath_descdma *dd,
871 struct list_head *head)
873 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
876 INIT_LIST_HEAD(head);
877 kfree(dd->dd_bufptr);
878 memset(dd, 0, sizeof(*dd));
881 /************************/
883 /************************/
885 static int __init ath9k_init(void)
889 /* Register rate control algorithm */
890 error = ath_rate_control_register();
893 "ath9k: Unable to register rate control "
899 error = ath_pci_init();
902 "ath9k: No PCI devices found, driver not installed.\n");
904 goto err_rate_unregister;
907 error = ath_ahb_init();
919 ath_rate_control_unregister();
923 module_init(ath9k_init);
925 static void __exit ath9k_exit(void)
927 is_ath9k_unloaded = true;
930 ath_rate_control_unregister();
931 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
933 module_exit(ath9k_exit);