2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR5416_AR9100_DEVID 0x000b
43 #define AR_SUBVENDOR_ID_NOG 0x0e11
44 #define AR_SUBVENDOR_ID_NEW_A 0x7065
45 #define AR5416_MAGIC 0x19641014
47 #define AR5416_DEVID_AR9287_PCI 0x002D
48 #define AR5416_DEVID_AR9287_PCIE 0x002E
50 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
51 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
52 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
54 /* Register read/write primitives */
55 #define REG_WRITE(_ah, _reg, _val) \
56 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
58 #define REG_READ(_ah, _reg) \
59 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
61 #define SM(_v, _f) (((_v) << _f##_S) & _f)
62 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
63 #define REG_RMW(_a, _r, _set, _clr) \
64 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
65 #define REG_RMW_FIELD(_a, _r, _f, _v) \
67 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
68 #define REG_SET_BIT(_a, _r, _f) \
69 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
70 #define REG_CLR_BIT(_a, _r, _f) \
71 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
73 #define DO_DELAY(x) do { \
74 if ((++(x) % 64) == 0) \
78 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
80 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
81 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
82 INI_RA((iniarray), r, (column))); \
87 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
88 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
89 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
90 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
91 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
92 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
93 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
95 #define AR_GPIOD_MASK 0x00001FFF
96 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
98 #define BASE_ACTIVATE_DELAY 100
99 #define RTC_PLL_SETTLE_DELAY 1000
100 #define COEF_SCALE_S 24
101 #define HT40_CHANNEL_CENTER_SHIFT 10
103 #define ATH9K_ANTENNA0_CHAINMASK 0x1
104 #define ATH9K_ANTENNA1_CHAINMASK 0x2
106 #define ATH9K_NUM_DMA_DEBUG_REGS 8
107 #define ATH9K_NUM_QUEUES 10
109 #define MAX_RATE_POWER 63
110 #define AH_WAIT_TIMEOUT 100000 /* (us) */
111 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
112 #define AH_TIME_QUANTUM 10
113 #define AR_KEYTABLE_SIZE 128
114 #define POWER_UP_TIME 10000
115 #define SPUR_RSSI_THRESH 40
117 #define CAB_TIMEOUT_VAL 10
118 #define BEACON_TIMEOUT_VAL 10
119 #define MIN_BEACON_TIMEOUT_VAL 1
122 #define INIT_CONFIG_STATUS 0x00000000
123 #define INIT_RSSI_THR 0x00000700
124 #define INIT_BCON_CNTRL_REG 0x00000000
126 #define TU_TO_USEC(_tu) ((_tu) << 10)
131 ATH9K_MODE_11NA_HT20,
132 ATH9K_MODE_11NG_HT20,
133 ATH9K_MODE_11NA_HT40PLUS,
134 ATH9K_MODE_11NA_HT40MINUS,
135 ATH9K_MODE_11NG_HT40PLUS,
136 ATH9K_MODE_11NG_HT40MINUS,
140 enum ath9k_ant_setting {
141 ATH9K_ANT_VARIABLE = 0,
147 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
148 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
149 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
150 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
151 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
152 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
153 ATH9K_HW_CAP_VEOL = BIT(6),
154 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
155 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
156 ATH9K_HW_CAP_HT = BIT(9),
157 ATH9K_HW_CAP_GTT = BIT(10),
158 ATH9K_HW_CAP_FASTCC = BIT(11),
159 ATH9K_HW_CAP_RFSILENT = BIT(12),
160 ATH9K_HW_CAP_CST = BIT(13),
161 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
162 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
163 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
166 enum ath9k_capability_type {
167 ATH9K_CAP_CIPHER = 0,
169 ATH9K_CAP_TKIP_SPLIT,
172 ATH9K_CAP_MCAST_KEYSRCH,
176 struct ath9k_hw_capabilities {
177 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
178 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
181 u16 low_5ghz_chan, high_5ghz_chan;
182 u16 low_2ghz_chan, high_2ghz_chan;
186 u16 tx_triglevel_max;
193 struct ath9k_ops_config {
194 int dma_beacon_response_time;
195 int sw_beacon_response_time;
196 int additional_swba_backoff;
198 int cwm_ignore_extcca;
199 u8 pcie_powersave_enable;
209 enum ath9k_ant_setting diversity_control;
210 u16 antenna_switch_swap;
211 int serialize_regmode;
212 bool intr_mitigation;
213 #define SPUR_DISABLE 0
214 #define SPUR_ENABLE_IOCTL 1
215 #define SPUR_ENABLE_EEPROM 2
216 #define AR_EEPROM_MODAL_SPURS 5
217 #define AR_SPUR_5413_1 1640
218 #define AR_SPUR_5413_2 1200
219 #define AR_NO_SPUR 0x8000
220 #define AR_BASE_FREQ_2GHZ 2300
221 #define AR_BASE_FREQ_5GHZ 4900
222 #define AR_SPUR_FEEQ_BOUND_HT40 19
223 #define AR_SPUR_FEEQ_BOUND_HT20 10
225 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
229 ATH9K_INT_RX = 0x00000001,
230 ATH9K_INT_RXDESC = 0x00000002,
231 ATH9K_INT_RXNOFRM = 0x00000008,
232 ATH9K_INT_RXEOL = 0x00000010,
233 ATH9K_INT_RXORN = 0x00000020,
234 ATH9K_INT_TX = 0x00000040,
235 ATH9K_INT_TXDESC = 0x00000080,
236 ATH9K_INT_TIM_TIMER = 0x00000100,
237 ATH9K_INT_TXURN = 0x00000800,
238 ATH9K_INT_MIB = 0x00001000,
239 ATH9K_INT_RXPHY = 0x00004000,
240 ATH9K_INT_RXKCM = 0x00008000,
241 ATH9K_INT_SWBA = 0x00010000,
242 ATH9K_INT_BMISS = 0x00040000,
243 ATH9K_INT_BNR = 0x00100000,
244 ATH9K_INT_TIM = 0x00200000,
245 ATH9K_INT_DTIM = 0x00400000,
246 ATH9K_INT_DTIMSYNC = 0x00800000,
247 ATH9K_INT_GPIO = 0x01000000,
248 ATH9K_INT_CABEND = 0x02000000,
249 ATH9K_INT_TSFOOR = 0x04000000,
250 ATH9K_INT_GENTIMER = 0x08000000,
251 ATH9K_INT_CST = 0x10000000,
252 ATH9K_INT_GTT = 0x20000000,
253 ATH9K_INT_FATAL = 0x40000000,
254 ATH9K_INT_GLOBAL = 0x80000000,
255 ATH9K_INT_BMISC = ATH9K_INT_TIM |
260 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
272 ATH9K_INT_NOCARD = 0xffffffff
275 #define CHANNEL_CW_INT 0x00002
276 #define CHANNEL_CCK 0x00020
277 #define CHANNEL_OFDM 0x00040
278 #define CHANNEL_2GHZ 0x00080
279 #define CHANNEL_5GHZ 0x00100
280 #define CHANNEL_PASSIVE 0x00200
281 #define CHANNEL_DYN 0x00400
282 #define CHANNEL_HALF 0x04000
283 #define CHANNEL_QUARTER 0x08000
284 #define CHANNEL_HT20 0x10000
285 #define CHANNEL_HT40PLUS 0x20000
286 #define CHANNEL_HT40MINUS 0x40000
288 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
289 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
290 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
291 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
292 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
293 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
294 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
295 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
296 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
297 #define CHANNEL_ALL \
306 struct ath9k_channel {
307 struct ieee80211_channel *chan;
312 bool oneTimeCalsDone;
315 int16_t rawNoiseFloor;
318 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
319 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
320 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
321 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
322 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
323 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
324 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
325 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
326 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
327 #define IS_CHAN_A_5MHZ_SPACED(_c) \
328 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
329 (((_c)->channel % 20) != 0) && \
330 (((_c)->channel % 10) != 0))
332 /* These macros check chanmode and not channelFlags */
333 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
334 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
335 ((_c)->chanmode == CHANNEL_G_HT20))
336 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
337 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
338 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
339 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
340 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
342 enum ath9k_power_mode {
345 ATH9K_PM_NETWORK_SLEEP,
349 enum ath9k_tp_scale {
350 ATH9K_TP_SCALE_MAX = 0,
358 SER_REG_MODE_OFF = 0,
360 SER_REG_MODE_AUTO = 2,
363 struct ath9k_beacon_state {
367 #define ATH9K_BEACON_PERIOD 0x0000ffff
368 #define ATH9K_BEACON_ENA 0x00800000
369 #define ATH9K_BEACON_RESET_TSF 0x01000000
370 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
373 u16 bs_cfpmaxduration;
376 u16 bs_bmissthreshold;
377 u32 bs_sleepduration;
378 u32 bs_tsfoor_threshold;
381 struct chan_centers {
388 ATH9K_RESET_POWER_ON,
393 struct ath9k_hw_version {
405 /* Generic TSF timer definitions */
407 #define ATH_MAX_GEN_TIMER 16
409 #define AR_GENTMR_BIT(_index) (1 << (_index))
412 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
413 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
415 #define debruijn32 0x077CB531UL
417 struct ath_gen_timer_configuration {
424 struct ath_gen_timer {
425 void (*trigger)(void *arg);
426 void (*overflow)(void *arg);
431 struct ath_gen_timer_table {
432 u32 gen_timer_index[32];
433 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
435 unsigned long timer_bits;
441 struct ieee80211_hw *hw;
442 struct ath_softc *ah_sc;
443 struct ath_common common;
444 struct ath9k_hw_version hw_version;
445 struct ath9k_ops_config config;
446 struct ath9k_hw_capabilities caps;
447 struct ath9k_channel channels[38];
448 struct ath9k_channel *curchan;
451 struct ar5416_eeprom_def def;
452 struct ar5416_eeprom_4k map4k;
453 struct ar9287_eeprom map9287;
455 const struct eeprom_ops *eep_ops;
456 enum ath9k_eep_map eep_map;
468 enum nl80211_iftype opmode;
469 enum ath9k_power_mode power_mode;
471 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
472 struct ath9k_pacal_info pacal_info;
473 struct ar5416Stats stats;
474 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
476 int16_t curchan_rad_index;
478 u32 txok_interrupt_mask;
479 u32 txerr_interrupt_mask;
480 u32 txdesc_interrupt_mask;
481 u32 txeol_interrupt_mask;
482 u32 txurn_interrupt_mask;
487 enum ath9k_cal_types supp_cals;
488 struct ath9k_cal_list iq_caldata;
489 struct ath9k_cal_list adcgain_caldata;
490 struct ath9k_cal_list adcdc_calinitdata;
491 struct ath9k_cal_list adcdc_caldata;
492 struct ath9k_cal_list *cal_list;
493 struct ath9k_cal_list *cal_list_last;
494 struct ath9k_cal_list *cal_list_curr;
495 #define totalPowerMeasI meas0.unsign
496 #define totalPowerMeasQ meas1.unsign
497 #define totalIqCorrMeas meas2.sign
498 #define totalAdcIOddPhase meas0.unsign
499 #define totalAdcIEvenPhase meas1.unsign
500 #define totalAdcQOddPhase meas2.unsign
501 #define totalAdcQEvenPhase meas3.unsign
502 #define totalAdcDcOffsetIOddPhase meas0.sign
503 #define totalAdcDcOffsetIEvenPhase meas1.sign
504 #define totalAdcDcOffsetQOddPhase meas2.sign
505 #define totalAdcDcOffsetQEvenPhase meas3.sign
507 u32 unsign[AR5416_MAX_CHAINS];
508 int32_t sign[AR5416_MAX_CHAINS];
511 u32 unsign[AR5416_MAX_CHAINS];
512 int32_t sign[AR5416_MAX_CHAINS];
515 u32 unsign[AR5416_MAX_CHAINS];
516 int32_t sign[AR5416_MAX_CHAINS];
519 u32 unsign[AR5416_MAX_CHAINS];
520 int32_t sign[AR5416_MAX_CHAINS];
524 u32 sta_id1_defaults;
530 } enable_32kHz_clock;
533 u32 *analogBank0Data;
534 u32 *analogBank1Data;
535 u32 *analogBank2Data;
536 u32 *analogBank3Data;
537 u32 *analogBank6Data;
538 u32 *analogBank6TPCData;
539 u32 *analogBank7Data;
543 int16_t txpower_indexoffset;
554 struct ar5416AniState *curani;
555 struct ar5416AniState ani[255];
556 int totalSizeDesired[5];
560 enum ath9k_ani_cmd ani_function;
562 /* Bluetooth coexistance */
563 struct ath_btcoex_hw btcoex_hw;
566 enum ath9k_ht_extprotspacing extprotspacing;
570 u32 originalGain[22];
575 struct ar5416IniArray iniModes;
576 struct ar5416IniArray iniCommon;
577 struct ar5416IniArray iniBank0;
578 struct ar5416IniArray iniBB_RfGain;
579 struct ar5416IniArray iniBank1;
580 struct ar5416IniArray iniBank2;
581 struct ar5416IniArray iniBank3;
582 struct ar5416IniArray iniBank6;
583 struct ar5416IniArray iniBank6TPC;
584 struct ar5416IniArray iniBank7;
585 struct ar5416IniArray iniAddac;
586 struct ar5416IniArray iniPcieSerdes;
587 struct ar5416IniArray iniModesAdditional;
588 struct ar5416IniArray iniModesRxGain;
589 struct ar5416IniArray iniModesTxGain;
591 u32 intr_gen_timer_trigger;
592 u32 intr_gen_timer_thresh;
593 struct ath_gen_timer_table hw_gen_timers;
596 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
601 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
603 return &(ath9k_hw_common(ah)->regulatory);
606 /* Initialization, Detach, Reset */
607 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
608 void ath9k_hw_detach(struct ath_hw *ah);
609 int ath9k_hw_init(struct ath_hw *ah);
610 void ath9k_hw_rf_free(struct ath_hw *ah);
611 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
612 bool bChannelChange);
613 void ath9k_hw_fill_cap_info(struct ath_hw *ah);
614 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
615 u32 capability, u32 *result);
616 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
617 u32 capability, u32 setting, int *status);
619 /* Key Cache Management */
620 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
621 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
622 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
623 const struct ath9k_keyval *k,
625 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
627 /* GPIO / RFKILL / Antennae */
628 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
629 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
630 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
632 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
633 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
634 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
635 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
636 enum ath9k_ant_setting settings,
637 struct ath9k_channel *chan,
638 u8 *tx_chainmask, u8 *rx_chainmask,
641 /* General Operation */
642 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
643 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
644 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
645 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
646 const struct ath_rate_table *rates,
647 u32 frameLen, u16 rateix, bool shortPreamble);
648 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
649 struct ath9k_channel *chan,
650 struct chan_centers *centers);
651 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
652 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
653 bool ath9k_hw_phy_disable(struct ath_hw *ah);
654 bool ath9k_hw_disable(struct ath_hw *ah);
655 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
656 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
657 void ath9k_hw_setopmode(struct ath_hw *ah);
658 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
659 void ath9k_hw_setbssidmask(struct ath_hw *ah);
660 void ath9k_hw_write_associd(struct ath_hw *ah);
661 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
662 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
663 void ath9k_hw_reset_tsf(struct ath_hw *ah);
664 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
665 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
666 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
667 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
668 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
669 const struct ath9k_beacon_state *bs);
671 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
673 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
675 /* Interrupt Handling */
676 bool ath9k_hw_intrpend(struct ath_hw *ah);
677 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
678 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
680 /* Generic hw timer primitives */
681 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
682 void (*trigger)(void *),
683 void (*overflow)(void *),
686 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
687 struct ath_gen_timer *timer,
690 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
692 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
693 void ath_gen_timer_isr(struct ath_hw *hw);
694 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
696 #define ATH_PCIE_CAP_LINK_CTRL 0x70
697 #define ATH_PCIE_CAP_LINK_L0S 1
698 #define ATH_PCIE_CAP_LINK_L1 2