2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <asm/unaligned.h>
26 #include "ar9003_mac.h"
27 #include "ar9003_mci.h"
28 #include "ar9003_phy.h"
32 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
41 struct ath_common *common = ath9k_hw_common(ah);
42 struct ath9k_channel *chan = ah->curchan;
43 unsigned int clockrate;
45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 else if (!chan) /* should really check for CCK instead */
49 clockrate = ATH9K_CLOCK_RATE_CCK;
50 else if (IS_CHAN_2GHZ(chan))
51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
58 if (IS_CHAN_HT40(chan))
60 if (IS_CHAN_HALF_RATE(chan))
62 if (IS_CHAN_QUARTER_RATE(chan))
66 common->clockrate = clockrate;
69 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
71 struct ath_common *common = ath9k_hw_common(ah);
73 return usecs * common->clockrate;
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
80 BUG_ON(timeout < AH_TIME_QUANTUM);
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
86 udelay(AH_TIME_QUANTUM);
89 ath_dbg(ath9k_hw_common(ah), ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
95 EXPORT_SYMBOL(ath9k_hw_wait);
97 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
102 if (IS_CHAN_HALF_RATE(chan))
104 else if (IS_CHAN_QUARTER_RATE(chan))
107 udelay(hw_delay + BASE_ACTIVATE_DELAY);
110 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
111 int column, unsigned int *writecnt)
115 ENABLE_REGWRITE_BUFFER(ah);
116 for (r = 0; r < array->ia_rows; r++) {
117 REG_WRITE(ah, INI_RA(array, r, 0),
118 INI_RA(array, r, column));
121 REGWRITE_BUFFER_FLUSH(ah);
124 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
129 for (i = 0, retval = 0; i < n; i++) {
130 retval = (retval << 1) | (val & 1);
136 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
138 u32 frameLen, u16 rateix,
141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
147 case WLAN_RC_PHY_CCK:
148 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
151 numBits = frameLen << 3;
152 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 case WLAN_RC_PHY_OFDM:
155 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_QUARTER
160 + OFDM_PREAMBLE_TIME_QUARTER
161 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
162 } else if (ah->curchan &&
163 IS_CHAN_HALF_RATE(ah->curchan)) {
164 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
165 numBits = OFDM_PLCP_BITS + (frameLen << 3);
166 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
167 txTime = OFDM_SIFS_TIME_HALF +
168 OFDM_PREAMBLE_TIME_HALF
169 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
172 numBits = OFDM_PLCP_BITS + (frameLen << 3);
173 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
174 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
175 + (numSymbols * OFDM_SYMBOL_TIME);
179 ath_err(ath9k_hw_common(ah),
180 "Unknown phy %u (rate ix %u)\n", phy, rateix);
187 EXPORT_SYMBOL(ath9k_hw_computetxtime);
189 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
190 struct ath9k_channel *chan,
191 struct chan_centers *centers)
195 if (!IS_CHAN_HT40(chan)) {
196 centers->ctl_center = centers->ext_center =
197 centers->synth_center = chan->channel;
201 if (IS_CHAN_HT40PLUS(chan)) {
202 centers->synth_center =
203 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
206 centers->synth_center =
207 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
211 centers->ctl_center =
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
213 /* 25 MHz spacing is supported by hw but not on upper layers */
214 centers->ext_center =
215 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
222 static void ath9k_hw_read_revisions(struct ath_hw *ah)
226 switch (ah->hw_version.devid) {
227 case AR5416_AR9100_DEVID:
228 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
230 case AR9300_DEVID_AR9330:
231 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
232 if (ah->get_mac_revision) {
233 ah->hw_version.macRev = ah->get_mac_revision();
235 val = REG_READ(ah, AR_SREV);
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
239 case AR9300_DEVID_AR9340:
240 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
241 val = REG_READ(ah, AR_SREV);
242 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
244 case AR9300_DEVID_QCA955X:
245 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
247 case AR9300_DEVID_AR953X:
248 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
252 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
255 val = REG_READ(ah, AR_SREV);
256 ah->hw_version.macVersion =
257 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
258 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
260 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
261 ah->is_pciexpress = true;
263 ah->is_pciexpress = (val &
264 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
266 if (!AR_SREV_9100(ah))
267 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
269 ah->hw_version.macRev = val & AR_SREV_REVISION;
271 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
272 ah->is_pciexpress = true;
276 /************************************/
277 /* HW Attach, Detach, Init Routines */
278 /************************************/
280 static void ath9k_hw_disablepcie(struct ath_hw *ah)
282 if (!AR_SREV_5416(ah))
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
295 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
298 /* This should work for all families including legacy */
299 static bool ath9k_hw_chip_test(struct ath_hw *ah)
301 struct ath_common *common = ath9k_hw_common(ah);
302 u32 regAddr[2] = { AR_STA_ID0 };
304 static const u32 patternData[4] = {
305 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
309 if (!AR_SREV_9300_20_OR_LATER(ah)) {
311 regAddr[1] = AR_PHY_BASE + (8 << 2);
315 for (i = 0; i < loop_max; i++) {
316 u32 addr = regAddr[i];
319 regHold[i] = REG_READ(ah, addr);
320 for (j = 0; j < 0x100; j++) {
321 wrData = (j << 16) | j;
322 REG_WRITE(ah, addr, wrData);
323 rdData = REG_READ(ah, addr);
324 if (rdData != wrData) {
326 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
327 addr, wrData, rdData);
331 for (j = 0; j < 4; j++) {
332 wrData = patternData[j];
333 REG_WRITE(ah, addr, wrData);
334 rdData = REG_READ(ah, addr);
335 if (wrData != rdData) {
337 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
338 addr, wrData, rdData);
342 REG_WRITE(ah, regAddr[i], regHold[i]);
349 static void ath9k_hw_init_config(struct ath_hw *ah)
351 struct ath_common *common = ath9k_hw_common(ah);
353 ah->config.dma_beacon_response_time = 1;
354 ah->config.sw_beacon_response_time = 6;
355 ah->config.cwm_ignore_extcca = 0;
356 ah->config.analog_shiftreg = 1;
358 ah->config.rx_intr_mitigation = true;
360 if (AR_SREV_9300_20_OR_LATER(ah)) {
361 ah->config.rimt_last = 500;
362 ah->config.rimt_first = 2000;
364 ah->config.rimt_last = 250;
365 ah->config.rimt_first = 700;
369 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
370 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
371 * This means we use it for all AR5416 devices, and the few
372 * minor PCI AR9280 devices out there.
374 * Serialization is required because these devices do not handle
375 * well the case of two concurrent reads/writes due to the latency
376 * involved. During one read/write another read/write can be issued
377 * on another CPU while the previous read/write may still be working
378 * on our hardware, if we hit this case the hardware poops in a loop.
379 * We prevent this by serializing reads and writes.
381 * This issue is not present on PCI-Express devices or pre-AR5416
382 * devices (legacy, 802.11abg).
384 if (num_possible_cpus() > 1)
385 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
387 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
388 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
389 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
390 !ah->is_pciexpress)) {
391 ah->config.serialize_regmode = SER_REG_MODE_ON;
393 ah->config.serialize_regmode = SER_REG_MODE_OFF;
397 ath_dbg(common, RESET, "serialize_regmode is %d\n",
398 ah->config.serialize_regmode);
400 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
401 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
403 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
406 static void ath9k_hw_init_defaults(struct ath_hw *ah)
408 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
410 regulatory->country_code = CTRY_DEFAULT;
411 regulatory->power_limit = MAX_RATE_POWER;
413 ah->hw_version.magic = AR5416_MAGIC;
414 ah->hw_version.subvendorid = 0;
416 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
417 AR_STA_ID1_MCAST_KSRCH;
418 if (AR_SREV_9100(ah))
419 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
421 ah->slottime = ATH9K_SLOT_TIME_9;
422 ah->globaltxtimeout = (u32) -1;
423 ah->power_mode = ATH9K_PM_UNDEFINED;
424 ah->htc_reset_init = true;
426 ah->ani_function = ATH9K_ANI_ALL;
427 if (!AR_SREV_9300_20_OR_LATER(ah))
428 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
430 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
431 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
433 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
436 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
438 struct ath_common *common = ath9k_hw_common(ah);
442 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
445 for (i = 0; i < 3; i++) {
446 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
448 common->macaddr[2 * i] = eeval >> 8;
449 common->macaddr[2 * i + 1] = eeval & 0xff;
451 if (sum == 0 || sum == 0xffff * 3)
452 return -EADDRNOTAVAIL;
457 static int ath9k_hw_post_init(struct ath_hw *ah)
459 struct ath_common *common = ath9k_hw_common(ah);
462 if (common->bus_ops->ath_bus_type != ATH_USB) {
463 if (!ath9k_hw_chip_test(ah))
467 if (!AR_SREV_9300_20_OR_LATER(ah)) {
468 ecode = ar9002_hw_rf_claim(ah);
473 ecode = ath9k_hw_eeprom_init(ah);
477 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
478 ah->eep_ops->get_eeprom_ver(ah),
479 ah->eep_ops->get_eeprom_rev(ah));
481 ath9k_hw_ani_init(ah);
484 * EEPROM needs to be initialized before we do this.
485 * This is required for regulatory compliance.
487 if (AR_SREV_9300_20_OR_LATER(ah)) {
488 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
489 if ((regdmn & 0xF0) == CTL_FCC) {
490 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
491 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
498 static int ath9k_hw_attach_ops(struct ath_hw *ah)
500 if (!AR_SREV_9300_20_OR_LATER(ah))
501 return ar9002_hw_attach_ops(ah);
503 ar9003_hw_attach_ops(ah);
507 /* Called for all hardware families */
508 static int __ath9k_hw_init(struct ath_hw *ah)
510 struct ath_common *common = ath9k_hw_common(ah);
513 ath9k_hw_read_revisions(ah);
515 switch (ah->hw_version.macVersion) {
516 case AR_SREV_VERSION_5416_PCI:
517 case AR_SREV_VERSION_5416_PCIE:
518 case AR_SREV_VERSION_9160:
519 case AR_SREV_VERSION_9100:
520 case AR_SREV_VERSION_9280:
521 case AR_SREV_VERSION_9285:
522 case AR_SREV_VERSION_9287:
523 case AR_SREV_VERSION_9271:
524 case AR_SREV_VERSION_9300:
525 case AR_SREV_VERSION_9330:
526 case AR_SREV_VERSION_9485:
527 case AR_SREV_VERSION_9340:
528 case AR_SREV_VERSION_9462:
529 case AR_SREV_VERSION_9550:
530 case AR_SREV_VERSION_9565:
531 case AR_SREV_VERSION_9531:
535 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
536 ah->hw_version.macVersion, ah->hw_version.macRev);
541 * Read back AR_WA into a permanent copy and set bits 14 and 17.
542 * We need to do this to avoid RMW of this register. We cannot
543 * read the reg when chip is asleep.
545 if (AR_SREV_9300_20_OR_LATER(ah)) {
546 ah->WARegVal = REG_READ(ah, AR_WA);
547 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
548 AR_WA_ASPM_TIMER_BASED_DISABLE);
551 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
552 ath_err(common, "Couldn't reset chip\n");
556 if (AR_SREV_9565(ah)) {
557 ah->WARegVal |= AR_WA_BIT22;
558 REG_WRITE(ah, AR_WA, ah->WARegVal);
561 ath9k_hw_init_defaults(ah);
562 ath9k_hw_init_config(ah);
564 r = ath9k_hw_attach_ops(ah);
568 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
569 ath_err(common, "Couldn't wakeup chip\n");
573 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
574 AR_SREV_9330(ah) || AR_SREV_9550(ah))
575 ah->is_pciexpress = false;
577 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
578 ath9k_hw_init_cal_settings(ah);
580 if (!ah->is_pciexpress)
581 ath9k_hw_disablepcie(ah);
583 r = ath9k_hw_post_init(ah);
587 ath9k_hw_init_mode_gain_regs(ah);
588 r = ath9k_hw_fill_cap_info(ah);
592 r = ath9k_hw_init_macaddr(ah);
594 ath_err(common, "Failed to initialize MAC address\n");
598 ath9k_hw_init_hang_checks(ah);
600 common->state = ATH_HW_INITIALIZED;
605 int ath9k_hw_init(struct ath_hw *ah)
608 struct ath_common *common = ath9k_hw_common(ah);
610 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
611 switch (ah->hw_version.devid) {
612 case AR5416_DEVID_PCI:
613 case AR5416_DEVID_PCIE:
614 case AR5416_AR9100_DEVID:
615 case AR9160_DEVID_PCI:
616 case AR9280_DEVID_PCI:
617 case AR9280_DEVID_PCIE:
618 case AR9285_DEVID_PCIE:
619 case AR9287_DEVID_PCI:
620 case AR9287_DEVID_PCIE:
621 case AR2427_DEVID_PCIE:
622 case AR9300_DEVID_PCIE:
623 case AR9300_DEVID_AR9485_PCIE:
624 case AR9300_DEVID_AR9330:
625 case AR9300_DEVID_AR9340:
626 case AR9300_DEVID_QCA955X:
627 case AR9300_DEVID_AR9580:
628 case AR9300_DEVID_AR9462:
629 case AR9485_DEVID_AR1111:
630 case AR9300_DEVID_AR9565:
631 case AR9300_DEVID_AR953X:
634 if (common->bus_ops->ath_bus_type == ATH_USB)
636 ath_err(common, "Hardware device ID 0x%04x not supported\n",
637 ah->hw_version.devid);
641 ret = __ath9k_hw_init(ah);
644 "Unable to initialize hardware; initialization status: %d\n",
651 EXPORT_SYMBOL(ath9k_hw_init);
653 static void ath9k_hw_init_qos(struct ath_hw *ah)
655 ENABLE_REGWRITE_BUFFER(ah);
657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
660 REG_WRITE(ah, AR_QOS_NO_ACK,
661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
671 REGWRITE_BUFFER_FLUSH(ah);
674 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
676 struct ath_common *common = ath9k_hw_common(ah);
679 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
683 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
687 if (WARN_ON_ONCE(i >= 100)) {
688 ath_err(common, "PLL4 meaurement not done\n");
695 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
697 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
699 static void ath9k_hw_init_pll(struct ath_hw *ah,
700 struct ath9k_channel *chan)
704 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
705 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
707 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
709 AR_CH0_DPLL2_KD, 0x40);
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
711 AR_CH0_DPLL2_KI, 0x4);
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
714 AR_CH0_BB_DPLL1_REFDIV, 0x5);
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
716 AR_CH0_BB_DPLL1_NINI, 0x58);
717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
718 AR_CH0_BB_DPLL1_NFRAC, 0x0);
720 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
721 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
725 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
727 /* program BB PLL phase_shift to 0x6 */
728 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
729 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
732 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
734 } else if (AR_SREV_9330(ah)) {
735 u32 ddr_dpll2, pll_control2, kd;
737 if (ah->is_clk_25mhz) {
738 ddr_dpll2 = 0x18e82f01;
739 pll_control2 = 0xe04a3d;
742 ddr_dpll2 = 0x19e82f01;
743 pll_control2 = 0x886666;
747 /* program DDR PLL ki and kd value */
748 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
750 /* program DDR PLL phase_shift */
751 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
752 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
754 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
757 /* program refdiv, nint, frac to RTC register */
758 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
760 /* program BB PLL kd and ki value */
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
764 /* program BB PLL phase_shift */
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
766 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
767 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
768 u32 regval, pll2_divint, pll2_divfrac, refdiv;
770 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
773 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
776 if (ah->is_clk_25mhz) {
777 if (AR_SREV_9531(ah)) {
779 pll2_divfrac = 0xa3d2;
783 pll2_divfrac = 0x1eb85;
787 if (AR_SREV_9340(ah)) {
793 pll2_divfrac = 0x26666;
798 regval = REG_READ(ah, AR_PHY_PLL_MODE);
799 if (AR_SREV_9531(ah))
800 regval |= (0x1 << 22);
802 regval |= (0x1 << 16);
803 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
806 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
807 (pll2_divint << 18) | pll2_divfrac);
810 regval = REG_READ(ah, AR_PHY_PLL_MODE);
811 if (AR_SREV_9340(ah))
812 regval = (regval & 0x80071fff) |
817 else if (AR_SREV_9531(ah))
818 regval = (regval & 0x01c00fff) |
825 regval = (regval & 0x80071fff) |
830 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
832 if (AR_SREV_9531(ah))
833 REG_WRITE(ah, AR_PHY_PLL_MODE,
834 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
836 REG_WRITE(ah, AR_PHY_PLL_MODE,
837 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
842 pll = ath9k_hw_compute_pll_control(ah, chan);
843 if (AR_SREV_9565(ah))
845 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
847 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
851 /* Switch the core clock for ar9271 to 117Mhz */
852 if (AR_SREV_9271(ah)) {
854 REG_WRITE(ah, 0x50040, 0x304);
857 udelay(RTC_PLL_SETTLE_DELAY);
859 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
861 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
862 if (ah->is_clk_25mhz) {
863 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
864 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
865 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
867 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
868 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
869 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
875 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
876 enum nl80211_iftype opmode)
878 u32 sync_default = AR_INTR_SYNC_DEFAULT;
879 u32 imr_reg = AR_IMR_TXERR |
885 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
886 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
888 if (AR_SREV_9300_20_OR_LATER(ah)) {
889 imr_reg |= AR_IMR_RXOK_HP;
890 if (ah->config.rx_intr_mitigation)
891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
893 imr_reg |= AR_IMR_RXOK_LP;
896 if (ah->config.rx_intr_mitigation)
897 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
899 imr_reg |= AR_IMR_RXOK;
902 if (ah->config.tx_intr_mitigation)
903 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
905 imr_reg |= AR_IMR_TXOK;
907 ENABLE_REGWRITE_BUFFER(ah);
909 REG_WRITE(ah, AR_IMR, imr_reg);
910 ah->imrs2_reg |= AR_IMR_S2_GTT;
911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
913 if (!AR_SREV_9100(ah)) {
914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
919 REGWRITE_BUFFER_FLUSH(ah);
921 if (AR_SREV_9300_20_OR_LATER(ah)) {
922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
929 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
932 val = min(val, (u32) 0xFFFF);
933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
936 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) 0xFFFF);
940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
943 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
945 u32 val = ath9k_hw_mac_to_clks(ah, us);
946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
950 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
952 u32 val = ath9k_hw_mac_to_clks(ah, us);
953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
957 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
962 ah->globaltxtimeout = (u32) -1;
965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
966 ah->globaltxtimeout = tu;
971 void ath9k_hw_init_global_settings(struct ath_hw *ah)
973 struct ath_common *common = ath9k_hw_common(ah);
974 const struct ath9k_channel *chan = ah->curchan;
975 int acktimeout, ctstimeout, ack_offset = 0;
978 int rx_lat = 0, tx_lat = 0, eifs = 0;
981 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
987 if (ah->misc_mode != 0)
988 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
990 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
996 if (IS_CHAN_5GHZ(chan))
1001 if (IS_CHAN_HALF_RATE(chan)) {
1005 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1011 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1013 rx_lat = (rx_lat * 4) - 1;
1015 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1022 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1023 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1024 reg = AR_USEC_ASYNC_FIFO;
1026 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1028 reg = REG_READ(ah, AR_USEC);
1030 rx_lat = MS(reg, AR_USEC_RX_LAT);
1031 tx_lat = MS(reg, AR_USEC_TX_LAT);
1033 slottime = ah->slottime;
1036 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1037 slottime += 3 * ah->coverage_class;
1038 acktimeout = slottime + sifstime + ack_offset;
1039 ctstimeout = acktimeout;
1042 * Workaround for early ACK timeouts, add an offset to match the
1043 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1044 * This was initially only meant to work around an issue with delayed
1045 * BA frames in some implementations, but it has been found to fix ACK
1046 * timeout issues in other cases as well.
1048 if (IS_CHAN_2GHZ(chan) &&
1049 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1050 acktimeout += 64 - sifstime - ah->slottime;
1051 ctstimeout += 48 - sifstime - ah->slottime;
1054 ath9k_hw_set_sifs_time(ah, sifstime);
1055 ath9k_hw_setslottime(ah, slottime);
1056 ath9k_hw_set_ack_timeout(ah, acktimeout);
1057 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1058 if (ah->globaltxtimeout != (u32) -1)
1059 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1061 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1062 REG_RMW(ah, AR_USEC,
1063 (common->clockrate - 1) |
1064 SM(rx_lat, AR_USEC_RX_LAT) |
1065 SM(tx_lat, AR_USEC_TX_LAT),
1066 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1069 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1071 void ath9k_hw_deinit(struct ath_hw *ah)
1073 struct ath_common *common = ath9k_hw_common(ah);
1075 if (common->state < ATH_HW_INITIALIZED)
1078 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1080 EXPORT_SYMBOL(ath9k_hw_deinit);
1086 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1088 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1090 if (IS_CHAN_2GHZ(chan))
1098 /****************************************/
1099 /* Reset and Channel Switching Routines */
1100 /****************************************/
1102 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1104 struct ath_common *common = ath9k_hw_common(ah);
1107 ENABLE_REGWRITE_BUFFER(ah);
1110 * set AHB_MODE not to do cacheline prefetches
1112 if (!AR_SREV_9300_20_OR_LATER(ah))
1113 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1116 * let mac dma reads be in 128 byte chunks
1118 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1120 REGWRITE_BUFFER_FLUSH(ah);
1123 * Restore TX Trigger Level to its pre-reset value.
1124 * The initial value depends on whether aggregation is enabled, and is
1125 * adjusted whenever underruns are detected.
1127 if (!AR_SREV_9300_20_OR_LATER(ah))
1128 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1130 ENABLE_REGWRITE_BUFFER(ah);
1133 * let mac dma writes be in 128 byte chunks
1135 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1138 * Setup receive FIFO threshold to hold off TX activities
1140 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1142 if (AR_SREV_9300_20_OR_LATER(ah)) {
1143 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1146 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1147 ah->caps.rx_status_len);
1151 * reduce the number of usable entries in PCU TXBUF to avoid
1152 * wrap around issues.
1154 if (AR_SREV_9285(ah)) {
1155 /* For AR9285 the number of Fifos are reduced to half.
1156 * So set the usable tx buf size also to half to
1157 * avoid data/delimiter underruns
1159 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1160 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1161 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1162 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1164 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1167 if (!AR_SREV_9271(ah))
1168 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1170 REGWRITE_BUFFER_FLUSH(ah);
1172 if (AR_SREV_9300_20_OR_LATER(ah))
1173 ath9k_hw_reset_txstatus_ring(ah);
1176 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1178 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1179 u32 set = AR_STA_ID1_KSRCH_MODE;
1182 case NL80211_IFTYPE_ADHOC:
1183 set |= AR_STA_ID1_ADHOC;
1184 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1186 case NL80211_IFTYPE_MESH_POINT:
1187 case NL80211_IFTYPE_AP:
1188 set |= AR_STA_ID1_STA_AP;
1190 case NL80211_IFTYPE_STATION:
1191 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1194 if (!ah->is_monitoring)
1198 REG_RMW(ah, AR_STA_ID1, set, mask);
1201 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1202 u32 *coef_mantissa, u32 *coef_exponent)
1204 u32 coef_exp, coef_man;
1206 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1207 if ((coef_scaled >> coef_exp) & 0x1)
1210 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1212 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1214 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1215 *coef_exponent = coef_exp - 16;
1219 * call external reset function to reset WMAC if:
1220 * - doing a cold reset
1221 * - we have pending frames in the TX queues.
1223 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1227 for (i = 0; i < AR_NUM_QCU; i++) {
1228 npend = ath9k_hw_numtxpending(ah, i);
1233 if (ah->external_reset &&
1234 (npend || type == ATH9K_RESET_COLD)) {
1237 ath_dbg(ath9k_hw_common(ah), RESET,
1238 "reset MAC via external reset\n");
1240 reset_err = ah->external_reset();
1242 ath_err(ath9k_hw_common(ah),
1243 "External reset failed, err=%d\n",
1248 REG_WRITE(ah, AR_RTC_RESET, 1);
1254 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1259 if (AR_SREV_9100(ah)) {
1260 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1261 AR_RTC_DERIVED_CLK_PERIOD, 1);
1262 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1265 ENABLE_REGWRITE_BUFFER(ah);
1267 if (AR_SREV_9300_20_OR_LATER(ah)) {
1268 REG_WRITE(ah, AR_WA, ah->WARegVal);
1272 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1273 AR_RTC_FORCE_WAKE_ON_INT);
1275 if (AR_SREV_9100(ah)) {
1276 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1277 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1279 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1280 if (AR_SREV_9340(ah))
1281 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1283 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1284 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1288 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1291 if (!AR_SREV_9300_20_OR_LATER(ah))
1293 REG_WRITE(ah, AR_RC, val);
1295 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1296 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1298 rst_flags = AR_RTC_RC_MAC_WARM;
1299 if (type == ATH9K_RESET_COLD)
1300 rst_flags |= AR_RTC_RC_MAC_COLD;
1303 if (AR_SREV_9330(ah)) {
1304 if (!ath9k_hw_ar9330_reset_war(ah, type))
1308 if (ath9k_hw_mci_is_enabled(ah))
1309 ar9003_mci_check_gpm_offset(ah);
1311 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1313 REGWRITE_BUFFER_FLUSH(ah);
1315 if (AR_SREV_9300_20_OR_LATER(ah))
1317 else if (AR_SREV_9100(ah))
1322 REG_WRITE(ah, AR_RTC_RC, 0);
1323 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1324 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1328 if (!AR_SREV_9100(ah))
1329 REG_WRITE(ah, AR_RC, 0);
1331 if (AR_SREV_9100(ah))
1337 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1339 ENABLE_REGWRITE_BUFFER(ah);
1341 if (AR_SREV_9300_20_OR_LATER(ah)) {
1342 REG_WRITE(ah, AR_WA, ah->WARegVal);
1346 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1347 AR_RTC_FORCE_WAKE_ON_INT);
1349 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1350 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1352 REG_WRITE(ah, AR_RTC_RESET, 0);
1354 REGWRITE_BUFFER_FLUSH(ah);
1358 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1359 REG_WRITE(ah, AR_RC, 0);
1361 REG_WRITE(ah, AR_RTC_RESET, 1);
1363 if (!ath9k_hw_wait(ah,
1368 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1372 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1375 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1379 if (AR_SREV_9300_20_OR_LATER(ah)) {
1380 REG_WRITE(ah, AR_WA, ah->WARegVal);
1384 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1385 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1387 if (!ah->reset_power_on)
1388 type = ATH9K_RESET_POWER_ON;
1391 case ATH9K_RESET_POWER_ON:
1392 ret = ath9k_hw_set_reset_power_on(ah);
1394 ah->reset_power_on = true;
1396 case ATH9K_RESET_WARM:
1397 case ATH9K_RESET_COLD:
1398 ret = ath9k_hw_set_reset(ah, type);
1407 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1408 struct ath9k_channel *chan)
1410 int reset_type = ATH9K_RESET_WARM;
1412 if (AR_SREV_9280(ah)) {
1413 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1414 reset_type = ATH9K_RESET_POWER_ON;
1416 reset_type = ATH9K_RESET_COLD;
1417 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1418 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1419 reset_type = ATH9K_RESET_COLD;
1421 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1424 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1427 ah->chip_fullsleep = false;
1429 if (AR_SREV_9330(ah))
1430 ar9003_hw_internal_regulator_apply(ah);
1431 ath9k_hw_init_pll(ah, chan);
1436 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1437 struct ath9k_channel *chan)
1439 struct ath_common *common = ath9k_hw_common(ah);
1440 struct ath9k_hw_capabilities *pCap = &ah->caps;
1441 bool band_switch = false, mode_diff = false;
1442 u8 ini_reloaded = 0;
1446 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1447 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1448 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1449 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1452 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1453 if (ath9k_hw_numtxpending(ah, qnum)) {
1454 ath_dbg(common, QUEUE,
1455 "Transmit frames pending on queue %d\n", qnum);
1460 if (!ath9k_hw_rfbus_req(ah)) {
1461 ath_err(common, "Could not kill baseband RX\n");
1465 if (band_switch || mode_diff) {
1466 ath9k_hw_mark_phy_inactive(ah);
1470 ath9k_hw_init_pll(ah, chan);
1472 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1473 ath_err(common, "Failed to do fast channel change\n");
1478 ath9k_hw_set_channel_regs(ah, chan);
1480 r = ath9k_hw_rf_set_freq(ah, chan);
1482 ath_err(common, "Failed to set channel\n");
1485 ath9k_hw_set_clockrate(ah);
1486 ath9k_hw_apply_txpower(ah, chan, false);
1488 ath9k_hw_set_delta_slope(ah, chan);
1489 ath9k_hw_spur_mitigate_freq(ah, chan);
1491 if (band_switch || ini_reloaded)
1492 ah->eep_ops->set_board_values(ah, chan);
1494 ath9k_hw_init_bb(ah, chan);
1495 ath9k_hw_rfbus_done(ah);
1497 if (band_switch || ini_reloaded) {
1498 ah->ah_flags |= AH_FASTCC;
1499 ath9k_hw_init_cal(ah, chan);
1500 ah->ah_flags &= ~AH_FASTCC;
1506 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1508 u32 gpio_mask = ah->gpio_mask;
1511 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1512 if (!(gpio_mask & 1))
1515 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1516 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1520 void ath9k_hw_check_nav(struct ath_hw *ah)
1522 struct ath_common *common = ath9k_hw_common(ah);
1525 val = REG_READ(ah, AR_NAV);
1526 if (val != 0xdeadbeef && val > 0x7fff) {
1527 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1528 REG_WRITE(ah, AR_NAV, 0);
1531 EXPORT_SYMBOL(ath9k_hw_check_nav);
1533 bool ath9k_hw_check_alive(struct ath_hw *ah)
1538 if (AR_SREV_9300(ah))
1539 return !ath9k_hw_detect_mac_hang(ah);
1541 if (AR_SREV_9285_12_OR_LATER(ah))
1544 last_val = REG_READ(ah, AR_OBS_BUS_1);
1546 reg = REG_READ(ah, AR_OBS_BUS_1);
1547 if (reg != last_val)
1552 if ((reg & 0x7E7FFFEF) == 0x00702400)
1555 switch (reg & 0x7E000B00) {
1563 } while (count-- > 0);
1567 EXPORT_SYMBOL(ath9k_hw_check_alive);
1569 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1571 /* Setup MFP options for CCMP */
1572 if (AR_SREV_9280_20_OR_LATER(ah)) {
1573 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1574 * frames when constructing CCMP AAD. */
1575 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1577 ah->sw_mgmt_crypto = false;
1578 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1579 /* Disable hardware crypto for management frames */
1580 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1581 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1582 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1583 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1584 ah->sw_mgmt_crypto = true;
1586 ah->sw_mgmt_crypto = true;
1590 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1591 u32 macStaId1, u32 saveDefAntenna)
1593 struct ath_common *common = ath9k_hw_common(ah);
1595 ENABLE_REGWRITE_BUFFER(ah);
1597 REG_RMW(ah, AR_STA_ID1, macStaId1
1598 | AR_STA_ID1_RTS_USE_DEF
1599 | ah->sta_id1_defaults,
1600 ~AR_STA_ID1_SADH_MASK);
1601 ath_hw_setbssidmask(common);
1602 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1603 ath9k_hw_write_associd(ah);
1604 REG_WRITE(ah, AR_ISR, ~0);
1605 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1607 REGWRITE_BUFFER_FLUSH(ah);
1609 ath9k_hw_set_operating_mode(ah, ah->opmode);
1612 static void ath9k_hw_init_queues(struct ath_hw *ah)
1616 ENABLE_REGWRITE_BUFFER(ah);
1618 for (i = 0; i < AR_NUM_DCU; i++)
1619 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1621 REGWRITE_BUFFER_FLUSH(ah);
1624 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1625 ath9k_hw_resettxqueue(ah, i);
1629 * For big endian systems turn on swapping for descriptors
1631 static void ath9k_hw_init_desc(struct ath_hw *ah)
1633 struct ath_common *common = ath9k_hw_common(ah);
1635 if (AR_SREV_9100(ah)) {
1637 mask = REG_READ(ah, AR_CFG);
1638 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1639 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1642 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1643 REG_WRITE(ah, AR_CFG, mask);
1644 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1645 REG_READ(ah, AR_CFG));
1648 if (common->bus_ops->ath_bus_type == ATH_USB) {
1649 /* Configure AR9271 target WLAN */
1650 if (AR_SREV_9271(ah))
1651 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1653 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1656 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1657 AR_SREV_9550(ah) || AR_SREV_9531(ah))
1658 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1660 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1666 * Fast channel change:
1667 * (Change synthesizer based on channel freq without resetting chip)
1669 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1671 struct ath_common *common = ath9k_hw_common(ah);
1672 struct ath9k_hw_capabilities *pCap = &ah->caps;
1675 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1678 if (ah->chip_fullsleep)
1684 if (chan->channel == ah->curchan->channel)
1687 if ((ah->curchan->channelFlags | chan->channelFlags) &
1688 (CHANNEL_HALF | CHANNEL_QUARTER))
1692 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1694 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1695 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1698 if (!ath9k_hw_check_alive(ah))
1702 * For AR9462, make sure that calibration data for
1703 * re-using are present.
1705 if (AR_SREV_9462(ah) && (ah->caldata &&
1706 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1707 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1708 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1711 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1712 ah->curchan->channel, chan->channel);
1714 ret = ath9k_hw_channel_change(ah, chan);
1718 if (ath9k_hw_mci_is_enabled(ah))
1719 ar9003_mci_2g5g_switch(ah, false);
1721 ath9k_hw_loadnf(ah, ah->curchan);
1722 ath9k_hw_start_nfcal(ah, true);
1724 if (AR_SREV_9271(ah))
1725 ar9002_hw_load_ani_reg(ah, chan);
1732 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1733 struct ath9k_hw_cal_data *caldata, bool fastcc)
1735 struct ath_common *common = ath9k_hw_common(ah);
1743 bool start_mci_reset = false;
1744 bool save_fullsleep = ah->chip_fullsleep;
1746 if (ath9k_hw_mci_is_enabled(ah)) {
1747 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1748 if (start_mci_reset)
1752 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1755 if (ah->curchan && !ah->chip_fullsleep)
1756 ath9k_hw_getnf(ah, ah->curchan);
1758 ah->caldata = caldata;
1759 if (caldata && (chan->channel != caldata->channel ||
1760 chan->channelFlags != caldata->channelFlags)) {
1761 /* Operating channel changed, reset channel calibration data */
1762 memset(caldata, 0, sizeof(*caldata));
1763 ath9k_init_nfcal_hist_buffer(ah, chan);
1764 } else if (caldata) {
1765 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1767 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1770 r = ath9k_hw_do_fastcc(ah, chan);
1775 if (ath9k_hw_mci_is_enabled(ah))
1776 ar9003_mci_stop_bt(ah, save_fullsleep);
1778 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1779 if (saveDefAntenna == 0)
1782 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1784 /* Save TSF before chip reset, a cold reset clears it */
1785 tsf = ath9k_hw_gettsf64(ah);
1786 getrawmonotonic(&ts);
1787 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
1789 saveLedState = REG_READ(ah, AR_CFG_LED) &
1790 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1791 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1793 ath9k_hw_mark_phy_inactive(ah);
1795 ah->paprd_table_write_done = false;
1797 /* Only required on the first reset */
1798 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1800 AR9271_RESET_POWER_DOWN_CONTROL,
1801 AR9271_RADIO_RF_RST);
1805 if (!ath9k_hw_chip_reset(ah, chan)) {
1806 ath_err(common, "Chip reset failed\n");
1810 /* Only required on the first reset */
1811 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1812 ah->htc_reset_init = false;
1814 AR9271_RESET_POWER_DOWN_CONTROL,
1815 AR9271_GATE_MAC_CTL);
1820 getrawmonotonic(&ts);
1821 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
1822 ath9k_hw_settsf64(ah, tsf + usec);
1824 if (AR_SREV_9280_20_OR_LATER(ah))
1825 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1827 if (!AR_SREV_9300_20_OR_LATER(ah))
1828 ar9002_hw_enable_async_fifo(ah);
1830 r = ath9k_hw_process_ini(ah, chan);
1834 ath9k_hw_set_rfmode(ah, chan);
1836 if (ath9k_hw_mci_is_enabled(ah))
1837 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1840 * Some AR91xx SoC devices frequently fail to accept TSF writes
1841 * right after the chip reset. When that happens, write a new
1842 * value after the initvals have been applied, with an offset
1843 * based on measured time difference
1845 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1847 ath9k_hw_settsf64(ah, tsf);
1850 ath9k_hw_init_mfp(ah);
1852 ath9k_hw_set_delta_slope(ah, chan);
1853 ath9k_hw_spur_mitigate_freq(ah, chan);
1854 ah->eep_ops->set_board_values(ah, chan);
1856 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1858 r = ath9k_hw_rf_set_freq(ah, chan);
1862 ath9k_hw_set_clockrate(ah);
1864 ath9k_hw_init_queues(ah);
1865 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1866 ath9k_hw_ani_cache_ini_regs(ah);
1867 ath9k_hw_init_qos(ah);
1869 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1870 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1872 ath9k_hw_init_global_settings(ah);
1874 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1875 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1876 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1877 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1878 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1879 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1880 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1883 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1885 ath9k_hw_set_dma(ah);
1887 if (!ath9k_hw_mci_is_enabled(ah))
1888 REG_WRITE(ah, AR_OBS, 8);
1890 if (ah->config.rx_intr_mitigation) {
1891 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1892 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
1895 if (ah->config.tx_intr_mitigation) {
1896 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1897 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1900 ath9k_hw_init_bb(ah, chan);
1903 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1904 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
1906 if (!ath9k_hw_init_cal(ah, chan))
1909 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1912 ENABLE_REGWRITE_BUFFER(ah);
1914 ath9k_hw_restore_chainmask(ah);
1915 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1917 REGWRITE_BUFFER_FLUSH(ah);
1919 ath9k_hw_init_desc(ah);
1921 if (ath9k_hw_btcoex_is_enabled(ah))
1922 ath9k_hw_btcoex_enable(ah);
1924 if (ath9k_hw_mci_is_enabled(ah))
1925 ar9003_mci_check_bt(ah);
1927 ath9k_hw_loadnf(ah, chan);
1928 ath9k_hw_start_nfcal(ah, true);
1930 if (AR_SREV_9300_20_OR_LATER(ah))
1931 ar9003_hw_bb_watchdog_config(ah);
1933 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
1934 ar9003_hw_disable_phy_restart(ah);
1936 ath9k_hw_apply_gpio_override(ah);
1938 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
1939 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1943 EXPORT_SYMBOL(ath9k_hw_reset);
1945 /******************************/
1946 /* Power Management (Chipset) */
1947 /******************************/
1950 * Notify Power Mgt is disabled in self-generated frames.
1951 * If requested, force chip to sleep.
1953 static void ath9k_set_power_sleep(struct ath_hw *ah)
1955 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1957 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1958 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1959 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1960 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
1961 /* xxx Required for WLAN only case ? */
1962 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1967 * Clear the RTC force wake bit to allow the
1968 * mac to go to sleep.
1970 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1972 if (ath9k_hw_mci_is_enabled(ah))
1975 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1976 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1978 /* Shutdown chip. Active low */
1979 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1980 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1984 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1985 if (AR_SREV_9300_20_OR_LATER(ah))
1986 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1990 * Notify Power Management is enabled in self-generating
1991 * frames. If request, set power mode of chip to
1992 * auto/normal. Duration in units of 128us (1/8 TU).
1994 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
1996 struct ath9k_hw_capabilities *pCap = &ah->caps;
1998 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2000 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2001 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2002 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2003 AR_RTC_FORCE_WAKE_ON_INT);
2006 /* When chip goes into network sleep, it could be waken
2007 * up by MCI_INT interrupt caused by BT's HW messages
2008 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2009 * rate (~100us). This will cause chip to leave and
2010 * re-enter network sleep mode frequently, which in
2011 * consequence will have WLAN MCI HW to generate lots of
2012 * SYS_WAKING and SYS_SLEEPING messages which will make
2013 * BT CPU to busy to process.
2015 if (ath9k_hw_mci_is_enabled(ah))
2016 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2017 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2019 * Clear the RTC force wake bit to allow the
2020 * mac to go to sleep.
2022 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2024 if (ath9k_hw_mci_is_enabled(ah))
2028 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2029 if (AR_SREV_9300_20_OR_LATER(ah))
2030 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2033 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2038 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2039 if (AR_SREV_9300_20_OR_LATER(ah)) {
2040 REG_WRITE(ah, AR_WA, ah->WARegVal);
2044 if ((REG_READ(ah, AR_RTC_STATUS) &
2045 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2046 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2049 if (!AR_SREV_9300_20_OR_LATER(ah))
2050 ath9k_hw_init_pll(ah, NULL);
2052 if (AR_SREV_9100(ah))
2053 REG_SET_BIT(ah, AR_RTC_RESET,
2056 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2057 AR_RTC_FORCE_WAKE_EN);
2058 if (AR_SREV_9100(ah))
2063 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2064 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2065 if (val == AR_RTC_STATUS_ON)
2068 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2069 AR_RTC_FORCE_WAKE_EN);
2072 ath_err(ath9k_hw_common(ah),
2073 "Failed to wakeup in %uus\n",
2074 POWER_UP_TIME / 20);
2078 if (ath9k_hw_mci_is_enabled(ah))
2079 ar9003_mci_set_power_awake(ah);
2081 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2086 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2088 struct ath_common *common = ath9k_hw_common(ah);
2090 static const char *modes[] = {
2097 if (ah->power_mode == mode)
2100 ath_dbg(common, RESET, "%s -> %s\n",
2101 modes[ah->power_mode], modes[mode]);
2104 case ATH9K_PM_AWAKE:
2105 status = ath9k_hw_set_power_awake(ah);
2107 case ATH9K_PM_FULL_SLEEP:
2108 if (ath9k_hw_mci_is_enabled(ah))
2109 ar9003_mci_set_full_sleep(ah);
2111 ath9k_set_power_sleep(ah);
2112 ah->chip_fullsleep = true;
2114 case ATH9K_PM_NETWORK_SLEEP:
2115 ath9k_set_power_network_sleep(ah);
2118 ath_err(common, "Unknown power mode %u\n", mode);
2121 ah->power_mode = mode;
2124 * XXX: If this warning never comes up after a while then
2125 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2126 * ath9k_hw_setpower() return type void.
2129 if (!(ah->ah_flags & AH_UNPLUGGED))
2130 ATH_DBG_WARN_ON_ONCE(!status);
2134 EXPORT_SYMBOL(ath9k_hw_setpower);
2136 /*******************/
2137 /* Beacon Handling */
2138 /*******************/
2140 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2144 ENABLE_REGWRITE_BUFFER(ah);
2146 switch (ah->opmode) {
2147 case NL80211_IFTYPE_ADHOC:
2148 REG_SET_BIT(ah, AR_TXCFG,
2149 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2150 case NL80211_IFTYPE_MESH_POINT:
2151 case NL80211_IFTYPE_AP:
2152 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2153 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2154 TU_TO_USEC(ah->config.dma_beacon_response_time));
2155 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2156 TU_TO_USEC(ah->config.sw_beacon_response_time));
2158 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2161 ath_dbg(ath9k_hw_common(ah), BEACON,
2162 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2167 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2168 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2169 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2171 REGWRITE_BUFFER_FLUSH(ah);
2173 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2175 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2177 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2178 const struct ath9k_beacon_state *bs)
2180 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2181 struct ath9k_hw_capabilities *pCap = &ah->caps;
2182 struct ath_common *common = ath9k_hw_common(ah);
2184 ENABLE_REGWRITE_BUFFER(ah);
2186 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2187 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2188 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2190 REGWRITE_BUFFER_FLUSH(ah);
2192 REG_RMW_FIELD(ah, AR_RSSI_THR,
2193 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2195 beaconintval = bs->bs_intval;
2197 if (bs->bs_sleepduration > beaconintval)
2198 beaconintval = bs->bs_sleepduration;
2200 dtimperiod = bs->bs_dtimperiod;
2201 if (bs->bs_sleepduration > dtimperiod)
2202 dtimperiod = bs->bs_sleepduration;
2204 if (beaconintval == dtimperiod)
2205 nextTbtt = bs->bs_nextdtim;
2207 nextTbtt = bs->bs_nexttbtt;
2209 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2210 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2211 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2212 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2214 ENABLE_REGWRITE_BUFFER(ah);
2216 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2217 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2219 REG_WRITE(ah, AR_SLEEP1,
2220 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2221 | AR_SLEEP1_ASSUME_DTIM);
2223 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2224 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2226 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2228 REG_WRITE(ah, AR_SLEEP2,
2229 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2231 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2232 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2234 REGWRITE_BUFFER_FLUSH(ah);
2236 REG_SET_BIT(ah, AR_TIMER_MODE,
2237 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2240 /* TSF Out of Range Threshold */
2241 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2243 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2245 /*******************/
2246 /* HW Capabilities */
2247 /*******************/
2249 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2251 eeprom_chainmask &= chip_chainmask;
2252 if (eeprom_chainmask)
2253 return eeprom_chainmask;
2255 return chip_chainmask;
2259 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2260 * @ah: the atheros hardware data structure
2262 * We enable DFS support upstream on chipsets which have passed a series
2263 * of tests. The testing requirements are going to be documented. Desired
2264 * test requirements are documented at:
2266 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2268 * Once a new chipset gets properly tested an individual commit can be used
2269 * to document the testing for DFS for that chipset.
2271 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2274 switch (ah->hw_version.macVersion) {
2275 /* for temporary testing DFS with 9280 */
2276 case AR_SREV_VERSION_9280:
2277 /* AR9580 will likely be our first target to get testing on */
2278 case AR_SREV_VERSION_9580:
2285 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2287 struct ath9k_hw_capabilities *pCap = &ah->caps;
2288 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2289 struct ath_common *common = ath9k_hw_common(ah);
2290 unsigned int chip_chainmask;
2293 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2295 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2296 regulatory->current_rd = eeval;
2298 if (ah->opmode != NL80211_IFTYPE_AP &&
2299 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2300 if (regulatory->current_rd == 0x64 ||
2301 regulatory->current_rd == 0x65)
2302 regulatory->current_rd += 5;
2303 else if (regulatory->current_rd == 0x41)
2304 regulatory->current_rd = 0x43;
2305 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2306 regulatory->current_rd);
2309 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2310 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2312 "no band has been marked as supported in EEPROM\n");
2316 if (eeval & AR5416_OPFLAGS_11A)
2317 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2319 if (eeval & AR5416_OPFLAGS_11G)
2320 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2322 if (AR_SREV_9485(ah) ||
2327 else if (AR_SREV_9462(ah))
2329 else if (!AR_SREV_9280_20_OR_LATER(ah))
2331 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2336 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2338 * For AR9271 we will temporarilly uses the rx chainmax as read from
2341 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2342 !(eeval & AR5416_OPFLAGS_11A) &&
2343 !(AR_SREV_9271(ah)))
2344 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2345 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2346 else if (AR_SREV_9100(ah))
2347 pCap->rx_chainmask = 0x7;
2349 /* Use rx_chainmask from EEPROM. */
2350 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2352 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2353 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2354 ah->txchainmask = pCap->tx_chainmask;
2355 ah->rxchainmask = pCap->rx_chainmask;
2357 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2359 /* enable key search for every frame in an aggregate */
2360 if (AR_SREV_9300_20_OR_LATER(ah))
2361 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2363 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2365 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2366 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2368 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2370 if (AR_SREV_9271(ah))
2371 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2372 else if (AR_DEVID_7010(ah))
2373 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2374 else if (AR_SREV_9300_20_OR_LATER(ah))
2375 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2376 else if (AR_SREV_9287_11_OR_LATER(ah))
2377 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2378 else if (AR_SREV_9285_12_OR_LATER(ah))
2379 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2380 else if (AR_SREV_9280_20_OR_LATER(ah))
2381 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2383 pCap->num_gpio_pins = AR_NUM_GPIO;
2385 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2386 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2388 pCap->rts_aggr_limit = (8 * 1024);
2390 #ifdef CONFIG_ATH9K_RFKILL
2391 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2392 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2394 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2395 ah->rfkill_polarity =
2396 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2398 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2401 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2402 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2404 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2406 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2407 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2409 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2411 if (AR_SREV_9300_20_OR_LATER(ah)) {
2412 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2413 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2414 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2416 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2417 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2418 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2419 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2420 pCap->txs_len = sizeof(struct ar9003_txs);
2422 pCap->tx_desc_len = sizeof(struct ath_desc);
2423 if (AR_SREV_9280_20(ah))
2424 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2427 if (AR_SREV_9300_20_OR_LATER(ah))
2428 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2430 if (AR_SREV_9300_20_OR_LATER(ah))
2431 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2433 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2434 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2436 if (AR_SREV_9285(ah)) {
2437 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2439 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2440 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2441 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2442 ath_info(common, "Enable LNA combining\n");
2447 if (AR_SREV_9300_20_OR_LATER(ah)) {
2448 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2449 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2452 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2453 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2454 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2455 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2456 ath_info(common, "Enable LNA combining\n");
2460 if (ath9k_hw_dfs_tested(ah))
2461 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2463 tx_chainmask = pCap->tx_chainmask;
2464 rx_chainmask = pCap->rx_chainmask;
2465 while (tx_chainmask || rx_chainmask) {
2466 if (tx_chainmask & BIT(0))
2467 pCap->max_txchains++;
2468 if (rx_chainmask & BIT(0))
2469 pCap->max_rxchains++;
2475 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2476 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2477 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2479 if (AR_SREV_9462_20_OR_LATER(ah))
2480 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2483 if (AR_SREV_9462(ah))
2484 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
2486 if (AR_SREV_9300_20_OR_LATER(ah) &&
2487 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2488 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2493 /****************************/
2494 /* GPIO / RFKILL / Antennae */
2495 /****************************/
2497 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2501 u32 gpio_shift, tmp;
2504 addr = AR_GPIO_OUTPUT_MUX3;
2506 addr = AR_GPIO_OUTPUT_MUX2;
2508 addr = AR_GPIO_OUTPUT_MUX1;
2510 gpio_shift = (gpio % 6) * 5;
2512 if (AR_SREV_9280_20_OR_LATER(ah)
2513 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2514 REG_RMW(ah, addr, (type << gpio_shift),
2515 (0x1f << gpio_shift));
2517 tmp = REG_READ(ah, addr);
2518 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2519 tmp &= ~(0x1f << gpio_shift);
2520 tmp |= (type << gpio_shift);
2521 REG_WRITE(ah, addr, tmp);
2525 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2529 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2531 if (AR_DEVID_7010(ah)) {
2533 REG_RMW(ah, AR7010_GPIO_OE,
2534 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2535 (AR7010_GPIO_OE_MASK << gpio_shift));
2539 gpio_shift = gpio << 1;
2542 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2543 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2545 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2547 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2549 #define MS_REG_READ(x, y) \
2550 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2552 if (gpio >= ah->caps.num_gpio_pins)
2555 if (AR_DEVID_7010(ah)) {
2557 val = REG_READ(ah, AR7010_GPIO_IN);
2558 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2559 } else if (AR_SREV_9300_20_OR_LATER(ah))
2560 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2561 AR_GPIO_BIT(gpio)) != 0;
2562 else if (AR_SREV_9271(ah))
2563 return MS_REG_READ(AR9271, gpio) != 0;
2564 else if (AR_SREV_9287_11_OR_LATER(ah))
2565 return MS_REG_READ(AR9287, gpio) != 0;
2566 else if (AR_SREV_9285_12_OR_LATER(ah))
2567 return MS_REG_READ(AR9285, gpio) != 0;
2568 else if (AR_SREV_9280_20_OR_LATER(ah))
2569 return MS_REG_READ(AR928X, gpio) != 0;
2571 return MS_REG_READ(AR, gpio) != 0;
2573 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2575 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2580 if (AR_DEVID_7010(ah)) {
2582 REG_RMW(ah, AR7010_GPIO_OE,
2583 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2584 (AR7010_GPIO_OE_MASK << gpio_shift));
2588 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2589 gpio_shift = 2 * gpio;
2592 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2593 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2595 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2597 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2599 if (AR_DEVID_7010(ah)) {
2601 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2606 if (AR_SREV_9271(ah))
2609 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2612 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2614 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2616 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2618 EXPORT_SYMBOL(ath9k_hw_setantenna);
2620 /*********************/
2621 /* General Operation */
2622 /*********************/
2624 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2626 u32 bits = REG_READ(ah, AR_RX_FILTER);
2627 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2629 if (phybits & AR_PHY_ERR_RADAR)
2630 bits |= ATH9K_RX_FILTER_PHYRADAR;
2631 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2632 bits |= ATH9K_RX_FILTER_PHYERR;
2636 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2638 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2642 ENABLE_REGWRITE_BUFFER(ah);
2644 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2645 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2647 REG_WRITE(ah, AR_RX_FILTER, bits);
2650 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2651 phybits |= AR_PHY_ERR_RADAR;
2652 if (bits & ATH9K_RX_FILTER_PHYERR)
2653 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2654 REG_WRITE(ah, AR_PHY_ERR, phybits);
2657 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2659 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2661 REGWRITE_BUFFER_FLUSH(ah);
2663 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2665 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2667 if (ath9k_hw_mci_is_enabled(ah))
2668 ar9003_mci_bt_gain_ctrl(ah);
2670 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2673 ath9k_hw_init_pll(ah, NULL);
2674 ah->htc_reset_init = true;
2677 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2679 bool ath9k_hw_disable(struct ath_hw *ah)
2681 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2684 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2687 ath9k_hw_init_pll(ah, NULL);
2690 EXPORT_SYMBOL(ath9k_hw_disable);
2692 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2694 enum eeprom_param gain_param;
2696 if (IS_CHAN_2GHZ(chan))
2697 gain_param = EEP_ANTENNA_GAIN_2G;
2699 gain_param = EEP_ANTENNA_GAIN_5G;
2701 return ah->eep_ops->get_eeprom(ah, gain_param);
2704 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2707 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2708 struct ieee80211_channel *channel;
2709 int chan_pwr, new_pwr, max_gain;
2710 int ant_gain, ant_reduction = 0;
2715 channel = chan->chan;
2716 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2717 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2718 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2720 ant_gain = get_antenna_gain(ah, chan);
2721 if (ant_gain > max_gain)
2722 ant_reduction = ant_gain - max_gain;
2724 ah->eep_ops->set_txpower(ah, chan,
2725 ath9k_regd_get_ctl(reg, chan),
2726 ant_reduction, new_pwr, test);
2729 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2731 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2732 struct ath9k_channel *chan = ah->curchan;
2733 struct ieee80211_channel *channel = chan->chan;
2735 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2737 channel->max_power = MAX_RATE_POWER / 2;
2739 ath9k_hw_apply_txpower(ah, chan, test);
2742 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2744 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2746 void ath9k_hw_setopmode(struct ath_hw *ah)
2748 ath9k_hw_set_operating_mode(ah, ah->opmode);
2750 EXPORT_SYMBOL(ath9k_hw_setopmode);
2752 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2754 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2755 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2757 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2759 void ath9k_hw_write_associd(struct ath_hw *ah)
2761 struct ath_common *common = ath9k_hw_common(ah);
2763 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2764 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2765 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2767 EXPORT_SYMBOL(ath9k_hw_write_associd);
2769 #define ATH9K_MAX_TSF_READ 10
2771 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2773 u32 tsf_lower, tsf_upper1, tsf_upper2;
2776 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2777 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2778 tsf_lower = REG_READ(ah, AR_TSF_L32);
2779 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2780 if (tsf_upper2 == tsf_upper1)
2782 tsf_upper1 = tsf_upper2;
2785 WARN_ON( i == ATH9K_MAX_TSF_READ );
2787 return (((u64)tsf_upper1 << 32) | tsf_lower);
2789 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2791 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2793 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2794 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2796 EXPORT_SYMBOL(ath9k_hw_settsf64);
2798 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2800 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2801 AH_TSF_WRITE_TIMEOUT))
2802 ath_dbg(ath9k_hw_common(ah), RESET,
2803 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2805 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2807 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2809 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2812 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2814 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2816 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2818 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2822 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2823 macmode = AR_2040_JOINED_RX_CLEAR;
2827 REG_WRITE(ah, AR_2040_MODE, macmode);
2830 /* HW Generic timers configuration */
2832 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2834 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2835 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2836 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2837 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2838 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2839 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2840 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2841 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2842 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2843 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2844 AR_NDP2_TIMER_MODE, 0x0002},
2845 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2846 AR_NDP2_TIMER_MODE, 0x0004},
2847 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2848 AR_NDP2_TIMER_MODE, 0x0008},
2849 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2850 AR_NDP2_TIMER_MODE, 0x0010},
2851 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2852 AR_NDP2_TIMER_MODE, 0x0020},
2853 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2854 AR_NDP2_TIMER_MODE, 0x0040},
2855 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2856 AR_NDP2_TIMER_MODE, 0x0080}
2859 /* HW generic timer primitives */
2861 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2863 return REG_READ(ah, AR_TSF_L32);
2865 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2867 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2868 void (*trigger)(void *),
2869 void (*overflow)(void *),
2873 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2874 struct ath_gen_timer *timer;
2876 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2877 (timer_index >= ATH_MAX_GEN_TIMER))
2880 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2884 /* allocate a hardware generic timer slot */
2885 timer_table->timers[timer_index] = timer;
2886 timer->index = timer_index;
2887 timer->trigger = trigger;
2888 timer->overflow = overflow;
2893 EXPORT_SYMBOL(ath_gen_timer_alloc);
2895 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2896 struct ath_gen_timer *timer,
2900 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2903 timer_table->timer_mask |= BIT(timer->index);
2906 * Program generic timer registers
2908 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2910 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2912 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2913 gen_tmr_configuration[timer->index].mode_mask);
2915 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2917 * Starting from AR9462, each generic timer can select which tsf
2918 * to use. But we still follow the old rule, 0 - 7 use tsf and
2921 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2922 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2923 (1 << timer->index));
2925 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2926 (1 << timer->index));
2930 mask |= SM(AR_GENTMR_BIT(timer->index),
2931 AR_IMR_S5_GENTIMER_TRIG);
2932 if (timer->overflow)
2933 mask |= SM(AR_GENTMR_BIT(timer->index),
2934 AR_IMR_S5_GENTIMER_THRESH);
2936 REG_SET_BIT(ah, AR_IMR_S5, mask);
2938 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2939 ah->imask |= ATH9K_INT_GENTIMER;
2940 ath9k_hw_set_interrupts(ah);
2943 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2945 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2947 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2949 /* Clear generic timer enable bits. */
2950 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2951 gen_tmr_configuration[timer->index].mode_mask);
2953 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2955 * Need to switch back to TSF if it was using TSF2.
2957 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2958 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2959 (1 << timer->index));
2963 /* Disable both trigger and thresh interrupt masks */
2964 REG_CLR_BIT(ah, AR_IMR_S5,
2965 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2966 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2968 timer_table->timer_mask &= ~BIT(timer->index);
2970 if (timer_table->timer_mask == 0) {
2971 ah->imask &= ~ATH9K_INT_GENTIMER;
2972 ath9k_hw_set_interrupts(ah);
2975 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2977 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2979 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2981 /* free the hardware generic timer slot */
2982 timer_table->timers[timer->index] = NULL;
2985 EXPORT_SYMBOL(ath_gen_timer_free);
2988 * Generic Timer Interrupts handling
2990 void ath_gen_timer_isr(struct ath_hw *ah)
2992 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2993 struct ath_gen_timer *timer;
2994 unsigned long trigger_mask, thresh_mask;
2997 /* get hardware generic timer interrupt status */
2998 trigger_mask = ah->intr_gen_timer_trigger;
2999 thresh_mask = ah->intr_gen_timer_thresh;
3000 trigger_mask &= timer_table->timer_mask;
3001 thresh_mask &= timer_table->timer_mask;
3003 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3004 timer = timer_table->timers[index];
3007 if (!timer->overflow)
3010 trigger_mask &= ~BIT(index);
3011 timer->overflow(timer->arg);
3014 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3015 timer = timer_table->timers[index];
3018 if (!timer->trigger)
3020 timer->trigger(timer->arg);
3023 EXPORT_SYMBOL(ath_gen_timer_isr);
3032 } ath_mac_bb_names[] = {
3033 /* Devices with external radios */
3034 { AR_SREV_VERSION_5416_PCI, "5416" },
3035 { AR_SREV_VERSION_5416_PCIE, "5418" },
3036 { AR_SREV_VERSION_9100, "9100" },
3037 { AR_SREV_VERSION_9160, "9160" },
3038 /* Single-chip solutions */
3039 { AR_SREV_VERSION_9280, "9280" },
3040 { AR_SREV_VERSION_9285, "9285" },
3041 { AR_SREV_VERSION_9287, "9287" },
3042 { AR_SREV_VERSION_9271, "9271" },
3043 { AR_SREV_VERSION_9300, "9300" },
3044 { AR_SREV_VERSION_9330, "9330" },
3045 { AR_SREV_VERSION_9340, "9340" },
3046 { AR_SREV_VERSION_9485, "9485" },
3047 { AR_SREV_VERSION_9462, "9462" },
3048 { AR_SREV_VERSION_9550, "9550" },
3049 { AR_SREV_VERSION_9565, "9565" },
3050 { AR_SREV_VERSION_9531, "9531" },
3053 /* For devices with external radios */
3057 } ath_rf_names[] = {
3059 { AR_RAD5133_SREV_MAJOR, "5133" },
3060 { AR_RAD5122_SREV_MAJOR, "5122" },
3061 { AR_RAD2133_SREV_MAJOR, "2133" },
3062 { AR_RAD2122_SREV_MAJOR, "2122" }
3066 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3068 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3072 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3073 if (ath_mac_bb_names[i].version == mac_bb_version) {
3074 return ath_mac_bb_names[i].name;
3082 * Return the RF name. "????" is returned if the RF is unknown.
3083 * Used for devices with external radios.
3085 static const char *ath9k_hw_rf_name(u16 rf_version)
3089 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3090 if (ath_rf_names[i].version == rf_version) {
3091 return ath_rf_names[i].name;
3098 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3102 /* chipsets >= AR9280 are single-chip */
3103 if (AR_SREV_9280_20_OR_LATER(ah)) {
3104 used = scnprintf(hw_name, len,
3105 "Atheros AR%s Rev:%x",
3106 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3107 ah->hw_version.macRev);
3110 used = scnprintf(hw_name, len,
3111 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3112 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3113 ah->hw_version.macRev,
3114 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3115 & AR_RADIO_SREV_MAJOR)),
3116 ah->hw_version.phyRev);
3119 hw_name[used] = '\0';
3121 EXPORT_SYMBOL(ath9k_hw_name);