drivers/net/wireless/ath/ath9k/eeprom_def.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static void ath9k_get_txgain_index(struct ath_hw *ah,
  21                 struct ath9k_channel *chan,
  22                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
  23                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
  24 {
  25         u8 pcdac, i = 0;
  26         u16 idxL = 0, idxR = 0, numPiers;
  27         bool match;
  28         struct chan_centers centers;
  29
  30         ath9k_hw_get_channel_centers(ah, chan, &centers);
  31
  32         for (numPiers = 0; numPiers < availPiers; numPiers++)
  33                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
  34                         break;
  35
  36         match = ath9k_hw_get_lower_upper_index(
  37                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
  38                         calChans, numPiers, &idxL, &idxR);
  39         if (match) {
  40                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
  41                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
  42         } else {
  43                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
  44                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
  45                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
  46         }
  47
  48         while (pcdac > ah->originalGain[i] &&
  49                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
  50                 i++;
  51
  52         *pcdacIdx = i;
  53 }
  54
  55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
  56                                 u32 initTxGain,
  57                                 int txPower,
  58                                 u8 *pPDADCValues)
  59 {
  60         u32 i;
  61         u32 offset;
  62
  63         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
  64                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  65         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
  66                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  67
  68         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
  69                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
  70
  71         offset = txPower;
  72         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
  73                 if (i < offset)
  74                         pPDADCValues[i] = 0x0;
  75                 else
  76                         pPDADCValues[i] = 0xFF;
  77 }
  78
  79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
  80 {
  81         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
  82 }
  83
  84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
  85 {
  86         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
  87 }
  88
  89 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
  90
  91 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
  92 {
  93         struct ath_common *common = ath9k_hw_common(ah);
  94         u16 *eep_data = (u16 *)&ah->eeprom.def;
  95         int addr, ar5416_eep_start_loc = 0x100;
  96
  97         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
  98                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
  99                                          eep_data)) {
 100                         ath_err(ath9k_hw_common(ah),
 101                                 "Unable to read eeprom region\n");
 102                         return false;
 103                 }
 104                 eep_data++;
 105         }
 106         return true;
 107 }
 108
 109 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
 110 {
 111         u16 *eep_data = (u16 *)&ah->eeprom.def;
 112
 113         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
 114                                      0x100, SIZE_EEPROM_DEF);
 115         return true;
 116 }
 117
 118 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
 119 {
 120         struct ath_common *common = ath9k_hw_common(ah);
 121
 122         if (!ath9k_hw_use_flash(ah)) {
 123                 ath_dbg(common, ATH_DBG_EEPROM,
 124                         "Reading from EEPROM, not flash\n");
 125         }
 126
 127         if (common->bus_ops->ath_bus_type == ATH_USB)
 128                 return __ath9k_hw_usb_def_fill_eeprom(ah);
 129         else
 130                 return __ath9k_hw_def_fill_eeprom(ah);
 131 }
 132
 133 #undef SIZE_EEPROM_DEF
 134
 135 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 136 {
 137         struct ar5416_eeprom_def *eep =
 138                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
 139         struct ath_common *common = ath9k_hw_common(ah);
 140         u16 *eepdata, temp, magic, magic2;
 141         u32 sum = 0, el;
 142         bool need_swap = false;
 143         int i, addr, size;
 144
 145         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 146                 ath_err(common, "Reading Magic # failed\n");
 147                 return false;
 148         }
 149
 150         if (!ath9k_hw_use_flash(ah)) {
 151                 ath_dbg(common, ATH_DBG_EEPROM,
 152                         "Read Magic = 0x%04X\n", magic);
 153
 154                 if (magic != AR5416_EEPROM_MAGIC) {
 155                         magic2 = swab16(magic);
 156
 157                         if (magic2 == AR5416_EEPROM_MAGIC) {
 158                                 size = sizeof(struct ar5416_eeprom_def);
 159                                 need_swap = true;
 160                                 eepdata = (u16 *) (&ah->eeprom);
 161
 162                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
 163                                         temp = swab16(*eepdata);
 164                                         *eepdata = temp;
 165                                         eepdata++;
 166                                 }
 167                         } else {
 168                                 ath_err(common,
 169                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 170                                 return -EINVAL;
 171                         }
 172                 }
 173         }
 174
 175         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 176                 need_swap ? "True" : "False");
 177
 178         if (need_swap)
 179                 el = swab16(ah->eeprom.def.baseEepHeader.length);
 180         else
 181                 el = ah->eeprom.def.baseEepHeader.length;
 182
 183         if (el > sizeof(struct ar5416_eeprom_def))
 184                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
 185         else
 186                 el = el / sizeof(u16);
 187
 188         eepdata = (u16 *)(&ah->eeprom);
 189
 190         for (i = 0; i < el; i++)
 191                 sum ^= *eepdata++;
 192
 193         if (need_swap) {
 194                 u32 integer, j;
 195                 u16 word;
 196
 197                 ath_dbg(common, ATH_DBG_EEPROM,
 198                         "EEPROM Endianness is not native.. Changing.\n");
 199
 200                 word = swab16(eep->baseEepHeader.length);
 201                 eep->baseEepHeader.length = word;
 202
 203                 word = swab16(eep->baseEepHeader.checksum);
 204                 eep->baseEepHeader.checksum = word;
 205
 206                 word = swab16(eep->baseEepHeader.version);
 207                 eep->baseEepHeader.version = word;
 208
 209                 word = swab16(eep->baseEepHeader.regDmn[0]);
 210                 eep->baseEepHeader.regDmn[0] = word;
 211
 212                 word = swab16(eep->baseEepHeader.regDmn[1]);
 213                 eep->baseEepHeader.regDmn[1] = word;
 214
 215                 word = swab16(eep->baseEepHeader.rfSilent);
 216                 eep->baseEepHeader.rfSilent = word;
 217
 218                 word = swab16(eep->baseEepHeader.blueToothOptions);
 219                 eep->baseEepHeader.blueToothOptions = word;
 220
 221                 word = swab16(eep->baseEepHeader.deviceCap);
 222                 eep->baseEepHeader.deviceCap = word;
 223
 224                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 225                         struct modal_eep_header *pModal =
 226                                 &eep->modalHeader[j];
 227                         integer = swab32(pModal->antCtrlCommon);
 228                         pModal->antCtrlCommon = integer;
 229
 230                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 231                                 integer = swab32(pModal->antCtrlChain[i]);
 232                                 pModal->antCtrlChain[i] = integer;
 233                         }
 234
 235                         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 236                                 word = swab16(pModal->spurChans[i].spurChan);
 237                                 pModal->spurChans[i].spurChan = word;
 238                         }
 239                 }
 240         }
 241
 242         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 243             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 244                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 245                         sum, ah->eep_ops->get_eeprom_ver(ah));
 246                 return -EINVAL;
 247         }
 248
 249         /* Enable fixup for AR_AN_TOP2 if necessary */
 250         if (AR_SREV_9280_20_OR_LATER(ah) &&
 251             (eep->baseEepHeader.version & 0xff) > 0x0a &&
 252             eep->baseEepHeader.pwdclkind == 0)
 253                 ah->need_an_top2_fixup = 1;
 254
 255         if ((common->bus_ops->ath_bus_type == ATH_USB) &&
 256             (AR_SREV_9280(ah)))
 257                 eep->modalHeader[0].xpaBiasLvl = 0;
 258
 259         return 0;
 260 }
 261
 262 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
 263                                    enum eeprom_param param)
 264 {
 265         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 266         struct modal_eep_header *pModal = eep->modalHeader;
 267         struct base_eep_header *pBase = &eep->baseEepHeader;
 268
 269         switch (param) {
 270         case EEP_NFTHRESH_5:
 271                 return pModal[0].noiseFloorThreshCh[0];
 272         case EEP_NFTHRESH_2:
 273                 return pModal[1].noiseFloorThreshCh[0];
 274         case EEP_MAC_LSW:
 275                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 276         case EEP_MAC_MID:
 277                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 278         case EEP_MAC_MSW:
 279                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 280         case EEP_REG_0:
 281                 return pBase->regDmn[0];
 282         case EEP_REG_1:
 283                 return pBase->regDmn[1];
 284         case EEP_OP_CAP:
 285                 return pBase->deviceCap;
 286         case EEP_OP_MODE:
 287                 return pBase->opCapFlags;
 288         case EEP_RF_SILENT:
 289                 return pBase->rfSilent;
 290         case EEP_OB_5:
 291                 return pModal[0].ob;
 292         case EEP_DB_5:
 293                 return pModal[0].db;
 294         case EEP_OB_2:
 295                 return pModal[1].ob;
 296         case EEP_DB_2:
 297                 return pModal[1].db;
 298         case EEP_MINOR_REV:
 299                 return AR5416_VER_MASK;
 300         case EEP_TX_MASK:
 301                 return pBase->txMask;
 302         case EEP_RX_MASK:
 303                 return pBase->rxMask;
 304         case EEP_FSTCLK_5G:
 305                 return pBase->fastClk5g;
 306         case EEP_RXGAIN_TYPE:
 307                 return pBase->rxGainType;
 308         case EEP_TXGAIN_TYPE:
 309                 return pBase->txGainType;
 310         case EEP_OL_PWRCTRL:
 311                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 312                         return pBase->openLoopPwrCntl ? true : false;
 313                 else
 314                         return false;
 315         case EEP_RC_CHAIN_MASK:
 316                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 317                         return pBase->rcChainMask;
 318                 else
 319                         return 0;
 320         case EEP_DAC_HPWR_5G:
 321                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
 322                         return pBase->dacHiPwrMode_5G;
 323                 else
 324                         return 0;
 325         case EEP_FRAC_N_5G:
 326                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
 327                         return pBase->frac_n_5g;
 328                 else
 329                         return 0;
 330         case EEP_PWR_TABLE_OFFSET:
 331                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 332                         return pBase->pwr_table_offset;
 333                 else
 334                         return AR5416_PWR_TABLE_OFFSET_DB;
 335         default:
 336                 return 0;
 337         }
 338 }
 339
 340 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
 341                                   struct modal_eep_header *pModal,
 342                                   struct ar5416_eeprom_def *eep,
 343                                   u8 txRxAttenLocal, int regChainOffset, int i)
 344 {
 345         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 346                 txRxAttenLocal = pModal->txRxAttenCh[i];
 347
 348                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 349                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 350                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 351                               pModal->bswMargin[i]);
 352                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 353                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 354                               pModal->bswAtten[i]);
 355                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 356                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 357                               pModal->xatten2Margin[i]);
 358                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 359                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 360                               pModal->xatten2Db[i]);
 361                 } else {
 362                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 363                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 364                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 365                           | SM(pModal-> bswMargin[i],
 366                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 367                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 368                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 369                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 370                           | SM(pModal->bswAtten[i],
 371                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 372                 }
 373         }
 374
 375         if (AR_SREV_9280_20_OR_LATER(ah)) {
 376                 REG_RMW_FIELD(ah,
 377                       AR_PHY_RXGAIN + regChainOffset,
 378                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 379                 REG_RMW_FIELD(ah,
 380                       AR_PHY_RXGAIN + regChainOffset,
 381                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
 382         } else {
 383                 REG_WRITE(ah,
 384                           AR_PHY_RXGAIN + regChainOffset,
 385                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
 386                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
 387                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
 388                 REG_WRITE(ah,
 389                           AR_PHY_GAIN_2GHZ + regChainOffset,
 390                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 391                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 392                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 393         }
 394 }
 395
 396 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
 397                                           struct ath9k_channel *chan)
 398 {
 399         struct modal_eep_header *pModal;
 400         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 401         int i, regChainOffset;
 402         u8 txRxAttenLocal;
 403
 404         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 405         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 406
 407         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
 408
 409         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 410                 if (AR_SREV_9280(ah)) {
 411                         if (i >= 2)
 412                                 break;
 413                 }
 414
 415                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 416                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
 417                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 418                 else
 419                         regChainOffset = i * 0x1000;
 420
 421                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 422                           pModal->antCtrlChain[i]);
 423
 424                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 425                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
 426                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 427                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 428                           SM(pModal->iqCalICh[i],
 429                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 430                           SM(pModal->iqCalQCh[i],
 431                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 432
 433                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
 434                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
 435                                               regChainOffset, i);
 436         }
 437
 438         if (AR_SREV_9280_20_OR_LATER(ah)) {
 439                 if (IS_CHAN_2GHZ(chan)) {
 440                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 441                                                   AR_AN_RF2G1_CH0_OB,
 442                                                   AR_AN_RF2G1_CH0_OB_S,
 443                                                   pModal->ob);
 444                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 445                                                   AR_AN_RF2G1_CH0_DB,
 446                                                   AR_AN_RF2G1_CH0_DB_S,
 447                                                   pModal->db);
 448                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 449                                                   AR_AN_RF2G1_CH1_OB,
 450                                                   AR_AN_RF2G1_CH1_OB_S,
 451                                                   pModal->ob_ch1);
 452                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 453                                                   AR_AN_RF2G1_CH1_DB,
 454                                                   AR_AN_RF2G1_CH1_DB_S,
 455                                                   pModal->db_ch1);
 456                 } else {
 457                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 458                                                   AR_AN_RF5G1_CH0_OB5,
 459                                                   AR_AN_RF5G1_CH0_OB5_S,
 460                                                   pModal->ob);
 461                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 462                                                   AR_AN_RF5G1_CH0_DB5,
 463                                                   AR_AN_RF5G1_CH0_DB5_S,
 464                                                   pModal->db);
 465                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 466                                                   AR_AN_RF5G1_CH1_OB5,
 467                                                   AR_AN_RF5G1_CH1_OB5_S,
 468                                                   pModal->ob_ch1);
 469                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 470                                                   AR_AN_RF5G1_CH1_DB5,
 471                                                   AR_AN_RF5G1_CH1_DB5_S,
 472                                                   pModal->db_ch1);
 473                 }
 474                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 475                                           AR_AN_TOP2_XPABIAS_LVL,
 476                                           AR_AN_TOP2_XPABIAS_LVL_S,
 477                                           pModal->xpaBiasLvl);
 478                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 479                                           AR_AN_TOP2_LOCALBIAS,
 480                                           AR_AN_TOP2_LOCALBIAS_S,
 481                                           !!(pModal->lna_ctl &
 482                                              LNA_CTL_LOCAL_BIAS));
 483                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 484                               !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
 485         }
 486
 487         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 488                       pModal->switchSettling);
 489         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 490                       pModal->adcDesiredSize);
 491
 492         if (!AR_SREV_9280_20_OR_LATER(ah))
 493                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 494                               AR_PHY_DESIRED_SZ_PGA,
 495                               pModal->pgaDesiredSize);
 496
 497         REG_WRITE(ah, AR_PHY_RF_CTL4,
 498                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 499                   | SM(pModal->txEndToXpaOff,
 500                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 501                   | SM(pModal->txFrameToXpaOn,
 502                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 503                   | SM(pModal->txFrameToXpaOn,
 504                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 505
 506         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 507                       pModal->txEndToRxOn);
 508
 509         if (AR_SREV_9280_20_OR_LATER(ah)) {
 510                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 511                               pModal->thresh62);
 512                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 513                               AR_PHY_EXT_CCA0_THRESH62,
 514                               pModal->thresh62);
 515         } else {
 516                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 517                               pModal->thresh62);
 518                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 519                               AR_PHY_EXT_CCA_THRESH62,
 520                               pModal->thresh62);
 521         }
 522
 523         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
 524                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 525                               AR_PHY_TX_END_DATA_START,
 526                               pModal->txFrameToDataStart);
 527                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 528                               pModal->txFrameToPaOn);
 529         }
 530
 531         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 532                 if (IS_CHAN_HT40(chan))
 533                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 534                                       AR_PHY_SETTLING_SWITCH,
 535                                       pModal->swSettleHt40);
 536         }
 537
 538         if (AR_SREV_9280_20_OR_LATER(ah) &&
 539             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 540                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
 541                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
 542                               pModal->miscBits);
 543
 544
 545         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
 546                 if (IS_CHAN_2GHZ(chan))
 547                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 548                                         eep->baseEepHeader.dacLpMode);
 549                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
 550                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
 551                 else
 552                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 553                                       eep->baseEepHeader.dacLpMode);
 554
 555                 udelay(100);
 556
 557                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
 558                               pModal->miscBits >> 2);
 559
 560                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
 561                               AR_PHY_TX_DESIRED_SCALE_CCK,
 562                               eep->baseEepHeader.desiredScaleCCK);
 563         }
 564 }
 565
 566 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 567                                    struct ath9k_channel *chan)
 568 {
 569 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
 570         struct modal_eep_header *pModal;
 571         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 572         u8 biaslevel;
 573
 574         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 575                 return;
 576
 577         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 578                 return;
 579
 580         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 581
 582         if (pModal->xpaBiasLvl != 0xff) {
 583                 biaslevel = pModal->xpaBiasLvl;
 584         } else {
 585                 u16 resetFreqBin, freqBin, freqCount = 0;
 586                 struct chan_centers centers;
 587
 588                 ath9k_hw_get_channel_centers(ah, chan, &centers);
 589
 590                 resetFreqBin = FREQ2FBIN(centers.synth_center,
 591                                          IS_CHAN_2GHZ(chan));
 592                 freqBin = XPA_LVL_FREQ(0) & 0xff;
 593                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
 594
 595                 freqCount++;
 596
 597                 while (freqCount < 3) {
 598                         if (XPA_LVL_FREQ(freqCount) == 0x0)
 599                                 break;
 600
 601                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
 602                         if (resetFreqBin >= freqBin)
 603                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
 604                         else
 605                                 break;
 606                         freqCount++;
 607                 }
 608         }
 609
 610         if (IS_CHAN_2GHZ(chan)) {
 611                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
 612                                         7, 1) & (~0x18)) | biaslevel << 3;
 613         } else {
 614                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
 615                                         6, 1) & (~0xc0)) | biaslevel << 6;
 616         }
 617 #undef XPA_LVL_FREQ
 618 }
 619
 620 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 621                                 u16 *gb,
 622                                 u16 numXpdGain,
 623                                 u16 pdGainOverlap_t2,
 624                                 int8_t pwr_table_offset,
 625                                 int16_t *diff)
 626
 627 {
 628         u16 k;
 629
 630         /* Prior to writing the boundaries or the pdadc vs. power table
 631          * into the chip registers the default starting point on the pdadc
 632          * vs. power table needs to be checked and the curve boundaries
 633          * adjusted accordingly
 634          */
 635         if (AR_SREV_9280_20_OR_LATER(ah)) {
 636                 u16 gb_limit;
 637
 638                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 639                         /* get the difference in dB */
 640                         *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 641                         /* get the number of half dB steps */
 642                         *diff *= 2;
 643                         /* change the original gain boundary settings
 644                          * by the number of half dB steps
 645                          */
 646                         for (k = 0; k < numXpdGain; k++)
 647                                 gb[k] = (u16)(gb[k] - *diff);
 648                 }
 649                 /* Because of a hardware limitation, ensure the gain boundary
 650                  * is not larger than (63 - overlap)
 651                  */
 652                 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 653
 654                 for (k = 0; k < numXpdGain; k++)
 655                         gb[k] = (u16)min(gb_limit, gb[k]);
 656         }
 657
 658         return *diff;
 659 }
 660
 661 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 662                                       int8_t pwr_table_offset,
 663                                       int16_t diff,
 664                                       u8 *pdadcValues)
 665 {
 666 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 667         u16 k;
 668
 669         /* If this is a board that has a pwrTableOffset that differs from
 670          * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 671          * pdadc vs pwr table needs to be adjusted prior to writing to the
 672          * chip.
 673          */
 674         if (AR_SREV_9280_20_OR_LATER(ah)) {
 675                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 676                         /* shift the table to start at the new offset */
 677                         for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 678                                 pdadcValues[k] = pdadcValues[k + diff];
 679                         }
 680
 681                         /* fill the back of the table */
 682                         for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 683                                 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 684                         }
 685                 }
 686         }
 687 #undef NUM_PDADC
 688 }
 689
 690 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
 691                                   struct ath9k_channel *chan,
 692                                   int16_t *pTxPowerIndexOffset)
 693 {
 694 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
 695 #define SM_PDGAIN_B(x, y) \
 696                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
 697         struct ath_common *common = ath9k_hw_common(ah);
 698         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 699         struct cal_data_per_freq *pRawDataset;
 700         u8 *pCalBChans = NULL;
 701         u16 pdGainOverlap_t2;
 702         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 703         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 704         u16 numPiers, i, j;
 705         int16_t diff = 0;
 706         u16 numXpdGain, xpdMask;
 707         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 708         u32 reg32, regOffset, regChainOffset;
 709         int16_t modalIdx;
 710         int8_t pwr_table_offset;
 711
 712         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 713         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
 714
 715         pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 716
 717         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 718             AR5416_EEP_MINOR_VER_2) {
 719                 pdGainOverlap_t2 =
 720                         pEepData->modalHeader[modalIdx].pdGainOverlap;
 721         } else {
 722                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 723                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 724         }
 725
 726         if (IS_CHAN_2GHZ(chan)) {
 727                 pCalBChans = pEepData->calFreqPier2G;
 728                 numPiers = AR5416_NUM_2G_CAL_PIERS;
 729         } else {
 730                 pCalBChans = pEepData->calFreqPier5G;
 731                 numPiers = AR5416_NUM_5G_CAL_PIERS;
 732         }
 733
 734         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
 735                 pRawDataset = pEepData->calPierData2G[0];
 736                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
 737                                  pRawDataset)->vpdPdg[0][0];
 738         }
 739
 740         numXpdGain = 0;
 741
 742         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 743                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 744                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 745                                 break;
 746                         xpdGainValues[numXpdGain] =
 747                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 748                         numXpdGain++;
 749                 }
 750         }
 751
 752         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 753                       (numXpdGain - 1) & 0x3);
 754         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 755                       xpdGainValues[0]);
 756         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 757                       xpdGainValues[1]);
 758         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 759                       xpdGainValues[2]);
 760
 761         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 762                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 763                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 764                     (i != 0)) {
 765                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 766                 } else
 767                         regChainOffset = i * 0x1000;
 768
 769                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 770                         if (IS_CHAN_2GHZ(chan))
 771                                 pRawDataset = pEepData->calPierData2G[i];
 772                         else
 773                                 pRawDataset = pEepData->calPierData5G[i];
 774
 775
 776                         if (OLC_FOR_AR9280_20_LATER) {
 777                                 u8 pcdacIdx;
 778                                 u8 txPower;
 779
 780                                 ath9k_get_txgain_index(ah, chan,
 781                                 (struct calDataPerFreqOpLoop *)pRawDataset,
 782                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
 783                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
 784                                                      txPower/2, pdadcValues);
 785                         } else {
 786                                 ath9k_hw_get_gain_boundaries_pdadcs(ah,
 787                                                         chan, pRawDataset,
 788                                                         pCalBChans, numPiers,
 789                                                         pdGainOverlap_t2,
 790                                                         gainBoundaries,
 791                                                         pdadcValues,
 792                                                         numXpdGain);
 793                         }
 794
 795                         diff = ath9k_change_gain_boundary_setting(ah,
 796                                                            gainBoundaries,
 797                                                            numXpdGain,
 798                                                            pdGainOverlap_t2,
 799                                                            pwr_table_offset,
 800                                                            &diff);
 801
 802                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 803                                 if (OLC_FOR_AR9280_20_LATER) {
 804                                         REG_WRITE(ah,
 805                                                 AR_PHY_TPCRG5 + regChainOffset,
 806                                                 SM(0x6,
 807                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
 808                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
 809                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
 810                                 } else {
 811                                         REG_WRITE(ah,
 812                                                 AR_PHY_TPCRG5 + regChainOffset,
 813                                                 SM(pdGainOverlap_t2,
 814                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
 815                                                 SM_PDGAIN_B(0, 1) |
 816                                                 SM_PDGAIN_B(1, 2) |
 817                                                 SM_PDGAIN_B(2, 3) |
 818                                                 SM_PDGAIN_B(3, 4));
 819                                 }
 820                         }
 821
 822
 823                         ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 824                                                   diff, pdadcValues);
 825
 826                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 827                         for (j = 0; j < 32; j++) {
 828                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 829                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 830                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 831                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 832                                 REG_WRITE(ah, regOffset, reg32);
 833
 834                                 ath_dbg(common, ATH_DBG_EEPROM,
 835                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 836                                         i, regChainOffset, regOffset,
 837                                         reg32);
 838                                 ath_dbg(common, ATH_DBG_EEPROM,
 839                                         "PDADC: Chain %d | PDADC %3d "
 840                                         "Value %3d | PDADC %3d Value %3d | "
 841                                         "PDADC %3d Value %3d | PDADC %3d "
 842                                         "Value %3d |\n",
 843                                         i, 4 * j, pdadcValues[4 * j],
 844                                         4 * j + 1, pdadcValues[4 * j + 1],
 845                                         4 * j + 2, pdadcValues[4 * j + 2],
 846                                         4 * j + 3, pdadcValues[4 * j + 3]);
 847
 848                                 regOffset += 4;
 849                         }
 850                 }
 851         }
 852
 853         *pTxPowerIndexOffset = 0;
 854 #undef SM_PD_GAIN
 855 #undef SM_PDGAIN_B
 856 }
 857
 858 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 859                                                   struct ath9k_channel *chan,
 860                                                   int16_t *ratesArray,
 861                                                   u16 cfgCtl,
 862                                                   u16 AntennaReduction,
 863                                                   u16 twiceMaxRegulatoryPower,
 864                                                   u16 powerLimit)
 865 {
 866 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
 867 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
 868
 869         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 870         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 871         u16 twiceMaxEdgePower = MAX_RATE_POWER;
 872         static const u16 tpScaleReductionTable[5] =
 873                 { 0, 3, 6, 9, MAX_RATE_POWER };
 874
 875         int i;
 876         int16_t twiceLargestAntenna;
 877         struct cal_ctl_data *rep;
 878         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 879                 0, { 0, 0, 0, 0}
 880         };
 881         struct cal_target_power_leg targetPowerOfdmExt = {
 882                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 883                 0, { 0, 0, 0, 0 }
 884         };
 885         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 886                 0, {0, 0, 0, 0}
 887         };
 888         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 889         static const u16 ctlModesFor11a[] = {
 890                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
 891         };
 892         static const u16 ctlModesFor11g[] = {
 893                 CTL_11B, CTL_11G, CTL_2GHT20,
 894                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 895         };
 896         u16 numCtlModes;
 897         const u16 *pCtlMode;
 898         u16 ctlMode, freq;
 899         struct chan_centers centers;
 900         int tx_chainmask;
 901         u16 twiceMinEdgePower;
 902
 903         tx_chainmask = ah->txchainmask;
 904
 905         ath9k_hw_get_channel_centers(ah, chan, &centers);
 906
 907         twiceLargestAntenna = max(
 908                 pEepData->modalHeader
 909                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
 910                 pEepData->modalHeader
 911                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
 912
 913         twiceLargestAntenna = max((u8)twiceLargestAntenna,
 914                                   pEepData->modalHeader
 915                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
 916
 917         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 918                                            twiceLargestAntenna, 0);
 919
 920         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 921
 922         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
 923                 maxRegAllowedPower -=
 924                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 925         }
 926
 927         scaledPower = min(powerLimit, maxRegAllowedPower);
 928
 929         switch (ar5416_get_ntxchains(tx_chainmask)) {
 930         case 1:
 931                 break;
 932         case 2:
 933                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
 934                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 935                 else
 936                         scaledPower = 0;
 937                 break;
 938         case 3:
 939                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
 940                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 941                 else
 942                         scaledPower = 0;
 943                 break;
 944         }
 945
 946         if (IS_CHAN_2GHZ(chan)) {
 947                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
 948                         SUB_NUM_CTL_MODES_AT_2G_40;
 949                 pCtlMode = ctlModesFor11g;
 950
 951                 ath9k_hw_get_legacy_target_powers(ah, chan,
 952                         pEepData->calTargetPowerCck,
 953                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 954                         &targetPowerCck, 4, false);
 955                 ath9k_hw_get_legacy_target_powers(ah, chan,
 956                         pEepData->calTargetPower2G,
 957                         AR5416_NUM_2G_20_TARGET_POWERS,
 958                         &targetPowerOfdm, 4, false);
 959                 ath9k_hw_get_target_powers(ah, chan,
 960                         pEepData->calTargetPower2GHT20,
 961                         AR5416_NUM_2G_20_TARGET_POWERS,
 962                         &targetPowerHt20, 8, false);
 963
 964                 if (IS_CHAN_HT40(chan)) {
 965                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 966                         ath9k_hw_get_target_powers(ah, chan,
 967                                 pEepData->calTargetPower2GHT40,
 968                                 AR5416_NUM_2G_40_TARGET_POWERS,
 969                                 &targetPowerHt40, 8, true);
 970                         ath9k_hw_get_legacy_target_powers(ah, chan,
 971                                 pEepData->calTargetPowerCck,
 972                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 973                                 &targetPowerCckExt, 4, true);
 974                         ath9k_hw_get_legacy_target_powers(ah, chan,
 975                                 pEepData->calTargetPower2G,
 976                                 AR5416_NUM_2G_20_TARGET_POWERS,
 977                                 &targetPowerOfdmExt, 4, true);
 978                 }
 979         } else {
 980                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
 981                         SUB_NUM_CTL_MODES_AT_5G_40;
 982                 pCtlMode = ctlModesFor11a;
 983
 984                 ath9k_hw_get_legacy_target_powers(ah, chan,
 985                         pEepData->calTargetPower5G,
 986                         AR5416_NUM_5G_20_TARGET_POWERS,
 987                         &targetPowerOfdm, 4, false);
 988                 ath9k_hw_get_target_powers(ah, chan,
 989                         pEepData->calTargetPower5GHT20,
 990                         AR5416_NUM_5G_20_TARGET_POWERS,
 991                         &targetPowerHt20, 8, false);
 992
 993                 if (IS_CHAN_HT40(chan)) {
 994                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
 995                         ath9k_hw_get_target_powers(ah, chan,
 996                                 pEepData->calTargetPower5GHT40,
 997                                 AR5416_NUM_5G_40_TARGET_POWERS,
 998                                 &targetPowerHt40, 8, true);
 999                         ath9k_hw_get_legacy_target_powers(ah, chan,
1000                                 pEepData->calTargetPower5G,
1001                                 AR5416_NUM_5G_20_TARGET_POWERS,
1002                                 &targetPowerOfdmExt, 4, true);
1003                 }
1004         }
1005
1006         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1007                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1008                         (pCtlMode[ctlMode] == CTL_2GHT40);
1009                 if (isHt40CtlMode)
1010                         freq = centers.synth_center;
1011                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1012                         freq = centers.ext_center;
1013                 else
1014                         freq = centers.ctl_center;
1015
1016                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1017                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
1018                         twiceMaxEdgePower = MAX_RATE_POWER;
1019
1020                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1021                         if ((((cfgCtl & ~CTL_MODE_M) |
1022                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1023                              pEepData->ctlIndex[i]) ||
1024                             (((cfgCtl & ~CTL_MODE_M) |
1025                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1026                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1027                                 rep = &(pEepData->ctlData[i]);
1028
1029                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1030                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1031                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1032
1033                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1034                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1035                                                                 twiceMinEdgePower);
1036                                 } else {
1037                                         twiceMaxEdgePower = twiceMinEdgePower;
1038                                         break;
1039                                 }
1040                         }
1041                 }
1042
1043                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1044
1045                 switch (pCtlMode[ctlMode]) {
1046                 case CTL_11B:
1047                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1048                                 targetPowerCck.tPow2x[i] =
1049                                         min((u16)targetPowerCck.tPow2x[i],
1050                                             minCtlPower);
1051                         }
1052                         break;
1053                 case CTL_11A:
1054                 case CTL_11G:
1055                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1056                                 targetPowerOfdm.tPow2x[i] =
1057                                         min((u16)targetPowerOfdm.tPow2x[i],
1058                                             minCtlPower);
1059                         }
1060                         break;
1061                 case CTL_5GHT20:
1062                 case CTL_2GHT20:
1063                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1064                                 targetPowerHt20.tPow2x[i] =
1065                                         min((u16)targetPowerHt20.tPow2x[i],
1066                                             minCtlPower);
1067                         }
1068                         break;
1069                 case CTL_11B_EXT:
1070                         targetPowerCckExt.tPow2x[0] = min((u16)
1071                                         targetPowerCckExt.tPow2x[0],
1072                                         minCtlPower);
1073                         break;
1074                 case CTL_11A_EXT:
1075                 case CTL_11G_EXT:
1076                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1077                                         targetPowerOfdmExt.tPow2x[0],
1078                                         minCtlPower);
1079                         break;
1080                 case CTL_5GHT40:
1081                 case CTL_2GHT40:
1082                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1083                                 targetPowerHt40.tPow2x[i] =
1084                                         min((u16)targetPowerHt40.tPow2x[i],
1085                                             minCtlPower);
1086                         }
1087                         break;
1088                 default:
1089                         break;
1090                 }
1091         }
1092
1093         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1094                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1095                 targetPowerOfdm.tPow2x[0];
1096         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1097         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1098         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1099         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1100
1101         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1102                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1103
1104         if (IS_CHAN_2GHZ(chan)) {
1105                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1106                 ratesArray[rate2s] = ratesArray[rate2l] =
1107                         targetPowerCck.tPow2x[1];
1108                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1109                         targetPowerCck.tPow2x[2];
1110                 ratesArray[rate11s] = ratesArray[rate11l] =
1111                         targetPowerCck.tPow2x[3];
1112         }
1113         if (IS_CHAN_HT40(chan)) {
1114                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1115                         ratesArray[rateHt40_0 + i] =
1116                                 targetPowerHt40.tPow2x[i];
1117                 }
1118                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1119                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1120                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1121                 if (IS_CHAN_2GHZ(chan)) {
1122                         ratesArray[rateExtCck] =
1123                                 targetPowerCckExt.tPow2x[0];
1124                 }
1125         }
1126 }
1127
1128 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1129                                     struct ath9k_channel *chan,
1130                                     u16 cfgCtl,
1131                                     u8 twiceAntennaReduction,
1132                                     u8 twiceMaxRegulatoryPower,
1133                                     u8 powerLimit, bool test)
1134 {
1135 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1136         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1137         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1138         struct modal_eep_header *pModal =
1139                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1140         int16_t ratesArray[Ar5416RateSize];
1141         int16_t txPowerIndexOffset = 0;
1142         u8 ht40PowerIncForPdadc = 2;
1143         int i, cck_ofdm_delta = 0;
1144
1145         memset(ratesArray, 0, sizeof(ratesArray));
1146
1147         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1148             AR5416_EEP_MINOR_VER_2) {
1149                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1150         }
1151
1152         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1153                                                &ratesArray[0], cfgCtl,
1154                                                twiceAntennaReduction,
1155                                                twiceMaxRegulatoryPower,
1156                                                powerLimit);
1157
1158         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1159
1160         regulatory->max_power_level = 0;
1161         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1162                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1163                 if (ratesArray[i] > MAX_RATE_POWER)
1164                         ratesArray[i] = MAX_RATE_POWER;
1165                 if (ratesArray[i] > regulatory->max_power_level)
1166                         regulatory->max_power_level = ratesArray[i];
1167         }
1168
1169         if (!test) {
1170                 i = rate6mb;
1171
1172                 if (IS_CHAN_HT40(chan))
1173                         i = rateHt40_0;
1174                 else if (IS_CHAN_HT20(chan))
1175                         i = rateHt20_0;
1176
1177                 regulatory->max_power_level = ratesArray[i];
1178         }
1179
1180         switch(ar5416_get_ntxchains(ah->txchainmask)) {
1181         case 1:
1182                 break;
1183         case 2:
1184                 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1185                 break;
1186         case 3:
1187                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1188                 break;
1189         default:
1190                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1191                         "Invalid chainmask configuration\n");
1192                 break;
1193         }
1194
1195         if (test)
1196                 return;
1197
1198         if (AR_SREV_9280_20_OR_LATER(ah)) {
1199                 for (i = 0; i < Ar5416RateSize; i++) {
1200                         int8_t pwr_table_offset;
1201
1202                         pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1203                                                         EEP_PWR_TABLE_OFFSET);
1204                         ratesArray[i] -= pwr_table_offset * 2;
1205                 }
1206         }
1207
1208         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1209                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1210                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1211                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1212                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1213         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1214                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1215                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1216                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1217                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1218
1219         if (IS_CHAN_2GHZ(chan)) {
1220                 if (OLC_FOR_AR9280_20_LATER) {
1221                         cck_ofdm_delta = 2;
1222                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1223                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1224                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1225                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1226                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1227                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1228                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1229                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1230                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1231                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1232                 } else {
1233                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1234                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1235                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1236                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1237                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1238                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1239                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1240                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1241                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1242                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1243                 }
1244         }
1245
1246         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1247                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1248                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1249                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1250                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1251         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1252                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1253                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1254                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1255                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1256
1257         if (IS_CHAN_HT40(chan)) {
1258                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1259                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1260                                        ht40PowerIncForPdadc, 24)
1261                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1262                                          ht40PowerIncForPdadc, 16)
1263                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1264                                          ht40PowerIncForPdadc, 8)
1265                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1266                                          ht40PowerIncForPdadc, 0));
1267                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1268                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1269                                        ht40PowerIncForPdadc, 24)
1270                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1271                                          ht40PowerIncForPdadc, 16)
1272                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1273                                          ht40PowerIncForPdadc, 8)
1274                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1275                                          ht40PowerIncForPdadc, 0));
1276                 if (OLC_FOR_AR9280_20_LATER) {
1277                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1278                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1279                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1280                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1281                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1282                 } else {
1283                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1284                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1285                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1286                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1287                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1288                 }
1289         }
1290
1291         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1292                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1293                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1294 }
1295
1296 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1297 {
1298 #define EEP_DEF_SPURCHAN \
1299         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1300         struct ath_common *common = ath9k_hw_common(ah);
1301
1302         u16 spur_val = AR_NO_SPUR;
1303
1304         ath_dbg(common, ATH_DBG_ANI,
1305                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1306                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1307
1308         switch (ah->config.spurmode) {
1309         case SPUR_DISABLE:
1310                 break;
1311         case SPUR_ENABLE_IOCTL:
1312                 spur_val = ah->config.spurchans[i][is2GHz];
1313                 ath_dbg(common, ATH_DBG_ANI,
1314                         "Getting spur val from new loc. %d\n", spur_val);
1315                 break;
1316         case SPUR_ENABLE_EEPROM:
1317                 spur_val = EEP_DEF_SPURCHAN;
1318                 break;
1319         }
1320
1321         return spur_val;
1322
1323 #undef EEP_DEF_SPURCHAN
1324 }
1325
1326 const struct eeprom_ops eep_def_ops = {
1327         .check_eeprom           = ath9k_hw_def_check_eeprom,
1328         .get_eeprom             = ath9k_hw_def_get_eeprom,
1329         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1330         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1331         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1332         .set_board_values       = ath9k_hw_def_set_board_values,
1333         .set_addac              = ath9k_hw_def_set_addac,
1334         .set_txpower            = ath9k_hw_def_set_txpower,
1335         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1336 };