2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9002_phy.h"
20 static void ath9k_get_txgain_index(struct ath_hw *ah,
21 struct ath9k_channel *chan,
22 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
23 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
26 u16 idxL = 0, idxR = 0, numPiers;
28 struct chan_centers centers;
30 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
32 for (numPiers = 0; numPiers < availPiers; numPiers++)
33 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
36 match = ath9k_hw_get_lower_upper_index(
37 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
38 calChans, numPiers, &idxL, &idxR);
40 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
41 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
43 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
44 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
45 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
48 while (pcdac > ah->originalGain[i] &&
49 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
72 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
74 pPDADCValues[i] = 0x0;
76 pPDADCValues[i] = 0xFF;
79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
81 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
86 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 struct ath_common *common = ath9k_hw_common(ah);
93 u16 *eep_data = (u16 *)&ah->eeprom.def;
94 int addr, ar5416_eep_start_loc = 0x100;
96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
99 ath_err(ath9k_hw_common(ah),
100 "Unable to read eeprom region\n");
106 #undef SIZE_EEPROM_DEF
109 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
111 struct ar5416_eeprom_def *eep =
112 (struct ar5416_eeprom_def *) &ah->eeprom.def;
113 struct ath_common *common = ath9k_hw_common(ah);
114 u16 *eepdata, temp, magic, magic2;
116 bool need_swap = false;
119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
120 ath_err(common, "Reading Magic # failed\n");
124 if (!ath9k_hw_use_flash(ah)) {
125 ath_dbg(common, ATH_DBG_EEPROM,
126 "Read Magic = 0x%04X\n", magic);
128 if (magic != AR5416_EEPROM_MAGIC) {
129 magic2 = swab16(magic);
131 if (magic2 == AR5416_EEPROM_MAGIC) {
132 size = sizeof(struct ar5416_eeprom_def);
134 eepdata = (u16 *) (&ah->eeprom);
136 for (addr = 0; addr < size / sizeof(u16); addr++) {
137 temp = swab16(*eepdata);
143 "Invalid EEPROM Magic. Endianness mismatch.\n");
149 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
150 need_swap ? "True" : "False");
153 el = swab16(ah->eeprom.def.baseEepHeader.length);
155 el = ah->eeprom.def.baseEepHeader.length;
157 if (el > sizeof(struct ar5416_eeprom_def))
158 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
160 el = el / sizeof(u16);
162 eepdata = (u16 *)(&ah->eeprom);
164 for (i = 0; i < el; i++)
171 ath_dbg(common, ATH_DBG_EEPROM,
172 "EEPROM Endianness is not native.. Changing.\n");
174 word = swab16(eep->baseEepHeader.length);
175 eep->baseEepHeader.length = word;
177 word = swab16(eep->baseEepHeader.checksum);
178 eep->baseEepHeader.checksum = word;
180 word = swab16(eep->baseEepHeader.version);
181 eep->baseEepHeader.version = word;
183 word = swab16(eep->baseEepHeader.regDmn[0]);
184 eep->baseEepHeader.regDmn[0] = word;
186 word = swab16(eep->baseEepHeader.regDmn[1]);
187 eep->baseEepHeader.regDmn[1] = word;
189 word = swab16(eep->baseEepHeader.rfSilent);
190 eep->baseEepHeader.rfSilent = word;
192 word = swab16(eep->baseEepHeader.blueToothOptions);
193 eep->baseEepHeader.blueToothOptions = word;
195 word = swab16(eep->baseEepHeader.deviceCap);
196 eep->baseEepHeader.deviceCap = word;
198 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
199 struct modal_eep_header *pModal =
200 &eep->modalHeader[j];
201 integer = swab32(pModal->antCtrlCommon);
202 pModal->antCtrlCommon = integer;
204 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
205 integer = swab32(pModal->antCtrlChain[i]);
206 pModal->antCtrlChain[i] = integer;
209 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
210 word = swab16(pModal->spurChans[i].spurChan);
211 pModal->spurChans[i].spurChan = word;
216 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
217 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
218 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah));
223 /* Enable fixup for AR_AN_TOP2 if necessary */
224 if (AR_SREV_9280_20_OR_LATER(ah) &&
225 (eep->baseEepHeader.version & 0xff) > 0x0a &&
226 eep->baseEepHeader.pwdclkind == 0)
227 ah->need_an_top2_fixup = 1;
232 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
233 enum eeprom_param param)
235 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
236 struct modal_eep_header *pModal = eep->modalHeader;
237 struct base_eep_header *pBase = &eep->baseEepHeader;
241 return pModal[0].noiseFloorThreshCh[0];
243 return pModal[1].noiseFloorThreshCh[0];
245 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
247 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
249 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
251 return pBase->regDmn[0];
253 return pBase->regDmn[1];
255 return pBase->deviceCap;
257 return pBase->opCapFlags;
259 return pBase->rfSilent;
269 return AR5416_VER_MASK;
271 return pBase->txMask;
273 return pBase->rxMask;
275 return pBase->fastClk5g;
276 case EEP_RXGAIN_TYPE:
277 return pBase->rxGainType;
278 case EEP_TXGAIN_TYPE:
279 return pBase->txGainType;
281 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
282 return pBase->openLoopPwrCntl ? true : false;
285 case EEP_RC_CHAIN_MASK:
286 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
287 return pBase->rcChainMask;
290 case EEP_DAC_HPWR_5G:
291 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
292 return pBase->dacHiPwrMode_5G;
296 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
297 return pBase->frac_n_5g;
300 case EEP_PWR_TABLE_OFFSET:
301 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
302 return pBase->pwr_table_offset;
304 return AR5416_PWR_TABLE_OFFSET_DB;
310 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
311 struct modal_eep_header *pModal,
312 struct ar5416_eeprom_def *eep,
313 u8 txRxAttenLocal, int regChainOffset, int i)
315 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
316 txRxAttenLocal = pModal->txRxAttenCh[i];
318 if (AR_SREV_9280_20_OR_LATER(ah)) {
319 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
320 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
321 pModal->bswMargin[i]);
322 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
323 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
324 pModal->bswAtten[i]);
325 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
326 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
327 pModal->xatten2Margin[i]);
328 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
329 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
330 pModal->xatten2Db[i]);
332 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
333 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
334 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
335 | SM(pModal-> bswMargin[i],
336 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
337 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
338 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
339 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
340 | SM(pModal->bswAtten[i],
341 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
345 if (AR_SREV_9280_20_OR_LATER(ah)) {
347 AR_PHY_RXGAIN + regChainOffset,
348 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
350 AR_PHY_RXGAIN + regChainOffset,
351 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
354 AR_PHY_RXGAIN + regChainOffset,
355 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
356 ~AR_PHY_RXGAIN_TXRX_ATTEN)
357 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
359 AR_PHY_GAIN_2GHZ + regChainOffset,
360 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
361 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
362 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
366 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
367 struct ath9k_channel *chan)
369 struct modal_eep_header *pModal;
370 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
371 int i, regChainOffset;
374 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
375 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
377 REG_WRITE(ah, AR_PHY_SWITCH_COM,
378 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
380 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
381 if (AR_SREV_9280(ah)) {
386 if (AR_SREV_5416_20_OR_LATER(ah) &&
387 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
388 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
390 regChainOffset = i * 0x1000;
392 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
393 pModal->antCtrlChain[i]);
395 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
396 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
397 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
398 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
399 SM(pModal->iqCalICh[i],
400 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
401 SM(pModal->iqCalQCh[i],
402 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
404 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
405 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
409 if (AR_SREV_9280_20_OR_LATER(ah)) {
410 if (IS_CHAN_2GHZ(chan)) {
411 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
413 AR_AN_RF2G1_CH0_OB_S,
415 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
417 AR_AN_RF2G1_CH0_DB_S,
419 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
421 AR_AN_RF2G1_CH1_OB_S,
423 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
425 AR_AN_RF2G1_CH1_DB_S,
428 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
430 AR_AN_RF5G1_CH0_OB5_S,
432 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
434 AR_AN_RF5G1_CH0_DB5_S,
436 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
438 AR_AN_RF5G1_CH1_OB5_S,
440 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
442 AR_AN_RF5G1_CH1_DB5_S,
445 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
446 AR_AN_TOP2_XPABIAS_LVL,
447 AR_AN_TOP2_XPABIAS_LVL_S,
449 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
450 AR_AN_TOP2_LOCALBIAS,
451 AR_AN_TOP2_LOCALBIAS_S,
453 LNA_CTL_LOCAL_BIAS));
454 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
455 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
458 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
459 pModal->switchSettling);
460 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
461 pModal->adcDesiredSize);
463 if (!AR_SREV_9280_20_OR_LATER(ah))
464 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
465 AR_PHY_DESIRED_SZ_PGA,
466 pModal->pgaDesiredSize);
468 REG_WRITE(ah, AR_PHY_RF_CTL4,
469 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
470 | SM(pModal->txEndToXpaOff,
471 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
472 | SM(pModal->txFrameToXpaOn,
473 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
474 | SM(pModal->txFrameToXpaOn,
475 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
477 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
478 pModal->txEndToRxOn);
480 if (AR_SREV_9280_20_OR_LATER(ah)) {
481 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
483 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
484 AR_PHY_EXT_CCA0_THRESH62,
487 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
489 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
490 AR_PHY_EXT_CCA_THRESH62,
494 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
495 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
496 AR_PHY_TX_END_DATA_START,
497 pModal->txFrameToDataStart);
498 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
499 pModal->txFrameToPaOn);
502 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
503 if (IS_CHAN_HT40(chan))
504 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
505 AR_PHY_SETTLING_SWITCH,
506 pModal->swSettleHt40);
509 if (AR_SREV_9280_20_OR_LATER(ah) &&
510 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
511 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
512 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
516 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
517 if (IS_CHAN_2GHZ(chan))
518 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
519 eep->baseEepHeader.dacLpMode);
520 else if (eep->baseEepHeader.dacHiPwrMode_5G)
521 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
523 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
524 eep->baseEepHeader.dacLpMode);
528 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
529 pModal->miscBits >> 2);
531 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
532 AR_PHY_TX_DESIRED_SCALE_CCK,
533 eep->baseEepHeader.desiredScaleCCK);
537 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
538 struct ath9k_channel *chan)
540 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
541 struct modal_eep_header *pModal;
542 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
545 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
548 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
551 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
553 if (pModal->xpaBiasLvl != 0xff) {
554 biaslevel = pModal->xpaBiasLvl;
556 u16 resetFreqBin, freqBin, freqCount = 0;
557 struct chan_centers centers;
559 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
561 resetFreqBin = FREQ2FBIN(centers.synth_center,
563 freqBin = XPA_LVL_FREQ(0) & 0xff;
564 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
568 while (freqCount < 3) {
569 if (XPA_LVL_FREQ(freqCount) == 0x0)
572 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
573 if (resetFreqBin >= freqBin)
574 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
581 if (IS_CHAN_2GHZ(chan)) {
582 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
583 7, 1) & (~0x18)) | biaslevel << 3;
585 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
586 6, 1) & (~0xc0)) | biaslevel << 6;
591 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
592 struct ath9k_channel *chan,
593 struct cal_data_per_freq *pRawDataSet,
594 u8 *bChans, u16 availPiers,
596 u16 *pPdGainBoundaries, u8 *pPDADCValues,
601 u16 idxL = 0, idxR = 0, numPiers;
602 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
603 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
604 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
605 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
606 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
607 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
609 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
610 u8 minPwrT4[AR5416_NUM_PD_GAINS];
611 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
614 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
616 int16_t minDelta = 0;
617 struct chan_centers centers;
619 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
620 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
622 for (numPiers = 0; numPiers < availPiers; numPiers++) {
623 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
627 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
629 bChans, numPiers, &idxL, &idxR);
632 for (i = 0; i < numXpdGains; i++) {
633 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
634 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
635 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
636 pRawDataSet[idxL].pwrPdg[i],
637 pRawDataSet[idxL].vpdPdg[i],
638 AR5416_PD_GAIN_ICEPTS,
642 for (i = 0; i < numXpdGains; i++) {
643 pVpdL = pRawDataSet[idxL].vpdPdg[i];
644 pPwrL = pRawDataSet[idxL].pwrPdg[i];
645 pVpdR = pRawDataSet[idxR].vpdPdg[i];
646 pPwrR = pRawDataSet[idxR].pwrPdg[i];
648 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
651 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
652 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
655 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
657 AR5416_PD_GAIN_ICEPTS,
659 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
661 AR5416_PD_GAIN_ICEPTS,
664 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
666 (u8)(ath9k_hw_interpolate((u16)
671 bChans[idxL], bChans[idxR],
672 vpdTableL[i][j], vpdTableR[i][j]));
679 for (i = 0; i < numXpdGains; i++) {
680 if (i == (numXpdGains - 1))
681 pPdGainBoundaries[i] =
682 (u16)(maxPwrT4[i] / 2);
684 pPdGainBoundaries[i] =
685 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
687 pPdGainBoundaries[i] =
688 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
690 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
691 minDelta = pPdGainBoundaries[0] - 23;
692 pPdGainBoundaries[0] = 23;
698 if (AR_SREV_9280_20_OR_LATER(ah))
699 ss = (int16_t)(0 - (minPwrT4[i] / 2));
703 ss = (int16_t)((pPdGainBoundaries[i - 1] -
705 tPdGainOverlap + 1 + minDelta);
707 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
708 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
710 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
711 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
712 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
716 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
717 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
719 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
720 tgtIndex : sizeCurrVpdTable;
722 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
723 pPDADCValues[k++] = vpdTableI[i][ss++];
726 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
727 vpdTableI[i][sizeCurrVpdTable - 2]);
728 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
730 if (tgtIndex >= maxIndex) {
731 while ((ss <= tgtIndex) &&
732 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
733 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
734 (ss - maxIndex + 1) * vpdStep));
735 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
742 while (i < AR5416_PD_GAINS_IN_MASK) {
743 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
747 while (k < AR5416_NUM_PDADC_VALUES) {
748 pPDADCValues[k] = pPDADCValues[k - 1];
753 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
756 u16 pdGainOverlap_t2,
757 int8_t pwr_table_offset,
763 /* Prior to writing the boundaries or the pdadc vs. power table
764 * into the chip registers the default starting point on the pdadc
765 * vs. power table needs to be checked and the curve boundaries
766 * adjusted accordingly
768 if (AR_SREV_9280_20_OR_LATER(ah)) {
771 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
772 /* get the difference in dB */
773 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
774 /* get the number of half dB steps */
776 /* change the original gain boundary settings
777 * by the number of half dB steps
779 for (k = 0; k < numXpdGain; k++)
780 gb[k] = (u16)(gb[k] - *diff);
782 /* Because of a hardware limitation, ensure the gain boundary
783 * is not larger than (63 - overlap)
785 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
787 for (k = 0; k < numXpdGain; k++)
788 gb[k] = (u16)min(gb_limit, gb[k]);
794 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
795 int8_t pwr_table_offset,
799 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
802 /* If this is a board that has a pwrTableOffset that differs from
803 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
804 * pdadc vs pwr table needs to be adjusted prior to writing to the
807 if (AR_SREV_9280_20_OR_LATER(ah)) {
808 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
809 /* shift the table to start at the new offset */
810 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
811 pdadcValues[k] = pdadcValues[k + diff];
814 /* fill the back of the table */
815 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
816 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
823 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
824 struct ath9k_channel *chan,
825 int16_t *pTxPowerIndexOffset)
827 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
828 #define SM_PDGAIN_B(x, y) \
829 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
830 struct ath_common *common = ath9k_hw_common(ah);
831 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
832 struct cal_data_per_freq *pRawDataset;
833 u8 *pCalBChans = NULL;
834 u16 pdGainOverlap_t2;
835 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
836 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
839 u16 numXpdGain, xpdMask;
840 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
841 u32 reg32, regOffset, regChainOffset;
843 int8_t pwr_table_offset;
845 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
846 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
848 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
850 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
851 AR5416_EEP_MINOR_VER_2) {
853 pEepData->modalHeader[modalIdx].pdGainOverlap;
855 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
856 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
859 if (IS_CHAN_2GHZ(chan)) {
860 pCalBChans = pEepData->calFreqPier2G;
861 numPiers = AR5416_NUM_2G_CAL_PIERS;
863 pCalBChans = pEepData->calFreqPier5G;
864 numPiers = AR5416_NUM_5G_CAL_PIERS;
867 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
868 pRawDataset = pEepData->calPierData2G[0];
869 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
870 pRawDataset)->vpdPdg[0][0];
875 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
876 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
877 if (numXpdGain >= AR5416_NUM_PD_GAINS)
879 xpdGainValues[numXpdGain] =
880 (u16)(AR5416_PD_GAINS_IN_MASK - i);
885 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
886 (numXpdGain - 1) & 0x3);
887 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
889 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
891 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
894 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
895 if (AR_SREV_5416_20_OR_LATER(ah) &&
896 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
898 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
900 regChainOffset = i * 0x1000;
902 if (pEepData->baseEepHeader.txMask & (1 << i)) {
903 if (IS_CHAN_2GHZ(chan))
904 pRawDataset = pEepData->calPierData2G[i];
906 pRawDataset = pEepData->calPierData5G[i];
909 if (OLC_FOR_AR9280_20_LATER) {
913 ath9k_get_txgain_index(ah, chan,
914 (struct calDataPerFreqOpLoop *)pRawDataset,
915 pCalBChans, numPiers, &txPower, &pcdacIdx);
916 ath9k_olc_get_pdadcs(ah, pcdacIdx,
917 txPower/2, pdadcValues);
919 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
921 pCalBChans, numPiers,
928 diff = ath9k_change_gain_boundary_setting(ah,
935 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
936 if (OLC_FOR_AR9280_20_LATER) {
938 AR_PHY_TPCRG5 + regChainOffset,
940 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
941 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
942 SM_PD_GAIN(3) | SM_PD_GAIN(4));
945 AR_PHY_TPCRG5 + regChainOffset,
947 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
956 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
959 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
960 for (j = 0; j < 32; j++) {
961 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
962 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
963 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
964 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
965 REG_WRITE(ah, regOffset, reg32);
967 ath_dbg(common, ATH_DBG_EEPROM,
968 "PDADC (%d,%4x): %4.4x %8.8x\n",
969 i, regChainOffset, regOffset,
971 ath_dbg(common, ATH_DBG_EEPROM,
972 "PDADC: Chain %d | PDADC %3d "
973 "Value %3d | PDADC %3d Value %3d | "
974 "PDADC %3d Value %3d | PDADC %3d "
976 i, 4 * j, pdadcValues[4 * j],
977 4 * j + 1, pdadcValues[4 * j + 1],
978 4 * j + 2, pdadcValues[4 * j + 2],
979 4 * j + 3, pdadcValues[4 * j + 3]);
986 *pTxPowerIndexOffset = 0;
991 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
992 struct ath9k_channel *chan,
995 u16 AntennaReduction,
996 u16 twiceMaxRegulatoryPower,
999 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
1000 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
1002 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1003 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1004 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1005 static const u16 tpScaleReductionTable[5] =
1006 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1009 int16_t twiceLargestAntenna;
1010 struct cal_ctl_data *rep;
1011 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1014 struct cal_target_power_leg targetPowerOfdmExt = {
1015 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1018 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1021 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1022 static const u16 ctlModesFor11a[] = {
1023 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1025 static const u16 ctlModesFor11g[] = {
1026 CTL_11B, CTL_11G, CTL_2GHT20,
1027 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1030 const u16 *pCtlMode;
1032 struct chan_centers centers;
1034 u16 twiceMinEdgePower;
1036 tx_chainmask = ah->txchainmask;
1038 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1040 twiceLargestAntenna = max(
1041 pEepData->modalHeader
1042 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1043 pEepData->modalHeader
1044 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1046 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1047 pEepData->modalHeader
1048 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1050 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1051 twiceLargestAntenna, 0);
1053 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1055 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
1056 maxRegAllowedPower -=
1057 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
1060 scaledPower = min(powerLimit, maxRegAllowedPower);
1062 switch (ar5416_get_ntxchains(tx_chainmask)) {
1066 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1069 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1073 scaledPower = max((u16)0, scaledPower);
1075 if (IS_CHAN_2GHZ(chan)) {
1076 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1077 SUB_NUM_CTL_MODES_AT_2G_40;
1078 pCtlMode = ctlModesFor11g;
1080 ath9k_hw_get_legacy_target_powers(ah, chan,
1081 pEepData->calTargetPowerCck,
1082 AR5416_NUM_2G_CCK_TARGET_POWERS,
1083 &targetPowerCck, 4, false);
1084 ath9k_hw_get_legacy_target_powers(ah, chan,
1085 pEepData->calTargetPower2G,
1086 AR5416_NUM_2G_20_TARGET_POWERS,
1087 &targetPowerOfdm, 4, false);
1088 ath9k_hw_get_target_powers(ah, chan,
1089 pEepData->calTargetPower2GHT20,
1090 AR5416_NUM_2G_20_TARGET_POWERS,
1091 &targetPowerHt20, 8, false);
1093 if (IS_CHAN_HT40(chan)) {
1094 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1095 ath9k_hw_get_target_powers(ah, chan,
1096 pEepData->calTargetPower2GHT40,
1097 AR5416_NUM_2G_40_TARGET_POWERS,
1098 &targetPowerHt40, 8, true);
1099 ath9k_hw_get_legacy_target_powers(ah, chan,
1100 pEepData->calTargetPowerCck,
1101 AR5416_NUM_2G_CCK_TARGET_POWERS,
1102 &targetPowerCckExt, 4, true);
1103 ath9k_hw_get_legacy_target_powers(ah, chan,
1104 pEepData->calTargetPower2G,
1105 AR5416_NUM_2G_20_TARGET_POWERS,
1106 &targetPowerOfdmExt, 4, true);
1109 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1110 SUB_NUM_CTL_MODES_AT_5G_40;
1111 pCtlMode = ctlModesFor11a;
1113 ath9k_hw_get_legacy_target_powers(ah, chan,
1114 pEepData->calTargetPower5G,
1115 AR5416_NUM_5G_20_TARGET_POWERS,
1116 &targetPowerOfdm, 4, false);
1117 ath9k_hw_get_target_powers(ah, chan,
1118 pEepData->calTargetPower5GHT20,
1119 AR5416_NUM_5G_20_TARGET_POWERS,
1120 &targetPowerHt20, 8, false);
1122 if (IS_CHAN_HT40(chan)) {
1123 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1124 ath9k_hw_get_target_powers(ah, chan,
1125 pEepData->calTargetPower5GHT40,
1126 AR5416_NUM_5G_40_TARGET_POWERS,
1127 &targetPowerHt40, 8, true);
1128 ath9k_hw_get_legacy_target_powers(ah, chan,
1129 pEepData->calTargetPower5G,
1130 AR5416_NUM_5G_20_TARGET_POWERS,
1131 &targetPowerOfdmExt, 4, true);
1135 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1136 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1137 (pCtlMode[ctlMode] == CTL_2GHT40);
1139 freq = centers.synth_center;
1140 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1141 freq = centers.ext_center;
1143 freq = centers.ctl_center;
1145 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1146 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1147 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1149 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1150 if ((((cfgCtl & ~CTL_MODE_M) |
1151 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1152 pEepData->ctlIndex[i]) ||
1153 (((cfgCtl & ~CTL_MODE_M) |
1154 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1155 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1156 rep = &(pEepData->ctlData[i]);
1158 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1159 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1160 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1162 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1163 twiceMaxEdgePower = min(twiceMaxEdgePower,
1166 twiceMaxEdgePower = twiceMinEdgePower;
1172 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1174 switch (pCtlMode[ctlMode]) {
1176 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1177 targetPowerCck.tPow2x[i] =
1178 min((u16)targetPowerCck.tPow2x[i],
1184 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1185 targetPowerOfdm.tPow2x[i] =
1186 min((u16)targetPowerOfdm.tPow2x[i],
1192 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1193 targetPowerHt20.tPow2x[i] =
1194 min((u16)targetPowerHt20.tPow2x[i],
1199 targetPowerCckExt.tPow2x[0] = min((u16)
1200 targetPowerCckExt.tPow2x[0],
1205 targetPowerOfdmExt.tPow2x[0] = min((u16)
1206 targetPowerOfdmExt.tPow2x[0],
1211 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1212 targetPowerHt40.tPow2x[i] =
1213 min((u16)targetPowerHt40.tPow2x[i],
1222 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1223 ratesArray[rate18mb] = ratesArray[rate24mb] =
1224 targetPowerOfdm.tPow2x[0];
1225 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1226 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1227 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1228 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1230 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1231 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1233 if (IS_CHAN_2GHZ(chan)) {
1234 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1235 ratesArray[rate2s] = ratesArray[rate2l] =
1236 targetPowerCck.tPow2x[1];
1237 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1238 targetPowerCck.tPow2x[2];
1239 ratesArray[rate11s] = ratesArray[rate11l] =
1240 targetPowerCck.tPow2x[3];
1242 if (IS_CHAN_HT40(chan)) {
1243 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1244 ratesArray[rateHt40_0 + i] =
1245 targetPowerHt40.tPow2x[i];
1247 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1248 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1249 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1250 if (IS_CHAN_2GHZ(chan)) {
1251 ratesArray[rateExtCck] =
1252 targetPowerCckExt.tPow2x[0];
1257 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1258 struct ath9k_channel *chan,
1260 u8 twiceAntennaReduction,
1261 u8 twiceMaxRegulatoryPower,
1262 u8 powerLimit, bool test)
1264 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1265 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1266 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1267 struct modal_eep_header *pModal =
1268 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1269 int16_t ratesArray[Ar5416RateSize];
1270 int16_t txPowerIndexOffset = 0;
1271 u8 ht40PowerIncForPdadc = 2;
1272 int i, cck_ofdm_delta = 0;
1274 memset(ratesArray, 0, sizeof(ratesArray));
1276 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1277 AR5416_EEP_MINOR_VER_2) {
1278 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1281 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1282 &ratesArray[0], cfgCtl,
1283 twiceAntennaReduction,
1284 twiceMaxRegulatoryPower,
1287 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1289 regulatory->max_power_level = 0;
1290 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1291 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1292 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1293 ratesArray[i] = AR5416_MAX_RATE_POWER;
1294 if (ratesArray[i] > regulatory->max_power_level)
1295 regulatory->max_power_level = ratesArray[i];
1301 if (IS_CHAN_HT40(chan))
1303 else if (IS_CHAN_HT20(chan))
1306 regulatory->max_power_level = ratesArray[i];
1309 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1313 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1316 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1319 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1320 "Invalid chainmask configuration\n");
1327 if (AR_SREV_9280_20_OR_LATER(ah)) {
1328 for (i = 0; i < Ar5416RateSize; i++) {
1329 int8_t pwr_table_offset;
1331 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1332 EEP_PWR_TABLE_OFFSET);
1333 ratesArray[i] -= pwr_table_offset * 2;
1337 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1338 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1339 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1340 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1341 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1342 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1343 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1344 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1345 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1346 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1348 if (IS_CHAN_2GHZ(chan)) {
1349 if (OLC_FOR_AR9280_20_LATER) {
1351 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1352 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1353 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1354 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1355 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1356 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1357 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1358 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1359 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1360 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1362 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1363 ATH9K_POW_SM(ratesArray[rate2s], 24)
1364 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1365 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1366 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1367 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1368 ATH9K_POW_SM(ratesArray[rate11s], 24)
1369 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1370 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1371 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1375 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1376 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1377 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1378 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1379 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1380 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1381 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1382 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1383 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1384 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1386 if (IS_CHAN_HT40(chan)) {
1387 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1388 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1389 ht40PowerIncForPdadc, 24)
1390 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1391 ht40PowerIncForPdadc, 16)
1392 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1393 ht40PowerIncForPdadc, 8)
1394 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1395 ht40PowerIncForPdadc, 0));
1396 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1397 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1398 ht40PowerIncForPdadc, 24)
1399 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1400 ht40PowerIncForPdadc, 16)
1401 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1402 ht40PowerIncForPdadc, 8)
1403 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1404 ht40PowerIncForPdadc, 0));
1405 if (OLC_FOR_AR9280_20_LATER) {
1406 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1407 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1408 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1409 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1410 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1412 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1413 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1414 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1415 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1416 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1420 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1421 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1422 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1425 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1426 enum ath9k_hal_freq_band freq_band)
1428 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1429 struct modal_eep_header *pModal =
1430 &(eep->modalHeader[freq_band]);
1431 struct base_eep_header *pBase = &eep->baseEepHeader;
1436 if (pBase->version >= 0x0E0D &&
1437 (pModal->lna_ctl & LNA_CTL_USE_ANT1))
1438 num_ant_config += 1;
1440 return num_ant_config;
1443 static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1444 struct ath9k_channel *chan)
1446 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1447 struct modal_eep_header *pModal =
1448 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1450 return pModal->antCtrlCommon;
1453 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1455 #define EEP_DEF_SPURCHAN \
1456 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1457 struct ath_common *common = ath9k_hw_common(ah);
1459 u16 spur_val = AR_NO_SPUR;
1461 ath_dbg(common, ATH_DBG_ANI,
1462 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1463 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1465 switch (ah->config.spurmode) {
1468 case SPUR_ENABLE_IOCTL:
1469 spur_val = ah->config.spurchans[i][is2GHz];
1470 ath_dbg(common, ATH_DBG_ANI,
1471 "Getting spur val from new loc. %d\n", spur_val);
1473 case SPUR_ENABLE_EEPROM:
1474 spur_val = EEP_DEF_SPURCHAN;
1480 #undef EEP_DEF_SPURCHAN
1483 const struct eeprom_ops eep_def_ops = {
1484 .check_eeprom = ath9k_hw_def_check_eeprom,
1485 .get_eeprom = ath9k_hw_def_get_eeprom,
1486 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1487 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1488 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1489 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1490 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1491 .set_board_values = ath9k_hw_def_set_board_values,
1492 .set_addac = ath9k_hw_def_set_addac,
1493 .set_txpower = ath9k_hw_def_set_txpower,
1494 .get_spur_channel = ath9k_hw_def_get_spur_channel