2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
21 REG_WRITE(ah, reg, val);
23 if (ah->config.analog_shiftreg)
27 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
30 REG_RMW(ah, reg, ((val << shift) & mask), mask);
32 if (ah->config.analog_shiftreg)
36 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
37 int16_t targetLeft, int16_t targetRight)
41 if (srcRight == srcLeft) {
44 rv = (int16_t) (((target - srcLeft) * targetRight +
45 (srcRight - target) * targetLeft) /
46 (srcRight - srcLeft));
51 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
52 u16 *indexL, u16 *indexR)
56 if (target <= pList[0]) {
57 *indexL = *indexR = 0;
60 if (target >= pList[listSize - 1]) {
61 *indexL = *indexR = (u16) (listSize - 1);
65 for (i = 0; i < listSize - 1; i++) {
66 if (pList[i] == target) {
67 *indexL = *indexR = i;
70 if (target < pList[i + 1]) {
72 *indexR = (u16) (i + 1);
79 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
80 int eep_start_loc, int size)
86 for (addr = 0; addr < size; addr++) {
87 addrdata[i] = AR5416_EEPROM_OFFSET +
88 ((addr + eep_start_loc) << AR5416_EEPROM_S);
91 REG_READ_MULTI(ah, addrdata, data, i);
93 for (j = 0; j < i; j++) {
102 REG_READ_MULTI(ah, addrdata, data, i);
104 for (j = 0; j < i; j++) {
111 static bool ath9k_hw_nvram_read_blob(struct ath_hw *ah, u32 off,
116 if (off * sizeof(u16) > ah->eeprom_blob->size)
119 blob_data = (u16 *)ah->eeprom_blob->data;
120 *data = blob_data[off];
124 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
126 struct ath_common *common = ath9k_hw_common(ah);
130 ret = ath9k_hw_nvram_read_blob(ah, off, data);
132 ret = common->bus_ops->eeprom_read(common, off, data);
135 ath_dbg(common, EEPROM,
136 "unable to read eeprom region at offset %u\n", off);
141 int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size)
146 struct ath_common *common = ath9k_hw_common(ah);
148 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
149 ath_err(common, "Reading Magic # failed\n");
153 *swap_needed = false;
154 if (swab16(magic) == AR5416_EEPROM_MAGIC) {
155 if (ah->ah_flags & AH_NO_EEP_SWAP) {
157 "Ignoring endianness difference in EEPROM magic bytes.\n");
161 } else if (magic != AR5416_EEPROM_MAGIC) {
162 if (ath9k_hw_use_flash(ah))
166 "Invalid EEPROM Magic (0x%04x).\n", magic);
170 eepdata = (u16 *)(&ah->eeprom);
173 ath_dbg(common, EEPROM,
174 "EEPROM Endianness is not native.. Changing.\n");
176 for (i = 0; i < size; i++)
177 eepdata[i] = swab16(eepdata[i]);
183 bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size)
186 u16 *eepdata = (u16 *)(&ah->eeprom);
187 struct ath_common *common = ath9k_hw_common(ah);
189 for (i = 0; i < size; i++)
193 ath_err(common, "Bad EEPROM checksum 0x%x\n", sum);
200 bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev)
202 struct ath_common *common = ath9k_hw_common(ah);
204 if (ah->eep_ops->get_eeprom_ver(ah) != version ||
205 ah->eep_ops->get_eeprom_rev(ah) < minrev) {
206 ath_err(common, "Bad EEPROM VER 0x%04x or REV 0x%04x\n",
207 ah->eep_ops->get_eeprom_ver(ah),
208 ah->eep_ops->get_eeprom_rev(ah));
215 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
216 u8 *pVpdList, u16 numIntercepts,
221 u16 idxL = 0, idxR = 0;
223 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
224 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
225 numIntercepts, &(idxL),
229 if (idxL == numIntercepts - 1)
230 idxL = (u16) (numIntercepts - 2);
231 if (pPwrList[idxL] == pPwrList[idxR])
234 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
235 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
236 (pPwrList[idxR] - pPwrList[idxL]));
237 pRetVpdList[i] = (u8) k;
242 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
243 struct ath9k_channel *chan,
244 struct cal_target_power_leg *powInfo,
246 struct cal_target_power_leg *pNewPower,
247 u16 numRates, bool isExtTarget)
249 struct chan_centers centers;
252 int matchIndex = -1, lowIndex = -1;
255 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
256 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
258 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
259 IS_CHAN_2GHZ(chan))) {
262 for (i = 0; (i < numChannels) &&
263 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
264 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
265 IS_CHAN_2GHZ(chan))) {
268 } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
269 IS_CHAN_2GHZ(chan)) && i > 0 &&
270 freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
271 IS_CHAN_2GHZ(chan))) {
276 if ((matchIndex == -1) && (lowIndex == -1))
280 if (matchIndex != -1) {
281 *pNewPower = powInfo[matchIndex];
283 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
285 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
288 for (i = 0; i < numRates; i++) {
289 pNewPower->tPow2x[i] =
290 (u8)ath9k_hw_interpolate(freq, clo, chi,
291 powInfo[lowIndex].tPow2x[i],
292 powInfo[lowIndex + 1].tPow2x[i]);
297 void ath9k_hw_get_target_powers(struct ath_hw *ah,
298 struct ath9k_channel *chan,
299 struct cal_target_power_ht *powInfo,
301 struct cal_target_power_ht *pNewPower,
302 u16 numRates, bool isHt40Target)
304 struct chan_centers centers;
307 int matchIndex = -1, lowIndex = -1;
310 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
311 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
313 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
316 for (i = 0; (i < numChannels) &&
317 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
318 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
319 IS_CHAN_2GHZ(chan))) {
323 if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
324 IS_CHAN_2GHZ(chan)) && i > 0 &&
325 freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
326 IS_CHAN_2GHZ(chan))) {
331 if ((matchIndex == -1) && (lowIndex == -1))
335 if (matchIndex != -1) {
336 *pNewPower = powInfo[matchIndex];
338 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
340 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
343 for (i = 0; i < numRates; i++) {
344 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
346 powInfo[lowIndex].tPow2x[i],
347 powInfo[lowIndex + 1].tPow2x[i]);
352 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
353 bool is2GHz, int num_band_edges)
355 u16 twiceMaxEdgePower = MAX_RATE_POWER;
358 for (i = 0; (i < num_band_edges) &&
359 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
360 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
361 twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
363 } else if ((i > 0) &&
364 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
366 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
368 CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
370 CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
376 return twiceMaxEdgePower;
379 u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
380 u8 antenna_reduction)
382 u16 reduction = antenna_reduction;
385 * Reduce scaled Power by number of chains active
386 * to get the per chain tx power level.
388 switch (ar5416_get_ntxchains(ah->txchainmask)) {
392 reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
395 reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
399 if (power_limit > reduction)
400 power_limit -= reduction;
407 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
409 struct ath_common *common = ath9k_hw_common(ah);
410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
412 switch (ar5416_get_ntxchains(ah->txchainmask)) {
416 regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
419 regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
422 ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
427 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
428 struct ath9k_channel *chan,
430 u8 *bChans, u16 availPiers,
432 u16 *pPdGainBoundaries, u8 *pPDADCValues,
437 u16 idxL = 0, idxR = 0, numPiers;
438 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
439 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
440 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
441 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
442 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
443 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
445 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
446 u8 minPwrT4[AR5416_NUM_PD_GAINS];
447 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
450 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
452 int16_t minDelta = 0;
453 struct chan_centers centers;
454 int pdgain_boundary_default;
455 struct cal_data_per_freq *data_def = pRawDataSet;
456 struct cal_data_per_freq_4k *data_4k = pRawDataSet;
457 struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
458 bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
461 if (AR_SREV_9287(ah))
462 intercepts = AR9287_PD_GAIN_ICEPTS;
464 intercepts = AR5416_PD_GAIN_ICEPTS;
466 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
467 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
469 for (numPiers = 0; numPiers < availPiers; numPiers++) {
470 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
474 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
476 bChans, numPiers, &idxL, &idxR);
479 if (AR_SREV_9287(ah)) {
480 /* FIXME: array overrun? */
481 for (i = 0; i < numXpdGains; i++) {
482 minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
483 maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
484 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
485 data_9287[idxL].pwrPdg[i],
486 data_9287[idxL].vpdPdg[i],
490 } else if (eeprom_4k) {
491 for (i = 0; i < numXpdGains; i++) {
492 minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
493 maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
494 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
495 data_4k[idxL].pwrPdg[i],
496 data_4k[idxL].vpdPdg[i],
501 for (i = 0; i < numXpdGains; i++) {
502 minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
503 maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
504 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
505 data_def[idxL].pwrPdg[i],
506 data_def[idxL].vpdPdg[i],
512 for (i = 0; i < numXpdGains; i++) {
513 if (AR_SREV_9287(ah)) {
514 pVpdL = data_9287[idxL].vpdPdg[i];
515 pPwrL = data_9287[idxL].pwrPdg[i];
516 pVpdR = data_9287[idxR].vpdPdg[i];
517 pPwrR = data_9287[idxR].pwrPdg[i];
518 } else if (eeprom_4k) {
519 pVpdL = data_4k[idxL].vpdPdg[i];
520 pPwrL = data_4k[idxL].pwrPdg[i];
521 pVpdR = data_4k[idxR].vpdPdg[i];
522 pPwrR = data_4k[idxR].pwrPdg[i];
524 pVpdL = data_def[idxL].vpdPdg[i];
525 pPwrL = data_def[idxL].pwrPdg[i];
526 pVpdR = data_def[idxR].vpdPdg[i];
527 pPwrR = data_def[idxR].pwrPdg[i];
530 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
533 min(pPwrL[intercepts - 1],
534 pPwrR[intercepts - 1]);
537 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
541 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
546 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
548 (u8)(ath9k_hw_interpolate((u16)
553 bChans[idxL], bChans[idxR],
554 vpdTableL[i][j], vpdTableR[i][j]));
561 for (i = 0; i < numXpdGains; i++) {
562 if (i == (numXpdGains - 1))
563 pPdGainBoundaries[i] =
564 (u16)(maxPwrT4[i] / 2);
566 pPdGainBoundaries[i] =
567 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
569 pPdGainBoundaries[i] =
570 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
575 if (AR_SREV_9280_20_OR_LATER(ah))
576 ss = (int16_t)(0 - (minPwrT4[i] / 2));
580 ss = (int16_t)((pPdGainBoundaries[i - 1] -
582 tPdGainOverlap + 1 + minDelta);
584 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
585 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
587 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
588 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
589 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
593 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
594 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
596 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
597 tgtIndex : sizeCurrVpdTable;
599 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
600 pPDADCValues[k++] = vpdTableI[i][ss++];
603 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
604 vpdTableI[i][sizeCurrVpdTable - 2]);
605 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
607 if (tgtIndex >= maxIndex) {
608 while ((ss <= tgtIndex) &&
609 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
610 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
611 (ss - maxIndex + 1) * vpdStep));
612 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
620 pdgain_boundary_default = 58;
622 pdgain_boundary_default = pPdGainBoundaries[i - 1];
624 while (i < AR5416_PD_GAINS_IN_MASK) {
625 pPdGainBoundaries[i] = pdgain_boundary_default;
629 while (k < AR5416_NUM_PDADC_VALUES) {
630 pPDADCValues[k] = pPDADCValues[k - 1];
635 int ath9k_hw_eeprom_init(struct ath_hw *ah)
639 if (AR_SREV_9300_20_OR_LATER(ah))
640 ah->eep_ops = &eep_ar9300_ops;
641 else if (AR_SREV_9287(ah)) {
642 ah->eep_ops = &eep_ar9287_ops;
643 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
644 ah->eep_ops = &eep_4k_ops;
646 ah->eep_ops = &eep_def_ops;
649 if (!ah->eep_ops->fill_eeprom(ah))
652 status = ah->eep_ops->check_eeprom(ah);