2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include "ar9003_mac.h"
19 static void ar9003_hw_rx_enable(struct ath_hw *hw)
21 REG_WRITE(hw, AR_CR, 0);
24 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
28 checksum = ads->info + ads->link
29 + ads->data0 + ads->ctl3
30 + ads->data1 + ads->ctl5
31 + ads->data2 + ads->ctl7
32 + ads->data3 + ads->ctl9;
34 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
37 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
39 struct ar9003_txc *ads = ds;
42 ads->ctl10 &= ~AR_TxPtrChkSum;
43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
46 static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
48 struct ar9003_txc *ads = ds;
50 *ds_link = &ads->link;
53 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
57 struct ath9k_hw_capabilities *pCap = &ah->caps;
59 struct ath_common *common = ath9k_hw_common(ah);
61 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
62 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
64 isr = REG_READ(ah, AR_ISR);
67 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
71 if (!isr && !sync_cause)
75 if (isr & AR_ISR_BCNMISC) {
77 isr2 = REG_READ(ah, AR_ISR_S2);
79 mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
81 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
83 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
85 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
87 mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
89 mask2 |= ((isr2 & AR_ISR_S2_CST) <<
91 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
93 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
94 MAP_ISR_S2_BB_WATCHDOG);
96 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
97 REG_WRITE(ah, AR_ISR_S2, isr2);
98 isr &= ~AR_ISR_BCNMISC;
102 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
103 isr = REG_READ(ah, AR_ISR_RAC);
105 if (isr == 0xffffffff) {
110 *masked = isr & ATH9K_INT_COMMON;
112 if (ah->config.rx_intr_mitigation)
113 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
114 *masked |= ATH9K_INT_RXLP;
116 if (ah->config.tx_intr_mitigation)
117 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
118 *masked |= ATH9K_INT_TX;
120 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
121 *masked |= ATH9K_INT_RXLP;
123 if (isr & AR_ISR_HP_RXOK)
124 *masked |= ATH9K_INT_RXHP;
126 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
127 *masked |= ATH9K_INT_TX;
129 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
131 s0 = REG_READ(ah, AR_ISR_S0);
132 REG_WRITE(ah, AR_ISR_S0, s0);
133 s1 = REG_READ(ah, AR_ISR_S1);
134 REG_WRITE(ah, AR_ISR_S1, s1);
136 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
141 if (isr & AR_ISR_GENTMR) {
144 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
145 s5 = REG_READ(ah, AR_ISR_S5_S);
147 s5 = REG_READ(ah, AR_ISR_S5);
149 ah->intr_gen_timer_trigger =
150 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
152 ah->intr_gen_timer_thresh =
153 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
155 if (ah->intr_gen_timer_trigger)
156 *masked |= ATH9K_INT_GENTIMER;
158 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
159 REG_WRITE(ah, AR_ISR_S5, s5);
160 isr &= ~AR_ISR_GENTMR;
167 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
168 REG_WRITE(ah, AR_ISR, isr);
170 (void) REG_READ(ah, AR_ISR);
173 if (*masked & ATH9K_INT_BB_WATCHDOG)
174 ar9003_hw_bb_watchdog_read(ah);
178 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
179 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
180 REG_WRITE(ah, AR_RC, 0);
181 *masked |= ATH9K_INT_FATAL;
184 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
185 ath_print(common, ATH_DBG_INTERRUPT,
186 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
188 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
189 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
195 static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
196 bool is_firstseg, bool is_lastseg,
197 const void *ds0, dma_addr_t buf_addr,
200 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
201 unsigned int descid = 0;
203 ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
204 (1 << AR_TxRxDesc_S) |
205 (1 << AR_CtrlStat_S) |
206 (qcu << AR_TxQcuNum_S) | 0x17;
208 ads->data0 = buf_addr;
213 ads->ctl3 = (seglen << AR_BufLen_S);
214 ads->ctl3 &= AR_BufLen;
216 /* Fill in pointer checksum and descriptor id */
217 ads->ctl10 = ar9003_calc_ptr_chksum(ads);
218 ads->ctl10 |= (descid << AR_TxDescId_S);
221 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
222 } else if (is_lastseg) {
225 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
226 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
228 /* XXX Intermediate descriptor in a multi-descriptor frame.*/
230 ads->ctl12 = AR_TxMore;
236 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
237 struct ath_tx_status *ts)
239 struct ar9003_txs *ads;
242 ads = &ah->ts_ring[ah->ts_tail];
244 status = ACCESS_ONCE(ads->status8);
245 if ((status & AR_TxDone) == 0)
248 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
250 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
251 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
252 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
253 "Tx Descriptor error %x\n", ads->ds_info);
254 memset(ads, 0, sizeof(*ads));
258 if (status & AR_TxOpExceeded)
259 ts->ts_status |= ATH9K_TXERR_XTXOP;
260 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
261 ts->ts_seqnum = MS(status, AR_SeqNum);
262 ts->tid = MS(status, AR_TxTid);
264 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
265 ts->desc_id = MS(ads->status1, AR_TxDescId);
266 ts->ts_tstamp = ads->status4;
270 status = ACCESS_ONCE(ads->status2);
271 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
272 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
273 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
274 if (status & AR_TxBaStatus) {
275 ts->ts_flags |= ATH9K_TX_BA;
276 ts->ba_low = ads->status5;
277 ts->ba_high = ads->status6;
280 status = ACCESS_ONCE(ads->status3);
281 if (status & AR_ExcessiveRetries)
282 ts->ts_status |= ATH9K_TXERR_XRETRY;
283 if (status & AR_Filtered)
284 ts->ts_status |= ATH9K_TXERR_FILT;
285 if (status & AR_FIFOUnderrun) {
286 ts->ts_status |= ATH9K_TXERR_FIFO;
287 ath9k_hw_updatetxtriglevel(ah, true);
289 if (status & AR_TxTimerExpired)
290 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
291 if (status & AR_DescCfgErr)
292 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
293 if (status & AR_TxDataUnderrun) {
294 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
295 ath9k_hw_updatetxtriglevel(ah, true);
297 if (status & AR_TxDelimUnderrun) {
298 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
299 ath9k_hw_updatetxtriglevel(ah, true);
301 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
302 ts->ts_longretry = MS(status, AR_DataFailCnt);
303 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
305 status = ACCESS_ONCE(ads->status7);
306 ts->ts_rssi = MS(status, AR_TxRSSICombined);
307 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
308 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
309 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
311 memset(ads, 0, sizeof(*ads));
316 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
317 u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
318 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
320 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
322 if (txpower > ah->txpower_limit)
323 txpower = ah->txpower_limit;
325 txpower += ah->txpower_indexoffset;
329 ads->ctl11 = (pktlen & AR_FrameLen)
330 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
331 | SM(txpower, AR_XmitPower)
332 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
333 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
334 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
335 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
338 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
339 | SM(type, AR_FrameType)
340 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
341 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
342 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
344 ads->ctl17 = SM(keyType, AR_EncrType) |
345 (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
347 ads->ctl19 = AR_Not_Sounding;
354 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
356 u32 durUpdateEn, u32 rtsctsRate,
358 struct ath9k_11n_rate_series series[],
359 u32 nseries, u32 flags)
361 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
362 struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
365 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
368 if (flags & ATH9K_TXDESC_RTSENA) {
369 ctl11 &= ~AR_CTSEnable;
370 ctl11 |= AR_RTSEnable;
372 ctl11 &= ~AR_RTSEnable;
373 ctl11 |= AR_CTSEnable;
378 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
381 ads->ctl13 = set11nTries(series, 0)
382 | set11nTries(series, 1)
383 | set11nTries(series, 2)
384 | set11nTries(series, 3)
385 | (durUpdateEn ? AR_DurUpdateEna : 0)
386 | SM(0, AR_BurstDur);
388 ads->ctl14 = set11nRate(series, 0)
389 | set11nRate(series, 1)
390 | set11nRate(series, 2)
391 | set11nRate(series, 3);
393 ads->ctl15 = set11nPktDurRTSCTS(series, 0)
394 | set11nPktDurRTSCTS(series, 1);
396 ads->ctl16 = set11nPktDurRTSCTS(series, 2)
397 | set11nPktDurRTSCTS(series, 3);
399 ads->ctl18 = set11nRateFlags(series, 0)
400 | set11nRateFlags(series, 1)
401 | set11nRateFlags(series, 2)
402 | set11nRateFlags(series, 3)
403 | SM(rtsctsRate, AR_RTSCTSRate);
404 ads->ctl19 = AR_Not_Sounding;
406 last_ads->ctl13 = ads->ctl13;
407 last_ads->ctl14 = ads->ctl14;
410 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
413 #define FIRST_DESC_NDELIMS 60
414 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
416 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
418 if (ah->ent_mode & AR_ENT_OTP_MPSD) {
421 * Add delimiter when using RTS/CTS with aggregation
422 * and non enterprise AR9003 card
425 ndelim = MS(ctl17, AR_PadDelim);
427 if (ndelim < FIRST_DESC_NDELIMS) {
428 aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
429 ndelim = FIRST_DESC_NDELIMS;
432 ctl17 &= ~AR_AggrLen;
433 ctl17 |= SM(aggrLen, AR_AggrLen);
435 ctl17 &= ~AR_PadDelim;
436 ctl17 |= SM(ndelim, AR_PadDelim);
440 ads->ctl17 &= ~AR_AggrLen;
441 ads->ctl17 |= SM(aggrLen, AR_AggrLen);
445 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
448 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
451 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
454 * We use a stack variable to manipulate ctl6 to reduce uncached
455 * read modify, modfiy, write.
458 ctl17 &= ~AR_PadDelim;
459 ctl17 |= SM(numDelims, AR_PadDelim);
463 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
465 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
467 ads->ctl12 |= AR_IsAggr;
468 ads->ctl12 &= ~AR_MoreAggr;
469 ads->ctl17 &= ~AR_PadDelim;
472 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
474 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
476 ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
479 static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
482 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
484 ads->ctl13 &= ~AR_BurstDur;
485 ads->ctl13 |= SM(burstDuration, AR_BurstDur);
489 static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
492 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
495 ads->ctl11 |= AR_VirtMoreFrag;
497 ads->ctl11 &= ~AR_VirtMoreFrag;
500 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
502 struct ar9003_txc *ads = ds;
504 ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
506 EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc);
508 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
510 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
512 ops->rx_enable = ar9003_hw_rx_enable;
513 ops->set_desc_link = ar9003_hw_set_desc_link;
514 ops->get_desc_link = ar9003_hw_get_desc_link;
515 ops->get_isr = ar9003_hw_get_isr;
516 ops->fill_txdesc = ar9003_hw_fill_txdesc;
517 ops->proc_txdesc = ar9003_hw_proc_txdesc;
518 ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
519 ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
520 ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
521 ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
522 ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
523 ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
524 ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
525 ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
528 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
530 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
532 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
534 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
535 enum ath9k_rx_qtype qtype)
537 if (qtype == ATH9K_RX_QUEUE_HP)
538 REG_WRITE(ah, AR_HP_RXDP, rxdp);
540 REG_WRITE(ah, AR_LP_RXDP, rxdp);
542 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
544 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
547 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
550 /* TODO: byte swap on big endian for ar9300_10 */
552 if ((rxsp->status11 & AR_RxDone) == 0)
555 if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
558 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
567 rxs->rs_datalen = rxsp->status2 & AR_DataLen;
568 rxs->rs_tstamp = rxsp->status3;
571 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
572 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
573 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
574 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
575 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
576 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
577 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
579 if (rxsp->status11 & AR_RxKeyIdxValid)
580 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
582 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
584 rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
585 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
587 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
588 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
589 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
590 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
591 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
593 rxs->evm0 = rxsp->status6;
594 rxs->evm1 = rxsp->status7;
595 rxs->evm2 = rxsp->status8;
596 rxs->evm3 = rxsp->status9;
597 rxs->evm4 = (rxsp->status10 & 0xffff);
599 if (rxsp->status11 & AR_PreDelimCRCErr)
600 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
602 if (rxsp->status11 & AR_PostDelimCRCErr)
603 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
605 if (rxsp->status11 & AR_DecryptBusyErr)
606 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
608 if ((rxsp->status11 & AR_RxFrameOK) == 0) {
610 * AR_CRCErr will bet set to true if we're on the last
611 * subframe and the AR_PostDelimCRCErr is caught.
612 * In a way this also gives us a guarantee that when
613 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
614 * possibly be reviewing the last subframe. AR_CRCErr
615 * is the CRC of the actual data.
617 if (rxsp->status11 & AR_CRCErr) {
618 rxs->rs_status |= ATH9K_RXERR_CRC;
619 } else if (rxsp->status11 & AR_PHYErr) {
620 phyerr = MS(rxsp->status11, AR_PHYErrCode);
622 * If we reach a point here where AR_PostDelimCRCErr is
623 * true it implies we're *not* on the last subframe. In
624 * in that case that we know already that the CRC of
625 * the frame was OK, and MAC would send an ACK for that
626 * subframe, even if we did get a phy error of type
627 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
628 * to frame that are prior to the last subframe.
629 * The AR_PostDelimCRCErr is the CRC for the MPDU
630 * delimiter, which contains the 4 reserved bits,
631 * the MPDU length (12 bits), and follows the MPDU
632 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
634 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
635 (rxsp->status11 & AR_PostDelimCRCErr)) {
638 rxs->rs_status |= ATH9K_RXERR_PHY;
639 rxs->rs_phyerr = phyerr;
642 } else if (rxsp->status11 & AR_DecryptCRCErr) {
643 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
644 } else if (rxsp->status11 & AR_MichaelErr) {
645 rxs->rs_status |= ATH9K_RXERR_MIC;
646 } else if (rxsp->status11 & AR_KeyMiss)
647 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
652 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
654 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
658 memset((void *) ah->ts_ring, 0,
659 ah->ts_size * sizeof(struct ar9003_txs));
661 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
662 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
663 ah->ts_paddr_start, ah->ts_paddr_end,
664 ah->ts_ring, ah->ts_size);
666 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
667 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
670 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
675 ah->ts_paddr_start = ts_paddr_start;
676 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
678 ah->ts_ring = (struct ar9003_txs *) ts_start;
680 ath9k_hw_reset_txstatus_ring(ah);
682 EXPORT_SYMBOL(ath9k_hw_setup_statusring);