2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_phy.h"
19 #include "ar9003_eeprom.h"
21 #define COMP_HDR_LEN 4
22 #define COMP_CKSUM_LEN 2
24 #define AR_CH0_TOP (0x00016288)
25 #define AR_CH0_TOP_XPABIASLVL (0x300)
26 #define AR_CH0_TOP_XPABIASLVL_S (8)
28 #define AR_CH0_THERM (0x00016290)
29 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31 #define AR_CH0_THERM_XPASHORT2GND 0x4
32 #define AR_CH0_THERM_XPASHORT2GND_S 2
34 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
35 #define AR_SWITCH_TABLE_COM_ALL_S (0)
37 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
40 #define AR_SWITCH_TABLE_ALL (0xfff)
41 #define AR_SWITCH_TABLE_ALL_S (0)
43 #define LE16(x) __constant_cpu_to_le16(x)
44 #define LE32(x) __constant_cpu_to_le32(x)
46 /* Local defines to distinguish between extension and control CTL's */
47 #define EXT_ADDITIVE (0x8000)
48 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
57 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
60 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
62 #define EEPROM_DATA_LEN_9485 1088
64 static int ar9003_hw_power_interpolate(int32_t x,
65 int32_t *px, int32_t *py, u_int16_t np);
68 static const struct ar9300_eeprom ar9300_default = {
71 .macAddr = {1, 2, 3, 4, 5, 6},
72 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
73 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
75 .regDmn = { LE16(0), LE16(0x1f) },
76 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
78 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
82 .blueToothOptions = 0,
84 .deviceType = 5, /* takes lower byte in eeprom location */
85 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
86 .params_for_tuning_caps = {0, 0},
87 .featureEnable = 0x0c,
89 * bit0 - enable tx temp comp - disabled
90 * bit1 - enable tx volt comp - disabled
91 * bit2 - enable fastClock - enabled
92 * bit3 - enable doubling - enabled
93 * bit4 - enable internal regulator - disabled
94 * bit5 - enable pa predistortion - disabled
96 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
97 .eepromWriteEnableGpio = 3,
100 .rxBandSelectGpio = 0xff,
105 /* ar9300_modal_eep_header 2g */
106 /* 4 idle,t1,t2,b(4 bits per setting) */
107 .antCtrlCommon = LE32(0x110),
108 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
109 .antCtrlCommon2 = LE32(0x22222),
112 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
113 * rx1, rx12, b (2 bits each)
115 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
118 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
119 * for ar9280 (0xa20c/b20c 5:0)
121 .xatten1DB = {0, 0, 0},
124 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
125 * for ar9280 (0xa20c/b20c 16:12
127 .xatten1Margin = {0, 0, 0},
132 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
133 * channels in usual fbin coding format
135 .spurChans = {0, 0, 0, 0, 0},
138 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
139 * if the register is per chain
141 .noiseFloorThreshCh = {-1, 0, 0},
142 .ob = {1, 1, 1},/* 3 chain */
143 .db_stage2 = {1, 1, 1}, /* 3 chain */
144 .db_stage3 = {0, 0, 0},
145 .db_stage4 = {0, 0, 0},
147 .txFrameToDataStart = 0x0e,
148 .txFrameToPaOn = 0x0e,
149 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
151 .switchSettling = 0x2c,
152 .adcDesiredSize = -30,
155 .txFrameToXpaOn = 0xe,
157 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
158 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
160 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
164 .ant_div_control = 0,
165 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
172 /* ar9300_cal_data_per_freq_op_loop 2g */
174 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
175 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
176 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
178 .calTarget_freqbin_Cck = {
182 .calTarget_freqbin_2G = {
187 .calTarget_freqbin_2GHT20 = {
192 .calTarget_freqbin_2GHT40 = {
197 .calTargetPowerCck = {
198 /* 1L-5L,5S,11L,11S */
199 { {36, 36, 36, 36} },
200 { {36, 36, 36, 36} },
202 .calTargetPower2G = {
204 { {32, 32, 28, 24} },
205 { {32, 32, 28, 24} },
206 { {32, 32, 28, 24} },
208 .calTargetPower2GHT20 = {
209 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
210 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
211 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
213 .calTargetPower2GHT40 = {
214 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
215 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
216 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
219 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
220 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
250 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
251 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
252 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
253 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
257 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
258 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
259 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
264 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
265 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
271 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
272 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
273 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
274 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
278 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
279 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
280 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
284 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
285 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
286 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
291 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
292 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
293 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
298 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
299 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
300 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
301 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
305 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
306 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
307 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
309 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
310 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
311 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
313 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
314 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
315 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
317 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
318 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
319 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
322 /* 4 idle,t1,t2,b (4 bits per setting) */
323 .antCtrlCommon = LE32(0x110),
324 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
325 .antCtrlCommon2 = LE32(0x22222),
326 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
328 LE16(0x000), LE16(0x000), LE16(0x000),
330 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
331 .xatten1DB = {0, 0, 0},
334 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
335 * for merlin (0xa20c/b20c 16:12
337 .xatten1Margin = {0, 0, 0},
340 /* spurChans spur channels in usual fbin coding format */
341 .spurChans = {0, 0, 0, 0, 0},
342 /* noiseFloorThreshCh Check if the register is per chain */
343 .noiseFloorThreshCh = {-1, 0, 0},
344 .ob = {3, 3, 3}, /* 3 chain */
345 .db_stage2 = {3, 3, 3}, /* 3 chain */
346 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
347 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
349 .txFrameToDataStart = 0x0e,
350 .txFrameToPaOn = 0x0e,
351 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
353 .switchSettling = 0x2d,
354 .adcDesiredSize = -30,
357 .txFrameToXpaOn = 0xe,
359 .papdRateMaskHt20 = LE32(0x0c80c080),
360 .papdRateMaskHt40 = LE32(0x0080c080),
362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
368 .xatten1DBLow = {0, 0, 0},
369 .xatten1MarginLow = {0, 0, 0},
370 .xatten1DBHigh = {0, 0, 0},
371 .xatten1MarginHigh = {0, 0, 0}
416 .calTarget_freqbin_5G = {
426 .calTarget_freqbin_5GHT20 = {
436 .calTarget_freqbin_5GHT40 = {
446 .calTargetPower5G = {
448 { {20, 20, 20, 10} },
449 { {20, 20, 20, 10} },
450 { {20, 20, 20, 10} },
451 { {20, 20, 20, 10} },
452 { {20, 20, 20, 10} },
453 { {20, 20, 20, 10} },
454 { {20, 20, 20, 10} },
455 { {20, 20, 20, 10} },
457 .calTargetPower5GHT20 = {
459 * 0_8_16,1-3_9-11_17-19,
460 * 4,5,6,7,12,13,14,15,20,21,22,23
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
466 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
467 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
468 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
469 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 .calTargetPower5GHT40 = {
473 * 0_8_16,1-3_9-11_17-19,
474 * 4,5,6,7,12,13,14,15,20,21,22,23
476 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
478 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
479 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
480 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
481 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
482 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
483 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
486 0x10, 0x16, 0x18, 0x40, 0x46,
487 0x48, 0x30, 0x36, 0x38
491 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
492 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
493 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
494 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
495 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
496 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
497 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
498 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
501 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
502 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
503 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
504 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
505 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
506 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
507 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
508 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
512 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
513 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
514 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
515 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
516 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
517 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
518 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
519 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
523 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
524 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
525 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
526 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
527 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
528 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
529 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
530 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
534 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
535 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
536 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
537 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
538 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
539 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
540 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
541 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
545 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
546 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
547 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
548 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
549 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
550 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
551 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
552 /* Data[5].ctlEdges[7].bChannel */ 0xFF
556 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
557 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
558 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
559 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
560 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
561 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
562 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
563 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
567 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
568 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
569 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
570 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
571 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
572 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
573 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
574 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
578 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
579 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
580 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
581 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
582 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
583 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
584 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
585 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
591 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
592 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
598 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
603 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
604 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
609 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
610 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
615 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
616 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
621 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
622 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
627 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
628 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
633 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
634 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
639 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
640 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
646 static const struct ar9300_eeprom ar9300_x113 = {
648 .templateVersion = 6,
649 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
650 .custData = {"x113-023-f0000"},
652 .regDmn = { LE16(0), LE16(0x1f) },
653 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
655 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
659 .blueToothOptions = 0,
661 .deviceType = 5, /* takes lower byte in eeprom location */
662 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
663 .params_for_tuning_caps = {0, 0},
664 .featureEnable = 0x0d,
666 * bit0 - enable tx temp comp - disabled
667 * bit1 - enable tx volt comp - disabled
668 * bit2 - enable fastClock - enabled
669 * bit3 - enable doubling - enabled
670 * bit4 - enable internal regulator - disabled
671 * bit5 - enable pa predistortion - disabled
673 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
674 .eepromWriteEnableGpio = 6,
675 .wlanDisableGpio = 0,
677 .rxBandSelectGpio = 0xff,
682 /* ar9300_modal_eep_header 2g */
683 /* 4 idle,t1,t2,b(4 bits per setting) */
684 .antCtrlCommon = LE32(0x110),
685 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
686 .antCtrlCommon2 = LE32(0x44444),
689 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
690 * rx1, rx12, b (2 bits each)
692 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
695 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
696 * for ar9280 (0xa20c/b20c 5:0)
698 .xatten1DB = {0, 0, 0},
701 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
702 * for ar9280 (0xa20c/b20c 16:12
704 .xatten1Margin = {0, 0, 0},
709 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
710 * channels in usual fbin coding format
712 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
715 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
716 * if the register is per chain
718 .noiseFloorThreshCh = {-1, 0, 0},
719 .ob = {1, 1, 1},/* 3 chain */
720 .db_stage2 = {1, 1, 1}, /* 3 chain */
721 .db_stage3 = {0, 0, 0},
722 .db_stage4 = {0, 0, 0},
724 .txFrameToDataStart = 0x0e,
725 .txFrameToPaOn = 0x0e,
726 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
728 .switchSettling = 0x2c,
729 .adcDesiredSize = -30,
732 .txFrameToXpaOn = 0xe,
734 .papdRateMaskHt20 = LE32(0x0c80c080),
735 .papdRateMaskHt40 = LE32(0x0080c080),
737 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
741 .ant_div_control = 0,
742 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
749 /* ar9300_cal_data_per_freq_op_loop 2g */
751 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
752 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
753 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
755 .calTarget_freqbin_Cck = {
759 .calTarget_freqbin_2G = {
764 .calTarget_freqbin_2GHT20 = {
769 .calTarget_freqbin_2GHT40 = {
774 .calTargetPowerCck = {
775 /* 1L-5L,5S,11L,11S */
776 { {34, 34, 34, 34} },
777 { {34, 34, 34, 34} },
779 .calTargetPower2G = {
781 { {34, 34, 32, 32} },
782 { {34, 34, 32, 32} },
783 { {34, 34, 32, 32} },
785 .calTargetPower2GHT20 = {
786 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
787 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
788 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
790 .calTargetPower2GHT40 = {
791 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
792 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
793 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
796 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
797 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
827 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
828 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
829 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
830 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
834 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
835 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
836 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
841 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
842 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
848 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
849 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
850 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
851 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
855 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
856 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
857 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
861 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
862 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
863 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
868 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
869 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
870 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
875 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
876 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
877 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
878 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
882 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
883 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
884 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
886 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
887 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
888 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
890 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
891 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
892 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
894 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
895 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
896 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
899 /* 4 idle,t1,t2,b (4 bits per setting) */
900 .antCtrlCommon = LE32(0x220),
901 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
902 .antCtrlCommon2 = LE32(0x11111),
903 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
905 LE16(0x150), LE16(0x150), LE16(0x150),
907 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
908 .xatten1DB = {0, 0, 0},
911 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
912 * for merlin (0xa20c/b20c 16:12
914 .xatten1Margin = {0, 0, 0},
917 /* spurChans spur channels in usual fbin coding format */
918 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
919 /* noiseFloorThreshCh Check if the register is per chain */
920 .noiseFloorThreshCh = {-1, 0, 0},
921 .ob = {3, 3, 3}, /* 3 chain */
922 .db_stage2 = {3, 3, 3}, /* 3 chain */
923 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
924 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
926 .txFrameToDataStart = 0x0e,
927 .txFrameToPaOn = 0x0e,
928 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
930 .switchSettling = 0x2d,
931 .adcDesiredSize = -30,
934 .txFrameToXpaOn = 0xe,
936 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
937 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
939 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
944 .tempSlopeHigh = 105,
945 .xatten1DBLow = {0, 0, 0},
946 .xatten1MarginLow = {0, 0, 0},
947 .xatten1DBHigh = {0, 0, 0},
948 .xatten1MarginHigh = {0, 0, 0}
993 .calTarget_freqbin_5G = {
1003 .calTarget_freqbin_5GHT20 = {
1013 .calTarget_freqbin_5GHT40 = {
1023 .calTargetPower5G = {
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1027 { {42, 40, 40, 34} },
1028 { {42, 40, 40, 34} },
1029 { {42, 40, 40, 34} },
1030 { {42, 40, 40, 34} },
1031 { {42, 40, 40, 34} },
1032 { {42, 40, 40, 34} },
1034 .calTargetPower5GHT20 = {
1036 * 0_8_16,1-3_9-11_17-19,
1037 * 4,5,6,7,12,13,14,15,20,21,22,23
1039 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1040 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1041 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1042 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1043 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1044 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1045 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1046 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1048 .calTargetPower5GHT40 = {
1050 * 0_8_16,1-3_9-11_17-19,
1051 * 4,5,6,7,12,13,14,15,20,21,22,23
1053 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1054 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1055 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1056 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1057 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1058 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1059 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1060 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1063 0x10, 0x16, 0x18, 0x40, 0x46,
1064 0x48, 0x30, 0x36, 0x38
1068 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1069 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1070 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1071 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1072 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1073 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1074 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1075 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1078 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1079 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1080 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1081 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1082 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1083 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1084 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1085 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1089 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1090 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1091 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1092 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1093 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1094 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1095 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1096 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1100 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1101 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1102 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1103 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1104 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1105 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1106 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1107 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1111 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1112 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1113 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1114 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1115 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1116 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1117 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1118 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1122 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1123 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1124 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1125 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1126 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1127 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1128 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1129 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1133 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1134 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1135 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1136 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1137 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1138 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1139 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1140 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1144 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1145 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1146 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1147 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1148 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1149 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1150 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1151 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1155 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1156 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1157 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1158 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1159 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1160 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1161 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1162 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1165 .ctlPowerData_5G = {
1168 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1169 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1175 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1180 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1181 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1186 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1187 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1192 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1193 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1198 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1199 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1204 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1205 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1210 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1211 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1216 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1217 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1224 static const struct ar9300_eeprom ar9300_h112 = {
1226 .templateVersion = 3,
1227 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1228 .custData = {"h112-241-f0000"},
1230 .regDmn = { LE16(0), LE16(0x1f) },
1231 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1233 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1237 .blueToothOptions = 0,
1239 .deviceType = 5, /* takes lower byte in eeprom location */
1240 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1241 .params_for_tuning_caps = {0, 0},
1242 .featureEnable = 0x0d,
1244 * bit0 - enable tx temp comp - disabled
1245 * bit1 - enable tx volt comp - disabled
1246 * bit2 - enable fastClock - enabled
1247 * bit3 - enable doubling - enabled
1248 * bit4 - enable internal regulator - disabled
1249 * bit5 - enable pa predistortion - disabled
1251 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1252 .eepromWriteEnableGpio = 6,
1253 .wlanDisableGpio = 0,
1255 .rxBandSelectGpio = 0xff,
1260 /* ar9300_modal_eep_header 2g */
1261 /* 4 idle,t1,t2,b(4 bits per setting) */
1262 .antCtrlCommon = LE32(0x110),
1263 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1264 .antCtrlCommon2 = LE32(0x44444),
1267 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1268 * rx1, rx12, b (2 bits each)
1270 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1273 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1274 * for ar9280 (0xa20c/b20c 5:0)
1276 .xatten1DB = {0, 0, 0},
1279 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1280 * for ar9280 (0xa20c/b20c 16:12
1282 .xatten1Margin = {0, 0, 0},
1287 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1288 * channels in usual fbin coding format
1290 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1293 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1294 * if the register is per chain
1296 .noiseFloorThreshCh = {-1, 0, 0},
1297 .ob = {1, 1, 1},/* 3 chain */
1298 .db_stage2 = {1, 1, 1}, /* 3 chain */
1299 .db_stage3 = {0, 0, 0},
1300 .db_stage4 = {0, 0, 0},
1302 .txFrameToDataStart = 0x0e,
1303 .txFrameToPaOn = 0x0e,
1304 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1306 .switchSettling = 0x2c,
1307 .adcDesiredSize = -30,
1310 .txFrameToXpaOn = 0xe,
1312 .papdRateMaskHt20 = LE32(0x80c080),
1313 .papdRateMaskHt40 = LE32(0x80c080),
1315 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1319 .ant_div_control = 0,
1320 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1327 /* ar9300_cal_data_per_freq_op_loop 2g */
1329 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1330 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1331 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1333 .calTarget_freqbin_Cck = {
1337 .calTarget_freqbin_2G = {
1342 .calTarget_freqbin_2GHT20 = {
1347 .calTarget_freqbin_2GHT40 = {
1352 .calTargetPowerCck = {
1353 /* 1L-5L,5S,11L,11S */
1354 { {34, 34, 34, 34} },
1355 { {34, 34, 34, 34} },
1357 .calTargetPower2G = {
1359 { {34, 34, 32, 32} },
1360 { {34, 34, 32, 32} },
1361 { {34, 34, 32, 32} },
1363 .calTargetPower2GHT20 = {
1364 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1365 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1366 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1368 .calTargetPower2GHT40 = {
1369 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1370 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1371 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1374 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1375 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1405 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1406 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1407 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1408 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1412 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1413 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1414 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1419 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1420 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1426 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1427 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1428 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1429 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1433 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1434 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1435 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1439 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1440 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1441 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1446 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1447 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1448 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1453 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1454 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1455 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1456 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1459 .ctlPowerData_2G = {
1460 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1461 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1462 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1464 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
1465 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1466 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1468 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1469 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1470 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1472 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1473 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1474 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1477 /* 4 idle,t1,t2,b (4 bits per setting) */
1478 .antCtrlCommon = LE32(0x220),
1479 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1480 .antCtrlCommon2 = LE32(0x44444),
1481 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1483 LE16(0x150), LE16(0x150), LE16(0x150),
1485 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1486 .xatten1DB = {0, 0, 0},
1489 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1490 * for merlin (0xa20c/b20c 16:12
1492 .xatten1Margin = {0, 0, 0},
1495 /* spurChans spur channels in usual fbin coding format */
1496 .spurChans = {0, 0, 0, 0, 0},
1497 /* noiseFloorThreshCh Check if the register is per chain */
1498 .noiseFloorThreshCh = {-1, 0, 0},
1499 .ob = {3, 3, 3}, /* 3 chain */
1500 .db_stage2 = {3, 3, 3}, /* 3 chain */
1501 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1502 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1504 .txFrameToDataStart = 0x0e,
1505 .txFrameToPaOn = 0x0e,
1506 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1508 .switchSettling = 0x2d,
1509 .adcDesiredSize = -30,
1512 .txFrameToXpaOn = 0xe,
1514 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1515 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1522 .tempSlopeHigh = 50,
1523 .xatten1DBLow = {0, 0, 0},
1524 .xatten1MarginLow = {0, 0, 0},
1525 .xatten1DBHigh = {0, 0, 0},
1526 .xatten1MarginHigh = {0, 0, 0}
1571 .calTarget_freqbin_5G = {
1581 .calTarget_freqbin_5GHT20 = {
1591 .calTarget_freqbin_5GHT40 = {
1601 .calTargetPower5G = {
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1605 { {30, 30, 28, 24} },
1606 { {30, 30, 28, 24} },
1607 { {30, 30, 28, 24} },
1608 { {30, 30, 28, 24} },
1609 { {30, 30, 28, 24} },
1610 { {30, 30, 28, 24} },
1612 .calTargetPower5GHT20 = {
1614 * 0_8_16,1-3_9-11_17-19,
1615 * 4,5,6,7,12,13,14,15,20,21,22,23
1617 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1618 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1619 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1620 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1621 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1622 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1623 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1624 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1626 .calTargetPower5GHT40 = {
1628 * 0_8_16,1-3_9-11_17-19,
1629 * 4,5,6,7,12,13,14,15,20,21,22,23
1631 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1632 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1633 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1634 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1635 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1636 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1637 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1638 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1641 0x10, 0x16, 0x18, 0x40, 0x46,
1642 0x48, 0x30, 0x36, 0x38
1646 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1647 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1648 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1649 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1650 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1651 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1652 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1653 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1656 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1657 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1658 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1659 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1660 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1661 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1662 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1663 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1667 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1668 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1669 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1670 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1671 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1672 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1673 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1674 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1678 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1679 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1680 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1681 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1682 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1683 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1684 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1685 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1689 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1690 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1691 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1692 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1693 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1694 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1695 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1696 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1700 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1701 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1702 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1703 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1704 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1705 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1706 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1707 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1711 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1712 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1713 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1714 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1715 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1716 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1717 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1718 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1722 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1723 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1724 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1725 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1726 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1727 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1728 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1729 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1733 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1734 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1735 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1736 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1737 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1738 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1739 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1740 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1743 .ctlPowerData_5G = {
1746 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1747 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1752 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1753 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1758 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1759 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1764 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1765 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1770 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1771 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1776 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1777 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1782 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1783 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1788 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1789 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1794 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1795 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1802 static const struct ar9300_eeprom ar9300_x112 = {
1804 .templateVersion = 5,
1805 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1806 .custData = {"x112-041-f0000"},
1808 .regDmn = { LE16(0), LE16(0x1f) },
1809 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1811 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1815 .blueToothOptions = 0,
1817 .deviceType = 5, /* takes lower byte in eeprom location */
1818 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1819 .params_for_tuning_caps = {0, 0},
1820 .featureEnable = 0x0d,
1822 * bit0 - enable tx temp comp - disabled
1823 * bit1 - enable tx volt comp - disabled
1824 * bit2 - enable fastclock - enabled
1825 * bit3 - enable doubling - enabled
1826 * bit4 - enable internal regulator - disabled
1827 * bit5 - enable pa predistortion - disabled
1829 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1830 .eepromWriteEnableGpio = 6,
1831 .wlanDisableGpio = 0,
1833 .rxBandSelectGpio = 0xff,
1838 /* ar9300_modal_eep_header 2g */
1839 /* 4 idle,t1,t2,b(4 bits per setting) */
1840 .antCtrlCommon = LE32(0x110),
1841 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1842 .antCtrlCommon2 = LE32(0x22222),
1845 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1846 * rx1, rx12, b (2 bits each)
1848 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1851 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1852 * for ar9280 (0xa20c/b20c 5:0)
1854 .xatten1DB = {0x1b, 0x1b, 0x1b},
1857 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1858 * for ar9280 (0xa20c/b20c 16:12
1860 .xatten1Margin = {0x15, 0x15, 0x15},
1865 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1866 * channels in usual fbin coding format
1868 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1871 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1872 * if the register is per chain
1874 .noiseFloorThreshCh = {-1, 0, 0},
1875 .ob = {1, 1, 1},/* 3 chain */
1876 .db_stage2 = {1, 1, 1}, /* 3 chain */
1877 .db_stage3 = {0, 0, 0},
1878 .db_stage4 = {0, 0, 0},
1880 .txFrameToDataStart = 0x0e,
1881 .txFrameToPaOn = 0x0e,
1882 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1884 .switchSettling = 0x2c,
1885 .adcDesiredSize = -30,
1888 .txFrameToXpaOn = 0xe,
1890 .papdRateMaskHt20 = LE32(0x0c80c080),
1891 .papdRateMaskHt40 = LE32(0x0080c080),
1893 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1897 .ant_div_control = 0,
1898 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1905 /* ar9300_cal_data_per_freq_op_loop 2g */
1907 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1908 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1909 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1911 .calTarget_freqbin_Cck = {
1915 .calTarget_freqbin_2G = {
1920 .calTarget_freqbin_2GHT20 = {
1925 .calTarget_freqbin_2GHT40 = {
1930 .calTargetPowerCck = {
1931 /* 1L-5L,5S,11L,11s */
1932 { {38, 38, 38, 38} },
1933 { {38, 38, 38, 38} },
1935 .calTargetPower2G = {
1937 { {38, 38, 36, 34} },
1938 { {38, 38, 36, 34} },
1939 { {38, 38, 34, 32} },
1941 .calTargetPower2GHT20 = {
1942 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1943 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1944 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1946 .calTargetPower2GHT40 = {
1947 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1948 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1949 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1952 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1953 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1983 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1984 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1985 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1986 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1990 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1991 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1992 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1997 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1998 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2004 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2005 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2006 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2007 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2011 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2012 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2013 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2017 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2018 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2019 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2024 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2025 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2026 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2031 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2032 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2033 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2034 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2037 .ctlPowerData_2G = {
2038 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2039 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2040 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2042 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2043 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2044 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2046 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2047 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2048 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2050 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2051 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2052 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2055 /* 4 idle,t1,t2,b (4 bits per setting) */
2056 .antCtrlCommon = LE32(0x110),
2057 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2058 .antCtrlCommon2 = LE32(0x22222),
2059 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2061 LE16(0x0), LE16(0x0), LE16(0x0),
2063 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2064 .xatten1DB = {0x13, 0x19, 0x17},
2067 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2068 * for merlin (0xa20c/b20c 16:12
2070 .xatten1Margin = {0x19, 0x19, 0x19},
2073 /* spurChans spur channels in usual fbin coding format */
2074 .spurChans = {0, 0, 0, 0, 0},
2075 /* noiseFloorThreshch check if the register is per chain */
2076 .noiseFloorThreshCh = {-1, 0, 0},
2077 .ob = {3, 3, 3}, /* 3 chain */
2078 .db_stage2 = {3, 3, 3}, /* 3 chain */
2079 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2080 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2082 .txFrameToDataStart = 0x0e,
2083 .txFrameToPaOn = 0x0e,
2084 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2086 .switchSettling = 0x2d,
2087 .adcDesiredSize = -30,
2090 .txFrameToXpaOn = 0xe,
2092 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2093 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2095 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2100 .tempSlopeHigh = 105,
2101 .xatten1DBLow = {0x10, 0x14, 0x10},
2102 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2103 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2104 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2149 .calTarget_freqbin_5G = {
2159 .calTarget_freqbin_5GHT20 = {
2169 .calTarget_freqbin_5GHT40 = {
2179 .calTargetPower5G = {
2181 { {32, 32, 28, 26} },
2182 { {32, 32, 28, 26} },
2183 { {32, 32, 28, 26} },
2184 { {32, 32, 26, 24} },
2185 { {32, 32, 26, 24} },
2186 { {32, 32, 24, 22} },
2187 { {30, 30, 24, 22} },
2188 { {30, 30, 24, 22} },
2190 .calTargetPower5GHT20 = {
2192 * 0_8_16,1-3_9-11_17-19,
2193 * 4,5,6,7,12,13,14,15,20,21,22,23
2195 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2196 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2197 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2198 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2199 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2200 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2201 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2202 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2204 .calTargetPower5GHT40 = {
2206 * 0_8_16,1-3_9-11_17-19,
2207 * 4,5,6,7,12,13,14,15,20,21,22,23
2209 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2210 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2211 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2212 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2213 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2214 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2215 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2216 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2219 0x10, 0x16, 0x18, 0x40, 0x46,
2220 0x48, 0x30, 0x36, 0x38
2224 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2225 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2226 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2227 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2228 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2229 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2230 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2231 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2234 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2235 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2236 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2237 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2238 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2239 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2240 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2241 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2245 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2246 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2247 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2248 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2249 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2250 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2251 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2252 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2256 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2257 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2258 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2259 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2260 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2261 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2262 /* Data[3].ctledges[6].bchannel */ 0xFF,
2263 /* Data[3].ctledges[7].bchannel */ 0xFF,
2267 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2268 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2269 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2270 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2271 /* Data[4].ctledges[4].bchannel */ 0xFF,
2272 /* Data[4].ctledges[5].bchannel */ 0xFF,
2273 /* Data[4].ctledges[6].bchannel */ 0xFF,
2274 /* Data[4].ctledges[7].bchannel */ 0xFF,
2278 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2279 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2280 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2281 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2282 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2283 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2284 /* Data[5].ctledges[6].bchannel */ 0xFF,
2285 /* Data[5].ctledges[7].bchannel */ 0xFF
2289 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2290 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2291 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2292 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2293 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2294 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2295 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2296 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2300 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2301 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2302 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2303 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2304 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2305 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2306 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2307 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2311 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2312 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2313 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2314 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2315 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2316 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2317 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2318 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2321 .ctlPowerData_5G = {
2324 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2325 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2330 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2331 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2336 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2337 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2342 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2343 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2348 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2349 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2354 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2355 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2360 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2361 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2366 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2367 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2372 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2373 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2379 static const struct ar9300_eeprom ar9300_h116 = {
2381 .templateVersion = 4,
2382 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2383 .custData = {"h116-041-f0000"},
2385 .regDmn = { LE16(0), LE16(0x1f) },
2386 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2388 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2392 .blueToothOptions = 0,
2394 .deviceType = 5, /* takes lower byte in eeprom location */
2395 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2396 .params_for_tuning_caps = {0, 0},
2397 .featureEnable = 0x0d,
2399 * bit0 - enable tx temp comp - disabled
2400 * bit1 - enable tx volt comp - disabled
2401 * bit2 - enable fastClock - enabled
2402 * bit3 - enable doubling - enabled
2403 * bit4 - enable internal regulator - disabled
2404 * bit5 - enable pa predistortion - disabled
2406 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2407 .eepromWriteEnableGpio = 6,
2408 .wlanDisableGpio = 0,
2410 .rxBandSelectGpio = 0xff,
2415 /* ar9300_modal_eep_header 2g */
2416 /* 4 idle,t1,t2,b(4 bits per setting) */
2417 .antCtrlCommon = LE32(0x110),
2418 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2419 .antCtrlCommon2 = LE32(0x44444),
2422 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2423 * rx1, rx12, b (2 bits each)
2425 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2428 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2429 * for ar9280 (0xa20c/b20c 5:0)
2431 .xatten1DB = {0x1f, 0x1f, 0x1f},
2434 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2435 * for ar9280 (0xa20c/b20c 16:12
2437 .xatten1Margin = {0x12, 0x12, 0x12},
2442 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2443 * channels in usual fbin coding format
2445 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2448 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2449 * if the register is per chain
2451 .noiseFloorThreshCh = {-1, 0, 0},
2452 .ob = {1, 1, 1},/* 3 chain */
2453 .db_stage2 = {1, 1, 1}, /* 3 chain */
2454 .db_stage3 = {0, 0, 0},
2455 .db_stage4 = {0, 0, 0},
2457 .txFrameToDataStart = 0x0e,
2458 .txFrameToPaOn = 0x0e,
2459 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2461 .switchSettling = 0x2c,
2462 .adcDesiredSize = -30,
2465 .txFrameToXpaOn = 0xe,
2467 .papdRateMaskHt20 = LE32(0x0c80C080),
2468 .papdRateMaskHt40 = LE32(0x0080C080),
2470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2474 .ant_div_control = 0,
2475 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2482 /* ar9300_cal_data_per_freq_op_loop 2g */
2484 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2485 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2486 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2488 .calTarget_freqbin_Cck = {
2492 .calTarget_freqbin_2G = {
2497 .calTarget_freqbin_2GHT20 = {
2502 .calTarget_freqbin_2GHT40 = {
2507 .calTargetPowerCck = {
2508 /* 1L-5L,5S,11L,11S */
2509 { {34, 34, 34, 34} },
2510 { {34, 34, 34, 34} },
2512 .calTargetPower2G = {
2514 { {34, 34, 32, 32} },
2515 { {34, 34, 32, 32} },
2516 { {34, 34, 32, 32} },
2518 .calTargetPower2GHT20 = {
2519 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2520 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2521 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2523 .calTargetPower2GHT40 = {
2524 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2525 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2526 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2529 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2530 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2560 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2561 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2562 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2563 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2567 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2568 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2569 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2574 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2575 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2581 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2582 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2583 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2584 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2588 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2589 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2590 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2594 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2595 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2596 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2601 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2602 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2603 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2608 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2609 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2610 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2611 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2614 .ctlPowerData_2G = {
2615 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2616 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2617 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2619 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2620 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2621 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2623 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2624 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2625 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2627 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2628 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2629 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2632 /* 4 idle,t1,t2,b (4 bits per setting) */
2633 .antCtrlCommon = LE32(0x220),
2634 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2635 .antCtrlCommon2 = LE32(0x44444),
2636 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2638 LE16(0x150), LE16(0x150), LE16(0x150),
2640 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2641 .xatten1DB = {0x19, 0x19, 0x19},
2644 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2645 * for merlin (0xa20c/b20c 16:12
2647 .xatten1Margin = {0x14, 0x14, 0x14},
2650 /* spurChans spur channels in usual fbin coding format */
2651 .spurChans = {0, 0, 0, 0, 0},
2652 /* noiseFloorThreshCh Check if the register is per chain */
2653 .noiseFloorThreshCh = {-1, 0, 0},
2654 .ob = {3, 3, 3}, /* 3 chain */
2655 .db_stage2 = {3, 3, 3}, /* 3 chain */
2656 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2657 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2659 .txFrameToDataStart = 0x0e,
2660 .txFrameToPaOn = 0x0e,
2661 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2663 .switchSettling = 0x2d,
2664 .adcDesiredSize = -30,
2667 .txFrameToXpaOn = 0xe,
2669 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2670 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2672 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2677 .tempSlopeHigh = 50,
2678 .xatten1DBLow = {0, 0, 0},
2679 .xatten1MarginLow = {0, 0, 0},
2680 .xatten1DBHigh = {0, 0, 0},
2681 .xatten1MarginHigh = {0, 0, 0}
2726 .calTarget_freqbin_5G = {
2736 .calTarget_freqbin_5GHT20 = {
2746 .calTarget_freqbin_5GHT40 = {
2756 .calTargetPower5G = {
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2760 { {30, 30, 28, 24} },
2761 { {30, 30, 28, 24} },
2762 { {30, 30, 28, 24} },
2763 { {30, 30, 28, 24} },
2764 { {30, 30, 28, 24} },
2765 { {30, 30, 28, 24} },
2767 .calTargetPower5GHT20 = {
2769 * 0_8_16,1-3_9-11_17-19,
2770 * 4,5,6,7,12,13,14,15,20,21,22,23
2772 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2773 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2774 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2775 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2776 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2777 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2778 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2779 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2781 .calTargetPower5GHT40 = {
2783 * 0_8_16,1-3_9-11_17-19,
2784 * 4,5,6,7,12,13,14,15,20,21,22,23
2786 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2787 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2788 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2789 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2790 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2791 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2792 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2793 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2796 0x10, 0x16, 0x18, 0x40, 0x46,
2797 0x48, 0x30, 0x36, 0x38
2801 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2804 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2805 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2806 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2807 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2808 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2811 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2812 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2813 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2814 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2815 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2816 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2817 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2818 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2822 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2823 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2824 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2825 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2826 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2827 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2828 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2829 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2833 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2834 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2835 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2836 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2837 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2838 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2839 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2840 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2844 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2845 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2846 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2847 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2848 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2849 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2850 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2851 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2855 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2856 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2857 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2858 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2859 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2860 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2861 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2862 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2866 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2867 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2868 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2869 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2870 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2871 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2872 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2873 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2877 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2878 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2879 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2880 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2881 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2882 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2883 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2884 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2888 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2889 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2890 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2891 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2892 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2893 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2894 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2895 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2898 .ctlPowerData_5G = {
2901 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2902 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2908 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2913 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2914 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2919 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2920 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2925 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2926 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2931 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2932 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2937 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2938 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2943 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2944 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2949 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2950 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2957 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2965 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2967 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2970 for (it = 0; it < N_LOOP; it++)
2971 if (ar9300_eep_templates[it]->templateVersion == id)
2972 return ar9300_eep_templates[it];
2978 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2980 if (fbin == AR5416_BCHAN_UNUSED)
2983 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2986 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2991 static int interpolate(int x, int xa, int xb, int ya, int yb)
2993 int bf, factor, plus;
2995 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2998 return ya + factor + plus;
3001 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3002 enum eeprom_param param)
3004 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3005 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3009 return eep->macAddr[0] << 8 | eep->macAddr[1];
3011 return eep->macAddr[2] << 8 | eep->macAddr[3];
3013 return eep->macAddr[4] << 8 | eep->macAddr[5];
3015 return le16_to_cpu(pBase->regDmn[0]);
3017 return le16_to_cpu(pBase->regDmn[1]);
3019 return pBase->deviceCap;
3021 return pBase->opCapFlags.opFlags;
3023 return pBase->rfSilent;
3025 return (pBase->txrxMask >> 4) & 0xf;
3027 return pBase->txrxMask & 0xf;
3028 case EEP_DRIVE_STRENGTH:
3029 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3030 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3031 case EEP_INTERNAL_REGULATOR:
3032 /* Bit 4 is internal regulator flag */
3033 return (pBase->featureEnable & 0x10) >> 4;
3035 return le32_to_cpu(pBase->swreg);
3037 return !!(pBase->featureEnable & BIT(5));
3038 case EEP_CHAIN_MASK_REDUCE:
3039 return (pBase->miscConfiguration >> 0x3) & 0x1;
3040 case EEP_ANT_DIV_CTL1:
3041 return le32_to_cpu(eep->base_ext1.ant_div_control);
3047 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3052 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3055 *buffer = (val >> (8 * (address % 2))) & 0xff;
3059 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3064 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3067 buffer[0] = val >> 8;
3068 buffer[1] = val & 0xff;
3073 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3076 struct ath_common *common = ath9k_hw_common(ah);
3079 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3080 ath_dbg(common, ATH_DBG_EEPROM,
3081 "eeprom address not in range\n");
3086 * Since we're reading the bytes in reverse order from a little-endian
3087 * word stream, an even address means we only use the lower half of
3088 * the 16-bit word at that address
3090 if (address % 2 == 0) {
3091 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3097 for (i = 0; i < count / 2; i++) {
3098 if (!ar9300_eeprom_read_word(common, address, buffer))
3106 if (!ar9300_eeprom_read_byte(common, address, buffer))
3112 ath_dbg(common, ATH_DBG_EEPROM,
3113 "unable to read eeprom region at offset %d\n", address);
3117 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3119 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3121 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3122 AR9300_OTP_STATUS_VALID, 1000))
3125 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3129 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3135 for (i = 0; i < count; i++) {
3136 int offset = 8 * ((address - i) % 4);
3137 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3140 buffer[i] = (data >> offset) & 0xff;
3147 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3148 int *length, int *major, int *minor)
3150 unsigned long value[4];
3156 *code = ((value[0] >> 5) & 0x0007);
3157 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3158 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3159 *major = (value[2] & 0x000f);
3160 *minor = (value[3] & 0x00ff);
3163 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3165 int it, checksum = 0;
3167 for (it = 0; it < dsize; it++) {
3168 checksum += data[it];
3175 static bool ar9300_uncompress_block(struct ath_hw *ah,
3185 struct ath_common *common = ath9k_hw_common(ah);
3189 for (it = 0; it < size; it += (length+2)) {
3193 length = block[it+1];
3196 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3197 ath_dbg(common, ATH_DBG_EEPROM,
3198 "Restore at %d: spot=%d offset=%d length=%d\n",
3199 it, spot, offset, length);
3200 memcpy(&mptr[spot], &block[it+2], length);
3202 } else if (length > 0) {
3203 ath_dbg(common, ATH_DBG_EEPROM,
3204 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3205 it, spot, offset, length);
3212 static int ar9300_compress_decision(struct ath_hw *ah,
3217 u8 *word, int length, int mdata_size)
3219 struct ath_common *common = ath9k_hw_common(ah);
3220 const struct ar9300_eeprom *eep = NULL;
3224 if (length != mdata_size) {
3225 ath_dbg(common, ATH_DBG_EEPROM,
3226 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3227 mdata_size, length);
3230 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3231 ath_dbg(common, ATH_DBG_EEPROM,
3232 "restored eeprom %d: uncompressed, length %d\n",
3235 case _CompressBlock:
3236 if (reference == 0) {
3238 eep = ar9003_eeprom_struct_find_by_id(reference);
3240 ath_dbg(common, ATH_DBG_EEPROM,
3241 "can't find reference eeprom struct %d\n",
3245 memcpy(mptr, eep, mdata_size);
3247 ath_dbg(common, ATH_DBG_EEPROM,
3248 "restore eeprom %d: block, reference %d, length %d\n",
3249 it, reference, length);
3250 ar9300_uncompress_block(ah, mptr, mdata_size,
3251 (u8 *) (word + COMP_HDR_LEN), length);
3254 ath_dbg(common, ATH_DBG_EEPROM,
3255 "unknown compression code %d\n", code);
3261 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3264 static bool ar9300_check_header(void *data)
3267 return !(*word == 0 || *word == ~0);
3270 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3275 if (!read(ah, base_addr, header, 4))
3278 return ar9300_check_header(header);
3281 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3284 struct ath_common *common = ath9k_hw_common(ah);
3285 u16 *data = (u16 *) mptr;
3288 for (i = 0; i < mdata_size / 2; i++, data++)
3289 ath9k_hw_nvram_read(common, i, data);
3294 * Read the configuration data from the eeprom.
3295 * The data can be put in any specified memory buffer.
3297 * Returns -1 on error.
3298 * Returns address of next memory location on success.
3300 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3301 u8 *mptr, int mdata_size)
3308 int reference, length, major, minor;
3311 u16 checksum, mchecksum;
3312 struct ath_common *common = ath9k_hw_common(ah);
3313 eeprom_read_op read;
3315 if (ath9k_hw_use_flash(ah))
3316 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3318 word = kzalloc(2048, GFP_KERNEL);
3322 memcpy(mptr, &ar9300_default, mdata_size);
3324 read = ar9300_read_eeprom;
3325 if (AR_SREV_9485(ah))
3326 cptr = AR9300_BASE_ADDR_4K;
3328 cptr = AR9300_BASE_ADDR;
3329 ath_dbg(common, ATH_DBG_EEPROM,
3330 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3331 if (ar9300_check_eeprom_header(ah, read, cptr))
3334 cptr = AR9300_BASE_ADDR_512;
3335 ath_dbg(common, ATH_DBG_EEPROM,
3336 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3337 if (ar9300_check_eeprom_header(ah, read, cptr))
3340 read = ar9300_read_otp;
3341 cptr = AR9300_BASE_ADDR;
3342 ath_dbg(common, ATH_DBG_EEPROM,
3343 "Trying OTP accesss at Address 0x%04x\n", cptr);
3344 if (ar9300_check_eeprom_header(ah, read, cptr))
3347 cptr = AR9300_BASE_ADDR_512;
3348 ath_dbg(common, ATH_DBG_EEPROM,
3349 "Trying OTP accesss at Address 0x%04x\n", cptr);
3350 if (ar9300_check_eeprom_header(ah, read, cptr))
3356 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
3358 for (it = 0; it < MSTATE; it++) {
3359 if (!read(ah, cptr, word, COMP_HDR_LEN))
3362 if (!ar9300_check_header(word))
3365 ar9300_comp_hdr_unpack(word, &code, &reference,
3366 &length, &major, &minor);
3367 ath_dbg(common, ATH_DBG_EEPROM,
3368 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3369 cptr, code, reference, length, major, minor);
3370 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3371 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3372 ath_dbg(common, ATH_DBG_EEPROM,
3373 "Skipping bad header\n");
3374 cptr -= COMP_HDR_LEN;
3379 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3380 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3381 mchecksum = word[COMP_HDR_LEN + osize] |
3382 (word[COMP_HDR_LEN + osize + 1] << 8);
3383 ath_dbg(common, ATH_DBG_EEPROM,
3384 "checksum %x %x\n", checksum, mchecksum);
3385 if (checksum == mchecksum) {
3386 ar9300_compress_decision(ah, it, code, reference, mptr,
3387 word, length, mdata_size);
3389 ath_dbg(common, ATH_DBG_EEPROM,
3390 "skipping block with bad checksum\n");
3392 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3404 * Restore the configuration structure by reading the eeprom.
3405 * This function destroys any existing in-memory structure
3408 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3410 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3412 if (ar9300_eeprom_restore_internal(ah, mptr,
3413 sizeof(struct ar9300_eeprom)) < 0)
3419 /* XXX: review hardware docs */
3420 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3422 return ah->eeprom.ar9300_eep.eepromVersion;
3425 /* XXX: could be read from the eepromVersion, not sure yet */
3426 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3431 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3433 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3436 return eep->modalHeader2G.xpaBiasLvl;
3438 return eep->modalHeader5G.xpaBiasLvl;
3441 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3443 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3445 if (AR_SREV_9485(ah))
3446 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3448 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3449 if (!AR_SREV_9340(ah)) {
3450 REG_RMW_FIELD(ah, AR_CH0_THERM,
3451 AR_CH0_THERM_XPABIASLVL_MSB,
3453 REG_RMW_FIELD(ah, AR_CH0_THERM,
3454 AR_CH0_THERM_XPASHORT2GND, 1);
3459 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3461 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3465 val = eep->modalHeader2G.antCtrlCommon;
3467 val = eep->modalHeader5G.antCtrlCommon;
3468 return le32_to_cpu(val);
3471 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3473 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3477 val = eep->modalHeader2G.antCtrlCommon2;
3479 val = eep->modalHeader5G.antCtrlCommon2;
3480 return le32_to_cpu(val);
3483 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3487 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3490 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3492 val = eep->modalHeader2G.antCtrlChain[chain];
3494 val = eep->modalHeader5G.antCtrlChain[chain];
3497 return le16_to_cpu(val);
3500 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3503 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3504 AR_PHY_SWITCH_CHAIN_0,
3505 AR_PHY_SWITCH_CHAIN_1,
3506 AR_PHY_SWITCH_CHAIN_2,
3509 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3511 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3513 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3514 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3516 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3517 if ((ah->rxchainmask & BIT(chain)) ||
3518 (ah->txchainmask & BIT(chain))) {
3519 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3521 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3522 AR_SWITCH_TABLE_ALL, value);
3526 if (AR_SREV_9485(ah)) {
3527 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3528 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
3530 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
3532 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
3537 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3542 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3544 if (!drive_strength)
3547 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3555 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3557 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3568 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3570 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3575 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3578 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3579 struct ath9k_channel *chan)
3583 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3585 if (chain >= 0 && chain < 3) {
3586 if (IS_CHAN_2GHZ(chan))
3587 return eep->modalHeader2G.xatten1DB[chain];
3588 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3589 t[0] = eep->base_ext2.xatten1DBLow[chain];
3591 t[1] = eep->modalHeader5G.xatten1DB[chain];
3593 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3595 value = ar9003_hw_power_interpolate((s32) chan->channel,
3599 return eep->modalHeader5G.xatten1DB[chain];
3606 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3607 struct ath9k_channel *chan)
3611 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3613 if (chain >= 0 && chain < 3) {
3614 if (IS_CHAN_2GHZ(chan))
3615 return eep->modalHeader2G.xatten1Margin[chain];
3616 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3617 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3619 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3621 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3623 value = ar9003_hw_power_interpolate((s32) chan->channel,
3627 return eep->modalHeader5G.xatten1Margin[chain];
3633 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3637 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3638 AR_PHY_EXT_ATTEN_CTL_1,
3639 AR_PHY_EXT_ATTEN_CTL_2,
3642 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3643 for (i = 0; i < 3; i++) {
3644 if (ah->txchainmask & BIT(i)) {
3645 value = ar9003_hw_atten_chain_get(ah, i, chan);
3646 REG_RMW_FIELD(ah, ext_atten_reg[i],
3647 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3649 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3650 REG_RMW_FIELD(ah, ext_atten_reg[i],
3651 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3657 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3661 while (pmu_set != REG_READ(ah, pmu_reg)) {
3664 REG_WRITE(ah, pmu_reg, pmu_set);
3671 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3673 int internal_regulator =
3674 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3676 if (internal_regulator) {
3677 if (AR_SREV_9485(ah)) {
3680 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3681 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3682 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3685 reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3686 (2 << 14) | (6 << 17) | (1 << 20) |
3687 (3 << 24) | (1 << 28);
3689 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3690 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3693 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3695 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3696 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3699 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3701 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3702 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3705 /* Internal regulator is ON. Write swreg register. */
3706 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3707 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3708 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3709 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3710 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3711 /* Set REG_CONTROL1.SWREG_PROGRAM */
3712 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3714 AR_RTC_REG_CONTROL1) |
3715 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3718 if (AR_SREV_9485(ah)) {
3719 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3720 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3724 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3725 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3728 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3729 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3733 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3736 AR_RTC_FORCE_SWREG_PRD));
3741 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3743 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3744 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3746 if (eep->baseEepHeader.featureEnable & 0x40) {
3747 tuning_caps_param &= 0x7f;
3748 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3750 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3755 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3756 struct ath9k_channel *chan)
3758 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3759 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3760 ar9003_hw_drive_strength_apply(ah);
3761 ar9003_hw_atten_apply(ah, chan);
3762 if (!AR_SREV_9340(ah))
3763 ar9003_hw_internal_regulator_apply(ah);
3764 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3765 ar9003_hw_apply_tuning_caps(ah);
3768 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3769 struct ath9k_channel *chan)
3774 * Returns the interpolated y value corresponding to the specified x value
3775 * from the np ordered pairs of data (px,py).
3776 * The pairs do not have to be in any order.
3777 * If the specified x value is less than any of the px,
3778 * the returned y value is equal to the py for the lowest px.
3779 * If the specified x value is greater than any of the px,
3780 * the returned y value is equal to the py for the highest px.
3782 static int ar9003_hw_power_interpolate(int32_t x,
3783 int32_t *px, int32_t *py, u_int16_t np)
3786 int lx = 0, ly = 0, lhave = 0;
3787 int hx = 0, hy = 0, hhave = 0;
3794 /* identify best lower and higher x calibration measurement */
3795 for (ip = 0; ip < np; ip++) {
3798 /* this measurement is higher than our desired x */
3800 if (!hhave || dx > (x - hx)) {
3801 /* new best higher x measurement */
3807 /* this measurement is lower than our desired x */
3809 if (!lhave || dx < (x - lx)) {
3810 /* new best lower x measurement */
3818 /* the low x is good */
3820 /* so is the high x */
3822 /* they're the same, so just pick one */
3825 else /* interpolate */
3826 y = interpolate(x, lx, hx, ly, hy);
3827 } else /* only low is good, use it */
3829 } else if (hhave) /* only high is good, use it */
3831 else /* nothing is good,this should never happen unless np=0, ???? */
3836 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3837 u16 rateIndex, u16 freq, bool is2GHz)
3840 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3841 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3842 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3843 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3847 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3848 pEepromTargetPwr = eep->calTargetPower2G;
3849 pFreqBin = eep->calTarget_freqbin_2G;
3851 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3852 pEepromTargetPwr = eep->calTargetPower5G;
3853 pFreqBin = eep->calTarget_freqbin_5G;
3857 * create array of channels and targetpower from
3858 * targetpower piers stored on eeprom
3860 for (i = 0; i < numPiers; i++) {
3861 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3862 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3865 /* interpolate to get target power for given frequency */
3866 return (u8) ar9003_hw_power_interpolate((s32) freq,
3868 targetPowerArray, numPiers);
3871 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3873 u16 freq, bool is2GHz)
3876 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3877 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3878 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3879 struct cal_tgt_pow_ht *pEepromTargetPwr;
3883 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3884 pEepromTargetPwr = eep->calTargetPower2GHT20;
3885 pFreqBin = eep->calTarget_freqbin_2GHT20;
3887 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3888 pEepromTargetPwr = eep->calTargetPower5GHT20;
3889 pFreqBin = eep->calTarget_freqbin_5GHT20;
3893 * create array of channels and targetpower
3894 * from targetpower piers stored on eeprom
3896 for (i = 0; i < numPiers; i++) {
3897 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3898 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3901 /* interpolate to get target power for given frequency */
3902 return (u8) ar9003_hw_power_interpolate((s32) freq,
3904 targetPowerArray, numPiers);
3907 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3909 u16 freq, bool is2GHz)
3912 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3913 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3914 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3915 struct cal_tgt_pow_ht *pEepromTargetPwr;
3919 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3920 pEepromTargetPwr = eep->calTargetPower2GHT40;
3921 pFreqBin = eep->calTarget_freqbin_2GHT40;
3923 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3924 pEepromTargetPwr = eep->calTargetPower5GHT40;
3925 pFreqBin = eep->calTarget_freqbin_5GHT40;
3929 * create array of channels and targetpower from
3930 * targetpower piers stored on eeprom
3932 for (i = 0; i < numPiers; i++) {
3933 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3934 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3937 /* interpolate to get target power for given frequency */
3938 return (u8) ar9003_hw_power_interpolate((s32) freq,
3940 targetPowerArray, numPiers);
3943 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3944 u16 rateIndex, u16 freq)
3946 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3947 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3948 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3949 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3950 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3951 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3954 * create array of channels and targetpower from
3955 * targetpower piers stored on eeprom
3957 for (i = 0; i < numPiers; i++) {
3958 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3959 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3962 /* interpolate to get target power for given frequency */
3963 return (u8) ar9003_hw_power_interpolate((s32) freq,
3965 targetPowerArray, numPiers);
3968 /* Set tx power registers to array of values passed in */
3969 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3971 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3972 /* make sure forced gain is not set */
3973 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
3975 /* Write the OFDM power per rate set */
3977 /* 6 (LSB), 9, 12, 18 (MSB) */
3978 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
3979 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3980 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3981 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3982 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3984 /* 24 (LSB), 36, 48, 54 (MSB) */
3985 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
3986 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3987 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3988 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3989 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3991 /* Write the CCK power per rate set */
3993 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3994 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
3995 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3996 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3997 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3998 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4000 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4001 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4002 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4003 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4004 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4005 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4008 /* Write the HT20 power per rate set */
4010 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4011 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4012 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4013 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4014 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4015 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4018 /* 6 (LSB), 7, 12, 13 (MSB) */
4019 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4020 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4021 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4022 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4023 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4026 /* 14 (LSB), 15, 20, 21 */
4027 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4028 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4029 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4030 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4031 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4034 /* Mixed HT20 and HT40 rates */
4036 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4037 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4038 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4039 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4040 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4041 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4045 * Write the HT40 power per rate set
4046 * correct PAR difference between HT40 and HT20/LEGACY
4047 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4049 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4050 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4051 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4052 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4053 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4056 /* 6 (LSB), 7, 12, 13 (MSB) */
4057 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4058 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4059 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4060 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4061 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4064 /* 14 (LSB), 15, 20, 21 */
4065 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4066 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4067 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4068 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4069 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4076 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4077 u8 *targetPowerValT2)
4079 /* XXX: hard code for now, need to get from eeprom struct */
4080 u8 ht40PowerIncForPdadc = 0;
4081 bool is2GHz = false;
4083 struct ath_common *common = ath9k_hw_common(ah);
4088 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4089 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4091 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4092 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4094 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4095 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4097 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4098 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4100 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4101 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4103 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4104 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4105 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4106 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4107 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4108 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4109 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4110 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4112 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4113 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4115 targetPowerValT2[ALL_TARGET_HT20_4] =
4116 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4118 targetPowerValT2[ALL_TARGET_HT20_5] =
4119 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4121 targetPowerValT2[ALL_TARGET_HT20_6] =
4122 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4124 targetPowerValT2[ALL_TARGET_HT20_7] =
4125 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4127 targetPowerValT2[ALL_TARGET_HT20_12] =
4128 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4130 targetPowerValT2[ALL_TARGET_HT20_13] =
4131 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4133 targetPowerValT2[ALL_TARGET_HT20_14] =
4134 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4136 targetPowerValT2[ALL_TARGET_HT20_15] =
4137 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4139 targetPowerValT2[ALL_TARGET_HT20_20] =
4140 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4142 targetPowerValT2[ALL_TARGET_HT20_21] =
4143 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4145 targetPowerValT2[ALL_TARGET_HT20_22] =
4146 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4148 targetPowerValT2[ALL_TARGET_HT20_23] =
4149 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4151 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4152 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4153 is2GHz) + ht40PowerIncForPdadc;
4154 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4155 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4157 is2GHz) + ht40PowerIncForPdadc;
4158 targetPowerValT2[ALL_TARGET_HT40_4] =
4159 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4160 is2GHz) + ht40PowerIncForPdadc;
4161 targetPowerValT2[ALL_TARGET_HT40_5] =
4162 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4163 is2GHz) + ht40PowerIncForPdadc;
4164 targetPowerValT2[ALL_TARGET_HT40_6] =
4165 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4166 is2GHz) + ht40PowerIncForPdadc;
4167 targetPowerValT2[ALL_TARGET_HT40_7] =
4168 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4169 is2GHz) + ht40PowerIncForPdadc;
4170 targetPowerValT2[ALL_TARGET_HT40_12] =
4171 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4172 is2GHz) + ht40PowerIncForPdadc;
4173 targetPowerValT2[ALL_TARGET_HT40_13] =
4174 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4175 is2GHz) + ht40PowerIncForPdadc;
4176 targetPowerValT2[ALL_TARGET_HT40_14] =
4177 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4178 is2GHz) + ht40PowerIncForPdadc;
4179 targetPowerValT2[ALL_TARGET_HT40_15] =
4180 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4181 is2GHz) + ht40PowerIncForPdadc;
4182 targetPowerValT2[ALL_TARGET_HT40_20] =
4183 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4184 is2GHz) + ht40PowerIncForPdadc;
4185 targetPowerValT2[ALL_TARGET_HT40_21] =
4186 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4187 is2GHz) + ht40PowerIncForPdadc;
4188 targetPowerValT2[ALL_TARGET_HT40_22] =
4189 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4190 is2GHz) + ht40PowerIncForPdadc;
4191 targetPowerValT2[ALL_TARGET_HT40_23] =
4192 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4193 is2GHz) + ht40PowerIncForPdadc;
4195 for (i = 0; i < ar9300RateSize; i++) {
4196 ath_dbg(common, ATH_DBG_EEPROM,
4197 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4201 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4207 int *ptemperature, int *pvoltage)
4210 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4212 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4213 struct ath_common *common = ath9k_hw_common(ah);
4215 if (ichain >= AR9300_MAX_CHAINS) {
4216 ath_dbg(common, ATH_DBG_EEPROM,
4217 "Invalid chain index, must be less than %d\n",
4222 if (mode) { /* 5GHz */
4223 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4224 ath_dbg(common, ATH_DBG_EEPROM,
4225 "Invalid 5GHz cal pier index, must be less than %d\n",
4226 AR9300_NUM_5G_CAL_PIERS);
4229 pCalPier = &(eep->calFreqPier5G[ipier]);
4230 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4233 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4234 ath_dbg(common, ATH_DBG_EEPROM,
4235 "Invalid 2GHz cal pier index, must be less than %d\n",
4236 AR9300_NUM_2G_CAL_PIERS);
4240 pCalPier = &(eep->calFreqPier2G[ipier]);
4241 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4245 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4246 *pcorrection = pCalPierStruct->refPower;
4247 *ptemperature = pCalPierStruct->tempMeas;
4248 *pvoltage = pCalPierStruct->voltMeas;
4253 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4256 int *voltage, int *temperature)
4259 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4262 REG_RMW(ah, AR_PHY_TPC_11_B0,
4263 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4264 AR_PHY_TPC_OLPC_GAIN_DELTA);
4265 if (ah->caps.tx_chainmask & BIT(1))
4266 REG_RMW(ah, AR_PHY_TPC_11_B1,
4267 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4268 AR_PHY_TPC_OLPC_GAIN_DELTA);
4269 if (ah->caps.tx_chainmask & BIT(2))
4270 REG_RMW(ah, AR_PHY_TPC_11_B2,
4271 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4272 AR_PHY_TPC_OLPC_GAIN_DELTA);
4274 /* enable open loop power control on chip */
4275 REG_RMW(ah, AR_PHY_TPC_6_B0,
4276 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4277 AR_PHY_TPC_6_ERROR_EST_MODE);
4278 if (ah->caps.tx_chainmask & BIT(1))
4279 REG_RMW(ah, AR_PHY_TPC_6_B1,
4280 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4281 AR_PHY_TPC_6_ERROR_EST_MODE);
4282 if (ah->caps.tx_chainmask & BIT(2))
4283 REG_RMW(ah, AR_PHY_TPC_6_B2,
4284 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4285 AR_PHY_TPC_6_ERROR_EST_MODE);
4288 * enable temperature compensation
4289 * Need to use register names
4291 if (frequency < 4000)
4292 tempSlope = eep->modalHeader2G.tempSlope;
4293 else if (eep->base_ext2.tempSlopeLow != 0) {
4294 t[0] = eep->base_ext2.tempSlopeLow;
4296 t[1] = eep->modalHeader5G.tempSlope;
4298 t[2] = eep->base_ext2.tempSlopeHigh;
4300 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4303 tempSlope = eep->modalHeader5G.tempSlope;
4305 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4306 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4312 /* Apply the recorded correction values. */
4313 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4315 int ichain, ipier, npier;
4317 int lfrequency[AR9300_MAX_CHAINS],
4318 lcorrection[AR9300_MAX_CHAINS],
4319 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4320 int hfrequency[AR9300_MAX_CHAINS],
4321 hcorrection[AR9300_MAX_CHAINS],
4322 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4324 int correction[AR9300_MAX_CHAINS],
4325 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4326 int pfrequency, pcorrection, ptemperature, pvoltage;
4327 struct ath_common *common = ath9k_hw_common(ah);
4329 mode = (frequency >= 4000);
4331 npier = AR9300_NUM_5G_CAL_PIERS;
4333 npier = AR9300_NUM_2G_CAL_PIERS;
4335 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4336 lfrequency[ichain] = 0;
4337 hfrequency[ichain] = 100000;
4339 /* identify best lower and higher frequency calibration measurement */
4340 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4341 for (ipier = 0; ipier < npier; ipier++) {
4342 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4343 &pfrequency, &pcorrection,
4344 &ptemperature, &pvoltage)) {
4345 fdiff = frequency - pfrequency;
4348 * this measurement is higher than
4349 * our desired frequency
4352 if (hfrequency[ichain] <= 0 ||
4353 hfrequency[ichain] >= 100000 ||
4355 (frequency - hfrequency[ichain])) {
4358 * frequency measurement
4360 hfrequency[ichain] = pfrequency;
4361 hcorrection[ichain] =
4363 htemperature[ichain] =
4365 hvoltage[ichain] = pvoltage;
4369 if (lfrequency[ichain] <= 0
4371 (frequency - lfrequency[ichain])) {
4374 * frequency measurement
4376 lfrequency[ichain] = pfrequency;
4377 lcorrection[ichain] =
4379 ltemperature[ichain] =
4381 lvoltage[ichain] = pvoltage;
4389 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4390 ath_dbg(common, ATH_DBG_EEPROM,
4391 "ch=%d f=%d low=%d %d h=%d %d\n",
4392 ichain, frequency, lfrequency[ichain],
4393 lcorrection[ichain], hfrequency[ichain],
4394 hcorrection[ichain]);
4395 /* they're the same, so just pick one */
4396 if (hfrequency[ichain] == lfrequency[ichain]) {
4397 correction[ichain] = lcorrection[ichain];
4398 voltage[ichain] = lvoltage[ichain];
4399 temperature[ichain] = ltemperature[ichain];
4401 /* the low frequency is good */
4402 else if (frequency - lfrequency[ichain] < 1000) {
4403 /* so is the high frequency, interpolate */
4404 if (hfrequency[ichain] - frequency < 1000) {
4406 correction[ichain] = interpolate(frequency,
4409 lcorrection[ichain],
4410 hcorrection[ichain]);
4412 temperature[ichain] = interpolate(frequency,
4415 ltemperature[ichain],
4416 htemperature[ichain]);
4418 voltage[ichain] = interpolate(frequency,
4424 /* only low is good, use it */
4426 correction[ichain] = lcorrection[ichain];
4427 temperature[ichain] = ltemperature[ichain];
4428 voltage[ichain] = lvoltage[ichain];
4431 /* only high is good, use it */
4432 else if (hfrequency[ichain] - frequency < 1000) {
4433 correction[ichain] = hcorrection[ichain];
4434 temperature[ichain] = htemperature[ichain];
4435 voltage[ichain] = hvoltage[ichain];
4436 } else { /* nothing is good, presume 0???? */
4437 correction[ichain] = 0;
4438 temperature[ichain] = 0;
4439 voltage[ichain] = 0;
4443 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4446 ath_dbg(common, ATH_DBG_EEPROM,
4447 "for frequency=%d, calibration correction = %d %d %d\n",
4448 frequency, correction[0], correction[1], correction[2]);
4453 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4458 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4459 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4462 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4464 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4467 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4473 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4474 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4476 u8 *ctl_freqbin = is2GHz ?
4477 &eep->ctl_freqbin_2G[idx][0] :
4478 &eep->ctl_freqbin_5G[idx][0];
4481 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4482 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4483 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4485 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4486 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4487 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4490 return MAX_RATE_POWER;
4494 * Find the maximum conformance test limit for the given channel and CTL info
4496 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4497 u16 freq, int idx, bool is2GHz)
4499 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4500 u8 *ctl_freqbin = is2GHz ?
4501 &eep->ctl_freqbin_2G[idx][0] :
4502 &eep->ctl_freqbin_5G[idx][0];
4503 u16 num_edges = is2GHz ?
4504 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4507 /* Get the edge power */
4509 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4512 * If there's an exact channel match or an inband flag set
4513 * on the lower channel use the given rdEdgePower
4515 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4517 ar9003_hw_get_direct_edge_power(eep, idx,
4520 } else if ((edge > 0) &&
4521 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4524 ar9003_hw_get_indirect_edge_power(eep, idx,
4528 * Leave loop - no more affecting edges possible in
4529 * this monotonic increasing list
4534 return twiceMaxEdgePower;
4537 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4538 struct ath9k_channel *chan,
4539 u8 *pPwrArray, u16 cfgCtl,
4540 u8 twiceAntennaReduction,
4541 u8 twiceMaxRegulatoryPower,
4544 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4545 struct ath_common *common = ath9k_hw_common(ah);
4546 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4547 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4548 static const u16 tpScaleReductionTable[5] = {
4549 0, 3, 6, 9, MAX_RATE_POWER
4552 int16_t twiceLargestAntenna;
4553 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4554 static const u16 ctlModesFor11a[] = {
4555 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4557 static const u16 ctlModesFor11g[] = {
4558 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4559 CTL_11G_EXT, CTL_2GHT40
4562 const u16 *pCtlMode;
4564 struct chan_centers centers;
4567 u16 twiceMinEdgePower;
4568 bool is2ghz = IS_CHAN_2GHZ(chan);
4570 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
4572 /* Compute TxPower reduction due to Antenna Gain */
4574 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4576 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4578 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4579 twiceLargestAntenna, 0);
4582 * scaledPower is the minimum of the user input power level
4583 * and the regulatory allowed power level
4585 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4587 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4588 maxRegAllowedPower -=
4589 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4592 scaledPower = min(powerLimit, maxRegAllowedPower);
4595 * Reduce scaled Power by number of chains active to get
4596 * to per chain tx power level
4598 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4602 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4605 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4609 scaledPower = max((u16)0, scaledPower);
4612 * Get target powers from EEPROM - our baseline for TX Power
4615 /* Setup for CTL modes */
4616 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4618 ARRAY_SIZE(ctlModesFor11g) -
4619 SUB_NUM_CTL_MODES_AT_2G_40;
4620 pCtlMode = ctlModesFor11g;
4621 if (IS_CHAN_HT40(chan))
4623 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4625 /* Setup for CTL modes */
4626 /* CTL_11A, CTL_5GHT20 */
4627 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4628 SUB_NUM_CTL_MODES_AT_5G_40;
4629 pCtlMode = ctlModesFor11a;
4630 if (IS_CHAN_HT40(chan))
4632 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4636 * For MIMO, need to apply regulatory caps individually across
4637 * dynamically running modes: CCK, OFDM, HT20, HT40
4639 * The outer loop walks through each possible applicable runtime mode.
4640 * The inner loop walks through each ctlIndex entry in EEPROM.
4641 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4643 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4644 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4645 (pCtlMode[ctlMode] == CTL_2GHT40);
4647 freq = centers.synth_center;
4648 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4649 freq = centers.ext_center;
4651 freq = centers.ctl_center;
4653 ath_dbg(common, ATH_DBG_REGULATORY,
4654 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4655 ctlMode, numCtlModes, isHt40CtlMode,
4656 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4658 /* walk through each CTL index stored in EEPROM */
4660 ctlIndex = pEepData->ctlIndex_2G;
4661 ctlNum = AR9300_NUM_CTLS_2G;
4663 ctlIndex = pEepData->ctlIndex_5G;
4664 ctlNum = AR9300_NUM_CTLS_5G;
4667 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4668 ath_dbg(common, ATH_DBG_REGULATORY,
4669 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4670 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4674 * compare test group from regulatory
4675 * channel list with test mode from pCtlMode
4678 if ((((cfgCtl & ~CTL_MODE_M) |
4679 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4681 (((cfgCtl & ~CTL_MODE_M) |
4682 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4683 ((ctlIndex[i] & CTL_MODE_M) |
4686 ar9003_hw_get_max_edge_power(pEepData,
4690 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4692 * Find the minimum of all CTL
4693 * edge powers that apply to
4697 min(twiceMaxEdgePower,
4708 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4710 ath_dbg(common, ATH_DBG_REGULATORY,
4711 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4712 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4713 scaledPower, minCtlPower);
4715 /* Apply ctl mode to correct target power set */
4716 switch (pCtlMode[ctlMode]) {
4718 for (i = ALL_TARGET_LEGACY_1L_5L;
4719 i <= ALL_TARGET_LEGACY_11S; i++)
4721 (u8)min((u16)pPwrArray[i],
4726 for (i = ALL_TARGET_LEGACY_6_24;
4727 i <= ALL_TARGET_LEGACY_54; i++)
4729 (u8)min((u16)pPwrArray[i],
4734 for (i = ALL_TARGET_HT20_0_8_16;
4735 i <= ALL_TARGET_HT20_21; i++)
4737 (u8)min((u16)pPwrArray[i],
4739 pPwrArray[ALL_TARGET_HT20_22] =
4740 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4742 pPwrArray[ALL_TARGET_HT20_23] =
4743 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4748 for (i = ALL_TARGET_HT40_0_8_16;
4749 i <= ALL_TARGET_HT40_23; i++)
4751 (u8)min((u16)pPwrArray[i],
4757 } /* end ctl mode checking */
4760 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4762 u8 mod_idx = mcs_idx % 8;
4765 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4767 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4770 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4771 struct ath9k_channel *chan, u16 cfgCtl,
4772 u8 twiceAntennaReduction,
4773 u8 twiceMaxRegulatoryPower,
4774 u8 powerLimit, bool test)
4776 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4777 struct ath_common *common = ath9k_hw_common(ah);
4778 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4779 struct ar9300_modal_eep_header *modal_hdr;
4780 u8 targetPowerValT2[ar9300RateSize];
4781 u8 target_power_val_t2_eep[ar9300RateSize];
4782 unsigned int i = 0, paprd_scale_factor = 0;
4783 u8 pwr_idx, min_pwridx = 0;
4785 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4787 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4788 if (IS_CHAN_2GHZ(chan))
4789 modal_hdr = &eep->modalHeader2G;
4791 modal_hdr = &eep->modalHeader5G;
4793 ah->paprd_ratemask =
4794 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4795 AR9300_PAPRD_RATE_MASK;
4797 ah->paprd_ratemask_ht40 =
4798 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4799 AR9300_PAPRD_RATE_MASK;
4801 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4802 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4803 ALL_TARGET_HT20_0_8_16;
4805 if (!ah->paprd_table_write_done) {
4806 memcpy(target_power_val_t2_eep, targetPowerValT2,
4807 sizeof(targetPowerValT2));
4808 for (i = 0; i < 24; i++) {
4809 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4810 if (ah->paprd_ratemask & (1 << i)) {
4811 if (targetPowerValT2[pwr_idx] &&
4812 targetPowerValT2[pwr_idx] ==
4813 target_power_val_t2_eep[pwr_idx])
4814 targetPowerValT2[pwr_idx] -=
4819 memcpy(target_power_val_t2_eep, targetPowerValT2,
4820 sizeof(targetPowerValT2));
4823 ar9003_hw_set_power_per_rate_table(ah, chan,
4824 targetPowerValT2, cfgCtl,
4825 twiceAntennaReduction,
4826 twiceMaxRegulatoryPower,
4829 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4830 for (i = 0; i < ar9300RateSize; i++) {
4831 if ((ah->paprd_ratemask & (1 << i)) &&
4832 (abs(targetPowerValT2[i] -
4833 target_power_val_t2_eep[i]) >
4834 paprd_scale_factor)) {
4835 ah->paprd_ratemask &= ~(1 << i);
4836 ath_dbg(common, ATH_DBG_EEPROM,
4837 "paprd disabled for mcs %d\n", i);
4842 regulatory->max_power_level = 0;
4843 for (i = 0; i < ar9300RateSize; i++) {
4844 if (targetPowerValT2[i] > regulatory->max_power_level)
4845 regulatory->max_power_level = targetPowerValT2[i];
4851 for (i = 0; i < ar9300RateSize; i++) {
4852 ath_dbg(common, ATH_DBG_EEPROM,
4853 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4857 * This is the TX power we send back to driver core,
4858 * and it can use to pass to userspace to display our
4859 * currently configured TX power setting.
4861 * Since power is rate dependent, use one of the indices
4862 * from the AR9300_Rates enum to select an entry from
4863 * targetPowerValT2[] to report. Currently returns the
4864 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4865 * as CCK power is less interesting (?).
4867 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4868 if (IS_CHAN_HT40(chan))
4869 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4870 else if (IS_CHAN_HT20(chan))
4871 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4873 ah->txpower_limit = targetPowerValT2[i];
4874 regulatory->max_power_level = targetPowerValT2[i];
4876 /* Write target power array to registers */
4877 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4878 ar9003_hw_calibration_apply(ah, chan->channel);
4880 if (IS_CHAN_2GHZ(chan)) {
4881 if (IS_CHAN_HT40(chan))
4882 i = ALL_TARGET_HT40_0_8_16;
4884 i = ALL_TARGET_HT20_0_8_16;
4886 if (IS_CHAN_HT40(chan))
4887 i = ALL_TARGET_HT40_7;
4889 i = ALL_TARGET_HT20_7;
4891 ah->paprd_target_power = targetPowerValT2[i];
4894 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4900 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4902 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4904 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4907 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4909 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4911 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4914 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
4916 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4919 return eep->modalHeader2G.spurChans;
4921 return eep->modalHeader5G.spurChans;
4924 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
4925 struct ath9k_channel *chan)
4927 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4929 if (IS_CHAN_2GHZ(chan))
4930 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
4931 AR9300_PAPRD_SCALE_1);
4933 if (chan->channel >= 5700)
4934 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
4935 AR9300_PAPRD_SCALE_1);
4936 else if (chan->channel >= 5400)
4937 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
4938 AR9300_PAPRD_SCALE_2);
4940 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
4941 AR9300_PAPRD_SCALE_1);
4945 const struct eeprom_ops eep_ar9300_ops = {
4946 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4947 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4948 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4949 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4950 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4951 .set_board_values = ath9k_hw_ar9300_set_board_values,
4952 .set_addac = ath9k_hw_ar9300_set_addac,
4953 .set_txpower = ath9k_hw_ar9300_set_txpower,
4954 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel