2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
22 #define COMP_HDR_LEN 4
23 #define COMP_CKSUM_LEN 2
25 #define LE16(x) __constant_cpu_to_le16(x)
26 #define LE32(x) __constant_cpu_to_le32(x)
28 /* Local defines to distinguish between extension and control CTL's */
29 #define EXT_ADDITIVE (0x8000)
30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
34 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
35 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
37 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
39 #define EEPROM_DATA_LEN_9485 1088
41 static int ar9003_hw_power_interpolate(int32_t x,
42 int32_t *px, int32_t *py, u_int16_t np);
45 static const struct ar9300_eeprom ar9300_default = {
48 .macAddr = {0, 2, 3, 4, 5, 6},
49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
52 .regDmn = { LE16(0), LE16(0x1f) },
53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
59 .blueToothOptions = 0,
61 .deviceType = 5, /* takes lower byte in eeprom location */
62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63 .params_for_tuning_caps = {0, 0},
64 .featureEnable = 0x0c,
66 * bit0 - enable tx temp comp - disabled
67 * bit1 - enable tx volt comp - disabled
68 * bit2 - enable fastClock - enabled
69 * bit3 - enable doubling - enabled
70 * bit4 - enable internal regulator - disabled
71 * bit5 - enable pa predistortion - disabled
73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74 .eepromWriteEnableGpio = 3,
77 .rxBandSelectGpio = 0xff,
82 /* ar9300_modal_eep_header 2g */
83 /* 4 idle,t1,t2,b(4 bits per setting) */
84 .antCtrlCommon = LE32(0x110),
85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
86 .antCtrlCommon2 = LE32(0x22222),
89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90 * rx1, rx12, b (2 bits each)
92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96 * for ar9280 (0xa20c/b20c 5:0)
98 .xatten1DB = {0, 0, 0},
101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102 * for ar9280 (0xa20c/b20c 16:12
104 .xatten1Margin = {0, 0, 0},
109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110 * channels in usual fbin coding format
112 .spurChans = {0, 0, 0, 0, 0},
115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116 * if the register is per chain
118 .noiseFloorThreshCh = {-1, 0, 0},
119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 .txFrameToDataStart = 0x0e,
123 .txFrameToPaOn = 0x0e,
124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
126 .switchSettling = 0x2c,
127 .adcDesiredSize = -30,
130 .txFrameToXpaOn = 0xe,
132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
135 0, 0, 0, 0, 0, 0, 0, 0,
139 .ant_div_control = 0,
140 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
147 /* ar9300_cal_data_per_freq_op_loop 2g */
149 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
150 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
151 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
153 .calTarget_freqbin_Cck = {
157 .calTarget_freqbin_2G = {
162 .calTarget_freqbin_2GHT20 = {
167 .calTarget_freqbin_2GHT40 = {
172 .calTargetPowerCck = {
173 /* 1L-5L,5S,11L,11S */
174 { {36, 36, 36, 36} },
175 { {36, 36, 36, 36} },
177 .calTargetPower2G = {
179 { {32, 32, 28, 24} },
180 { {32, 32, 28, 24} },
181 { {32, 32, 28, 24} },
183 .calTargetPower2GHT20 = {
184 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
185 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
186 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
188 .calTargetPower2GHT40 = {
189 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
190 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
194 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
195 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
225 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
226 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
227 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
228 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
232 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
233 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
234 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
239 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
240 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
246 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
247 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
248 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
249 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
253 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
254 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
255 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
259 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
260 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
261 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
266 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
267 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
268 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
273 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
274 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
275 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
276 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
280 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
281 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
282 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
284 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
285 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
286 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
288 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
290 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
294 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
297 /* 4 idle,t1,t2,b (4 bits per setting) */
298 .antCtrlCommon = LE32(0x110),
299 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
300 .antCtrlCommon2 = LE32(0x22222),
301 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
303 LE16(0x000), LE16(0x000), LE16(0x000),
305 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
306 .xatten1DB = {0, 0, 0},
309 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
310 * for merlin (0xa20c/b20c 16:12
312 .xatten1Margin = {0, 0, 0},
315 /* spurChans spur channels in usual fbin coding format */
316 .spurChans = {0, 0, 0, 0, 0},
317 /* noiseFloorThreshCh Check if the register is per chain */
318 .noiseFloorThreshCh = {-1, 0, 0},
319 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
322 .txFrameToDataStart = 0x0e,
323 .txFrameToPaOn = 0x0e,
324 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
326 .switchSettling = 0x2d,
327 .adcDesiredSize = -30,
330 .txFrameToXpaOn = 0xe,
332 .papdRateMaskHt20 = LE32(0x0c80c080),
333 .papdRateMaskHt40 = LE32(0x0080c080),
335 0, 0, 0, 0, 0, 0, 0, 0,
341 .xatten1DBLow = {0, 0, 0},
342 .xatten1MarginLow = {0, 0, 0},
343 .xatten1DBHigh = {0, 0, 0},
344 .xatten1MarginHigh = {0, 0, 0}
389 .calTarget_freqbin_5G = {
399 .calTarget_freqbin_5GHT20 = {
409 .calTarget_freqbin_5GHT40 = {
419 .calTargetPower5G = {
421 { {20, 20, 20, 10} },
422 { {20, 20, 20, 10} },
423 { {20, 20, 20, 10} },
424 { {20, 20, 20, 10} },
425 { {20, 20, 20, 10} },
426 { {20, 20, 20, 10} },
427 { {20, 20, 20, 10} },
428 { {20, 20, 20, 10} },
430 .calTargetPower5GHT20 = {
432 * 0_8_16,1-3_9-11_17-19,
433 * 4,5,6,7,12,13,14,15,20,21,22,23
435 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
436 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
437 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
444 .calTargetPower5GHT40 = {
446 * 0_8_16,1-3_9-11_17-19,
447 * 4,5,6,7,12,13,14,15,20,21,22,23
449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 0x10, 0x16, 0x18, 0x40, 0x46,
460 0x48, 0x30, 0x36, 0x38
464 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
465 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
466 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
467 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
468 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
469 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
470 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
471 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
474 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
475 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
476 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
477 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
478 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
479 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
480 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
481 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
485 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
486 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
487 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
488 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
489 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
490 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
491 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
492 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
496 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
497 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
498 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
499 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
500 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
501 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
502 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
503 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
507 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
508 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
509 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
510 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
511 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
512 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
513 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
514 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
518 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
519 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
520 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
521 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
522 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
523 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
524 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
525 /* Data[5].ctlEdges[7].bChannel */ 0xFF
529 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
530 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
531 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
532 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
533 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
534 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
535 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
536 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
544 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
545 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
546 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
547 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
551 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
552 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
553 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
554 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
555 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
556 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
557 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
558 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
564 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
565 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
570 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
571 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
576 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
577 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
582 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
583 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
588 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
589 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
594 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
595 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
600 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
601 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
606 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
607 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
612 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
613 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
619 static const struct ar9300_eeprom ar9300_x113 = {
621 .templateVersion = 6,
622 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
623 .custData = {"x113-023-f0000"},
625 .regDmn = { LE16(0), LE16(0x1f) },
626 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
628 .opFlags = AR5416_OPFLAGS_11A,
632 .blueToothOptions = 0,
634 .deviceType = 5, /* takes lower byte in eeprom location */
635 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
636 .params_for_tuning_caps = {0, 0},
637 .featureEnable = 0x0d,
639 * bit0 - enable tx temp comp - disabled
640 * bit1 - enable tx volt comp - disabled
641 * bit2 - enable fastClock - enabled
642 * bit3 - enable doubling - enabled
643 * bit4 - enable internal regulator - disabled
644 * bit5 - enable pa predistortion - disabled
646 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
647 .eepromWriteEnableGpio = 6,
648 .wlanDisableGpio = 0,
650 .rxBandSelectGpio = 0xff,
655 /* ar9300_modal_eep_header 2g */
656 /* 4 idle,t1,t2,b(4 bits per setting) */
657 .antCtrlCommon = LE32(0x110),
658 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
659 .antCtrlCommon2 = LE32(0x44444),
662 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
663 * rx1, rx12, b (2 bits each)
665 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
668 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
669 * for ar9280 (0xa20c/b20c 5:0)
671 .xatten1DB = {0, 0, 0},
674 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
675 * for ar9280 (0xa20c/b20c 16:12
677 .xatten1Margin = {0, 0, 0},
682 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
683 * channels in usual fbin coding format
685 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
688 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
689 * if the register is per chain
691 .noiseFloorThreshCh = {-1, 0, 0},
692 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
695 .txFrameToDataStart = 0x0e,
696 .txFrameToPaOn = 0x0e,
697 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
699 .switchSettling = 0x2c,
700 .adcDesiredSize = -30,
703 .txFrameToXpaOn = 0xe,
705 .papdRateMaskHt20 = LE32(0x0c80c080),
706 .papdRateMaskHt40 = LE32(0x0080c080),
708 0, 0, 0, 0, 0, 0, 0, 0,
712 .ant_div_control = 0,
713 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
720 /* ar9300_cal_data_per_freq_op_loop 2g */
722 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
723 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
724 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
726 .calTarget_freqbin_Cck = {
730 .calTarget_freqbin_2G = {
735 .calTarget_freqbin_2GHT20 = {
740 .calTarget_freqbin_2GHT40 = {
745 .calTargetPowerCck = {
746 /* 1L-5L,5S,11L,11S */
747 { {34, 34, 34, 34} },
748 { {34, 34, 34, 34} },
750 .calTargetPower2G = {
752 { {34, 34, 32, 32} },
753 { {34, 34, 32, 32} },
754 { {34, 34, 32, 32} },
756 .calTargetPower2GHT20 = {
757 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
758 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
759 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
761 .calTargetPower2GHT40 = {
762 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
763 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
764 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
767 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
768 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
798 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
799 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
800 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
801 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
805 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
806 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
807 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
812 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
813 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
819 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
820 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
821 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
822 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
826 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
827 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
828 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
832 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
833 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
834 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
839 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
840 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
841 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
846 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
847 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
848 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
849 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
853 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
854 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
855 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
857 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
858 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
859 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
861 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
862 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
866 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
870 /* 4 idle,t1,t2,b (4 bits per setting) */
871 .antCtrlCommon = LE32(0x220),
872 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
873 .antCtrlCommon2 = LE32(0x11111),
874 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
876 LE16(0x150), LE16(0x150), LE16(0x150),
878 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
879 .xatten1DB = {0, 0, 0},
882 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
883 * for merlin (0xa20c/b20c 16:12
885 .xatten1Margin = {0, 0, 0},
888 /* spurChans spur channels in usual fbin coding format */
889 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
890 /* noiseFloorThreshCh Check if the register is per chain */
891 .noiseFloorThreshCh = {-1, 0, 0},
892 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
895 .txFrameToDataStart = 0x0e,
896 .txFrameToPaOn = 0x0e,
897 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
899 .switchSettling = 0x2d,
900 .adcDesiredSize = -30,
903 .txFrameToXpaOn = 0xe,
905 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
906 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
908 0, 0, 0, 0, 0, 0, 0, 0,
913 .tempSlopeHigh = 105,
914 .xatten1DBLow = {0, 0, 0},
915 .xatten1MarginLow = {0, 0, 0},
916 .xatten1DBHigh = {0, 0, 0},
917 .xatten1MarginHigh = {0, 0, 0}
962 .calTarget_freqbin_5G = {
972 .calTarget_freqbin_5GHT20 = {
982 .calTarget_freqbin_5GHT40 = {
992 .calTargetPower5G = {
994 { {42, 40, 40, 34} },
995 { {42, 40, 40, 34} },
996 { {42, 40, 40, 34} },
997 { {42, 40, 40, 34} },
998 { {42, 40, 40, 34} },
999 { {42, 40, 40, 34} },
1000 { {42, 40, 40, 34} },
1001 { {42, 40, 40, 34} },
1003 .calTargetPower5GHT20 = {
1005 * 0_8_16,1-3_9-11_17-19,
1006 * 4,5,6,7,12,13,14,15,20,21,22,23
1008 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1009 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1010 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1011 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1012 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1015 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1017 .calTargetPower5GHT40 = {
1019 * 0_8_16,1-3_9-11_17-19,
1020 * 4,5,6,7,12,13,14,15,20,21,22,23
1022 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1023 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1024 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1025 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1026 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1029 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1032 0x10, 0x16, 0x18, 0x40, 0x46,
1033 0x48, 0x30, 0x36, 0x38
1037 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1038 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1039 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1040 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1041 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1042 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1043 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1044 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1047 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1048 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1049 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1050 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1051 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1052 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1053 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1054 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1058 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1059 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1060 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1061 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1062 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1063 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1064 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1065 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1069 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1071 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1072 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1073 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1074 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1076 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1080 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1081 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1082 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1083 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1084 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1085 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1086 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1087 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1091 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1092 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1093 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1094 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1095 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1096 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1097 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1098 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1102 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1103 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1104 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1105 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1106 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1107 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1108 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1113 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1115 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1116 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1117 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1118 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1119 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1120 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1124 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1125 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1126 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1127 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1128 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1129 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1130 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1131 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1134 .ctlPowerData_5G = {
1137 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1138 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1143 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1149 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1155 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1161 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1179 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1185 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1186 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1193 static const struct ar9300_eeprom ar9300_h112 = {
1195 .templateVersion = 3,
1196 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1197 .custData = {"h112-241-f0000"},
1199 .regDmn = { LE16(0), LE16(0x1f) },
1200 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1202 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1206 .blueToothOptions = 0,
1208 .deviceType = 5, /* takes lower byte in eeprom location */
1209 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1210 .params_for_tuning_caps = {0, 0},
1211 .featureEnable = 0x0d,
1213 * bit0 - enable tx temp comp - disabled
1214 * bit1 - enable tx volt comp - disabled
1215 * bit2 - enable fastClock - enabled
1216 * bit3 - enable doubling - enabled
1217 * bit4 - enable internal regulator - disabled
1218 * bit5 - enable pa predistortion - disabled
1220 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1221 .eepromWriteEnableGpio = 6,
1222 .wlanDisableGpio = 0,
1224 .rxBandSelectGpio = 0xff,
1229 /* ar9300_modal_eep_header 2g */
1230 /* 4 idle,t1,t2,b(4 bits per setting) */
1231 .antCtrlCommon = LE32(0x110),
1232 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1233 .antCtrlCommon2 = LE32(0x44444),
1236 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1237 * rx1, rx12, b (2 bits each)
1239 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1242 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1243 * for ar9280 (0xa20c/b20c 5:0)
1245 .xatten1DB = {0, 0, 0},
1248 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1249 * for ar9280 (0xa20c/b20c 16:12
1251 .xatten1Margin = {0, 0, 0},
1256 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1257 * channels in usual fbin coding format
1259 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1262 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1263 * if the register is per chain
1265 .noiseFloorThreshCh = {-1, 0, 0},
1266 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1269 .txFrameToDataStart = 0x0e,
1270 .txFrameToPaOn = 0x0e,
1271 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1273 .switchSettling = 0x2c,
1274 .adcDesiredSize = -30,
1277 .txFrameToXpaOn = 0xe,
1279 .papdRateMaskHt20 = LE32(0x0c80c080),
1280 .papdRateMaskHt40 = LE32(0x0080c080),
1282 0, 0, 0, 0, 0, 0, 0, 0,
1286 .ant_div_control = 0,
1287 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1294 /* ar9300_cal_data_per_freq_op_loop 2g */
1296 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1297 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1298 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1300 .calTarget_freqbin_Cck = {
1304 .calTarget_freqbin_2G = {
1309 .calTarget_freqbin_2GHT20 = {
1314 .calTarget_freqbin_2GHT40 = {
1319 .calTargetPowerCck = {
1320 /* 1L-5L,5S,11L,11S */
1321 { {34, 34, 34, 34} },
1322 { {34, 34, 34, 34} },
1324 .calTargetPower2G = {
1326 { {34, 34, 32, 32} },
1327 { {34, 34, 32, 32} },
1328 { {34, 34, 32, 32} },
1330 .calTargetPower2GHT20 = {
1331 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1332 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1333 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1335 .calTargetPower2GHT40 = {
1336 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1337 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1338 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1341 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1342 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1372 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1373 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1374 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1375 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1379 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1380 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1381 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1386 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1387 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1393 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1394 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1395 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1396 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1400 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1402 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1406 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1413 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1420 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1426 .ctlPowerData_2G = {
1427 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1428 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1429 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1431 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1432 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1435 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1436 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1439 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1444 /* 4 idle,t1,t2,b (4 bits per setting) */
1445 .antCtrlCommon = LE32(0x220),
1446 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1447 .antCtrlCommon2 = LE32(0x44444),
1448 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1450 LE16(0x150), LE16(0x150), LE16(0x150),
1452 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1453 .xatten1DB = {0, 0, 0},
1456 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1457 * for merlin (0xa20c/b20c 16:12
1459 .xatten1Margin = {0, 0, 0},
1462 /* spurChans spur channels in usual fbin coding format */
1463 .spurChans = {0, 0, 0, 0, 0},
1464 /* noiseFloorThreshCh Check if the register is per chain */
1465 .noiseFloorThreshCh = {-1, 0, 0},
1466 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1469 .txFrameToDataStart = 0x0e,
1470 .txFrameToPaOn = 0x0e,
1471 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1473 .switchSettling = 0x2d,
1474 .adcDesiredSize = -30,
1477 .txFrameToXpaOn = 0xe,
1479 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1482 0, 0, 0, 0, 0, 0, 0, 0,
1487 .tempSlopeHigh = 50,
1488 .xatten1DBLow = {0, 0, 0},
1489 .xatten1MarginLow = {0, 0, 0},
1490 .xatten1DBHigh = {0, 0, 0},
1491 .xatten1MarginHigh = {0, 0, 0}
1536 .calTarget_freqbin_5G = {
1546 .calTarget_freqbin_5GHT20 = {
1556 .calTarget_freqbin_5GHT40 = {
1566 .calTargetPower5G = {
1568 { {30, 30, 28, 24} },
1569 { {30, 30, 28, 24} },
1570 { {30, 30, 28, 24} },
1571 { {30, 30, 28, 24} },
1572 { {30, 30, 28, 24} },
1573 { {30, 30, 28, 24} },
1574 { {30, 30, 28, 24} },
1575 { {30, 30, 28, 24} },
1577 .calTargetPower5GHT20 = {
1579 * 0_8_16,1-3_9-11_17-19,
1580 * 4,5,6,7,12,13,14,15,20,21,22,23
1582 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1583 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1584 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1585 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1586 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1587 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1588 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1589 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1591 .calTargetPower5GHT40 = {
1593 * 0_8_16,1-3_9-11_17-19,
1594 * 4,5,6,7,12,13,14,15,20,21,22,23
1596 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1597 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1598 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1599 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1600 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1601 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1602 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1603 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1606 0x10, 0x16, 0x18, 0x40, 0x46,
1607 0x48, 0x30, 0x36, 0x38
1611 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1612 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1613 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1614 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1615 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1616 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1617 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1618 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1621 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1622 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1623 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1624 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1625 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1626 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1627 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1628 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1632 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1633 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1634 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1635 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1636 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1637 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1638 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1639 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1643 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1644 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1645 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1646 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1647 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1648 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1649 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1650 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1654 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1657 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1658 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1659 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1660 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1661 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1665 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1666 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1667 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1668 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1669 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1670 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1671 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1672 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1676 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1677 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1678 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1679 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1680 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1681 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1682 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1683 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1687 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1688 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1689 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1690 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1691 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1692 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1693 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1694 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1698 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1699 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1700 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1701 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1702 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1703 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1704 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1705 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1708 .ctlPowerData_5G = {
1711 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1712 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1717 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1718 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1723 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1724 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1729 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1730 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1736 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1742 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1747 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1753 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1754 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1759 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1760 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1767 static const struct ar9300_eeprom ar9300_x112 = {
1769 .templateVersion = 5,
1770 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1771 .custData = {"x112-041-f0000"},
1773 .regDmn = { LE16(0), LE16(0x1f) },
1774 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1776 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1780 .blueToothOptions = 0,
1782 .deviceType = 5, /* takes lower byte in eeprom location */
1783 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1784 .params_for_tuning_caps = {0, 0},
1785 .featureEnable = 0x0d,
1787 * bit0 - enable tx temp comp - disabled
1788 * bit1 - enable tx volt comp - disabled
1789 * bit2 - enable fastclock - enabled
1790 * bit3 - enable doubling - enabled
1791 * bit4 - enable internal regulator - disabled
1792 * bit5 - enable pa predistortion - disabled
1794 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1795 .eepromWriteEnableGpio = 6,
1796 .wlanDisableGpio = 0,
1798 .rxBandSelectGpio = 0xff,
1803 /* ar9300_modal_eep_header 2g */
1804 /* 4 idle,t1,t2,b(4 bits per setting) */
1805 .antCtrlCommon = LE32(0x110),
1806 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1807 .antCtrlCommon2 = LE32(0x22222),
1810 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1811 * rx1, rx12, b (2 bits each)
1813 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1816 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1817 * for ar9280 (0xa20c/b20c 5:0)
1819 .xatten1DB = {0x1b, 0x1b, 0x1b},
1822 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1823 * for ar9280 (0xa20c/b20c 16:12
1825 .xatten1Margin = {0x15, 0x15, 0x15},
1830 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1831 * channels in usual fbin coding format
1833 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1836 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1837 * if the register is per chain
1839 .noiseFloorThreshCh = {-1, 0, 0},
1840 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1843 .txFrameToDataStart = 0x0e,
1844 .txFrameToPaOn = 0x0e,
1845 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1847 .switchSettling = 0x2c,
1848 .adcDesiredSize = -30,
1851 .txFrameToXpaOn = 0xe,
1853 .papdRateMaskHt20 = LE32(0x0c80c080),
1854 .papdRateMaskHt40 = LE32(0x0080c080),
1856 0, 0, 0, 0, 0, 0, 0, 0,
1860 .ant_div_control = 0,
1861 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1868 /* ar9300_cal_data_per_freq_op_loop 2g */
1870 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1871 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1872 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1874 .calTarget_freqbin_Cck = {
1878 .calTarget_freqbin_2G = {
1883 .calTarget_freqbin_2GHT20 = {
1888 .calTarget_freqbin_2GHT40 = {
1893 .calTargetPowerCck = {
1894 /* 1L-5L,5S,11L,11s */
1895 { {38, 38, 38, 38} },
1896 { {38, 38, 38, 38} },
1898 .calTargetPower2G = {
1900 { {38, 38, 36, 34} },
1901 { {38, 38, 36, 34} },
1902 { {38, 38, 34, 32} },
1904 .calTargetPower2GHT20 = {
1905 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1906 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1907 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1909 .calTargetPower2GHT40 = {
1910 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1911 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1912 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1915 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1916 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1946 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1947 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1948 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1949 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1953 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1954 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1955 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1960 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1961 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1967 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1968 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1969 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1970 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1974 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1975 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1976 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1995 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1996 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1997 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2000 .ctlPowerData_2G = {
2001 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2002 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2003 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2005 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2006 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2007 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2009 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2010 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2011 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2013 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2015 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2018 /* 4 idle,t1,t2,b (4 bits per setting) */
2019 .antCtrlCommon = LE32(0x110),
2020 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2021 .antCtrlCommon2 = LE32(0x22222),
2022 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2024 LE16(0x0), LE16(0x0), LE16(0x0),
2026 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2027 .xatten1DB = {0x13, 0x19, 0x17},
2030 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2031 * for merlin (0xa20c/b20c 16:12
2033 .xatten1Margin = {0x19, 0x19, 0x19},
2036 /* spurChans spur channels in usual fbin coding format */
2037 .spurChans = {0, 0, 0, 0, 0},
2038 /* noiseFloorThreshch check if the register is per chain */
2039 .noiseFloorThreshCh = {-1, 0, 0},
2040 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2043 .txFrameToDataStart = 0x0e,
2044 .txFrameToPaOn = 0x0e,
2045 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2047 .switchSettling = 0x2d,
2048 .adcDesiredSize = -30,
2051 .txFrameToXpaOn = 0xe,
2053 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2056 0, 0, 0, 0, 0, 0, 0, 0,
2061 .tempSlopeHigh = 105,
2062 .xatten1DBLow = {0x10, 0x14, 0x10},
2063 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2064 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2065 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2110 .calTarget_freqbin_5G = {
2120 .calTarget_freqbin_5GHT20 = {
2130 .calTarget_freqbin_5GHT40 = {
2140 .calTargetPower5G = {
2142 { {32, 32, 28, 26} },
2143 { {32, 32, 28, 26} },
2144 { {32, 32, 28, 26} },
2145 { {32, 32, 26, 24} },
2146 { {32, 32, 26, 24} },
2147 { {32, 32, 24, 22} },
2148 { {30, 30, 24, 22} },
2149 { {30, 30, 24, 22} },
2151 .calTargetPower5GHT20 = {
2153 * 0_8_16,1-3_9-11_17-19,
2154 * 4,5,6,7,12,13,14,15,20,21,22,23
2156 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2157 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2158 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2159 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2160 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2161 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2162 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2163 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2165 .calTargetPower5GHT40 = {
2167 * 0_8_16,1-3_9-11_17-19,
2168 * 4,5,6,7,12,13,14,15,20,21,22,23
2170 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2171 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2172 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2173 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2174 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2175 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2176 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2177 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2180 0x10, 0x16, 0x18, 0x40, 0x46,
2181 0x48, 0x30, 0x36, 0x38
2185 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2186 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2187 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2188 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2189 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2190 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2191 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2192 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2195 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2196 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2197 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2198 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2199 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2200 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2201 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2202 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2206 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2207 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2208 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2209 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2210 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2211 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2212 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2213 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2217 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2218 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2219 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2221 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2223 /* Data[3].ctledges[6].bchannel */ 0xFF,
2224 /* Data[3].ctledges[7].bchannel */ 0xFF,
2228 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2231 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2232 /* Data[4].ctledges[4].bchannel */ 0xFF,
2233 /* Data[4].ctledges[5].bchannel */ 0xFF,
2234 /* Data[4].ctledges[6].bchannel */ 0xFF,
2235 /* Data[4].ctledges[7].bchannel */ 0xFF,
2239 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2241 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2242 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2243 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2244 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2245 /* Data[5].ctledges[6].bchannel */ 0xFF,
2246 /* Data[5].ctledges[7].bchannel */ 0xFF
2250 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2253 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2254 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2256 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2257 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2261 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2264 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2265 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2266 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2267 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2268 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2272 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2274 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2275 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2277 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2279 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2282 .ctlPowerData_5G = {
2285 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2286 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2291 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2292 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2297 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2298 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2303 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2304 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2309 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2310 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2315 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2316 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2322 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2327 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2328 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2333 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2334 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2340 static const struct ar9300_eeprom ar9300_h116 = {
2342 .templateVersion = 4,
2343 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2344 .custData = {"h116-041-f0000"},
2346 .regDmn = { LE16(0), LE16(0x1f) },
2347 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2349 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2353 .blueToothOptions = 0,
2355 .deviceType = 5, /* takes lower byte in eeprom location */
2356 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2357 .params_for_tuning_caps = {0, 0},
2358 .featureEnable = 0x0d,
2360 * bit0 - enable tx temp comp - disabled
2361 * bit1 - enable tx volt comp - disabled
2362 * bit2 - enable fastClock - enabled
2363 * bit3 - enable doubling - enabled
2364 * bit4 - enable internal regulator - disabled
2365 * bit5 - enable pa predistortion - disabled
2367 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2368 .eepromWriteEnableGpio = 6,
2369 .wlanDisableGpio = 0,
2371 .rxBandSelectGpio = 0xff,
2376 /* ar9300_modal_eep_header 2g */
2377 /* 4 idle,t1,t2,b(4 bits per setting) */
2378 .antCtrlCommon = LE32(0x110),
2379 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2380 .antCtrlCommon2 = LE32(0x44444),
2383 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2384 * rx1, rx12, b (2 bits each)
2386 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2389 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2390 * for ar9280 (0xa20c/b20c 5:0)
2392 .xatten1DB = {0x1f, 0x1f, 0x1f},
2395 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2396 * for ar9280 (0xa20c/b20c 16:12
2398 .xatten1Margin = {0x12, 0x12, 0x12},
2403 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2404 * channels in usual fbin coding format
2406 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2409 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2410 * if the register is per chain
2412 .noiseFloorThreshCh = {-1, 0, 0},
2413 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2416 .txFrameToDataStart = 0x0e,
2417 .txFrameToPaOn = 0x0e,
2418 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2420 .switchSettling = 0x2c,
2421 .adcDesiredSize = -30,
2424 .txFrameToXpaOn = 0xe,
2426 .papdRateMaskHt20 = LE32(0x0c80C080),
2427 .papdRateMaskHt40 = LE32(0x0080C080),
2429 0, 0, 0, 0, 0, 0, 0, 0,
2433 .ant_div_control = 0,
2434 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2441 /* ar9300_cal_data_per_freq_op_loop 2g */
2443 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2444 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2445 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2447 .calTarget_freqbin_Cck = {
2451 .calTarget_freqbin_2G = {
2456 .calTarget_freqbin_2GHT20 = {
2461 .calTarget_freqbin_2GHT40 = {
2466 .calTargetPowerCck = {
2467 /* 1L-5L,5S,11L,11S */
2468 { {34, 34, 34, 34} },
2469 { {34, 34, 34, 34} },
2471 .calTargetPower2G = {
2473 { {34, 34, 32, 32} },
2474 { {34, 34, 32, 32} },
2475 { {34, 34, 32, 32} },
2477 .calTargetPower2GHT20 = {
2478 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2479 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2480 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2482 .calTargetPower2GHT40 = {
2483 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2484 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2485 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2488 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2489 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2519 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2520 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2521 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2522 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2526 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2527 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2528 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2533 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2547 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2553 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2554 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2555 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2560 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2561 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2562 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2567 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2568 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2569 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2570 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2573 .ctlPowerData_2G = {
2574 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2575 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2576 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2578 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2579 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2580 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2582 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2583 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2586 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2587 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2588 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2591 /* 4 idle,t1,t2,b (4 bits per setting) */
2592 .antCtrlCommon = LE32(0x220),
2593 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2594 .antCtrlCommon2 = LE32(0x44444),
2595 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2597 LE16(0x150), LE16(0x150), LE16(0x150),
2599 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2600 .xatten1DB = {0x19, 0x19, 0x19},
2603 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2604 * for merlin (0xa20c/b20c 16:12
2606 .xatten1Margin = {0x14, 0x14, 0x14},
2609 /* spurChans spur channels in usual fbin coding format */
2610 .spurChans = {0, 0, 0, 0, 0},
2611 /* noiseFloorThreshCh Check if the register is per chain */
2612 .noiseFloorThreshCh = {-1, 0, 0},
2613 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2616 .txFrameToDataStart = 0x0e,
2617 .txFrameToPaOn = 0x0e,
2618 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2620 .switchSettling = 0x2d,
2621 .adcDesiredSize = -30,
2624 .txFrameToXpaOn = 0xe,
2626 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2629 0, 0, 0, 0, 0, 0, 0, 0,
2634 .tempSlopeHigh = 50,
2635 .xatten1DBLow = {0, 0, 0},
2636 .xatten1MarginLow = {0, 0, 0},
2637 .xatten1DBHigh = {0, 0, 0},
2638 .xatten1MarginHigh = {0, 0, 0}
2683 .calTarget_freqbin_5G = {
2693 .calTarget_freqbin_5GHT20 = {
2703 .calTarget_freqbin_5GHT40 = {
2713 .calTargetPower5G = {
2715 { {30, 30, 28, 24} },
2716 { {30, 30, 28, 24} },
2717 { {30, 30, 28, 24} },
2718 { {30, 30, 28, 24} },
2719 { {30, 30, 28, 24} },
2720 { {30, 30, 28, 24} },
2721 { {30, 30, 28, 24} },
2722 { {30, 30, 28, 24} },
2724 .calTargetPower5GHT20 = {
2726 * 0_8_16,1-3_9-11_17-19,
2727 * 4,5,6,7,12,13,14,15,20,21,22,23
2729 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2730 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2731 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2732 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2733 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2734 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2735 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2736 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2738 .calTargetPower5GHT40 = {
2740 * 0_8_16,1-3_9-11_17-19,
2741 * 4,5,6,7,12,13,14,15,20,21,22,23
2743 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2744 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2745 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2746 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2747 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2748 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2749 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2750 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2753 0x10, 0x16, 0x18, 0x40, 0x46,
2754 0x48, 0x30, 0x36, 0x38
2758 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2759 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2760 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2761 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2762 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2763 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2764 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2765 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2768 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2769 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2770 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2771 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2772 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2773 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2774 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2775 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2779 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2780 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2781 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2782 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2783 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2784 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2785 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2786 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2790 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2791 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2792 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2793 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2794 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2795 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2796 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2797 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2801 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2804 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2805 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2806 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2807 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2808 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2812 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2813 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2814 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2815 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2816 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2817 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2818 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2819 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2825 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2826 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2827 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2828 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2829 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2834 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2836 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2837 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2838 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2839 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2841 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2845 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2846 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2847 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2848 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2849 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2850 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2851 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2852 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2855 .ctlPowerData_5G = {
2858 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2859 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2864 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2865 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2870 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2871 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2876 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2877 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2882 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2883 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2888 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2889 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2894 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2895 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2900 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2901 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2906 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2914 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2922 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2924 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2927 for (it = 0; it < N_LOOP; it++)
2928 if (ar9300_eep_templates[it]->templateVersion == id)
2929 return ar9300_eep_templates[it];
2934 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2939 static int interpolate(int x, int xa, int xb, int ya, int yb)
2941 int bf, factor, plus;
2943 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2946 return ya + factor + plus;
2949 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2950 enum eeprom_param param)
2952 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2953 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2957 return get_unaligned_be16(eep->macAddr);
2959 return get_unaligned_be16(eep->macAddr + 2);
2961 return get_unaligned_be16(eep->macAddr + 4);
2963 return le16_to_cpu(pBase->regDmn[0]);
2965 return pBase->deviceCap;
2967 return pBase->opCapFlags.opFlags;
2969 return pBase->rfSilent;
2971 return (pBase->txrxMask >> 4) & 0xf;
2973 return pBase->txrxMask & 0xf;
2974 case EEP_DRIVE_STRENGTH:
2975 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
2976 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2977 case EEP_INTERNAL_REGULATOR:
2978 /* Bit 4 is internal regulator flag */
2979 return (pBase->featureEnable & 0x10) >> 4;
2981 return le32_to_cpu(pBase->swreg);
2983 return !!(pBase->featureEnable & BIT(5));
2984 case EEP_CHAIN_MASK_REDUCE:
2985 return (pBase->miscConfiguration >> 0x3) & 0x1;
2986 case EEP_ANT_DIV_CTL1:
2987 return eep->base_ext1.ant_div_control;
2988 case EEP_ANTENNA_GAIN_5G:
2989 return eep->modalHeader5G.antennaGain;
2990 case EEP_ANTENNA_GAIN_2G:
2991 return eep->modalHeader2G.antennaGain;
2992 case EEP_QUICK_DROP:
2993 return pBase->miscConfiguration & BIT(1);
2999 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3004 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3007 *buffer = (val >> (8 * (address % 2))) & 0xff;
3011 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3016 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3019 buffer[0] = val >> 8;
3020 buffer[1] = val & 0xff;
3025 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3028 struct ath_common *common = ath9k_hw_common(ah);
3031 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3032 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3037 * Since we're reading the bytes in reverse order from a little-endian
3038 * word stream, an even address means we only use the lower half of
3039 * the 16-bit word at that address
3041 if (address % 2 == 0) {
3042 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3048 for (i = 0; i < count / 2; i++) {
3049 if (!ar9300_eeprom_read_word(common, address, buffer))
3057 if (!ar9300_eeprom_read_byte(common, address, buffer))
3063 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3068 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3070 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3072 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3073 AR9300_OTP_STATUS_VALID, 1000))
3076 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3080 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3086 for (i = 0; i < count; i++) {
3087 int offset = 8 * ((address - i) % 4);
3088 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3091 buffer[i] = (data >> offset) & 0xff;
3098 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3099 int *length, int *major, int *minor)
3101 unsigned long value[4];
3107 *code = ((value[0] >> 5) & 0x0007);
3108 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3109 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3110 *major = (value[2] & 0x000f);
3111 *minor = (value[3] & 0x00ff);
3114 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3116 int it, checksum = 0;
3118 for (it = 0; it < dsize; it++) {
3119 checksum += data[it];
3126 static bool ar9300_uncompress_block(struct ath_hw *ah,
3136 struct ath_common *common = ath9k_hw_common(ah);
3140 for (it = 0; it < size; it += (length+2)) {
3144 length = block[it+1];
3147 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3148 ath_dbg(common, EEPROM,
3149 "Restore at %d: spot=%d offset=%d length=%d\n",
3150 it, spot, offset, length);
3151 memcpy(&mptr[spot], &block[it+2], length);
3153 } else if (length > 0) {
3154 ath_dbg(common, EEPROM,
3155 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3156 it, spot, offset, length);
3163 static int ar9300_compress_decision(struct ath_hw *ah,
3168 u8 *word, int length, int mdata_size)
3170 struct ath_common *common = ath9k_hw_common(ah);
3171 const struct ar9300_eeprom *eep = NULL;
3175 if (length != mdata_size) {
3176 ath_dbg(common, EEPROM,
3177 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3178 mdata_size, length);
3181 memcpy(mptr, word + COMP_HDR_LEN, length);
3182 ath_dbg(common, EEPROM,
3183 "restored eeprom %d: uncompressed, length %d\n",
3186 case _CompressBlock:
3187 if (reference == 0) {
3189 eep = ar9003_eeprom_struct_find_by_id(reference);
3191 ath_dbg(common, EEPROM,
3192 "can't find reference eeprom struct %d\n",
3196 memcpy(mptr, eep, mdata_size);
3198 ath_dbg(common, EEPROM,
3199 "restore eeprom %d: block, reference %d, length %d\n",
3200 it, reference, length);
3201 ar9300_uncompress_block(ah, mptr, mdata_size,
3202 (word + COMP_HDR_LEN), length);
3205 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3211 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3214 static bool ar9300_check_header(void *data)
3217 return !(*word == 0 || *word == ~0);
3220 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3225 if (!read(ah, base_addr, header, 4))
3228 return ar9300_check_header(header);
3231 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3234 struct ath_common *common = ath9k_hw_common(ah);
3235 u16 *data = (u16 *) mptr;
3238 for (i = 0; i < mdata_size / 2; i++, data++)
3239 ath9k_hw_nvram_read(common, i, data);
3244 * Read the configuration data from the eeprom.
3245 * The data can be put in any specified memory buffer.
3247 * Returns -1 on error.
3248 * Returns address of next memory location on success.
3250 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3251 u8 *mptr, int mdata_size)
3258 int reference, length, major, minor;
3261 u16 checksum, mchecksum;
3262 struct ath_common *common = ath9k_hw_common(ah);
3263 eeprom_read_op read;
3265 if (ath9k_hw_use_flash(ah))
3266 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3268 word = kzalloc(2048, GFP_KERNEL);
3272 memcpy(mptr, &ar9300_default, mdata_size);
3274 read = ar9300_read_eeprom;
3275 if (AR_SREV_9485(ah))
3276 cptr = AR9300_BASE_ADDR_4K;
3277 else if (AR_SREV_9330(ah))
3278 cptr = AR9300_BASE_ADDR_512;
3280 cptr = AR9300_BASE_ADDR;
3281 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3283 if (ar9300_check_eeprom_header(ah, read, cptr))
3286 cptr = AR9300_BASE_ADDR_512;
3287 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3289 if (ar9300_check_eeprom_header(ah, read, cptr))
3292 read = ar9300_read_otp;
3293 cptr = AR9300_BASE_ADDR;
3294 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3295 if (ar9300_check_eeprom_header(ah, read, cptr))
3298 cptr = AR9300_BASE_ADDR_512;
3299 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3300 if (ar9300_check_eeprom_header(ah, read, cptr))
3306 ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3308 for (it = 0; it < MSTATE; it++) {
3309 if (!read(ah, cptr, word, COMP_HDR_LEN))
3312 if (!ar9300_check_header(word))
3315 ar9300_comp_hdr_unpack(word, &code, &reference,
3316 &length, &major, &minor);
3317 ath_dbg(common, EEPROM,
3318 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3319 cptr, code, reference, length, major, minor);
3320 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3321 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3322 ath_dbg(common, EEPROM, "Skipping bad header\n");
3323 cptr -= COMP_HDR_LEN;
3328 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3329 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3330 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3331 ath_dbg(common, EEPROM, "checksum %x %x\n",
3332 checksum, mchecksum);
3333 if (checksum == mchecksum) {
3334 ar9300_compress_decision(ah, it, code, reference, mptr,
3335 word, length, mdata_size);
3337 ath_dbg(common, EEPROM,
3338 "skipping block with bad checksum\n");
3340 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3352 * Restore the configuration structure by reading the eeprom.
3353 * This function destroys any existing in-memory structure
3356 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3358 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3360 if (ar9300_eeprom_restore_internal(ah, mptr,
3361 sizeof(struct ar9300_eeprom)) < 0)
3367 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3368 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3369 struct ar9300_modal_eep_header *modal_hdr)
3371 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3372 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3373 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3374 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3375 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3376 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3377 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3378 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3379 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3380 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3381 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3382 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3383 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3384 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3385 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3386 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3387 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3388 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3389 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3390 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3391 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3392 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3393 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3394 PR_EEP("Quick Drop", modal_hdr->quick_drop);
3395 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3396 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3397 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3398 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3399 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3400 PR_EEP("txClip", modal_hdr->txClip);
3401 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3406 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3407 u8 *buf, u32 len, u32 size)
3409 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3410 struct ar9300_base_eep_hdr *pBase;
3412 if (!dump_base_hdr) {
3413 len += snprintf(buf + len, size - len,
3414 "%20s :\n", "2GHz modal Header");
3415 len = ar9003_dump_modal_eeprom(buf, len, size,
3416 &eep->modalHeader2G);
3417 len += snprintf(buf + len, size - len,
3418 "%20s :\n", "5GHz modal Header");
3419 len = ar9003_dump_modal_eeprom(buf, len, size,
3420 &eep->modalHeader5G);
3424 pBase = &eep->baseEepHeader;
3426 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3427 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3428 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3429 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3430 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3431 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3432 AR5416_OPFLAGS_11A));
3433 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3434 AR5416_OPFLAGS_11G));
3435 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3436 AR5416_OPFLAGS_N_2G_HT20));
3437 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3438 AR5416_OPFLAGS_N_2G_HT40));
3439 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3440 AR5416_OPFLAGS_N_5G_HT20));
3441 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3442 AR5416_OPFLAGS_N_5G_HT40));
3443 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3444 PR_EEP("RF Silent", pBase->rfSilent);
3445 PR_EEP("BT option", pBase->blueToothOptions);
3446 PR_EEP("Device Cap", pBase->deviceCap);
3447 PR_EEP("Device Type", pBase->deviceType);
3448 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3449 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3450 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3451 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3452 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3453 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3454 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3455 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3456 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3457 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3458 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3459 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3460 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3461 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3462 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3463 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3464 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3465 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3466 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3468 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3469 ah->eeprom.ar9300_eep.macAddr);
3477 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3478 u8 *buf, u32 len, u32 size)
3484 /* XXX: review hardware docs */
3485 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3487 return ah->eeprom.ar9300_eep.eepromVersion;
3490 /* XXX: could be read from the eepromVersion, not sure yet */
3491 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3496 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3498 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3501 return eep->modalHeader2G.xpaBiasLvl;
3503 return eep->modalHeader5G.xpaBiasLvl;
3506 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3508 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3510 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3511 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3512 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
3513 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3515 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3516 REG_RMW_FIELD(ah, AR_CH0_THERM,
3517 AR_CH0_THERM_XPABIASLVL_MSB,
3519 REG_RMW_FIELD(ah, AR_CH0_THERM,
3520 AR_CH0_THERM_XPASHORT2GND, 1);
3524 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3526 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3530 val = eep->modalHeader2G.switchcomspdt;
3532 val = eep->modalHeader5G.switchcomspdt;
3533 return le16_to_cpu(val);
3537 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3539 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3543 val = eep->modalHeader2G.antCtrlCommon;
3545 val = eep->modalHeader5G.antCtrlCommon;
3546 return le32_to_cpu(val);
3549 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3551 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3555 val = eep->modalHeader2G.antCtrlCommon2;
3557 val = eep->modalHeader5G.antCtrlCommon2;
3558 return le32_to_cpu(val);
3561 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3565 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3568 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3570 val = eep->modalHeader2G.antCtrlChain[chain];
3572 val = eep->modalHeader5G.antCtrlChain[chain];
3575 return le16_to_cpu(val);
3578 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3583 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3584 AR_PHY_SWITCH_CHAIN_0,
3585 AR_PHY_SWITCH_CHAIN_1,
3586 AR_PHY_SWITCH_CHAIN_2,
3589 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3591 if (AR_SREV_9462(ah)) {
3592 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3593 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3594 } else if (AR_SREV_9550(ah)) {
3595 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3596 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3598 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3599 AR_SWITCH_TABLE_COM_ALL, value);
3603 * AR9462 defines new switch table for BT/WLAN,
3604 * here's new field name in XXX.ref for both 2G and 5G.
3605 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3606 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3607 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3609 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3610 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3612 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3613 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3615 if (AR_SREV_9462_20_OR_LATER(ah)) {
3616 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3617 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3618 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3619 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3622 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3623 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3625 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3626 if ((ah->rxchainmask & BIT(chain)) ||
3627 (ah->txchainmask & BIT(chain))) {
3628 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3630 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3631 AR_SWITCH_TABLE_ALL, value);
3635 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3636 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3638 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3639 * are the fields present
3641 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3642 regval &= (~AR_ANT_DIV_CTRL_ALL);
3643 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3645 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3646 regval |= ((value >> 6) & 0x1) <<
3647 AR_PHY_9485_ANT_DIV_LNADIV_S;
3648 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3650 /*enable fast_div */
3651 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3652 regval &= (~AR_FAST_DIV_ENABLE);
3653 regval |= ((value >> 7) & 0x1) <<
3654 AR_FAST_DIV_ENABLE_S;
3655 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3657 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3658 /* check whether antenna diversity is enabled */
3659 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3660 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3662 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3665 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3666 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3667 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3668 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3669 /* by default use LNA1 for the main antenna */
3670 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3671 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3672 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3673 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3674 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3682 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3687 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3689 if (!drive_strength)
3692 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3700 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3702 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3713 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3715 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3720 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3723 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3724 struct ath9k_channel *chan)
3728 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3730 if (chain >= 0 && chain < 3) {
3731 if (IS_CHAN_2GHZ(chan))
3732 return eep->modalHeader2G.xatten1DB[chain];
3733 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3734 t[0] = eep->base_ext2.xatten1DBLow[chain];
3736 t[1] = eep->modalHeader5G.xatten1DB[chain];
3738 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3740 value = ar9003_hw_power_interpolate((s32) chan->channel,
3744 return eep->modalHeader5G.xatten1DB[chain];
3751 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3752 struct ath9k_channel *chan)
3756 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3758 if (chain >= 0 && chain < 3) {
3759 if (IS_CHAN_2GHZ(chan))
3760 return eep->modalHeader2G.xatten1Margin[chain];
3761 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3762 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3764 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3766 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3768 value = ar9003_hw_power_interpolate((s32) chan->channel,
3772 return eep->modalHeader5G.xatten1Margin[chain];
3778 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3782 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3783 AR_PHY_EXT_ATTEN_CTL_1,
3784 AR_PHY_EXT_ATTEN_CTL_2,
3787 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3788 for (i = 0; i < 3; i++) {
3789 if (ah->txchainmask & BIT(i)) {
3790 value = ar9003_hw_atten_chain_get(ah, i, chan);
3791 REG_RMW_FIELD(ah, ext_atten_reg[i],
3792 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3794 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3795 REG_RMW_FIELD(ah, ext_atten_reg[i],
3796 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3802 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3806 while (pmu_set != REG_READ(ah, pmu_reg)) {
3809 REG_WRITE(ah, pmu_reg, pmu_set);
3816 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3818 int internal_regulator =
3819 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3822 if (internal_regulator) {
3823 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3826 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3827 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3828 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3831 if (AR_SREV_9330(ah)) {
3832 if (ah->is_clk_25mhz) {
3833 reg_pmu_set = (3 << 1) | (8 << 4) |
3834 (3 << 8) | (1 << 14) |
3835 (6 << 17) | (1 << 20) |
3838 reg_pmu_set = (4 << 1) | (7 << 4) |
3839 (3 << 8) | (1 << 14) |
3840 (6 << 17) | (1 << 20) |
3844 reg_pmu_set = (5 << 1) | (7 << 4) |
3845 (2 << 8) | (2 << 14) |
3846 (6 << 17) | (1 << 20) |
3847 (3 << 24) | (1 << 28);
3850 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3851 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3854 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3856 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3857 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3860 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3862 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3863 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3865 } else if (AR_SREV_9462(ah)) {
3866 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3867 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3869 /* Internal regulator is ON. Write swreg register. */
3870 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3871 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3872 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3873 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3874 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3875 /* Set REG_CONTROL1.SWREG_PROGRAM */
3876 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3878 AR_RTC_REG_CONTROL1) |
3879 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3882 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3883 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3884 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3888 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3889 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3892 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3893 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3896 } else if (AR_SREV_9462(ah))
3897 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3899 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3900 AR_RTC_FORCE_SWREG_PRD;
3901 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3907 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3909 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3910 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3912 if (eep->baseEepHeader.featureEnable & 0x40) {
3913 tuning_caps_param &= 0x7f;
3914 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3916 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3921 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3923 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3924 int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
3925 s32 t[3], f[3] = {5180, 5500, 5785};
3931 quick_drop = eep->modalHeader2G.quick_drop;
3933 t[0] = eep->base_ext1.quick_drop_low;
3934 t[1] = eep->modalHeader5G.quick_drop;
3935 t[2] = eep->base_ext1.quick_drop_high;
3936 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3938 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3941 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3943 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3946 value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
3947 eep->modalHeader5G.txEndToXpaOff;
3949 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3950 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3951 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3952 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3955 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3956 struct ath9k_channel *chan)
3958 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3959 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3960 ar9003_hw_drive_strength_apply(ah);
3961 ar9003_hw_atten_apply(ah, chan);
3962 ar9003_hw_quick_drop_apply(ah, chan->channel);
3963 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
3964 ar9003_hw_internal_regulator_apply(ah);
3965 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3966 ar9003_hw_apply_tuning_caps(ah);
3967 ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
3970 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3971 struct ath9k_channel *chan)
3976 * Returns the interpolated y value corresponding to the specified x value
3977 * from the np ordered pairs of data (px,py).
3978 * The pairs do not have to be in any order.
3979 * If the specified x value is less than any of the px,
3980 * the returned y value is equal to the py for the lowest px.
3981 * If the specified x value is greater than any of the px,
3982 * the returned y value is equal to the py for the highest px.
3984 static int ar9003_hw_power_interpolate(int32_t x,
3985 int32_t *px, int32_t *py, u_int16_t np)
3988 int lx = 0, ly = 0, lhave = 0;
3989 int hx = 0, hy = 0, hhave = 0;
3996 /* identify best lower and higher x calibration measurement */
3997 for (ip = 0; ip < np; ip++) {
4000 /* this measurement is higher than our desired x */
4002 if (!hhave || dx > (x - hx)) {
4003 /* new best higher x measurement */
4009 /* this measurement is lower than our desired x */
4011 if (!lhave || dx < (x - lx)) {
4012 /* new best lower x measurement */
4020 /* the low x is good */
4022 /* so is the high x */
4024 /* they're the same, so just pick one */
4027 else /* interpolate */
4028 y = interpolate(x, lx, hx, ly, hy);
4029 } else /* only low is good, use it */
4031 } else if (hhave) /* only high is good, use it */
4033 else /* nothing is good,this should never happen unless np=0, ???? */
4038 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4039 u16 rateIndex, u16 freq, bool is2GHz)
4042 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4043 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4044 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4045 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4049 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4050 pEepromTargetPwr = eep->calTargetPower2G;
4051 pFreqBin = eep->calTarget_freqbin_2G;
4053 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4054 pEepromTargetPwr = eep->calTargetPower5G;
4055 pFreqBin = eep->calTarget_freqbin_5G;
4059 * create array of channels and targetpower from
4060 * targetpower piers stored on eeprom
4062 for (i = 0; i < numPiers; i++) {
4063 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4064 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4067 /* interpolate to get target power for given frequency */
4068 return (u8) ar9003_hw_power_interpolate((s32) freq,
4070 targetPowerArray, numPiers);
4073 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4075 u16 freq, bool is2GHz)
4078 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4079 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4080 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4081 struct cal_tgt_pow_ht *pEepromTargetPwr;
4085 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4086 pEepromTargetPwr = eep->calTargetPower2GHT20;
4087 pFreqBin = eep->calTarget_freqbin_2GHT20;
4089 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4090 pEepromTargetPwr = eep->calTargetPower5GHT20;
4091 pFreqBin = eep->calTarget_freqbin_5GHT20;
4095 * create array of channels and targetpower
4096 * from targetpower piers stored on eeprom
4098 for (i = 0; i < numPiers; i++) {
4099 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4100 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4103 /* interpolate to get target power for given frequency */
4104 return (u8) ar9003_hw_power_interpolate((s32) freq,
4106 targetPowerArray, numPiers);
4109 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4111 u16 freq, bool is2GHz)
4114 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4115 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4116 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4117 struct cal_tgt_pow_ht *pEepromTargetPwr;
4121 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4122 pEepromTargetPwr = eep->calTargetPower2GHT40;
4123 pFreqBin = eep->calTarget_freqbin_2GHT40;
4125 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4126 pEepromTargetPwr = eep->calTargetPower5GHT40;
4127 pFreqBin = eep->calTarget_freqbin_5GHT40;
4131 * create array of channels and targetpower from
4132 * targetpower piers stored on eeprom
4134 for (i = 0; i < numPiers; i++) {
4135 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4136 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4139 /* interpolate to get target power for given frequency */
4140 return (u8) ar9003_hw_power_interpolate((s32) freq,
4142 targetPowerArray, numPiers);
4145 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4146 u16 rateIndex, u16 freq)
4148 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4149 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4150 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4151 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4152 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4153 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4156 * create array of channels and targetpower from
4157 * targetpower piers stored on eeprom
4159 for (i = 0; i < numPiers; i++) {
4160 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4161 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4164 /* interpolate to get target power for given frequency */
4165 return (u8) ar9003_hw_power_interpolate((s32) freq,
4167 targetPowerArray, numPiers);
4170 /* Set tx power registers to array of values passed in */
4171 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4173 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4174 /* make sure forced gain is not set */
4175 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4177 /* Write the OFDM power per rate set */
4179 /* 6 (LSB), 9, 12, 18 (MSB) */
4180 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4181 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4182 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4183 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4184 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4186 /* 24 (LSB), 36, 48, 54 (MSB) */
4187 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4188 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4189 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4190 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4191 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4193 /* Write the CCK power per rate set */
4195 /* 1L (LSB), reserved, 2L, 2S (MSB) */
4196 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4197 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4198 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4199 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4200 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4202 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4203 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4204 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4205 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4206 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4207 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4210 /* Write the power for duplicated frames - HT40 */
4212 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4213 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4214 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4215 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4216 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4217 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4220 /* Write the HT20 power per rate set */
4222 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4223 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4224 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4225 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4226 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4227 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4230 /* 6 (LSB), 7, 12, 13 (MSB) */
4231 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4232 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4233 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4234 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4235 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4238 /* 14 (LSB), 15, 20, 21 */
4239 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4240 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4241 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4242 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4243 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4246 /* Mixed HT20 and HT40 rates */
4248 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4249 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4250 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4251 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4252 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4253 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4257 * Write the HT40 power per rate set
4258 * correct PAR difference between HT40 and HT20/LEGACY
4259 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4261 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4262 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4263 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4264 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4265 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4268 /* 6 (LSB), 7, 12, 13 (MSB) */
4269 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4270 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4271 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4272 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4273 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4276 /* 14 (LSB), 15, 20, 21 */
4277 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4278 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4279 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4280 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4281 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4288 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4289 u8 *targetPowerValT2,
4292 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4293 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4295 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4296 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4298 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4299 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4301 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4302 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4306 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4307 u8 *targetPowerValT2)
4309 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4310 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4312 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4313 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4314 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4315 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4316 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4317 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4320 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4321 u8 *targetPowerValT2, bool is2GHz)
4323 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4324 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4326 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4327 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4329 targetPowerValT2[ALL_TARGET_HT20_4] =
4330 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4332 targetPowerValT2[ALL_TARGET_HT20_5] =
4333 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4335 targetPowerValT2[ALL_TARGET_HT20_6] =
4336 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4338 targetPowerValT2[ALL_TARGET_HT20_7] =
4339 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4341 targetPowerValT2[ALL_TARGET_HT20_12] =
4342 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4344 targetPowerValT2[ALL_TARGET_HT20_13] =
4345 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4347 targetPowerValT2[ALL_TARGET_HT20_14] =
4348 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4350 targetPowerValT2[ALL_TARGET_HT20_15] =
4351 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4353 targetPowerValT2[ALL_TARGET_HT20_20] =
4354 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4356 targetPowerValT2[ALL_TARGET_HT20_21] =
4357 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4359 targetPowerValT2[ALL_TARGET_HT20_22] =
4360 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4362 targetPowerValT2[ALL_TARGET_HT20_23] =
4363 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4367 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4369 u8 *targetPowerValT2,
4372 /* XXX: hard code for now, need to get from eeprom struct */
4373 u8 ht40PowerIncForPdadc = 0;
4375 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4376 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4377 is2GHz) + ht40PowerIncForPdadc;
4378 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4379 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4381 is2GHz) + ht40PowerIncForPdadc;
4382 targetPowerValT2[ALL_TARGET_HT40_4] =
4383 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4384 is2GHz) + ht40PowerIncForPdadc;
4385 targetPowerValT2[ALL_TARGET_HT40_5] =
4386 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4387 is2GHz) + ht40PowerIncForPdadc;
4388 targetPowerValT2[ALL_TARGET_HT40_6] =
4389 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4390 is2GHz) + ht40PowerIncForPdadc;
4391 targetPowerValT2[ALL_TARGET_HT40_7] =
4392 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4393 is2GHz) + ht40PowerIncForPdadc;
4394 targetPowerValT2[ALL_TARGET_HT40_12] =
4395 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4396 is2GHz) + ht40PowerIncForPdadc;
4397 targetPowerValT2[ALL_TARGET_HT40_13] =
4398 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4399 is2GHz) + ht40PowerIncForPdadc;
4400 targetPowerValT2[ALL_TARGET_HT40_14] =
4401 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4402 is2GHz) + ht40PowerIncForPdadc;
4403 targetPowerValT2[ALL_TARGET_HT40_15] =
4404 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4405 is2GHz) + ht40PowerIncForPdadc;
4406 targetPowerValT2[ALL_TARGET_HT40_20] =
4407 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4408 is2GHz) + ht40PowerIncForPdadc;
4409 targetPowerValT2[ALL_TARGET_HT40_21] =
4410 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4411 is2GHz) + ht40PowerIncForPdadc;
4412 targetPowerValT2[ALL_TARGET_HT40_22] =
4413 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4414 is2GHz) + ht40PowerIncForPdadc;
4415 targetPowerValT2[ALL_TARGET_HT40_23] =
4416 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4417 is2GHz) + ht40PowerIncForPdadc;
4420 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4421 struct ath9k_channel *chan,
4422 u8 *targetPowerValT2)
4424 bool is2GHz = IS_CHAN_2GHZ(chan);
4426 struct ath_common *common = ath9k_hw_common(ah);
4427 u16 freq = chan->channel;
4430 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4432 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4433 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4435 if (IS_CHAN_HT40(chan))
4436 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4439 for (i = 0; i < ar9300RateSize; i++) {
4440 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4441 i, targetPowerValT2[i]);
4445 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4451 int *ptemperature, int *pvoltage)
4454 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4456 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4457 struct ath_common *common = ath9k_hw_common(ah);
4459 if (ichain >= AR9300_MAX_CHAINS) {
4460 ath_dbg(common, EEPROM,
4461 "Invalid chain index, must be less than %d\n",
4466 if (mode) { /* 5GHz */
4467 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4468 ath_dbg(common, EEPROM,
4469 "Invalid 5GHz cal pier index, must be less than %d\n",
4470 AR9300_NUM_5G_CAL_PIERS);
4473 pCalPier = &(eep->calFreqPier5G[ipier]);
4474 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4477 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4478 ath_dbg(common, EEPROM,
4479 "Invalid 2GHz cal pier index, must be less than %d\n",
4480 AR9300_NUM_2G_CAL_PIERS);
4484 pCalPier = &(eep->calFreqPier2G[ipier]);
4485 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4489 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
4490 *pcorrection = pCalPierStruct->refPower;
4491 *ptemperature = pCalPierStruct->tempMeas;
4492 *pvoltage = pCalPierStruct->voltMeas;
4497 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4500 int *voltage, int *temperature)
4503 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4506 REG_RMW(ah, AR_PHY_TPC_11_B0,
4507 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4508 AR_PHY_TPC_OLPC_GAIN_DELTA);
4509 if (ah->caps.tx_chainmask & BIT(1))
4510 REG_RMW(ah, AR_PHY_TPC_11_B1,
4511 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4512 AR_PHY_TPC_OLPC_GAIN_DELTA);
4513 if (ah->caps.tx_chainmask & BIT(2))
4514 REG_RMW(ah, AR_PHY_TPC_11_B2,
4515 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4516 AR_PHY_TPC_OLPC_GAIN_DELTA);
4518 /* enable open loop power control on chip */
4519 REG_RMW(ah, AR_PHY_TPC_6_B0,
4520 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4521 AR_PHY_TPC_6_ERROR_EST_MODE);
4522 if (ah->caps.tx_chainmask & BIT(1))
4523 REG_RMW(ah, AR_PHY_TPC_6_B1,
4524 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4525 AR_PHY_TPC_6_ERROR_EST_MODE);
4526 if (ah->caps.tx_chainmask & BIT(2))
4527 REG_RMW(ah, AR_PHY_TPC_6_B2,
4528 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4529 AR_PHY_TPC_6_ERROR_EST_MODE);
4532 * enable temperature compensation
4533 * Need to use register names
4535 if (frequency < 4000)
4536 tempSlope = eep->modalHeader2G.tempSlope;
4537 else if (eep->base_ext2.tempSlopeLow != 0) {
4538 t[0] = eep->base_ext2.tempSlopeLow;
4540 t[1] = eep->modalHeader5G.tempSlope;
4542 t[2] = eep->base_ext2.tempSlopeHigh;
4544 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4547 tempSlope = eep->modalHeader5G.tempSlope;
4549 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4551 if (AR_SREV_9462_20(ah))
4552 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4553 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4556 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4562 /* Apply the recorded correction values. */
4563 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4565 int ichain, ipier, npier;
4567 int lfrequency[AR9300_MAX_CHAINS],
4568 lcorrection[AR9300_MAX_CHAINS],
4569 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4570 int hfrequency[AR9300_MAX_CHAINS],
4571 hcorrection[AR9300_MAX_CHAINS],
4572 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4574 int correction[AR9300_MAX_CHAINS],
4575 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4576 int pfrequency, pcorrection, ptemperature, pvoltage;
4577 struct ath_common *common = ath9k_hw_common(ah);
4579 mode = (frequency >= 4000);
4581 npier = AR9300_NUM_5G_CAL_PIERS;
4583 npier = AR9300_NUM_2G_CAL_PIERS;
4585 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4586 lfrequency[ichain] = 0;
4587 hfrequency[ichain] = 100000;
4589 /* identify best lower and higher frequency calibration measurement */
4590 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4591 for (ipier = 0; ipier < npier; ipier++) {
4592 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4593 &pfrequency, &pcorrection,
4594 &ptemperature, &pvoltage)) {
4595 fdiff = frequency - pfrequency;
4598 * this measurement is higher than
4599 * our desired frequency
4602 if (hfrequency[ichain] <= 0 ||
4603 hfrequency[ichain] >= 100000 ||
4605 (frequency - hfrequency[ichain])) {
4608 * frequency measurement
4610 hfrequency[ichain] = pfrequency;
4611 hcorrection[ichain] =
4613 htemperature[ichain] =
4615 hvoltage[ichain] = pvoltage;
4619 if (lfrequency[ichain] <= 0
4621 (frequency - lfrequency[ichain])) {
4624 * frequency measurement
4626 lfrequency[ichain] = pfrequency;
4627 lcorrection[ichain] =
4629 ltemperature[ichain] =
4631 lvoltage[ichain] = pvoltage;
4639 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4640 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4641 ichain, frequency, lfrequency[ichain],
4642 lcorrection[ichain], hfrequency[ichain],
4643 hcorrection[ichain]);
4644 /* they're the same, so just pick one */
4645 if (hfrequency[ichain] == lfrequency[ichain]) {
4646 correction[ichain] = lcorrection[ichain];
4647 voltage[ichain] = lvoltage[ichain];
4648 temperature[ichain] = ltemperature[ichain];
4650 /* the low frequency is good */
4651 else if (frequency - lfrequency[ichain] < 1000) {
4652 /* so is the high frequency, interpolate */
4653 if (hfrequency[ichain] - frequency < 1000) {
4655 correction[ichain] = interpolate(frequency,
4658 lcorrection[ichain],
4659 hcorrection[ichain]);
4661 temperature[ichain] = interpolate(frequency,
4664 ltemperature[ichain],
4665 htemperature[ichain]);
4667 voltage[ichain] = interpolate(frequency,
4673 /* only low is good, use it */
4675 correction[ichain] = lcorrection[ichain];
4676 temperature[ichain] = ltemperature[ichain];
4677 voltage[ichain] = lvoltage[ichain];
4680 /* only high is good, use it */
4681 else if (hfrequency[ichain] - frequency < 1000) {
4682 correction[ichain] = hcorrection[ichain];
4683 temperature[ichain] = htemperature[ichain];
4684 voltage[ichain] = hvoltage[ichain];
4685 } else { /* nothing is good, presume 0???? */
4686 correction[ichain] = 0;
4687 temperature[ichain] = 0;
4688 voltage[ichain] = 0;
4692 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4695 ath_dbg(common, EEPROM,
4696 "for frequency=%d, calibration correction = %d %d %d\n",
4697 frequency, correction[0], correction[1], correction[2]);
4702 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4707 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4708 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4711 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4713 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4716 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4722 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4723 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4725 u8 *ctl_freqbin = is2GHz ?
4726 &eep->ctl_freqbin_2G[idx][0] :
4727 &eep->ctl_freqbin_5G[idx][0];
4730 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4731 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4732 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4734 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4735 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4736 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4739 return MAX_RATE_POWER;
4743 * Find the maximum conformance test limit for the given channel and CTL info
4745 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4746 u16 freq, int idx, bool is2GHz)
4748 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4749 u8 *ctl_freqbin = is2GHz ?
4750 &eep->ctl_freqbin_2G[idx][0] :
4751 &eep->ctl_freqbin_5G[idx][0];
4752 u16 num_edges = is2GHz ?
4753 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4756 /* Get the edge power */
4758 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4761 * If there's an exact channel match or an inband flag set
4762 * on the lower channel use the given rdEdgePower
4764 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4766 ar9003_hw_get_direct_edge_power(eep, idx,
4769 } else if ((edge > 0) &&
4770 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4773 ar9003_hw_get_indirect_edge_power(eep, idx,
4777 * Leave loop - no more affecting edges possible in
4778 * this monotonic increasing list
4783 return twiceMaxEdgePower;
4786 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4787 struct ath9k_channel *chan,
4788 u8 *pPwrArray, u16 cfgCtl,
4789 u8 antenna_reduction,
4792 struct ath_common *common = ath9k_hw_common(ah);
4793 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4794 u16 twiceMaxEdgePower;
4796 u16 scaledPower = 0, minCtlPower;
4797 static const u16 ctlModesFor11a[] = {
4798 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4800 static const u16 ctlModesFor11g[] = {
4801 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4802 CTL_11G_EXT, CTL_2GHT40
4805 const u16 *pCtlMode;
4807 struct chan_centers centers;
4810 u16 twiceMinEdgePower;
4811 bool is2ghz = IS_CHAN_2GHZ(chan);
4813 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
4814 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4818 /* Setup for CTL modes */
4819 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4821 ARRAY_SIZE(ctlModesFor11g) -
4822 SUB_NUM_CTL_MODES_AT_2G_40;
4823 pCtlMode = ctlModesFor11g;
4824 if (IS_CHAN_HT40(chan))
4826 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4828 /* Setup for CTL modes */
4829 /* CTL_11A, CTL_5GHT20 */
4830 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4831 SUB_NUM_CTL_MODES_AT_5G_40;
4832 pCtlMode = ctlModesFor11a;
4833 if (IS_CHAN_HT40(chan))
4835 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4839 * For MIMO, need to apply regulatory caps individually across
4840 * dynamically running modes: CCK, OFDM, HT20, HT40
4842 * The outer loop walks through each possible applicable runtime mode.
4843 * The inner loop walks through each ctlIndex entry in EEPROM.
4844 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4846 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4847 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4848 (pCtlMode[ctlMode] == CTL_2GHT40);
4850 freq = centers.synth_center;
4851 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4852 freq = centers.ext_center;
4854 freq = centers.ctl_center;
4856 ath_dbg(common, REGULATORY,
4857 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4858 ctlMode, numCtlModes, isHt40CtlMode,
4859 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4861 /* walk through each CTL index stored in EEPROM */
4863 ctlIndex = pEepData->ctlIndex_2G;
4864 ctlNum = AR9300_NUM_CTLS_2G;
4866 ctlIndex = pEepData->ctlIndex_5G;
4867 ctlNum = AR9300_NUM_CTLS_5G;
4870 twiceMaxEdgePower = MAX_RATE_POWER;
4871 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4872 ath_dbg(common, REGULATORY,
4873 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4874 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4878 * compare test group from regulatory
4879 * channel list with test mode from pCtlMode
4882 if ((((cfgCtl & ~CTL_MODE_M) |
4883 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4885 (((cfgCtl & ~CTL_MODE_M) |
4886 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4887 ((ctlIndex[i] & CTL_MODE_M) |
4890 ar9003_hw_get_max_edge_power(pEepData,
4894 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4896 * Find the minimum of all CTL
4897 * edge powers that apply to
4901 min(twiceMaxEdgePower,
4912 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4914 ath_dbg(common, REGULATORY,
4915 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4916 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4917 scaledPower, minCtlPower);
4919 /* Apply ctl mode to correct target power set */
4920 switch (pCtlMode[ctlMode]) {
4922 for (i = ALL_TARGET_LEGACY_1L_5L;
4923 i <= ALL_TARGET_LEGACY_11S; i++)
4925 (u8)min((u16)pPwrArray[i],
4930 for (i = ALL_TARGET_LEGACY_6_24;
4931 i <= ALL_TARGET_LEGACY_54; i++)
4933 (u8)min((u16)pPwrArray[i],
4938 for (i = ALL_TARGET_HT20_0_8_16;
4939 i <= ALL_TARGET_HT20_21; i++)
4941 (u8)min((u16)pPwrArray[i],
4943 pPwrArray[ALL_TARGET_HT20_22] =
4944 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4946 pPwrArray[ALL_TARGET_HT20_23] =
4947 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4952 for (i = ALL_TARGET_HT40_0_8_16;
4953 i <= ALL_TARGET_HT40_23; i++)
4955 (u8)min((u16)pPwrArray[i],
4961 } /* end ctl mode checking */
4964 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4966 u8 mod_idx = mcs_idx % 8;
4969 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4971 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4974 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4975 struct ath9k_channel *chan, u16 cfgCtl,
4976 u8 twiceAntennaReduction,
4977 u8 powerLimit, bool test)
4979 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4980 struct ath_common *common = ath9k_hw_common(ah);
4981 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4982 struct ar9300_modal_eep_header *modal_hdr;
4983 u8 targetPowerValT2[ar9300RateSize];
4984 u8 target_power_val_t2_eep[ar9300RateSize];
4985 unsigned int i = 0, paprd_scale_factor = 0;
4986 u8 pwr_idx, min_pwridx = 0;
4988 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
4991 * Get target powers from EEPROM - our baseline for TX Power
4993 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
4995 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4996 if (IS_CHAN_2GHZ(chan))
4997 modal_hdr = &eep->modalHeader2G;
4999 modal_hdr = &eep->modalHeader5G;
5001 ah->paprd_ratemask =
5002 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5003 AR9300_PAPRD_RATE_MASK;
5005 ah->paprd_ratemask_ht40 =
5006 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5007 AR9300_PAPRD_RATE_MASK;
5009 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5010 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5011 ALL_TARGET_HT20_0_8_16;
5013 if (!ah->paprd_table_write_done) {
5014 memcpy(target_power_val_t2_eep, targetPowerValT2,
5015 sizeof(targetPowerValT2));
5016 for (i = 0; i < 24; i++) {
5017 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5018 if (ah->paprd_ratemask & (1 << i)) {
5019 if (targetPowerValT2[pwr_idx] &&
5020 targetPowerValT2[pwr_idx] ==
5021 target_power_val_t2_eep[pwr_idx])
5022 targetPowerValT2[pwr_idx] -=
5027 memcpy(target_power_val_t2_eep, targetPowerValT2,
5028 sizeof(targetPowerValT2));
5031 ar9003_hw_set_power_per_rate_table(ah, chan,
5032 targetPowerValT2, cfgCtl,
5033 twiceAntennaReduction,
5036 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5037 for (i = 0; i < ar9300RateSize; i++) {
5038 if ((ah->paprd_ratemask & (1 << i)) &&
5039 (abs(targetPowerValT2[i] -
5040 target_power_val_t2_eep[i]) >
5041 paprd_scale_factor)) {
5042 ah->paprd_ratemask &= ~(1 << i);
5043 ath_dbg(common, EEPROM,
5044 "paprd disabled for mcs %d\n", i);
5049 regulatory->max_power_level = 0;
5050 for (i = 0; i < ar9300RateSize; i++) {
5051 if (targetPowerValT2[i] > regulatory->max_power_level)
5052 regulatory->max_power_level = targetPowerValT2[i];
5055 ath9k_hw_update_regulatory_maxpower(ah);
5060 for (i = 0; i < ar9300RateSize; i++) {
5061 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5062 i, targetPowerValT2[i]);
5065 /* Write target power array to registers */
5066 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5067 ar9003_hw_calibration_apply(ah, chan->channel);
5069 if (IS_CHAN_2GHZ(chan)) {
5070 if (IS_CHAN_HT40(chan))
5071 i = ALL_TARGET_HT40_0_8_16;
5073 i = ALL_TARGET_HT20_0_8_16;
5075 if (IS_CHAN_HT40(chan))
5076 i = ALL_TARGET_HT40_7;
5078 i = ALL_TARGET_HT20_7;
5080 ah->paprd_target_power = targetPowerValT2[i];
5083 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5089 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5091 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5093 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5096 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5098 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5100 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5103 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5105 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5108 return eep->modalHeader2G.spurChans;
5110 return eep->modalHeader5G.spurChans;
5113 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5114 struct ath9k_channel *chan)
5116 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5118 if (IS_CHAN_2GHZ(chan))
5119 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5120 AR9300_PAPRD_SCALE_1);
5122 if (chan->channel >= 5700)
5123 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5124 AR9300_PAPRD_SCALE_1);
5125 else if (chan->channel >= 5400)
5126 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5127 AR9300_PAPRD_SCALE_2);
5129 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5130 AR9300_PAPRD_SCALE_1);
5134 const struct eeprom_ops eep_ar9300_ops = {
5135 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5136 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5137 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5138 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5139 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5140 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5141 .set_board_values = ath9k_hw_ar9300_set_board_values,
5142 .set_addac = ath9k_hw_ar9300_set_addac,
5143 .set_txpower = ath9k_hw_ar9300_set_txpower,
5144 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel