1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/module.h>
17 #define ATH12K_PCI_BAR_NUM 0
18 #define ATH12K_PCI_DMA_MASK 32
20 #define ATH12K_PCI_IRQ_CE0_OFFSET 3
22 #define WINDOW_ENABLE_BIT 0x40000000
23 #define WINDOW_REG_ADDRESS 0x310c
24 #define WINDOW_VALUE_MASK GENMASK(24, 19)
25 #define WINDOW_START 0x80000
26 #define WINDOW_RANGE_MASK GENMASK(18, 0)
27 #define WINDOW_STATIC_MASK GENMASK(31, 6)
29 #define TCSR_SOC_HW_VERSION 0x1B00000
30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4)
33 /* BAR0 + 4k is always accessible, and no
34 * need to force wakeup.
37 #define ACCESS_ALWAYS_OFF 0xFE0
39 #define QCN9274_DEVICE_ID 0x1109
40 #define WCN7850_DEVICE_ID 0x1107
42 static const struct pci_device_id ath12k_pci_id_table[] = {
43 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
44 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
48 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
50 /* TODO: revisit IRQ mapping for new SRNG's */
51 static const struct ath12k_msi_config ath12k_msi_config[] = {
55 .users = (struct ath12k_msi_user[]) {
56 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
57 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
58 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
63 static const struct ath12k_msi_config msi_config_one_msi = {
66 .users = (struct ath12k_msi_user[]) {
67 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
68 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
69 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
70 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
74 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {
95 "host2reo-re-injection",
97 "host2rxdma-monitor-ring3",
98 "host2rxdma-monitor-ring2",
99 "host2rxdma-monitor-ring1",
101 "wbm2host-rx-release",
103 "reo2host-destination-ring4",
104 "reo2host-destination-ring3",
105 "reo2host-destination-ring2",
106 "reo2host-destination-ring1",
107 "rxdma2host-monitor-destination-mac3",
108 "rxdma2host-monitor-destination-mac2",
109 "rxdma2host-monitor-destination-mac1",
110 "ppdu-end-interrupts-mac3",
111 "ppdu-end-interrupts-mac2",
112 "ppdu-end-interrupts-mac1",
113 "rxdma2host-monitor-status-ring-mac3",
114 "rxdma2host-monitor-status-ring-mac2",
115 "rxdma2host-monitor-status-ring-mac1",
116 "host2rxdma-host-buf-ring-mac3",
117 "host2rxdma-host-buf-ring-mac2",
118 "host2rxdma-host-buf-ring-mac1",
119 "rxdma2host-destination-ring-mac3",
120 "rxdma2host-destination-ring-mac2",
121 "rxdma2host-destination-ring-mac1",
122 "host2tcl-input-ring4",
123 "host2tcl-input-ring3",
124 "host2tcl-input-ring2",
125 "host2tcl-input-ring1",
126 "wbm2host-tx-completions-ring4",
127 "wbm2host-tx-completions-ring3",
128 "wbm2host-tx-completions-ring2",
129 "wbm2host-tx-completions-ring1",
130 "tcl2host-status-ring",
133 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab)
135 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
137 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
140 static void ath12k_pci_bus_release(struct ath12k_base *ab)
142 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
144 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
147 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = {
152 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = {
153 .wakeup = ath12k_pci_bus_wake_up,
154 .release = ath12k_pci_bus_release,
157 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset)
159 struct ath12k_base *ab = ab_pci->ab;
161 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK);
164 lockdep_assert_held(&ab_pci->window_lock);
166 /* Preserve the static window configuration and reset only dynamic window */
167 static_window = ab_pci->register_window & WINDOW_STATIC_MASK;
168 window |= static_window;
170 if (window != ab_pci->register_window) {
171 iowrite32(WINDOW_ENABLE_BIT | window,
172 ab->mem + WINDOW_REG_ADDRESS);
173 ioread32(ab->mem + WINDOW_REG_ADDRESS);
174 ab_pci->register_window = window;
178 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci)
180 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK);
181 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK);
184 window = (umac_window << 12) | (ce_window << 6);
186 spin_lock_bh(&ab_pci->window_lock);
187 ab_pci->register_window = window;
188 spin_unlock_bh(&ab_pci->window_lock);
190 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
193 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab,
198 /* If offset lies within DP register range, use 3rd window */
199 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
200 window_start = 3 * WINDOW_START;
201 /* If offset lies within CE register range, use 2nd window */
202 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
203 window_start = 2 * WINDOW_START;
204 /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE
207 else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) &&
208 !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK))
211 window_start = WINDOW_START;
216 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
220 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
222 val |= PCIE_SOC_GLOBAL_RESET_V;
224 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
226 /* TODO: exact time to sleep is uncertain */
230 /* Need to toggle V bit back otherwise stuck in reset status */
231 val &= ~PCIE_SOC_GLOBAL_RESET_V;
233 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
237 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
238 if (val == 0xffffffff)
239 ath12k_warn(ab, "link down error during global reset\n");
242 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab)
247 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
248 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val);
250 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
251 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
253 /* TODO: exact time to sleep is uncertain */
256 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
257 * continuing warm path and entering dead loop.
259 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0);
262 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
263 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
265 /* A read clear register. clear the register to prevent
266 * Q6 from entering wrong code path.
268 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
269 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val);
272 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab)
277 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
279 /* PCIE link seems very unstable after the Hot Reset*/
280 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
281 if (val == 0xffffffff)
284 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
285 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
288 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);
290 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
291 val |= GCC_GCC_PCIE_HOT_RST_VAL;
292 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
293 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
295 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
300 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab)
302 /* This is a WAR for PCIE Hotreset.
303 * When target receive Hotreset, but will set the interrupt.
304 * So when download SBL again, SBL will open Interrupt and
305 * receive it, and crash immediately.
307 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
310 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab)
314 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
315 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
316 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
319 static void ath12k_pci_force_wake(struct ath12k_base *ab)
321 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
325 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on)
328 ath12k_pci_enable_ltssm(ab);
329 ath12k_pci_clear_all_intrs(ab);
330 ath12k_pci_set_wlaon_pwr_ctrl(ab);
333 ath12k_mhi_clear_vector(ab);
334 ath12k_pci_clear_dbg_registers(ab);
335 ath12k_pci_soc_global_reset(ab);
336 ath12k_mhi_set_mhictrl_reset(ab);
339 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab)
343 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
344 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
346 for (j = 0; j < irq_grp->num_irq; j++)
347 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
349 netif_napi_del(&irq_grp->napi);
353 static void ath12k_pci_free_irq(struct ath12k_base *ab)
357 for (i = 0; i < ab->hw_params->ce_count; i++) {
358 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
360 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
361 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
364 ath12k_pci_free_ext_irq(ab);
367 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)
369 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
372 /* In case of one MSI vector, we handle irq enable/disable in a
373 * uniform way since we only have one irq
375 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
378 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
379 enable_irq(ab->irq_num[irq_idx]);
382 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)
384 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
387 /* In case of one MSI vector, we handle irq enable/disable in a
388 * uniform way since we only have one irq
390 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
393 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
394 disable_irq_nosync(ab->irq_num[irq_idx]);
397 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)
401 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
403 for (i = 0; i < ab->hw_params->ce_count; i++) {
404 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
406 ath12k_pci_ce_irq_disable(ab, i);
410 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab)
415 for (i = 0; i < ab->hw_params->ce_count; i++) {
416 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
419 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
420 synchronize_irq(ab->irq_num[irq_idx]);
424 static void ath12k_pci_ce_tasklet(struct tasklet_struct *t)
426 struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
427 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
429 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
431 enable_irq(ce_pipe->ab->irq_num[irq_idx]);
434 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)
436 struct ath12k_ce_pipe *ce_pipe = arg;
437 struct ath12k_base *ab = ce_pipe->ab;
438 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
440 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
443 /* last interrupt received for this CE */
444 ce_pipe->timestamp = jiffies;
446 disable_irq_nosync(ab->irq_num[irq_idx]);
448 tasklet_schedule(&ce_pipe->intr_tq);
453 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
455 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab);
458 /* In case of one MSI vector, we handle irq enable/disable
459 * in a uniform way since we only have one irq
461 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
464 for (i = 0; i < irq_grp->num_irq; i++)
465 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
468 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
472 clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
474 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
475 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
477 ath12k_pci_ext_grp_disable(irq_grp);
479 napi_synchronize(&irq_grp->napi);
480 napi_disable(&irq_grp->napi);
484 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)
486 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab);
489 /* In case of one MSI vector, we handle irq enable/disable in a
490 * uniform way since we only have one irq
492 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
495 for (i = 0; i < irq_grp->num_irq; i++)
496 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
499 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab)
503 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
504 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
506 for (j = 0; j < irq_grp->num_irq; j++) {
507 irq_idx = irq_grp->irqs[j];
508 synchronize_irq(ab->irq_num[irq_idx]);
513 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
515 struct ath12k_ext_irq_grp *irq_grp = container_of(napi,
516 struct ath12k_ext_irq_grp,
518 struct ath12k_base *ab = irq_grp->ab;
522 work_done = ath12k_dp_service_srng(ab, irq_grp, budget);
523 if (work_done < budget) {
524 napi_complete_done(napi, work_done);
525 for (i = 0; i < irq_grp->num_irq; i++)
526 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
529 if (work_done > budget)
535 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)
537 struct ath12k_ext_irq_grp *irq_grp = arg;
538 struct ath12k_base *ab = irq_grp->ab;
541 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
544 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);
546 /* last interrupt received for this group */
547 irq_grp->timestamp = jiffies;
549 for (i = 0; i < irq_grp->num_irq; i++)
550 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
552 napi_schedule(&irq_grp->napi);
557 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)
559 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
560 int i, j, ret, num_vectors = 0;
561 u32 user_base_data = 0, base_vector = 0, base_idx;
563 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
564 ret = ath12k_pci_get_user_msi_assignment(ab, "DP",
571 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
572 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
577 init_dummy_netdev(&irq_grp->napi_ndev);
578 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
579 ath12k_pci_ext_grp_napi_poll);
581 if (ab->hw_params->ring_mask->tx[i] ||
582 ab->hw_params->ring_mask->rx[i] ||
583 ab->hw_params->ring_mask->rx_err[i] ||
584 ab->hw_params->ring_mask->rx_wbm_rel[i] ||
585 ab->hw_params->ring_mask->reo_status[i] ||
586 ab->hw_params->ring_mask->host2rxdma[i] ||
587 ab->hw_params->ring_mask->rx_mon_dest[i]) {
591 irq_grp->num_irq = num_irq;
592 irq_grp->irqs[0] = base_idx + i;
594 for (j = 0; j < irq_grp->num_irq; j++) {
595 int irq_idx = irq_grp->irqs[j];
596 int vector = (i % num_vectors) + base_vector;
597 int irq = ath12k_pci_get_msi_irq(ab->dev, vector);
599 ab->irq_num[irq_idx] = irq;
601 ath12k_dbg(ab, ATH12K_DBG_PCI,
602 "irq:%d group:%d\n", irq, i);
604 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
605 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler,
607 "DP_EXT_IRQ", irq_grp);
609 ath12k_err(ab, "failed request irq %d: %d\n",
614 ath12k_pci_ext_grp_disable(irq_grp);
620 static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci,
621 const struct cpumask *m)
623 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
626 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
629 static int ath12k_pci_config_irq(struct ath12k_base *ab)
631 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
632 struct ath12k_ce_pipe *ce_pipe;
634 u32 msi_data_count, msi_data_idx;
636 unsigned int msi_data;
637 int irq, i, ret, irq_idx;
639 ret = ath12k_pci_get_user_msi_assignment(ab,
640 "CE", &msi_data_count,
641 &msi_data_start, &msi_irq_start);
645 /* Configure CE irqs */
647 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
648 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
651 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
652 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data);
653 ce_pipe = &ab->ce.ce_pipe[i];
655 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
657 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet);
659 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler,
660 ab_pci->irq_flags, irq_name[irq_idx],
663 ath12k_err(ab, "failed to request irq %d: %d\n",
668 ab->irq_num[irq_idx] = irq;
671 ath12k_pci_ce_irq_disable(ab, i);
674 ret = ath12k_pci_ext_irq_config(ab);
681 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
683 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
685 cfg->tgt_ce = ab->hw_params->target_ce_config;
686 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
688 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
689 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
690 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
693 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
697 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
699 for (i = 0; i < ab->hw_params->ce_count; i++) {
700 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
702 ath12k_pci_ce_irq_enable(ab, i);
706 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable)
708 struct pci_dev *dev = ab_pci->pdev;
711 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
714 control |= PCI_MSI_FLAGS_ENABLE;
716 control &= ~PCI_MSI_FLAGS_ENABLE;
718 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
721 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci)
723 ath12k_pci_msi_config(ab_pci, true);
726 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci)
728 ath12k_pci_msi_config(ab_pci, false);
731 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)
733 struct ath12k_base *ab = ab_pci->ab;
734 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
735 struct msi_desc *msi_desc;
739 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
740 msi_config->total_vectors,
741 msi_config->total_vectors,
744 if (num_vectors == msi_config->total_vectors) {
745 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
746 ab_pci->irq_flags = IRQF_SHARED;
748 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
752 if (num_vectors < 0) {
754 goto reset_msi_config;
756 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
757 ab_pci->msi_config = &msi_config_one_msi;
758 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
759 ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n");
762 ath12k_info(ab, "MSI vectors: %d\n", num_vectors);
764 ath12k_pci_msi_disable(ab_pci);
766 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
768 ath12k_err(ab, "msi_desc is NULL!\n");
770 goto free_msi_vector;
773 ab_pci->msi_ep_base_data = msi_desc->msg.data;
774 if (msi_desc->pci.msi_attrib.is_64)
775 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
777 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
782 pci_free_irq_vectors(ab_pci->pdev);
788 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci)
790 pci_free_irq_vectors(ab_pci->pdev);
793 static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci)
795 struct msi_desc *msi_desc;
797 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
799 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n");
800 pci_free_irq_vectors(ab_pci->pdev);
804 ab_pci->msi_ep_base_data = msi_desc->msg.data;
806 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
807 ab_pci->msi_ep_base_data);
812 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev)
814 struct ath12k_base *ab = ab_pci->ab;
818 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
819 if (device_id != ab_pci->dev_id) {
820 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
821 device_id, ab_pci->dev_id);
826 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM);
828 ath12k_err(ab, "failed to assign pci resource: %d\n", ret);
832 ret = pci_enable_device(pdev);
834 ath12k_err(ab, "failed to enable pci device: %d\n", ret);
838 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci");
840 ath12k_err(ab, "failed to request pci region: %d\n", ret);
844 ret = dma_set_mask_and_coherent(&pdev->dev,
845 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK));
847 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n",
848 ATH12K_PCI_DMA_MASK, ret);
852 pci_set_master(pdev);
854 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM);
855 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0);
857 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM);
862 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
866 pci_release_region(pdev, ATH12K_PCI_BAR_NUM);
868 pci_disable_device(pdev);
873 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci)
875 struct ath12k_base *ab = ab_pci->ab;
876 struct pci_dev *pci_dev = ab_pci->pdev;
878 pci_iounmap(pci_dev, ab->mem);
880 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM);
881 if (pci_is_enabled(pci_dev))
882 pci_disable_device(pci_dev);
885 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci)
887 struct ath12k_base *ab = ab_pci->ab;
889 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
892 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
894 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
895 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
897 /* disable L0s and L1 */
898 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
899 PCI_EXP_LNKCTL_ASPMC);
901 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
904 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
906 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
907 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
908 PCI_EXP_LNKCTL_ASPMC,
910 PCI_EXP_LNKCTL_ASPMC);
913 static void ath12k_pci_kill_tasklets(struct ath12k_base *ab)
917 for (i = 0; i < ab->hw_params->ce_count; i++) {
918 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
920 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
923 tasklet_kill(&ce_pipe->intr_tq);
927 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab)
929 ath12k_pci_ce_irqs_disable(ab);
930 ath12k_pci_sync_ce_irqs(ab);
931 ath12k_pci_kill_tasklets(ab);
934 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
935 u8 *ul_pipe, u8 *dl_pipe)
937 const struct service_to_pipe *entry;
938 bool ul_set = false, dl_set = false;
941 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) {
942 entry = &ab->hw_params->svc_to_ce_map[i];
944 if (__le32_to_cpu(entry->service_id) != service_id)
947 switch (__le32_to_cpu(entry->pipedir)) {
952 *dl_pipe = __le32_to_cpu(entry->pipenum);
957 *ul_pipe = __le32_to_cpu(entry->pipenum);
963 *dl_pipe = __le32_to_cpu(entry->pipenum);
964 *ul_pipe = __le32_to_cpu(entry->pipenum);
971 if (WARN_ON(!ul_set || !dl_set))
977 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector)
979 struct pci_dev *pci_dev = to_pci_dev(dev);
981 return pci_irq_vector(pci_dev, vector);
984 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
985 int *num_vectors, u32 *user_base_data,
988 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
989 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
992 for (idx = 0; idx < msi_config->total_users; idx++) {
993 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
994 *num_vectors = msi_config->users[idx].num_vectors;
995 *base_vector = msi_config->users[idx].base_vector;
996 *user_base_data = *base_vector + ab_pci->msi_ep_base_data;
998 ath12k_dbg(ab, ATH12K_DBG_PCI,
999 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
1000 user_name, *num_vectors, *user_base_data,
1007 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
1012 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
1015 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1016 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
1018 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
1021 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
1022 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
1029 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
1032 u32 i, msi_data_idx;
1034 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
1035 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
1043 *msi_idx = msi_data_idx;
1046 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab)
1048 ath12k_pci_ce_irqs_enable(ab);
1051 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab)
1053 ath12k_pci_ce_irq_disable_sync(ab);
1056 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)
1060 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
1062 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
1063 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
1065 napi_enable(&irq_grp->napi);
1066 ath12k_pci_ext_grp_enable(irq_grp);
1070 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
1072 __ath12k_pci_ext_irq_disable(ab);
1073 ath12k_pci_sync_ext_irqs(ab);
1076 int ath12k_pci_hif_suspend(struct ath12k_base *ab)
1078 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
1080 ath12k_mhi_suspend(ar_pci);
1085 int ath12k_pci_hif_resume(struct ath12k_base *ab)
1087 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
1089 ath12k_mhi_resume(ar_pci);
1094 void ath12k_pci_stop(struct ath12k_base *ab)
1096 ath12k_pci_ce_irq_disable_sync(ab);
1097 ath12k_ce_cleanup_pipes(ab);
1100 int ath12k_pci_start(struct ath12k_base *ab)
1102 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1104 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1106 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
1107 ath12k_pci_aspm_restore(ab_pci);
1109 ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
1111 ath12k_pci_ce_irqs_enable(ab);
1112 ath12k_ce_rx_post_buf(ab);
1117 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset)
1119 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1120 u32 val, window_start;
1123 /* for offset beyond BAR + 4K - 32, may
1124 * need to wakeup MHI to access.
1126 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1127 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1128 ret = ab_pci->pci_ops->wakeup(ab);
1130 if (offset < WINDOW_START) {
1131 val = ioread32(ab->mem + offset);
1133 if (ab->static_window_map)
1134 window_start = ath12k_pci_get_window_start(ab, offset);
1136 window_start = WINDOW_START;
1138 if (window_start == WINDOW_START) {
1139 spin_lock_bh(&ab_pci->window_lock);
1140 ath12k_pci_select_window(ab_pci, offset);
1141 val = ioread32(ab->mem + window_start +
1142 (offset & WINDOW_RANGE_MASK));
1143 spin_unlock_bh(&ab_pci->window_lock);
1145 if ((!window_start) &&
1146 (offset >= PCI_MHIREGLEN_REG &&
1147 offset <= PCI_MHI_REGION_END))
1148 offset = offset - PCI_MHIREGLEN_REG;
1150 val = ioread32(ab->mem + window_start +
1151 (offset & WINDOW_RANGE_MASK));
1155 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1156 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1158 ab_pci->pci_ops->release(ab);
1162 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value)
1164 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1168 /* for offset beyond BAR + 4K - 32, may
1169 * need to wakeup MHI to access.
1171 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1172 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1173 ret = ab_pci->pci_ops->wakeup(ab);
1175 if (offset < WINDOW_START) {
1176 iowrite32(value, ab->mem + offset);
1178 if (ab->static_window_map)
1179 window_start = ath12k_pci_get_window_start(ab, offset);
1181 window_start = WINDOW_START;
1183 if (window_start == WINDOW_START) {
1184 spin_lock_bh(&ab_pci->window_lock);
1185 ath12k_pci_select_window(ab_pci, offset);
1186 iowrite32(value, ab->mem + window_start +
1187 (offset & WINDOW_RANGE_MASK));
1188 spin_unlock_bh(&ab_pci->window_lock);
1190 if ((!window_start) &&
1191 (offset >= PCI_MHIREGLEN_REG &&
1192 offset <= PCI_MHI_REGION_END))
1193 offset = offset - PCI_MHIREGLEN_REG;
1195 iowrite32(value, ab->mem + window_start +
1196 (offset & WINDOW_RANGE_MASK));
1200 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1201 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1203 ab_pci->pci_ops->release(ab);
1206 int ath12k_pci_power_up(struct ath12k_base *ab)
1208 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1211 ab_pci->register_window = 0;
1212 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1213 ath12k_pci_sw_reset(ab_pci->ab, true);
1215 /* Disable ASPM during firmware download due to problems switching
1218 ath12k_pci_aspm_disable(ab_pci);
1220 ath12k_pci_msi_enable(ab_pci);
1222 ret = ath12k_mhi_start(ab_pci);
1224 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1228 if (ab->static_window_map)
1229 ath12k_pci_select_static_window(ab_pci);
1234 void ath12k_pci_power_down(struct ath12k_base *ab)
1236 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1238 /* restore aspm in case firmware bootup fails */
1239 ath12k_pci_aspm_restore(ab_pci);
1241 ath12k_pci_force_wake(ab_pci->ab);
1242 ath12k_pci_msi_disable(ab_pci);
1243 ath12k_mhi_stop(ab_pci);
1244 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1245 ath12k_pci_sw_reset(ab_pci->ab, false);
1248 static const struct ath12k_hif_ops ath12k_pci_hif_ops = {
1249 .start = ath12k_pci_start,
1250 .stop = ath12k_pci_stop,
1251 .read32 = ath12k_pci_read32,
1252 .write32 = ath12k_pci_write32,
1253 .power_down = ath12k_pci_power_down,
1254 .power_up = ath12k_pci_power_up,
1255 .suspend = ath12k_pci_hif_suspend,
1256 .resume = ath12k_pci_hif_resume,
1257 .irq_enable = ath12k_pci_ext_irq_enable,
1258 .irq_disable = ath12k_pci_ext_irq_disable,
1259 .get_msi_address = ath12k_pci_get_msi_address,
1260 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment,
1261 .map_service_to_pipe = ath12k_pci_map_service_to_pipe,
1262 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable,
1263 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable,
1264 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx,
1268 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor)
1272 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION);
1273 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
1275 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
1278 ath12k_dbg(ab, ATH12K_DBG_PCI,
1279 "pci tcsr_soc_hw_version major %d minor %d\n",
1283 static int ath12k_pci_probe(struct pci_dev *pdev,
1284 const struct pci_device_id *pci_dev)
1286 struct ath12k_base *ab;
1287 struct ath12k_pci *ab_pci;
1288 u32 soc_hw_version_major, soc_hw_version_minor;
1291 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI);
1293 dev_err(&pdev->dev, "failed to allocate ath12k base\n");
1297 ab->dev = &pdev->dev;
1298 pci_set_drvdata(pdev, ab);
1299 ab_pci = ath12k_pci_priv(ab);
1300 ab_pci->dev_id = pci_dev->device;
1302 ab_pci->pdev = pdev;
1303 ab->hif.ops = &ath12k_pci_hif_ops;
1304 pci_set_drvdata(pdev, ab);
1305 spin_lock_init(&ab_pci->window_lock);
1307 ret = ath12k_pci_claim(ab_pci, pdev);
1309 ath12k_err(ab, "failed to claim device: %d\n", ret);
1313 ath12k_dbg(ab, ATH12K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
1314 pdev->vendor, pdev->device,
1315 pdev->subsystem_vendor, pdev->subsystem_device);
1317 ab->id.vendor = pdev->vendor;
1318 ab->id.device = pdev->device;
1319 ab->id.subsystem_vendor = pdev->subsystem_vendor;
1320 ab->id.subsystem_device = pdev->subsystem_device;
1322 switch (pci_dev->device) {
1323 case QCN9274_DEVICE_ID:
1324 ab_pci->msi_config = &ath12k_msi_config[0];
1325 ab->static_window_map = true;
1326 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274;
1327 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1328 &soc_hw_version_minor);
1329 switch (soc_hw_version_major) {
1330 case ATH12K_PCI_SOC_HW_VERSION_2:
1331 ab->hw_rev = ATH12K_HW_QCN9274_HW20;
1333 case ATH12K_PCI_SOC_HW_VERSION_1:
1334 ab->hw_rev = ATH12K_HW_QCN9274_HW10;
1338 "Unknown hardware version found for QCN9274: 0x%x\n",
1339 soc_hw_version_major);
1341 goto err_pci_free_region;
1344 case WCN7850_DEVICE_ID:
1345 ab->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
1346 ab_pci->msi_config = &ath12k_msi_config[0];
1347 ab->static_window_map = false;
1348 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850;
1349 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1350 &soc_hw_version_minor);
1351 switch (soc_hw_version_major) {
1352 case ATH12K_PCI_SOC_HW_VERSION_2:
1353 ab->hw_rev = ATH12K_HW_WCN7850_HW20;
1357 "Unknown hardware version found for WCN7850: 0x%x\n",
1358 soc_hw_version_major);
1360 goto err_pci_free_region;
1365 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1368 goto err_pci_free_region;
1371 ret = ath12k_pci_msi_alloc(ab_pci);
1373 ath12k_err(ab, "failed to alloc msi: %d\n", ret);
1374 goto err_pci_free_region;
1377 ret = ath12k_core_pre_init(ab);
1379 goto err_pci_msi_free;
1381 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
1383 ath12k_err(ab, "failed to set irq affinity %d\n", ret);
1384 goto err_pci_msi_free;
1387 ret = ath12k_mhi_register(ab_pci);
1389 ath12k_err(ab, "failed to register mhi: %d\n", ret);
1390 goto err_irq_affinity_cleanup;
1393 ret = ath12k_hal_srng_init(ab);
1395 goto err_mhi_unregister;
1397 ret = ath12k_ce_alloc_pipes(ab);
1399 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1400 goto err_hal_srng_deinit;
1403 ath12k_pci_init_qmi_ce_config(ab);
1405 ret = ath12k_pci_config_irq(ab);
1407 ath12k_err(ab, "failed to config irq: %d\n", ret);
1411 /* kernel may allocate a dummy vector before request_irq and
1412 * then allocate a real vector when request_irq is called.
1413 * So get msi_data here again to avoid spurious interrupt
1414 * as msi_data will configured to srngs.
1416 ret = ath12k_pci_config_msi_data(ab_pci);
1418 ath12k_err(ab, "failed to config msi_data: %d\n", ret);
1422 ret = ath12k_core_init(ab);
1424 ath12k_err(ab, "failed to init core: %d\n", ret);
1430 ath12k_pci_free_irq(ab);
1433 ath12k_ce_free_pipes(ab);
1435 err_hal_srng_deinit:
1436 ath12k_hal_srng_deinit(ab);
1439 ath12k_mhi_unregister(ab_pci);
1442 ath12k_pci_msi_free(ab_pci);
1444 err_irq_affinity_cleanup:
1445 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);
1447 err_pci_free_region:
1448 ath12k_pci_free_region(ab_pci);
1451 ath12k_core_free(ab);
1456 static void ath12k_pci_remove(struct pci_dev *pdev)
1458 struct ath12k_base *ab = pci_get_drvdata(pdev);
1459 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1461 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);
1463 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1464 ath12k_pci_power_down(ab);
1465 ath12k_qmi_deinit_service(ab);
1469 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags);
1471 cancel_work_sync(&ab->reset_work);
1472 ath12k_core_deinit(ab);
1475 ath12k_mhi_unregister(ab_pci);
1477 ath12k_pci_free_irq(ab);
1478 ath12k_pci_msi_free(ab_pci);
1479 ath12k_pci_free_region(ab_pci);
1481 ath12k_hal_srng_deinit(ab);
1482 ath12k_ce_free_pipes(ab);
1483 ath12k_core_free(ab);
1486 static void ath12k_pci_shutdown(struct pci_dev *pdev)
1488 struct ath12k_base *ab = pci_get_drvdata(pdev);
1489 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1491 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);
1492 ath12k_pci_power_down(ab);
1495 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev)
1497 struct ath12k_base *ab = dev_get_drvdata(dev);
1500 ret = ath12k_core_suspend(ab);
1502 ath12k_warn(ab, "failed to suspend core: %d\n", ret);
1507 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev)
1509 struct ath12k_base *ab = dev_get_drvdata(dev);
1512 ret = ath12k_core_resume(ab);
1514 ath12k_warn(ab, "failed to resume core: %d\n", ret);
1519 static SIMPLE_DEV_PM_OPS(ath12k_pci_pm_ops,
1520 ath12k_pci_pm_suspend,
1521 ath12k_pci_pm_resume);
1523 static struct pci_driver ath12k_pci_driver = {
1524 .name = "ath12k_pci",
1525 .id_table = ath12k_pci_id_table,
1526 .probe = ath12k_pci_probe,
1527 .remove = ath12k_pci_remove,
1528 .shutdown = ath12k_pci_shutdown,
1529 .driver.pm = &ath12k_pci_pm_ops,
1532 static int ath12k_pci_init(void)
1536 ret = pci_register_driver(&ath12k_pci_driver);
1538 pr_err("failed to register ath12k pci driver: %d\n",
1545 module_init(ath12k_pci_init);
1547 static void ath12k_pci_exit(void)
1549 pci_unregister_driver(&ath12k_pci_driver);
1552 module_exit(ath12k_pci_exit);
1554 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11be WLAN devices");
1555 MODULE_LICENSE("Dual BSD/GPL");