drivers/net/wireless/ath/ath12k/dp_mon.c

   1 // SPDX-License-Identifier: BSD-3-Clause-Clear
   2 /*
   3  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #include "dp_mon.h"
   8 #include "debug.h"
   9 #include "dp_rx.h"
  10 #include "dp_tx.h"
  11 #include "peer.h"
  12
  13 static void ath12k_dp_mon_rx_handle_ofdma_info(void *rx_tlv,
  14                                                struct hal_rx_user_status *rx_user_status)
  15 {
  16         struct hal_rx_ppdu_end_user_stats *ppdu_end_user = rx_tlv;
  17
  18         rx_user_status->ul_ofdma_user_v0_word0 =
  19                 __le32_to_cpu(ppdu_end_user->usr_resp_ref);
  20         rx_user_status->ul_ofdma_user_v0_word1 =
  21                 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);
  22 }
  23
  24 static void
  25 ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,
  26                                      void *ppduinfo,
  27                                      struct hal_rx_user_status *rx_user_status)
  28 {
  29         u32 mpdu_ok_byte_count = __le32_to_cpu(stats->mpdu_ok_cnt);
  30         u32 mpdu_err_byte_count = __le32_to_cpu(stats->mpdu_err_cnt);
  31
  32         rx_user_status->mpdu_ok_byte_count =
  33                 u32_get_bits(mpdu_ok_byte_count,
  34                              HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT);
  35         rx_user_status->mpdu_err_byte_count =
  36                 u32_get_bits(mpdu_err_byte_count,
  37                              HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT);
  38 }
  39
  40 static void
  41 ath12k_dp_mon_rx_populate_mu_user_info(void *rx_tlv,
  42                                        struct hal_rx_mon_ppdu_info *ppdu_info,
  43                                        struct hal_rx_user_status *rx_user_status)
  44 {
  45         rx_user_status->ast_index = ppdu_info->ast_index;
  46         rx_user_status->tid = ppdu_info->tid;
  47         rx_user_status->tcp_ack_msdu_count =
  48                 ppdu_info->tcp_ack_msdu_count;
  49         rx_user_status->tcp_msdu_count =
  50                 ppdu_info->tcp_msdu_count;
  51         rx_user_status->udp_msdu_count =
  52                 ppdu_info->udp_msdu_count;
  53         rx_user_status->other_msdu_count =
  54                 ppdu_info->other_msdu_count;
  55         rx_user_status->frame_control = ppdu_info->frame_control;
  56         rx_user_status->frame_control_info_valid =
  57                 ppdu_info->frame_control_info_valid;
  58         rx_user_status->data_sequence_control_info_valid =
  59                 ppdu_info->data_sequence_control_info_valid;
  60         rx_user_status->first_data_seq_ctrl =
  61                 ppdu_info->first_data_seq_ctrl;
  62         rx_user_status->preamble_type = ppdu_info->preamble_type;
  63         rx_user_status->ht_flags = ppdu_info->ht_flags;
  64         rx_user_status->vht_flags = ppdu_info->vht_flags;
  65         rx_user_status->he_flags = ppdu_info->he_flags;
  66         rx_user_status->rs_flags = ppdu_info->rs_flags;
  67
  68         rx_user_status->mpdu_cnt_fcs_ok =
  69                 ppdu_info->num_mpdu_fcs_ok;
  70         rx_user_status->mpdu_cnt_fcs_err =
  71                 ppdu_info->num_mpdu_fcs_err;
  72         memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],
  73                HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  74                sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
  75
  76         ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
  77 }
  78
  79 static void ath12k_dp_mon_parse_vht_sig_a(u8 *tlv_data,
  80                                           struct hal_rx_mon_ppdu_info *ppdu_info)
  81 {
  82         struct hal_rx_vht_sig_a_info *vht_sig =
  83                         (struct hal_rx_vht_sig_a_info *)tlv_data;
  84         u32 nsts, group_id, info0, info1;
  85         u8 gi_setting;
  86
  87         info0 = __le32_to_cpu(vht_sig->info0);
  88         info1 = __le32_to_cpu(vht_sig->info1);
  89
  90         ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
  91         ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS);
  92         gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING);
  93         switch (gi_setting) {
  94         case HAL_RX_VHT_SIG_A_NORMAL_GI:
  95                 ppdu_info->gi = HAL_RX_GI_0_8_US;
  96                 break;
  97         case HAL_RX_VHT_SIG_A_SHORT_GI:
  98         case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
  99                 ppdu_info->gi = HAL_RX_GI_0_4_US;
 100                 break;
 101         }
 102
 103         ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC);
 104         nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS);
 105         if (ppdu_info->is_stbc && nsts > 0)
 106                 nsts = ((nsts + 1) >> 1) - 1;
 107
 108         ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK);
 109         ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW);
 110         ppdu_info->beamformed = u32_get_bits(info1,
 111                                              HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED);
 112         group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID);
 113         if (group_id == 0 || group_id == 63)
 114                 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 115         else
 116                 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 117         ppdu_info->vht_flag_values5 = group_id;
 118         ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
 119                                             ppdu_info->nss);
 120         ppdu_info->vht_flag_values2 = ppdu_info->bw;
 121         ppdu_info->vht_flag_values4 =
 122                 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
 123 }
 124
 125 static void ath12k_dp_mon_parse_ht_sig(u8 *tlv_data,
 126                                        struct hal_rx_mon_ppdu_info *ppdu_info)
 127 {
 128         struct hal_rx_ht_sig_info *ht_sig =
 129                         (struct hal_rx_ht_sig_info *)tlv_data;
 130         u32 info0 = __le32_to_cpu(ht_sig->info0);
 131         u32 info1 = __le32_to_cpu(ht_sig->info1);
 132
 133         ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS);
 134         ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW);
 135         ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC);
 136         ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING);
 137         ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI);
 138         ppdu_info->nss = (ppdu_info->mcs >> 3);
 139         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 140 }
 141
 142 static void ath12k_dp_mon_parse_l_sig_b(u8 *tlv_data,
 143                                         struct hal_rx_mon_ppdu_info *ppdu_info)
 144 {
 145         struct hal_rx_lsig_b_info *lsigb =
 146                         (struct hal_rx_lsig_b_info *)tlv_data;
 147         u32 info0 = __le32_to_cpu(lsigb->info0);
 148         u8 rate;
 149
 150         rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE);
 151         switch (rate) {
 152         case 1:
 153                 rate = HAL_RX_LEGACY_RATE_1_MBPS;
 154                 break;
 155         case 2:
 156         case 5:
 157                 rate = HAL_RX_LEGACY_RATE_2_MBPS;
 158                 break;
 159         case 3:
 160         case 6:
 161                 rate = HAL_RX_LEGACY_RATE_5_5_MBPS;
 162                 break;
 163         case 4:
 164         case 7:
 165                 rate = HAL_RX_LEGACY_RATE_11_MBPS;
 166                 break;
 167         default:
 168                 rate = HAL_RX_LEGACY_RATE_INVALID;
 169         }
 170
 171         ppdu_info->rate = rate;
 172         ppdu_info->cck_flag = 1;
 173         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 174 }
 175
 176 static void ath12k_dp_mon_parse_l_sig_a(u8 *tlv_data,
 177                                         struct hal_rx_mon_ppdu_info *ppdu_info)
 178 {
 179         struct hal_rx_lsig_a_info *lsiga =
 180                         (struct hal_rx_lsig_a_info *)tlv_data;
 181         u32 info0 = __le32_to_cpu(lsiga->info0);
 182         u8 rate;
 183
 184         rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE);
 185         switch (rate) {
 186         case 8:
 187                 rate = HAL_RX_LEGACY_RATE_48_MBPS;
 188                 break;
 189         case 9:
 190                 rate = HAL_RX_LEGACY_RATE_24_MBPS;
 191                 break;
 192         case 10:
 193                 rate = HAL_RX_LEGACY_RATE_12_MBPS;
 194                 break;
 195         case 11:
 196                 rate = HAL_RX_LEGACY_RATE_6_MBPS;
 197                 break;
 198         case 12:
 199                 rate = HAL_RX_LEGACY_RATE_54_MBPS;
 200                 break;
 201         case 13:
 202                 rate = HAL_RX_LEGACY_RATE_36_MBPS;
 203                 break;
 204         case 14:
 205                 rate = HAL_RX_LEGACY_RATE_18_MBPS;
 206                 break;
 207         case 15:
 208                 rate = HAL_RX_LEGACY_RATE_9_MBPS;
 209                 break;
 210         default:
 211                 rate = HAL_RX_LEGACY_RATE_INVALID;
 212         }
 213
 214         ppdu_info->rate = rate;
 215         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 216 }
 217
 218 static void ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 *tlv_data,
 219                                                 struct hal_rx_mon_ppdu_info *ppdu_info)
 220 {
 221         struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
 222                         (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
 223         u32 info0, value;
 224
 225         info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
 226
 227         ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN;
 228
 229         /* HE-data2 */
 230         ppdu_info->he_data2 |= HE_TXBF_KNOWN;
 231
 232         ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS);
 233         value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
 234         ppdu_info->he_data3 |= value;
 235
 236         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM);
 237         value = value << HE_DCM_SHIFT;
 238         ppdu_info->he_data3 |= value;
 239
 240         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING);
 241         ppdu_info->ldpc = value;
 242         value = value << HE_CODING_SHIFT;
 243         ppdu_info->he_data3 |= value;
 244
 245         /* HE-data4 */
 246         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID);
 247         value = value << HE_STA_ID_SHIFT;
 248         ppdu_info->he_data4 |= value;
 249
 250         ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS);
 251         ppdu_info->beamformed = u32_get_bits(info0,
 252                                              HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF);
 253         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
 254 }
 255
 256 static void ath12k_dp_mon_parse_he_sig_b2_mu(u8 *tlv_data,
 257                                              struct hal_rx_mon_ppdu_info *ppdu_info)
 258 {
 259         struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
 260                         (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
 261         u32 info0, value;
 262
 263         info0 = __le32_to_cpu(he_sig_b2_mu->info0);
 264
 265         ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN;
 266
 267         ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS);
 268         value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
 269         ppdu_info->he_data3 |= value;
 270
 271         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING);
 272         ppdu_info->ldpc = value;
 273         value = value << HE_CODING_SHIFT;
 274         ppdu_info->he_data3 |= value;
 275
 276         value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID);
 277         value = value << HE_STA_ID_SHIFT;
 278         ppdu_info->he_data4 |= value;
 279
 280         ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS);
 281 }
 282
 283 static void ath12k_dp_mon_parse_he_sig_b1_mu(u8 *tlv_data,
 284                                              struct hal_rx_mon_ppdu_info *ppdu_info)
 285 {
 286         struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
 287                         (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
 288         u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
 289         u16 ru_tones;
 290
 291         ru_tones = u32_get_bits(info0,
 292                                 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION);
 293         ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
 294         ppdu_info->he_RU[0] = ru_tones;
 295         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 296 }
 297
 298 static void ath12k_dp_mon_parse_he_sig_mu(u8 *tlv_data,
 299                                           struct hal_rx_mon_ppdu_info *ppdu_info)
 300 {
 301         struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
 302                         (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
 303         u32 info0, info1, value;
 304         u16 he_gi = 0, he_ltf = 0;
 305
 306         info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
 307         info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
 308
 309         ppdu_info->he_mu_flags = 1;
 310
 311         ppdu_info->he_data1 = HE_MU_FORMAT_TYPE;
 312         ppdu_info->he_data1 |=
 313                         HE_BSS_COLOR_KNOWN |
 314                         HE_DL_UL_KNOWN |
 315                         HE_LDPC_EXTRA_SYMBOL_KNOWN |
 316                         HE_STBC_KNOWN |
 317                         HE_DATA_BW_RU_KNOWN |
 318                         HE_DOPPLER_KNOWN;
 319
 320         ppdu_info->he_data2 =
 321                         HE_GI_KNOWN |
 322                         HE_LTF_SYMBOLS_KNOWN |
 323                         HE_PRE_FEC_PADDING_KNOWN |
 324                         HE_PE_DISAMBIGUITY_KNOWN |
 325                         HE_TXOP_KNOWN |
 326                         HE_MIDABLE_PERIODICITY_KNOWN;
 327
 328         /* data3 */
 329         ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR);
 330         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG);
 331         value = value << HE_DL_UL_SHIFT;
 332         ppdu_info->he_data3 |= value;
 333
 334         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA);
 335         value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
 336         ppdu_info->he_data3 |= value;
 337
 338         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC);
 339         value = value << HE_STBC_SHIFT;
 340         ppdu_info->he_data3 |= value;
 341
 342         /* data4 */
 343         ppdu_info->he_data4 = u32_get_bits(info0,
 344                                            HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE);
 345         ppdu_info->he_data4 = value;
 346
 347         /* data5 */
 348         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
 349         ppdu_info->he_data5 = value;
 350         ppdu_info->bw = value;
 351
 352         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE);
 353         switch (value) {
 354         case 0:
 355                 he_gi = HE_GI_0_8;
 356                 he_ltf = HE_LTF_4_X;
 357                 break;
 358         case 1:
 359                 he_gi = HE_GI_0_8;
 360                 he_ltf = HE_LTF_2_X;
 361                 break;
 362         case 2:
 363                 he_gi = HE_GI_1_6;
 364                 he_ltf = HE_LTF_2_X;
 365                 break;
 366         case 3:
 367                 he_gi = HE_GI_3_2;
 368                 he_ltf = HE_LTF_4_X;
 369                 break;
 370         }
 371
 372         ppdu_info->gi = he_gi;
 373         value = he_gi << HE_GI_SHIFT;
 374         ppdu_info->he_data5 |= value;
 375
 376         value = he_ltf << HE_LTF_SIZE_SHIFT;
 377         ppdu_info->he_data5 |= value;
 378
 379         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB);
 380         value = (value << HE_LTF_SYM_SHIFT);
 381         ppdu_info->he_data5 |= value;
 382
 383         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR);
 384         value = value << HE_PRE_FEC_PAD_SHIFT;
 385         ppdu_info->he_data5 |= value;
 386
 387         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM);
 388         value = value << HE_PE_DISAMBIGUITY_SHIFT;
 389         ppdu_info->he_data5 |= value;
 390
 391         /*data6*/
 392         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION);
 393         value = value << HE_DOPPLER_SHIFT;
 394         ppdu_info->he_data6 |= value;
 395
 396         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION);
 397         value = value << HE_TXOP_SHIFT;
 398         ppdu_info->he_data6 |= value;
 399
 400         /* HE-MU Flags */
 401         /* HE-MU-flags1 */
 402         ppdu_info->he_flags1 =
 403                 HE_SIG_B_MCS_KNOWN |
 404                 HE_SIG_B_DCM_KNOWN |
 405                 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN |
 406                 HE_SIG_B_SYM_NUM_KNOWN |
 407                 HE_RU_0_KNOWN;
 408
 409         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB);
 410         ppdu_info->he_flags1 |= value;
 411         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB);
 412         value = value << HE_DCM_FLAG_1_SHIFT;
 413         ppdu_info->he_flags1 |= value;
 414
 415         /* HE-MU-flags2 */
 416         ppdu_info->he_flags2 = HE_BW_KNOWN;
 417
 418         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
 419         ppdu_info->he_flags2 |= value;
 420         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB);
 421         value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT;
 422         ppdu_info->he_flags2 |= value;
 423         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB);
 424         value = value - 1;
 425         value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT;
 426         ppdu_info->he_flags2 |= value;
 427
 428         ppdu_info->is_stbc = info1 &
 429                              HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC;
 430         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 431 }
 432
 433 static void ath12k_dp_mon_parse_he_sig_su(u8 *tlv_data,
 434                                           struct hal_rx_mon_ppdu_info *ppdu_info)
 435 {
 436         struct hal_rx_he_sig_a_su_info *he_sig_a =
 437                         (struct hal_rx_he_sig_a_su_info *)tlv_data;
 438         u32 info0, info1, value;
 439         u32 dcm;
 440         u8 he_dcm = 0, he_stbc = 0;
 441         u16 he_gi = 0, he_ltf = 0;
 442
 443         ppdu_info->he_flags = 1;
 444
 445         info0 = __le32_to_cpu(he_sig_a->info0);
 446         info1 = __le32_to_cpu(he_sig_a->info1);
 447
 448         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND);
 449         if (value == 0)
 450                 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE;
 451         else
 452                 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE;
 453
 454         ppdu_info->he_data1 |=
 455                         HE_BSS_COLOR_KNOWN |
 456                         HE_BEAM_CHANGE_KNOWN |
 457                         HE_DL_UL_KNOWN |
 458                         HE_MCS_KNOWN |
 459                         HE_DCM_KNOWN |
 460                         HE_CODING_KNOWN |
 461                         HE_LDPC_EXTRA_SYMBOL_KNOWN |
 462                         HE_STBC_KNOWN |
 463                         HE_DATA_BW_RU_KNOWN |
 464                         HE_DOPPLER_KNOWN;
 465
 466         ppdu_info->he_data2 |=
 467                         HE_GI_KNOWN |
 468                         HE_TXBF_KNOWN |
 469                         HE_PE_DISAMBIGUITY_KNOWN |
 470                         HE_TXOP_KNOWN |
 471                         HE_LTF_SYMBOLS_KNOWN |
 472                         HE_PRE_FEC_PADDING_KNOWN |
 473                         HE_MIDABLE_PERIODICITY_KNOWN;
 474
 475         ppdu_info->he_data3 = u32_get_bits(info0,
 476                                            HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR);
 477         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE);
 478         value = value << HE_BEAM_CHANGE_SHIFT;
 479         ppdu_info->he_data3 |= value;
 480         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG);
 481         value = value << HE_DL_UL_SHIFT;
 482         ppdu_info->he_data3 |= value;
 483
 484         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
 485         ppdu_info->mcs = value;
 486         value = value << HE_TRANSMIT_MCS_SHIFT;
 487         ppdu_info->he_data3 |= value;
 488
 489         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
 490         he_dcm = value;
 491         value = value << HE_DCM_SHIFT;
 492         ppdu_info->he_data3 |= value;
 493         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
 494         value = value << HE_CODING_SHIFT;
 495         ppdu_info->he_data3 |= value;
 496         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA);
 497         value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
 498         ppdu_info->he_data3 |= value;
 499         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
 500         he_stbc = value;
 501         value = value << HE_STBC_SHIFT;
 502         ppdu_info->he_data3 |= value;
 503
 504         /* data4 */
 505         ppdu_info->he_data4 = u32_get_bits(info0,
 506                                            HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE);
 507
 508         /* data5 */
 509         value = u32_get_bits(info0,
 510                              HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
 511         ppdu_info->he_data5 = value;
 512         ppdu_info->bw = value;
 513         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE);
 514         switch (value) {
 515         case 0:
 516                 he_gi = HE_GI_0_8;
 517                 he_ltf = HE_LTF_1_X;
 518                 break;
 519         case 1:
 520                 he_gi = HE_GI_0_8;
 521                 he_ltf = HE_LTF_2_X;
 522                 break;
 523         case 2:
 524                 he_gi = HE_GI_1_6;
 525                 he_ltf = HE_LTF_2_X;
 526                 break;
 527         case 3:
 528                 if (he_dcm && he_stbc) {
 529                         he_gi = HE_GI_0_8;
 530                         he_ltf = HE_LTF_4_X;
 531                 } else {
 532                         he_gi = HE_GI_3_2;
 533                         he_ltf = HE_LTF_4_X;
 534                 }
 535                 break;
 536         }
 537         ppdu_info->gi = he_gi;
 538         value = he_gi << HE_GI_SHIFT;
 539         ppdu_info->he_data5 |= value;
 540         value = he_ltf << HE_LTF_SIZE_SHIFT;
 541         ppdu_info->ltf_size = he_ltf;
 542         ppdu_info->he_data5 |= value;
 543
 544         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
 545         value = (value << HE_LTF_SYM_SHIFT);
 546         ppdu_info->he_data5 |= value;
 547
 548         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR);
 549         value = value << HE_PRE_FEC_PAD_SHIFT;
 550         ppdu_info->he_data5 |= value;
 551
 552         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
 553         value = value << HE_TXBF_SHIFT;
 554         ppdu_info->he_data5 |= value;
 555         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM);
 556         value = value << HE_PE_DISAMBIGUITY_SHIFT;
 557         ppdu_info->he_data5 |= value;
 558
 559         /* data6 */
 560         value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
 561         value++;
 562         ppdu_info->he_data6 = value;
 563         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND);
 564         value = value << HE_DOPPLER_SHIFT;
 565         ppdu_info->he_data6 |= value;
 566         value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION);
 567         value = value << HE_TXOP_SHIFT;
 568         ppdu_info->he_data6 |= value;
 569
 570         ppdu_info->mcs =
 571                 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
 572         ppdu_info->bw =
 573                 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
 574         ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
 575         ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
 576         ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
 577         dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
 578         ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
 579         ppdu_info->dcm = dcm;
 580         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 581 }
 582
 583 static enum hal_rx_mon_status
 584 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab,
 585                                   struct ath12k_mon_data *pmon,
 586                                   u32 tlv_tag, u8 *tlv_data, u32 userid)
 587 {
 588         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
 589         u32 info[7];
 590
 591         switch (tlv_tag) {
 592         case HAL_RX_PPDU_START: {
 593                 struct hal_rx_ppdu_start *ppdu_start =
 594                         (struct hal_rx_ppdu_start *)tlv_data;
 595
 596                 info[0] = __le32_to_cpu(ppdu_start->info0);
 597
 598                 ppdu_info->ppdu_id =
 599                         u32_get_bits(info[0], HAL_RX_PPDU_START_INFO0_PPDU_ID);
 600                 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num);
 601                 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts);
 602
 603                 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) {
 604                         ppdu_info->last_ppdu_id = ppdu_info->ppdu_id;
 605                         ppdu_info->num_users = 0;
 606                         memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0,
 607                                HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
 608                                sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
 609                 }
 610                 break;
 611         }
 612         case HAL_RX_PPDU_END_USER_STATS: {
 613                 struct hal_rx_ppdu_end_user_stats *eu_stats =
 614                         (struct hal_rx_ppdu_end_user_stats *)tlv_data;
 615
 616                 info[0] = __le32_to_cpu(eu_stats->info0);
 617                 info[1] = __le32_to_cpu(eu_stats->info1);
 618                 info[2] = __le32_to_cpu(eu_stats->info2);
 619                 info[4] = __le32_to_cpu(eu_stats->info4);
 620                 info[5] = __le32_to_cpu(eu_stats->info5);
 621                 info[6] = __le32_to_cpu(eu_stats->info6);
 622
 623                 ppdu_info->ast_index =
 624                         u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX);
 625                 ppdu_info->fc_valid =
 626                         u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID);
 627                 ppdu_info->tid =
 628                         ffs(u32_get_bits(info[6],
 629                                          HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP)
 630                                          - 1);
 631                 ppdu_info->tcp_msdu_count =
 632                         u32_get_bits(info[4],
 633                                      HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT);
 634                 ppdu_info->udp_msdu_count =
 635                         u32_get_bits(info[4],
 636                                      HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT);
 637                 ppdu_info->other_msdu_count =
 638                         u32_get_bits(info[5],
 639                                      HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT);
 640                 ppdu_info->tcp_ack_msdu_count =
 641                         u32_get_bits(info[5],
 642                                      HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT);
 643                 ppdu_info->preamble_type =
 644                         u32_get_bits(info[1],
 645                                      HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE);
 646                 ppdu_info->num_mpdu_fcs_ok =
 647                         u32_get_bits(info[1],
 648                                      HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK);
 649                 ppdu_info->num_mpdu_fcs_err =
 650                         u32_get_bits(info[0],
 651                                      HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR);
 652                 switch (ppdu_info->preamble_type) {
 653                 case HAL_RX_PREAMBLE_11N:
 654                         ppdu_info->ht_flags = 1;
 655                         break;
 656                 case HAL_RX_PREAMBLE_11AC:
 657                         ppdu_info->vht_flags = 1;
 658                         break;
 659                 case HAL_RX_PREAMBLE_11AX:
 660                         ppdu_info->he_flags = 1;
 661                         break;
 662                 default:
 663                         break;
 664                 }
 665
 666                 if (userid < HAL_MAX_UL_MU_USERS) {
 667                         struct hal_rx_user_status *rxuser_stats =
 668                                 &ppdu_info->userstats[userid];
 669                         ppdu_info->num_users += 1;
 670
 671                         ath12k_dp_mon_rx_handle_ofdma_info(tlv_data, rxuser_stats);
 672                         ath12k_dp_mon_rx_populate_mu_user_info(tlv_data, ppdu_info,
 673                                                                rxuser_stats);
 674                 }
 675                 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
 676                 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]);
 677                 break;
 678         }
 679         case HAL_RX_PPDU_END_USER_STATS_EXT: {
 680                 struct hal_rx_ppdu_end_user_stats_ext *eu_stats =
 681                         (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data;
 682                 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1);
 683                 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2);
 684                 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3);
 685                 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4);
 686                 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5);
 687                 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6);
 688                 break;
 689         }
 690         case HAL_PHYRX_HT_SIG:
 691                 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info);
 692                 break;
 693
 694         case HAL_PHYRX_L_SIG_B:
 695                 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info);
 696                 break;
 697
 698         case HAL_PHYRX_L_SIG_A:
 699                 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info);
 700                 break;
 701
 702         case HAL_PHYRX_VHT_SIG_A:
 703                 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info);
 704                 break;
 705
 706         case HAL_PHYRX_HE_SIG_A_SU:
 707                 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info);
 708                 break;
 709
 710         case HAL_PHYRX_HE_SIG_A_MU_DL:
 711                 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info);
 712                 break;
 713
 714         case HAL_PHYRX_HE_SIG_B1_MU:
 715                 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info);
 716                 break;
 717
 718         case HAL_PHYRX_HE_SIG_B2_MU:
 719                 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info);
 720                 break;
 721
 722         case HAL_PHYRX_HE_SIG_B2_OFDMA:
 723                 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info);
 724                 break;
 725
 726         case HAL_PHYRX_RSSI_LEGACY: {
 727                 struct hal_rx_phyrx_rssi_legacy_info *rssi =
 728                         (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
 729                 u32 reception_type = 0;
 730                 u32 rssi_legacy_info = __le32_to_cpu(rssi->rsvd[0]);
 731
 732                 info[0] = __le32_to_cpu(rssi->info0);
 733
 734                 /* TODO: Please note that the combined rssi will not be accurate
 735                  * in MU case. Rssi in MU needs to be retrieved from
 736                  * PHYRX_OTHER_RECEIVE_INFO TLV.
 737                  */
 738                 ppdu_info->rssi_comb =
 739                         u32_get_bits(info[0],
 740                                      HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB);
 741                 reception_type =
 742                         u32_get_bits(rssi_legacy_info,
 743                                      HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION);
 744
 745                 switch (reception_type) {
 746                 case HAL_RECEPTION_TYPE_ULOFMDA:
 747                         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
 748                         break;
 749                 case HAL_RECEPTION_TYPE_ULMIMO:
 750                         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
 751                         break;
 752                 default:
 753                         ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
 754                         break;
 755                 }
 756                 break;
 757         }
 758         case HAL_RXPCU_PPDU_END_INFO: {
 759                 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
 760                         (struct hal_rx_ppdu_end_duration *)tlv_data;
 761
 762                 info[0] = __le32_to_cpu(ppdu_rx_duration->info0);
 763                 ppdu_info->rx_duration =
 764                         u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION);
 765                 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
 766                 ppdu_info->tsft = (ppdu_info->tsft << 32) |
 767                                    __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
 768                 break;
 769         }
 770         case HAL_RX_MPDU_START: {
 771                 struct hal_rx_mpdu_start *mpdu_start =
 772                         (struct hal_rx_mpdu_start *)tlv_data;
 773                 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
 774                 u16 peer_id;
 775
 776                 info[1] = __le32_to_cpu(mpdu_start->info1);
 777                 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID);
 778                 if (peer_id)
 779                         ppdu_info->peer_id = peer_id;
 780
 781                 ppdu_info->mpdu_len += u32_get_bits(info[1],
 782                                                     HAL_RX_MPDU_START_INFO2_MPDU_LEN);
 783                 if (userid < HAL_MAX_UL_MU_USERS) {
 784                         info[0] = __le32_to_cpu(mpdu_start->info0);
 785                         ppdu_info->userid = userid;
 786                         ppdu_info->ampdu_id[userid] =
 787                                 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID);
 788                 }
 789
 790                 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
 791                 if (!mon_mpdu)
 792                         return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
 793
 794                 break;
 795         }
 796         case HAL_RX_MSDU_START:
 797                 /* TODO: add msdu start parsing logic */
 798                 break;
 799         case HAL_MON_BUF_ADDR: {
 800                 struct dp_rxdma_mon_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring;
 801                 struct dp_mon_packet_info *packet_info =
 802                         (struct dp_mon_packet_info *)tlv_data;
 803                 int buf_id = u32_get_bits(packet_info->cookie,
 804                                           DP_RXDMA_BUF_COOKIE_BUF_ID);
 805                 struct sk_buff *msdu;
 806                 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
 807                 struct ath12k_skb_rxcb *rxcb;
 808
 809                 spin_lock_bh(&buf_ring->idr_lock);
 810                 msdu = idr_remove(&buf_ring->bufs_idr, buf_id);
 811                 spin_unlock_bh(&buf_ring->idr_lock);
 812
 813                 if (unlikely(!msdu)) {
 814                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
 815                                     buf_id);
 816                         return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
 817                 }
 818
 819                 rxcb = ATH12K_SKB_RXCB(msdu);
 820                 dma_unmap_single(ab->dev, rxcb->paddr,
 821                                  msdu->len + skb_tailroom(msdu),
 822                                  DMA_FROM_DEVICE);
 823
 824                 if (mon_mpdu->tail)
 825                         mon_mpdu->tail->next = msdu;
 826                 else
 827                         mon_mpdu->tail = msdu;
 828
 829                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
 830
 831                 break;
 832         }
 833         case HAL_RX_MSDU_END: {
 834                 struct rx_msdu_end_qcn9274 *msdu_end =
 835                         (struct rx_msdu_end_qcn9274 *)tlv_data;
 836                 bool is_first_msdu_in_mpdu;
 837                 u16 msdu_end_info;
 838
 839                 msdu_end_info = __le16_to_cpu(msdu_end->info5);
 840                 is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info,
 841                                                      RX_MSDU_END_INFO5_FIRST_MSDU);
 842                 if (is_first_msdu_in_mpdu) {
 843                         pmon->mon_mpdu->head = pmon->mon_mpdu->tail;
 844                         pmon->mon_mpdu->tail = NULL;
 845                 }
 846                 break;
 847         }
 848         case HAL_RX_MPDU_END:
 849                 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list);
 850                 break;
 851         case HAL_DUMMY:
 852                 return HAL_RX_MON_STATUS_BUF_DONE;
 853         case HAL_RX_PPDU_END_STATUS_DONE:
 854         case 0:
 855                 return HAL_RX_MON_STATUS_PPDU_DONE;
 856         default:
 857                 break;
 858         }
 859
 860         return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
 861 }
 862
 863 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar, struct sk_buff *msdu)
 864 {
 865         u32 rx_pkt_offset, l2_hdr_offset;
 866
 867         rx_pkt_offset = ar->ab->hw_params->hal_desc_sz;
 868         l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab,
 869                                              (struct hal_rx_desc *)msdu->data);
 870         skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
 871 }
 872
 873 static struct sk_buff *
 874 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar,
 875                             u32 mac_id, struct sk_buff *head_msdu,
 876                             struct ieee80211_rx_status *rxs, bool *fcs_err)
 877 {
 878         struct ath12k_base *ab = ar->ab;
 879         struct sk_buff *msdu, *mpdu_buf, *prev_buf;
 880         struct hal_rx_desc *rx_desc;
 881         u8 *hdr_desc, *dest, decap_format;
 882         struct ieee80211_hdr_3addr *wh;
 883         u32 err_bitmap;
 884
 885         mpdu_buf = NULL;
 886
 887         if (!head_msdu)
 888                 goto err_merge_fail;
 889
 890         rx_desc = (struct hal_rx_desc *)head_msdu->data;
 891         err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
 892
 893         if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
 894                 *fcs_err = true;
 895
 896         decap_format = ath12k_dp_rx_h_decap_type(ab, rx_desc);
 897
 898         ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
 899
 900         if (decap_format == DP_RX_DECAP_TYPE_RAW) {
 901                 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu);
 902
 903                 prev_buf = head_msdu;
 904                 msdu = head_msdu->next;
 905
 906                 while (msdu) {
 907                         ath12k_dp_mon_rx_msdus_set_payload(ar, msdu);
 908
 909                         prev_buf = msdu;
 910                         msdu = msdu->next;
 911                 }
 912
 913                 prev_buf->next = NULL;
 914
 915                 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
 916         } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
 917                 u8 qos_pkt = 0;
 918
 919                 rx_desc = (struct hal_rx_desc *)head_msdu->data;
 920                 hdr_desc = ab->hw_params->hal_ops->rx_desc_get_msdu_payload(rx_desc);
 921
 922                 /* Base size */
 923                 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
 924
 925                 if (ieee80211_is_data_qos(wh->frame_control))
 926                         qos_pkt = 1;
 927
 928                 msdu = head_msdu;
 929
 930                 while (msdu) {
 931                         ath12k_dp_mon_rx_msdus_set_payload(ar, msdu);
 932                         if (qos_pkt) {
 933                                 dest = skb_push(msdu, sizeof(__le16));
 934                                 if (!dest)
 935                                         goto err_merge_fail;
 936                                 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
 937                         }
 938                         prev_buf = msdu;
 939                         msdu = msdu->next;
 940                 }
 941                 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
 942                 if (!dest)
 943                         goto err_merge_fail;
 944
 945                 ath12k_dbg(ab, ATH12K_DBG_DATA,
 946                            "mpdu_buf %pK mpdu_buf->len %u",
 947                            prev_buf, prev_buf->len);
 948         } else {
 949                 ath12k_dbg(ab, ATH12K_DBG_DATA,
 950                            "decap format %d is not supported!\n",
 951                            decap_format);
 952                 goto err_merge_fail;
 953         }
 954
 955         return head_msdu;
 956
 957 err_merge_fail:
 958         if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
 959                 ath12k_dbg(ab, ATH12K_DBG_DATA,
 960                            "err_merge_fail mpdu_buf %pK", mpdu_buf);
 961                 /* Free the head buffer */
 962                 dev_kfree_skb_any(mpdu_buf);
 963         }
 964         return NULL;
 965 }
 966
 967 static void
 968 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
 969                                     u8 *rtap_buf)
 970 {
 971         u32 rtap_len = 0;
 972
 973         put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
 974         rtap_len += 2;
 975
 976         put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
 977         rtap_len += 2;
 978
 979         put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
 980         rtap_len += 2;
 981
 982         put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
 983         rtap_len += 2;
 984
 985         put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
 986         rtap_len += 2;
 987
 988         put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
 989 }
 990
 991 static void
 992 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
 993                                        u8 *rtap_buf)
 994 {
 995         u32 rtap_len = 0;
 996
 997         put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
 998         rtap_len += 2;
 999
1000         put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
1001         rtap_len += 2;
1002
1003         rtap_buf[rtap_len] = rx_status->he_RU[0];
1004         rtap_len += 1;
1005
1006         rtap_buf[rtap_len] = rx_status->he_RU[1];
1007         rtap_len += 1;
1008
1009         rtap_buf[rtap_len] = rx_status->he_RU[2];
1010         rtap_len += 1;
1011
1012         rtap_buf[rtap_len] = rx_status->he_RU[3];
1013 }
1014
1015 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar,
1016                                           struct hal_rx_mon_ppdu_info *ppduinfo,
1017                                           struct sk_buff *mon_skb,
1018                                           struct ieee80211_rx_status *rxs)
1019 {
1020         struct ieee80211_supported_band *sband;
1021         u8 *ptr = NULL;
1022         u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid];
1023
1024         rxs->flag |= RX_FLAG_MACTIME_START;
1025         rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR;
1026         rxs->nss = ppduinfo->nss + 1;
1027
1028         if (ampdu_id) {
1029                 rxs->flag |= RX_FLAG_AMPDU_DETAILS;
1030                 rxs->ampdu_reference = ampdu_id;
1031         }
1032
1033         if (ppduinfo->he_mu_flags) {
1034                 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
1035                 rxs->encoding = RX_ENC_HE;
1036                 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
1037                 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr);
1038         } else if (ppduinfo->he_flags) {
1039                 rxs->flag |= RX_FLAG_RADIOTAP_HE;
1040                 rxs->encoding = RX_ENC_HE;
1041                 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
1042                 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr);
1043                 rxs->rate_idx = ppduinfo->rate;
1044         } else if (ppduinfo->vht_flags) {
1045                 rxs->encoding = RX_ENC_VHT;
1046                 rxs->rate_idx = ppduinfo->rate;
1047         } else if (ppduinfo->ht_flags) {
1048                 rxs->encoding = RX_ENC_HT;
1049                 rxs->rate_idx = ppduinfo->rate;
1050         } else {
1051                 rxs->encoding = RX_ENC_LEGACY;
1052                 sband = &ar->mac.sbands[rxs->band];
1053                 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
1054                                                           ppduinfo->cck_flag);
1055         }
1056
1057         rxs->mactime = ppduinfo->tsft;
1058 }
1059
1060 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
1061                                           struct sk_buff *msdu,
1062                                           struct ieee80211_rx_status *status)
1063 {
1064         static const struct ieee80211_radiotap_he known = {
1065                 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1066                                      IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
1067                 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
1068         };
1069         struct ieee80211_rx_status *rx_status;
1070         struct ieee80211_radiotap_he *he = NULL;
1071         struct ieee80211_sta *pubsta = NULL;
1072         struct ath12k_peer *peer;
1073         struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1074         u8 decap = DP_RX_DECAP_TYPE_RAW;
1075         bool is_mcbc = rxcb->is_mcbc;
1076         bool is_eapol_tkip = rxcb->is_eapol;
1077
1078         if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
1079             !(status->flag & RX_FLAG_SKIP_MONITOR)) {
1080                 he = skb_push(msdu, sizeof(known));
1081                 memcpy(he, &known, sizeof(known));
1082                 status->flag |= RX_FLAG_RADIOTAP_HE;
1083         }
1084
1085         if (!(status->flag & RX_FLAG_ONLY_MONITOR))
1086                 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc);
1087         spin_lock_bh(&ar->ab->base_lock);
1088         peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
1089         if (peer && peer->sta)
1090                 pubsta = peer->sta;
1091         spin_unlock_bh(&ar->ab->base_lock);
1092
1093         ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
1094                    "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
1095                    msdu,
1096                    msdu->len,
1097                    peer ? peer->addr : NULL,
1098                    rxcb->tid,
1099                    (is_mcbc) ? "mcast" : "ucast",
1100                    (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
1101                    (status->encoding == RX_ENC_HT) ? "ht" : "",
1102                    (status->encoding == RX_ENC_VHT) ? "vht" : "",
1103                    (status->encoding == RX_ENC_HE) ? "he" : "",
1104                    (status->bw == RATE_INFO_BW_40) ? "40" : "",
1105                    (status->bw == RATE_INFO_BW_80) ? "80" : "",
1106                    (status->bw == RATE_INFO_BW_160) ? "160" : "",
1107                    (status->bw == RATE_INFO_BW_320) ? "320" : "",
1108                    status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
1109                    status->rate_idx,
1110                    status->nss,
1111                    status->freq,
1112                    status->band, status->flag,
1113                    !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
1114                    !!(status->flag & RX_FLAG_MMIC_ERROR),
1115                    !!(status->flag & RX_FLAG_AMSDU_MORE));
1116
1117         ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
1118                         msdu->data, msdu->len);
1119         rx_status = IEEE80211_SKB_RXCB(msdu);
1120         *rx_status = *status;
1121
1122         /* TODO: trace rx packet */
1123
1124         /* PN for multicast packets are not validate in HW,
1125          * so skip 802.3 rx path
1126          * Also, fast_rx expects the STA to be authorized, hence
1127          * eapol packets are sent in slow path.
1128          */
1129         if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip &&
1130             !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
1131                 rx_status->flag |= RX_FLAG_8023;
1132
1133         ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
1134 }
1135
1136 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id,
1137                                     struct sk_buff *head_msdu,
1138                                     struct hal_rx_mon_ppdu_info *ppduinfo,
1139                                     struct napi_struct *napi)
1140 {
1141         struct ath12k_pdev_dp *dp = &ar->dp;
1142         struct sk_buff *mon_skb, *skb_next, *header;
1143         struct ieee80211_rx_status *rxs = &dp->rx_status;
1144         bool fcs_err = false;
1145
1146         mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id, head_msdu,
1147                                               rxs, &fcs_err);
1148         if (!mon_skb)
1149                 goto mon_deliver_fail;
1150
1151         header = mon_skb;
1152         rxs->flag = 0;
1153
1154         if (fcs_err)
1155                 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
1156
1157         do {
1158                 skb_next = mon_skb->next;
1159                 if (!skb_next)
1160                         rxs->flag &= ~RX_FLAG_AMSDU_MORE;
1161                 else
1162                         rxs->flag |= RX_FLAG_AMSDU_MORE;
1163
1164                 if (mon_skb == header) {
1165                         header = NULL;
1166                         rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
1167                 } else {
1168                         rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
1169                 }
1170                 rxs->flag |= RX_FLAG_ONLY_MONITOR;
1171                 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs);
1172                 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs);
1173                 mon_skb = skb_next;
1174         } while (mon_skb);
1175         rxs->flag = 0;
1176
1177         return 0;
1178
1179 mon_deliver_fail:
1180         mon_skb = head_msdu;
1181         while (mon_skb) {
1182                 skb_next = mon_skb->next;
1183                 dev_kfree_skb_any(mon_skb);
1184                 mon_skb = skb_next;
1185         }
1186         return -EINVAL;
1187 }
1188
1189 static enum hal_rx_mon_status
1190 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon,
1191                             struct sk_buff *skb)
1192 {
1193         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1194         struct hal_tlv_hdr *tlv;
1195         enum hal_rx_mon_status hal_status;
1196         u32 tlv_userid = 0;
1197         u16 tlv_tag, tlv_len;
1198         u8 *ptr = skb->data;
1199
1200         memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info));
1201
1202         do {
1203                 tlv = (struct hal_tlv_hdr *)ptr;
1204                 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1205                 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
1206                 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
1207                 ptr += sizeof(*tlv);
1208
1209                 /* The actual length of PPDU_END is the combined length of many PHY
1210                  * TLVs that follow. Skip the TLV header and
1211                  * rx_rxpcu_classification_overview that follows the header to get to
1212                  * next TLV.
1213                  */
1214
1215                 if (tlv_tag == HAL_RX_PPDU_END)
1216                         tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1217
1218                 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon,
1219                                                                tlv_tag, ptr, tlv_userid);
1220                 ptr += tlv_len;
1221                 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1222
1223                 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1224                         break;
1225
1226         } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1227
1228         return hal_status;
1229 }
1230
1231 enum hal_rx_mon_status
1232 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,
1233                                   struct ath12k_mon_data *pmon,
1234                                   int mac_id,
1235                                   struct sk_buff *skb,
1236                                   struct napi_struct *napi)
1237 {
1238         struct ath12k_base *ab = ar->ab;
1239         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1240         struct dp_mon_mpdu *tmp;
1241         struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
1242         struct sk_buff *head_msdu, *tail_msdu;
1243         enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1244
1245         ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
1246
1247         list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) {
1248                 list_del(&mon_mpdu->list);
1249                 head_msdu = mon_mpdu->head;
1250                 tail_msdu = mon_mpdu->tail;
1251
1252                 if (head_msdu && tail_msdu) {
1253                         ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu,
1254                                                  ppdu_info, napi);
1255                 }
1256
1257                 kfree(mon_mpdu);
1258         }
1259         return hal_status;
1260 }
1261
1262 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,
1263                                 struct dp_rxdma_mon_ring *buf_ring,
1264                                 int req_entries)
1265 {
1266         struct hal_mon_buf_ring *mon_buf;
1267         struct sk_buff *skb;
1268         struct hal_srng *srng;
1269         dma_addr_t paddr;
1270         u32 cookie;
1271         int buf_id;
1272
1273         srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id];
1274         spin_lock_bh(&srng->lock);
1275         ath12k_hal_srng_access_begin(ab, srng);
1276
1277         while (req_entries > 0) {
1278                 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE);
1279                 if (unlikely(!skb))
1280                         goto fail_alloc_skb;
1281
1282                 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) {
1283                         skb_pull(skb,
1284                                  PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
1285                                  skb->data);
1286                 }
1287
1288                 paddr = dma_map_single(ab->dev, skb->data,
1289                                        skb->len + skb_tailroom(skb),
1290                                        DMA_FROM_DEVICE);
1291
1292                 if (unlikely(dma_mapping_error(ab->dev, paddr)))
1293                         goto fail_free_skb;
1294
1295                 spin_lock_bh(&buf_ring->idr_lock);
1296                 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0,
1297                                    buf_ring->bufs_max * 3, GFP_ATOMIC);
1298                 spin_unlock_bh(&buf_ring->idr_lock);
1299
1300                 if (unlikely(buf_id < 0))
1301                         goto fail_dma_unmap;
1302
1303                 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng);
1304                 if (unlikely(!mon_buf))
1305                         goto fail_idr_remove;
1306
1307                 ATH12K_SKB_RXCB(skb)->paddr = paddr;
1308
1309                 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
1310
1311                 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr));
1312                 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr));
1313                 mon_buf->cookie = cpu_to_le64(cookie);
1314
1315                 req_entries--;
1316         }
1317
1318         ath12k_hal_srng_access_end(ab, srng);
1319         spin_unlock_bh(&srng->lock);
1320         return 0;
1321
1322 fail_idr_remove:
1323         spin_lock_bh(&buf_ring->idr_lock);
1324         idr_remove(&buf_ring->bufs_idr, buf_id);
1325         spin_unlock_bh(&buf_ring->idr_lock);
1326 fail_dma_unmap:
1327         dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
1328                          DMA_FROM_DEVICE);
1329 fail_free_skb:
1330         dev_kfree_skb_any(skb);
1331 fail_alloc_skb:
1332         ath12k_hal_srng_access_end(ab, srng);
1333         spin_unlock_bh(&srng->lock);
1334         return -ENOMEM;
1335 }
1336
1337 static struct dp_mon_tx_ppdu_info *
1338 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon,
1339                                unsigned int ppdu_id,
1340                                enum dp_mon_tx_ppdu_info_type type)
1341 {
1342         struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1343
1344         if (type == DP_MON_TX_PROT_PPDU_INFO) {
1345                 tx_ppdu_info = pmon->tx_prot_ppdu_info;
1346
1347                 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1348                         return tx_ppdu_info;
1349                 kfree(tx_ppdu_info);
1350         } else {
1351                 tx_ppdu_info = pmon->tx_data_ppdu_info;
1352
1353                 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1354                         return tx_ppdu_info;
1355                 kfree(tx_ppdu_info);
1356         }
1357
1358         /* allocate new tx_ppdu_info */
1359         tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC);
1360         if (!tx_ppdu_info)
1361                 return NULL;
1362
1363         tx_ppdu_info->is_used = 0;
1364         tx_ppdu_info->ppdu_id = ppdu_id;
1365
1366         if (type == DP_MON_TX_PROT_PPDU_INFO)
1367                 pmon->tx_prot_ppdu_info = tx_ppdu_info;
1368         else
1369                 pmon->tx_data_ppdu_info = tx_ppdu_info;
1370
1371         return tx_ppdu_info;
1372 }
1373
1374 static struct dp_mon_tx_ppdu_info *
1375 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon,
1376                                u16 tlv_tag)
1377 {
1378         switch (tlv_tag) {
1379         case HAL_TX_FES_SETUP:
1380         case HAL_TX_FLUSH:
1381         case HAL_PCU_PPDU_SETUP_INIT:
1382         case HAL_TX_PEER_ENTRY:
1383         case HAL_TX_QUEUE_EXTENSION:
1384         case HAL_TX_MPDU_START:
1385         case HAL_TX_MSDU_START:
1386         case HAL_TX_DATA:
1387         case HAL_MON_BUF_ADDR:
1388         case HAL_TX_MPDU_END:
1389         case HAL_TX_LAST_MPDU_FETCHED:
1390         case HAL_TX_LAST_MPDU_END:
1391         case HAL_COEX_TX_REQ:
1392         case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP:
1393         case HAL_SCH_CRITICAL_TLV_REFERENCE:
1394         case HAL_TX_FES_SETUP_COMPLETE:
1395         case HAL_TQM_MPDU_GLOBAL_START:
1396         case HAL_SCHEDULER_END:
1397         case HAL_TX_FES_STATUS_USER_PPDU:
1398                 break;
1399         case HAL_TX_FES_STATUS_PROT: {
1400                 if (!pmon->tx_prot_ppdu_info->is_used)
1401                         pmon->tx_prot_ppdu_info->is_used = true;
1402
1403                 return pmon->tx_prot_ppdu_info;
1404         }
1405         }
1406
1407         if (!pmon->tx_data_ppdu_info->is_used)
1408                 pmon->tx_data_ppdu_info->is_used = true;
1409
1410         return pmon->tx_data_ppdu_info;
1411 }
1412
1413 #define MAX_MONITOR_HEADER 512
1414 #define MAX_DUMMY_FRM_BODY 128
1415
1416 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void)
1417 {
1418         struct sk_buff *skb;
1419
1420         skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY);
1421         if (!skb)
1422                 return NULL;
1423
1424         skb_reserve(skb, MAX_MONITOR_HEADER);
1425
1426         if (!IS_ALIGNED((unsigned long)skb->data, 4))
1427                 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data);
1428
1429         return skb;
1430 }
1431
1432 static int
1433 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1434 {
1435         struct sk_buff *skb;
1436         struct ieee80211_cts *cts;
1437
1438         skb = ath12k_dp_mon_tx_alloc_skb();
1439         if (!skb)
1440                 return -ENOMEM;
1441
1442         cts = (struct ieee80211_cts *)skb->data;
1443         memset(cts, 0, MAX_DUMMY_FRM_BODY);
1444         cts->frame_control =
1445                 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS);
1446         cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1447         memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra));
1448
1449         skb_put(skb, sizeof(*cts));
1450         tx_ppdu_info->tx_mon_mpdu->head = skb;
1451         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1452         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1453                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1454
1455         return 0;
1456 }
1457
1458 static int
1459 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1460 {
1461         struct sk_buff *skb;
1462         struct ieee80211_rts *rts;
1463
1464         skb = ath12k_dp_mon_tx_alloc_skb();
1465         if (!skb)
1466                 return -ENOMEM;
1467
1468         rts = (struct ieee80211_rts *)skb->data;
1469         memset(rts, 0, MAX_DUMMY_FRM_BODY);
1470         rts->frame_control =
1471                 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS);
1472         rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1473         memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra));
1474         memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta));
1475
1476         skb_put(skb, sizeof(*rts));
1477         tx_ppdu_info->tx_mon_mpdu->head = skb;
1478         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1479         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1480                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1481
1482         return 0;
1483 }
1484
1485 static int
1486 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1487 {
1488         struct sk_buff *skb;
1489         struct ieee80211_qos_hdr *qhdr;
1490
1491         skb = ath12k_dp_mon_tx_alloc_skb();
1492         if (!skb)
1493                 return -ENOMEM;
1494
1495         qhdr = (struct ieee80211_qos_hdr *)skb->data;
1496         memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1497         qhdr->frame_control =
1498                 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1499         qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1500         memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1501         memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1502         memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1503
1504         skb_put(skb, sizeof(*qhdr));
1505         tx_ppdu_info->tx_mon_mpdu->head = skb;
1506         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1507         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1508                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1509
1510         return 0;
1511 }
1512
1513 static int
1514 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1515 {
1516         struct sk_buff *skb;
1517         struct dp_mon_qosframe_addr4 *qhdr;
1518
1519         skb = ath12k_dp_mon_tx_alloc_skb();
1520         if (!skb)
1521                 return -ENOMEM;
1522
1523         qhdr = (struct dp_mon_qosframe_addr4 *)skb->data;
1524         memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1525         qhdr->frame_control =
1526                 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1527         qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1528         memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1529         memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1530         memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1531         memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN);
1532
1533         skb_put(skb, sizeof(*qhdr));
1534         tx_ppdu_info->tx_mon_mpdu->head = skb;
1535         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1536         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1537                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1538
1539         return 0;
1540 }
1541
1542 static int
1543 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1544 {
1545         struct sk_buff *skb;
1546         struct dp_mon_frame_min_one *fbmhdr;
1547
1548         skb = ath12k_dp_mon_tx_alloc_skb();
1549         if (!skb)
1550                 return -ENOMEM;
1551
1552         fbmhdr = (struct dp_mon_frame_min_one *)skb->data;
1553         memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY);
1554         fbmhdr->frame_control =
1555                 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK);
1556         memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1557
1558         /* set duration zero for ack frame */
1559         fbmhdr->duration = 0;
1560
1561         skb_put(skb, sizeof(*fbmhdr));
1562         tx_ppdu_info->tx_mon_mpdu->head = skb;
1563         tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1564         list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1565                       &tx_ppdu_info->dp_tx_mon_mpdu_list);
1566
1567         return 0;
1568 }
1569
1570 static int
1571 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1572 {
1573         int ret = 0;
1574
1575         switch (tx_ppdu_info->rx_status.medium_prot_type) {
1576         case DP_MON_TX_MEDIUM_RTS_LEGACY:
1577         case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW:
1578         case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW:
1579                 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info);
1580                 break;
1581         case DP_MON_TX_MEDIUM_CTS2SELF:
1582                 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1583                 break;
1584         case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR:
1585                 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info);
1586                 break;
1587         case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR:
1588                 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info);
1589                 break;
1590         }
1591
1592         return ret;
1593 }
1594
1595 static enum dp_mon_tx_tlv_status
1596 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,
1597                                   struct ath12k_mon_data *pmon,
1598                                   u16 tlv_tag, u8 *tlv_data, u32 userid)
1599 {
1600         struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1601         enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1602         u32 info[7];
1603
1604         tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag);
1605
1606         switch (tlv_tag) {
1607         case HAL_TX_FES_SETUP: {
1608                 struct hal_tx_fes_setup *tx_fes_setup =
1609                                         (struct hal_tx_fes_setup *)tlv_data;
1610
1611                 info[0] = __le32_to_cpu(tx_fes_setup->info0);
1612                 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id);
1613                 tx_ppdu_info->num_users =
1614                         u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1615                 status = DP_MON_TX_FES_SETUP;
1616                 break;
1617         }
1618
1619         case HAL_TX_FES_STATUS_END: {
1620                 struct hal_tx_fes_status_end *tx_fes_status_end =
1621                         (struct hal_tx_fes_status_end *)tlv_data;
1622                 u32 tst_15_0, tst_31_16;
1623
1624                 info[0] = __le32_to_cpu(tx_fes_status_end->info0);
1625                 tst_15_0 =
1626                         u32_get_bits(info[0],
1627                                      HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0);
1628                 tst_31_16 =
1629                         u32_get_bits(info[0],
1630                                      HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16);
1631
1632                 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16));
1633                 status = DP_MON_TX_FES_STATUS_END;
1634                 break;
1635         }
1636
1637         case HAL_RX_RESPONSE_REQUIRED_INFO: {
1638                 struct hal_rx_resp_req_info *rx_resp_req_info =
1639                         (struct hal_rx_resp_req_info *)tlv_data;
1640                 u32 addr_32;
1641                 u16 addr_16;
1642
1643                 info[0] = __le32_to_cpu(rx_resp_req_info->info0);
1644                 info[1] = __le32_to_cpu(rx_resp_req_info->info1);
1645                 info[2] = __le32_to_cpu(rx_resp_req_info->info2);
1646                 info[3] = __le32_to_cpu(rx_resp_req_info->info3);
1647                 info[4] = __le32_to_cpu(rx_resp_req_info->info4);
1648                 info[5] = __le32_to_cpu(rx_resp_req_info->info5);
1649
1650                 tx_ppdu_info->rx_status.ppdu_id =
1651                         u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID);
1652                 tx_ppdu_info->rx_status.reception_type =
1653                         u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE);
1654                 tx_ppdu_info->rx_status.rx_duration =
1655                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION);
1656                 tx_ppdu_info->rx_status.mcs =
1657                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS);
1658                 tx_ppdu_info->rx_status.sgi =
1659                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI);
1660                 tx_ppdu_info->rx_status.is_stbc =
1661                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC);
1662                 tx_ppdu_info->rx_status.ldpc =
1663                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC);
1664                 tx_ppdu_info->rx_status.is_ampdu =
1665                         u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU);
1666                 tx_ppdu_info->rx_status.num_users =
1667                         u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER);
1668
1669                 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0);
1670                 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32);
1671                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1672
1673                 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0);
1674                 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16);
1675                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1676
1677                 if (tx_ppdu_info->rx_status.reception_type == 0)
1678                         ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1679                 status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1680                 break;
1681         }
1682
1683         case HAL_PCU_PPDU_SETUP_INIT: {
1684                 struct hal_tx_pcu_ppdu_setup_init *ppdu_setup =
1685                         (struct hal_tx_pcu_ppdu_setup_init *)tlv_data;
1686                 u32 addr_32;
1687                 u16 addr_16;
1688
1689                 info[0] = __le32_to_cpu(ppdu_setup->info0);
1690                 info[1] = __le32_to_cpu(ppdu_setup->info1);
1691                 info[2] = __le32_to_cpu(ppdu_setup->info2);
1692                 info[3] = __le32_to_cpu(ppdu_setup->info3);
1693                 info[4] = __le32_to_cpu(ppdu_setup->info4);
1694                 info[5] = __le32_to_cpu(ppdu_setup->info5);
1695                 info[6] = __le32_to_cpu(ppdu_setup->info6);
1696
1697                 /* protection frame address 1 */
1698                 addr_32 = u32_get_bits(info[1],
1699                                        HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0);
1700                 addr_16 = u32_get_bits(info[2],
1701                                        HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32);
1702                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1703
1704                 /* protection frame address 2 */
1705                 addr_16 = u32_get_bits(info[2],
1706                                        HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0);
1707                 addr_32 = u32_get_bits(info[3],
1708                                        HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16);
1709                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1710
1711                 /* protection frame address 3 */
1712                 addr_32 = u32_get_bits(info[4],
1713                                        HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0);
1714                 addr_16 = u32_get_bits(info[5],
1715                                        HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32);
1716                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3);
1717
1718                 /* protection frame address 4 */
1719                 addr_16 = u32_get_bits(info[5],
1720                                        HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0);
1721                 addr_32 = u32_get_bits(info[6],
1722                                        HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16);
1723                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4);
1724
1725                 status = u32_get_bits(info[0],
1726                                       HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE);
1727                 break;
1728         }
1729
1730         case HAL_TX_QUEUE_EXTENSION: {
1731                 struct hal_tx_queue_exten *tx_q_exten =
1732                         (struct hal_tx_queue_exten *)tlv_data;
1733
1734                 info[0] = __le32_to_cpu(tx_q_exten->info0);
1735
1736                 tx_ppdu_info->rx_status.frame_control =
1737                         u32_get_bits(info[0],
1738                                      HAL_TX_Q_EXT_INFO0_FRAME_CTRL);
1739                 tx_ppdu_info->rx_status.fc_valid = true;
1740                 break;
1741         }
1742
1743         case HAL_TX_FES_STATUS_START: {
1744                 struct hal_tx_fes_status_start *tx_fes_start =
1745                         (struct hal_tx_fes_status_start *)tlv_data;
1746
1747                 info[0] = __le32_to_cpu(tx_fes_start->info0);
1748
1749                 tx_ppdu_info->rx_status.medium_prot_type =
1750                         u32_get_bits(info[0],
1751                                      HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE);
1752                 break;
1753         }
1754
1755         case HAL_TX_FES_STATUS_PROT: {
1756                 struct hal_tx_fes_status_prot *tx_fes_status =
1757                         (struct hal_tx_fes_status_prot *)tlv_data;
1758                 u32 start_timestamp;
1759                 u32 end_timestamp;
1760
1761                 info[0] = __le32_to_cpu(tx_fes_status->info0);
1762                 info[1] = __le32_to_cpu(tx_fes_status->info1);
1763
1764                 start_timestamp =
1765                         u32_get_bits(info[0],
1766                                      HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0);
1767                 start_timestamp |=
1768                         u32_get_bits(info[0],
1769                                      HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15;
1770                 end_timestamp =
1771                         u32_get_bits(info[1],
1772                                      HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0);
1773                 end_timestamp |=
1774                         u32_get_bits(info[1],
1775                                      HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15;
1776                 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp;
1777
1778                 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info);
1779                 break;
1780         }
1781
1782         case HAL_TX_FES_STATUS_START_PPDU:
1783         case HAL_TX_FES_STATUS_START_PROT: {
1784                 struct hal_tx_fes_status_start_prot *tx_fes_stat_start =
1785                         (struct hal_tx_fes_status_start_prot *)tlv_data;
1786                 u64 ppdu_ts;
1787
1788                 info[0] = __le32_to_cpu(tx_fes_stat_start->info0);
1789
1790                 tx_ppdu_info->rx_status.ppdu_ts =
1791                         u32_get_bits(info[0],
1792                                      HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32);
1793                 ppdu_ts = (u32_get_bits(info[1],
1794                                         HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32));
1795                 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32;
1796                 break;
1797         }
1798
1799         case HAL_TX_FES_STATUS_USER_PPDU: {
1800                 struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu =
1801                         (struct hal_tx_fes_status_user_ppdu *)tlv_data;
1802
1803                 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0);
1804
1805                 tx_ppdu_info->rx_status.rx_duration =
1806                         u32_get_bits(info[0],
1807                                      HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION);
1808                 break;
1809         }
1810
1811         case HAL_MACTX_HE_SIG_A_SU:
1812                 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status);
1813                 break;
1814
1815         case HAL_MACTX_HE_SIG_A_MU_DL:
1816                 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status);
1817                 break;
1818
1819         case HAL_MACTX_HE_SIG_B1_MU:
1820                 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status);
1821                 break;
1822
1823         case HAL_MACTX_HE_SIG_B2_MU:
1824                 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status);
1825                 break;
1826
1827         case HAL_MACTX_HE_SIG_B2_OFDMA:
1828                 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status);
1829                 break;
1830
1831         case HAL_MACTX_VHT_SIG_A:
1832                 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1833                 break;
1834
1835         case HAL_MACTX_L_SIG_A:
1836                 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1837                 break;
1838
1839         case HAL_MACTX_L_SIG_B:
1840                 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status);
1841                 break;
1842
1843         case HAL_RX_FRAME_BITMAP_ACK: {
1844                 struct hal_rx_frame_bitmap_ack *fbm_ack =
1845                         (struct hal_rx_frame_bitmap_ack *)tlv_data;
1846                 u32 addr_32;
1847                 u16 addr_16;
1848
1849                 info[0] = __le32_to_cpu(fbm_ack->info0);
1850                 info[1] = __le32_to_cpu(fbm_ack->info1);
1851
1852                 addr_32 = u32_get_bits(info[0],
1853                                        HAL_RX_FBM_ACK_INFO0_ADDR1_31_0);
1854                 addr_16 = u32_get_bits(info[1],
1855                                        HAL_RX_FBM_ACK_INFO1_ADDR1_47_32);
1856                 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1857
1858                 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info);
1859                 break;
1860         }
1861
1862         case HAL_MACTX_PHY_DESC: {
1863                 struct hal_tx_phy_desc *tx_phy_desc =
1864                         (struct hal_tx_phy_desc *)tlv_data;
1865
1866                 info[0] = __le32_to_cpu(tx_phy_desc->info0);
1867                 info[1] = __le32_to_cpu(tx_phy_desc->info1);
1868                 info[2] = __le32_to_cpu(tx_phy_desc->info2);
1869                 info[3] = __le32_to_cpu(tx_phy_desc->info3);
1870
1871                 tx_ppdu_info->rx_status.beamformed =
1872                         u32_get_bits(info[0],
1873                                      HAL_TX_PHY_DESC_INFO0_BF_TYPE);
1874                 tx_ppdu_info->rx_status.preamble_type =
1875                         u32_get_bits(info[0],
1876                                      HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B);
1877                 tx_ppdu_info->rx_status.mcs =
1878                         u32_get_bits(info[1],
1879                                      HAL_TX_PHY_DESC_INFO1_MCS);
1880                 tx_ppdu_info->rx_status.ltf_size =
1881                         u32_get_bits(info[3],
1882                                      HAL_TX_PHY_DESC_INFO3_LTF_SIZE);
1883                 tx_ppdu_info->rx_status.nss =
1884                         u32_get_bits(info[2],
1885                                      HAL_TX_PHY_DESC_INFO2_NSS);
1886                 tx_ppdu_info->rx_status.chan_num =
1887                         u32_get_bits(info[3],
1888                                      HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL);
1889                 tx_ppdu_info->rx_status.bw =
1890                         u32_get_bits(info[0],
1891                                      HAL_TX_PHY_DESC_INFO0_BANDWIDTH);
1892                 break;
1893         }
1894
1895         case HAL_TX_MPDU_START: {
1896                 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
1897
1898                 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
1899                 if (!mon_mpdu)
1900                         return DP_MON_TX_STATUS_PPDU_NOT_DONE;
1901                 status = DP_MON_TX_MPDU_START;
1902                 break;
1903         }
1904
1905         case HAL_MON_BUF_ADDR: {
1906                 struct dp_rxdma_mon_ring *buf_ring = &ab->dp.tx_mon_buf_ring;
1907                 struct dp_mon_packet_info *packet_info =
1908                         (struct dp_mon_packet_info *)tlv_data;
1909                 int buf_id = u32_get_bits(packet_info->cookie,
1910                                           DP_RXDMA_BUF_COOKIE_BUF_ID);
1911                 struct sk_buff *msdu;
1912                 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
1913                 struct ath12k_skb_rxcb *rxcb;
1914
1915                 spin_lock_bh(&buf_ring->idr_lock);
1916                 msdu = idr_remove(&buf_ring->bufs_idr, buf_id);
1917                 spin_unlock_bh(&buf_ring->idr_lock);
1918
1919                 if (unlikely(!msdu)) {
1920                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
1921                                     buf_id);
1922                         return DP_MON_TX_STATUS_PPDU_NOT_DONE;
1923                 }
1924
1925                 rxcb = ATH12K_SKB_RXCB(msdu);
1926                 dma_unmap_single(ab->dev, rxcb->paddr,
1927                                  msdu->len + skb_tailroom(msdu),
1928                                  DMA_FROM_DEVICE);
1929
1930                 if (!mon_mpdu->head)
1931                         mon_mpdu->head = msdu;
1932                 else if (mon_mpdu->tail)
1933                         mon_mpdu->tail->next = msdu;
1934
1935                 mon_mpdu->tail = msdu;
1936
1937                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
1938                 status = DP_MON_TX_BUFFER_ADDR;
1939                 break;
1940         }
1941
1942         case HAL_TX_MPDU_END:
1943                 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1944                               &tx_ppdu_info->dp_tx_mon_mpdu_list);
1945                 break;
1946         }
1947
1948         return status;
1949 }
1950
1951 enum dp_mon_tx_tlv_status
1952 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,
1953                                      struct hal_tlv_hdr *tx_tlv,
1954                                      u8 *num_users)
1955 {
1956         u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1957         u32 info0;
1958
1959         switch (tlv_tag) {
1960         case HAL_TX_FES_SETUP: {
1961                 struct hal_tx_fes_setup *tx_fes_setup =
1962                                 (struct hal_tx_fes_setup *)tx_tlv;
1963
1964                 info0 = __le32_to_cpu(tx_fes_setup->info0);
1965
1966                 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1967                 tlv_status = DP_MON_TX_FES_SETUP;
1968                 break;
1969         }
1970
1971         case HAL_RX_RESPONSE_REQUIRED_INFO: {
1972                 /* TODO: need to update *num_users */
1973                 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1974                 break;
1975         }
1976         }
1977
1978         return tlv_status;
1979 }
1980
1981 static void
1982 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id,
1983                                    struct napi_struct *napi,
1984                                    struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1985 {
1986         struct dp_mon_mpdu *tmp, *mon_mpdu;
1987         struct sk_buff *head_msdu;
1988
1989         list_for_each_entry_safe(mon_mpdu, tmp,
1990                                  &tx_ppdu_info->dp_tx_mon_mpdu_list, list) {
1991                 list_del(&mon_mpdu->list);
1992                 head_msdu = mon_mpdu->head;
1993
1994                 if (head_msdu)
1995                         ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu,
1996                                                  &tx_ppdu_info->rx_status, napi);
1997
1998                 kfree(mon_mpdu);
1999         }
2000 }
2001
2002 enum hal_rx_mon_status
2003 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar,
2004                                   struct ath12k_mon_data *pmon,
2005                                   int mac_id,
2006                                   struct sk_buff *skb,
2007                                   struct napi_struct *napi,
2008                                   u32 ppdu_id)
2009 {
2010         struct ath12k_base *ab = ar->ab;
2011         struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info;
2012         struct hal_tlv_hdr *tlv;
2013         u8 *ptr = skb->data;
2014         u16 tlv_tag;
2015         u16 tlv_len;
2016         u32 tlv_userid = 0;
2017         u8 num_user;
2018         u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2019
2020         tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2021                                                            DP_MON_TX_PROT_PPDU_INFO);
2022         if (!tx_prot_ppdu_info)
2023                 return -ENOMEM;
2024
2025         tlv = (struct hal_tlv_hdr *)ptr;
2026         tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2027
2028         tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user);
2029         if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user)
2030                 return -EINVAL;
2031
2032         tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2033                                                            DP_MON_TX_DATA_PPDU_INFO);
2034         if (!tx_data_ppdu_info)
2035                 return -ENOMEM;
2036
2037         do {
2038                 tlv = (struct hal_tlv_hdr *)ptr;
2039                 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2040                 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
2041                 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
2042
2043                 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon,
2044                                                                tlv_tag, ptr,
2045                                                                tlv_userid);
2046                 ptr += tlv_len;
2047                 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
2048                 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE)
2049                         break;
2050         } while (tlv_status != DP_MON_TX_FES_STATUS_END);
2051
2052         ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info);
2053         ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info);
2054
2055         return tlv_status;
2056 }
2057
2058 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget,
2059                                enum dp_monitor_mode monitor_mode,
2060                                struct napi_struct *napi)
2061 {
2062         struct hal_mon_dest_desc *mon_dst_desc;
2063         struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2064         struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2065         struct ath12k_base *ab = ar->ab;
2066         struct ath12k_dp *dp = &ab->dp;
2067         struct sk_buff *skb;
2068         struct ath12k_skb_rxcb *rxcb;
2069         struct dp_srng *mon_dst_ring;
2070         struct hal_srng *srng;
2071         struct dp_rxdma_mon_ring *buf_ring;
2072         u64 cookie;
2073         u32 ppdu_id;
2074         int num_buffs_reaped = 0, srng_id, buf_id;
2075         u8 dest_idx = 0, i;
2076         bool end_of_ppdu;
2077         struct hal_rx_mon_ppdu_info *ppdu_info;
2078         struct ath12k_peer *peer = NULL;
2079
2080         ppdu_info = &pmon->mon_ppdu_info;
2081         memset(ppdu_info, 0, sizeof(*ppdu_info));
2082         ppdu_info->peer_id = HAL_INVALID_PEERID;
2083
2084         srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2085
2086         if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) {
2087                 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2088                 buf_ring = &dp->rxdma_mon_buf_ring;
2089         } else {
2090                 mon_dst_ring = &pdev_dp->tx_mon_dst_ring[srng_id];
2091                 buf_ring = &dp->tx_mon_buf_ring;
2092         }
2093
2094         srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2095
2096         spin_lock_bh(&srng->lock);
2097         ath12k_hal_srng_access_begin(ab, srng);
2098
2099         while (likely(*budget)) {
2100                 *budget -= 1;
2101                 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2102                 if (unlikely(!mon_dst_desc))
2103                         break;
2104
2105                 cookie = le32_to_cpu(mon_dst_desc->cookie);
2106                 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2107
2108                 spin_lock_bh(&buf_ring->idr_lock);
2109                 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2110                 spin_unlock_bh(&buf_ring->idr_lock);
2111
2112                 if (unlikely(!skb)) {
2113                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2114                                     buf_id);
2115                         goto move_next;
2116                 }
2117
2118                 rxcb = ATH12K_SKB_RXCB(skb);
2119                 dma_unmap_single(ab->dev, rxcb->paddr,
2120                                  skb->len + skb_tailroom(skb),
2121                                  DMA_FROM_DEVICE);
2122
2123                 pmon->dest_skb_q[dest_idx] = skb;
2124                 dest_idx++;
2125                 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id);
2126                 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2127                                             HAL_MON_DEST_INFO0_END_OF_PPDU);
2128                 if (!end_of_ppdu)
2129                         continue;
2130
2131                 for (i = 0; i < dest_idx; i++) {
2132                         skb = pmon->dest_skb_q[i];
2133
2134                         if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE)
2135                                 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id,
2136                                                                   skb, napi);
2137                         else
2138                                 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id,
2139                                                                   skb, napi, ppdu_id);
2140
2141                         peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2142
2143                         if (!peer || !peer->sta) {
2144                                 ath12k_dbg(ab, ATH12K_DBG_DATA,
2145                                            "failed to find the peer with peer_id %d\n",
2146                                            ppdu_info->peer_id);
2147                                 dev_kfree_skb_any(skb);
2148                                 continue;
2149                         }
2150
2151                         dev_kfree_skb_any(skb);
2152                         pmon->dest_skb_q[i] = NULL;
2153                 }
2154
2155                 dest_idx = 0;
2156 move_next:
2157                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2158                 ath12k_hal_srng_src_get_next_entry(ab, srng);
2159                 num_buffs_reaped++;
2160         }
2161
2162         ath12k_hal_srng_access_end(ab, srng);
2163         spin_unlock_bh(&srng->lock);
2164
2165         return num_buffs_reaped;
2166 }
2167
2168 static void
2169 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats,
2170                                               struct hal_rx_mon_ppdu_info *ppdu_info,
2171                                               struct hal_rx_user_status *user_stats,
2172                                               u32 num_msdu)
2173 {
2174         u32 rate_idx = 0;
2175         u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs;
2176         u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1;
2177         u32 bw_idx = ppdu_info->bw;
2178         u32 gi_idx = ppdu_info->gi;
2179
2180         if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) ||
2181             (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) {
2182                 return;
2183         }
2184
2185         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N ||
2186             ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) {
2187                 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx;
2188                 rate_idx += bw_idx * 2 + gi_idx;
2189         } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) {
2190                 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi);
2191                 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx;
2192                 rate_idx += bw_idx * 3 + gi_idx;
2193         } else {
2194                 return;
2195         }
2196
2197         rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu;
2198         if (user_stats)
2199                 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count;
2200         else
2201                 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len;
2202 }
2203
2204 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar,
2205                                                   struct ath12k_sta *arsta,
2206                                                   struct hal_rx_mon_ppdu_info *ppdu_info)
2207 {
2208         struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats;
2209         u32 num_msdu;
2210
2211         if (!rx_stats)
2212                 return;
2213
2214         arsta->rssi_comb = ppdu_info->rssi_comb;
2215
2216         num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2217                    ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2218
2219         rx_stats->num_msdu += num_msdu;
2220         rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2221                                     ppdu_info->tcp_ack_msdu_count;
2222         rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2223         rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2224
2225         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2226             ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2227                 ppdu_info->nss = 1;
2228                 ppdu_info->mcs = HAL_RX_MAX_MCS;
2229                 ppdu_info->tid = IEEE80211_NUM_TIDS;
2230         }
2231
2232         if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2233                 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2234
2235         if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2236                 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2237
2238         if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2239                 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2240
2241         if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2242                 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2243
2244         if (ppdu_info->is_stbc)
2245                 rx_stats->stbc_count += num_msdu;
2246
2247         if (ppdu_info->beamformed)
2248                 rx_stats->beamformed_count += num_msdu;
2249
2250         if (ppdu_info->num_mpdu_fcs_ok > 1)
2251                 rx_stats->ampdu_msdu_count += num_msdu;
2252         else
2253                 rx_stats->non_ampdu_msdu_count += num_msdu;
2254
2255         rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2256         rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2257         rx_stats->dcm_count += ppdu_info->dcm;
2258
2259         rx_stats->rx_duration += ppdu_info->rx_duration;
2260         arsta->rx_duration = rx_stats->rx_duration;
2261
2262         if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) {
2263                 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu;
2264                 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len;
2265         }
2266
2267         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N &&
2268             ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) {
2269                 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu;
2270                 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2271                 /* To fit into rate table for HT packets */
2272                 ppdu_info->mcs = ppdu_info->mcs % 8;
2273         }
2274
2275         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC &&
2276             ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) {
2277                 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu;
2278                 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2279         }
2280
2281         if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX &&
2282             ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) {
2283                 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu;
2284                 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2285         }
2286
2287         if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2288              ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) &&
2289              ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) {
2290                 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu;
2291                 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len;
2292         }
2293
2294         if (ppdu_info->gi < HAL_RX_GI_MAX) {
2295                 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2296                 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len;
2297         }
2298
2299         if (ppdu_info->bw < HAL_RX_BW_MAX) {
2300                 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2301                 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len;
2302         }
2303
2304         ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2305                                                       NULL, num_msdu);
2306 }
2307
2308 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info)
2309 {
2310         struct hal_rx_user_status *rx_user_status;
2311         u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size;
2312
2313         if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
2314               ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2315               ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
2316                 return;
2317
2318         num_users = ppdu_info->num_users;
2319         if (num_users > HAL_MAX_UL_MU_USERS)
2320                 num_users = HAL_MAX_UL_MU_USERS;
2321
2322         for (i = 0; i < num_users; i++) {
2323                 rx_user_status = &ppdu_info->userstats[i];
2324                 mu_ul_user_v0_word0 =
2325                         rx_user_status->ul_ofdma_user_v0_word0;
2326                 mu_ul_user_v0_word1 =
2327                         rx_user_status->ul_ofdma_user_v0_word1;
2328
2329                 if (u32_get_bits(mu_ul_user_v0_word0,
2330                                  HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) &&
2331                     !u32_get_bits(mu_ul_user_v0_word0,
2332                                   HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) {
2333                         rx_user_status->mcs =
2334                                 u32_get_bits(mu_ul_user_v0_word1,
2335                                              HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS);
2336                         rx_user_status->nss =
2337                                 u32_get_bits(mu_ul_user_v0_word1,
2338                                              HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1;
2339
2340                         rx_user_status->ofdma_info_valid = 1;
2341                         rx_user_status->ul_ofdma_ru_start_index =
2342                                 u32_get_bits(mu_ul_user_v0_word1,
2343                                              HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START);
2344
2345                         ru_size = u32_get_bits(mu_ul_user_v0_word1,
2346                                                HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE);
2347                         rx_user_status->ul_ofdma_ru_width = ru_size;
2348                         rx_user_status->ul_ofdma_ru_size = ru_size;
2349                 }
2350                 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1,
2351                                                     HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC);
2352         }
2353         ppdu_info->ldpc = 1;
2354 }
2355
2356 static void
2357 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar,
2358                                    struct hal_rx_mon_ppdu_info *ppdu_info,
2359                                    u32 uid)
2360 {
2361         struct ath12k_sta *arsta = NULL;
2362         struct ath12k_rx_peer_stats *rx_stats = NULL;
2363         struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid];
2364         struct ath12k_peer *peer;
2365         u32 num_msdu;
2366
2367         if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF)
2368                 return;
2369
2370         peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index);
2371
2372         if (!peer) {
2373                 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n",
2374                             user_stats->ast_index);
2375                 return;
2376         }
2377
2378         arsta = ath12k_sta_to_arsta(peer->sta);
2379         rx_stats = arsta->rx_stats;
2380
2381         if (!rx_stats)
2382                 return;
2383
2384         arsta->rssi_comb = ppdu_info->rssi_comb;
2385
2386         num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count +
2387                    user_stats->udp_msdu_count + user_stats->other_msdu_count;
2388
2389         rx_stats->num_msdu += num_msdu;
2390         rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count +
2391                                     user_stats->tcp_ack_msdu_count;
2392         rx_stats->udp_msdu_count += user_stats->udp_msdu_count;
2393         rx_stats->other_msdu_count += user_stats->other_msdu_count;
2394
2395         if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2396                 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2397
2398         if (user_stats->tid <= IEEE80211_NUM_TIDS)
2399                 rx_stats->tid_count[user_stats->tid] += num_msdu;
2400
2401         if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX)
2402                 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu;
2403
2404         if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2405                 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2406
2407         if (ppdu_info->is_stbc)
2408                 rx_stats->stbc_count += num_msdu;
2409
2410         if (ppdu_info->beamformed)
2411                 rx_stats->beamformed_count += num_msdu;
2412
2413         if (user_stats->mpdu_cnt_fcs_ok > 1)
2414                 rx_stats->ampdu_msdu_count += num_msdu;
2415         else
2416                 rx_stats->non_ampdu_msdu_count += num_msdu;
2417
2418         rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok;
2419         rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err;
2420         rx_stats->dcm_count += ppdu_info->dcm;
2421         if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2422             ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)
2423                 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu;
2424
2425         rx_stats->rx_duration += ppdu_info->rx_duration;
2426         arsta->rx_duration = rx_stats->rx_duration;
2427
2428         if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) {
2429                 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu;
2430                 rx_stats->byte_stats.nss_count[user_stats->nss - 1] +=
2431                                                 user_stats->mpdu_ok_byte_count;
2432         }
2433
2434         if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX &&
2435             user_stats->mcs <= HAL_RX_MAX_MCS_HE) {
2436                 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu;
2437                 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] +=
2438                                                 user_stats->mpdu_ok_byte_count;
2439         }
2440
2441         if (ppdu_info->gi < HAL_RX_GI_MAX) {
2442                 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2443                 rx_stats->byte_stats.gi_count[ppdu_info->gi] +=
2444                                                 user_stats->mpdu_ok_byte_count;
2445         }
2446
2447         if (ppdu_info->bw < HAL_RX_BW_MAX) {
2448                 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2449                 rx_stats->byte_stats.bw_count[ppdu_info->bw] +=
2450                                                 user_stats->mpdu_ok_byte_count;
2451         }
2452
2453         ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2454                                                       user_stats, num_msdu);
2455 }
2456
2457 static void
2458 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar,
2459                                       struct hal_rx_mon_ppdu_info *ppdu_info)
2460 {
2461         u32 num_users, i;
2462
2463         num_users = ppdu_info->num_users;
2464         if (num_users > HAL_MAX_UL_MU_USERS)
2465                 num_users = HAL_MAX_UL_MU_USERS;
2466
2467         for (i = 0; i < num_users; i++)
2468                 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i);
2469 }
2470
2471 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id,
2472                                    struct napi_struct *napi, int *budget)
2473 {
2474         struct ath12k_base *ab = ar->ab;
2475         struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2476         struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2477         struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
2478         struct ath12k_dp *dp = &ab->dp;
2479         struct hal_mon_dest_desc *mon_dst_desc;
2480         struct sk_buff *skb;
2481         struct ath12k_skb_rxcb *rxcb;
2482         struct dp_srng *mon_dst_ring;
2483         struct hal_srng *srng;
2484         struct dp_rxdma_mon_ring *buf_ring;
2485         struct ath12k_sta *arsta = NULL;
2486         struct ath12k_peer *peer;
2487         u64 cookie;
2488         int num_buffs_reaped = 0, srng_id, buf_id;
2489         u8 dest_idx = 0, i;
2490         bool end_of_ppdu;
2491         u32 hal_status;
2492
2493         srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2494         mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2495         buf_ring = &dp->rxdma_mon_buf_ring;
2496
2497         srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2498         spin_lock_bh(&srng->lock);
2499         ath12k_hal_srng_access_begin(ab, srng);
2500
2501         while (likely(*budget)) {
2502                 *budget -= 1;
2503                 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2504                 if (unlikely(!mon_dst_desc))
2505                         break;
2506                 cookie = le32_to_cpu(mon_dst_desc->cookie);
2507                 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2508
2509                 spin_lock_bh(&buf_ring->idr_lock);
2510                 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2511                 spin_unlock_bh(&buf_ring->idr_lock);
2512
2513                 if (unlikely(!skb)) {
2514                         ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2515                                     buf_id);
2516                         goto move_next;
2517                 }
2518
2519                 rxcb = ATH12K_SKB_RXCB(skb);
2520                 dma_unmap_single(ab->dev, rxcb->paddr,
2521                                  skb->len + skb_tailroom(skb),
2522                                  DMA_FROM_DEVICE);
2523                 pmon->dest_skb_q[dest_idx] = skb;
2524                 dest_idx++;
2525                 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2526                                             HAL_MON_DEST_INFO0_END_OF_PPDU);
2527                 if (!end_of_ppdu)
2528                         continue;
2529
2530                 for (i = 0; i < dest_idx; i++) {
2531                         skb = pmon->dest_skb_q[i];
2532                         hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
2533
2534                         if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
2535                             hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2536                                 dev_kfree_skb_any(skb);
2537                                 continue;
2538                         }
2539
2540                         rcu_read_lock();
2541                         spin_lock_bh(&ab->base_lock);
2542                         peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2543                         if (!peer || !peer->sta) {
2544                                 ath12k_dbg(ab, ATH12K_DBG_DATA,
2545                                            "failed to find the peer with peer_id %d\n",
2546                                            ppdu_info->peer_id);
2547                                 spin_unlock_bh(&ab->base_lock);
2548                                 rcu_read_unlock();
2549                                 dev_kfree_skb_any(skb);
2550                                 continue;
2551                         }
2552
2553                         if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) {
2554                                 arsta = ath12k_sta_to_arsta(peer->sta);
2555                                 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta,
2556                                                                       ppdu_info);
2557                         } else if ((ppdu_info->fc_valid) &&
2558                                    (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) {
2559                                 ath12k_dp_mon_rx_process_ulofdma(ppdu_info);
2560                                 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info);
2561                         }
2562
2563                         spin_unlock_bh(&ab->base_lock);
2564                         rcu_read_unlock();
2565                         dev_kfree_skb_any(skb);
2566                         memset(ppdu_info, 0, sizeof(*ppdu_info));
2567                         ppdu_info->peer_id = HAL_INVALID_PEERID;
2568                 }
2569
2570                 dest_idx = 0;
2571 move_next:
2572                 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2573                 ath12k_hal_srng_src_get_next_entry(ab, srng);
2574                 num_buffs_reaped++;
2575         }
2576
2577         ath12k_hal_srng_access_end(ab, srng);
2578         spin_unlock_bh(&srng->lock);
2579         return num_buffs_reaped;
2580 }
2581
2582 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id,
2583                                struct napi_struct *napi, int budget,
2584                                enum dp_monitor_mode monitor_mode)
2585 {
2586         struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id);
2587         int num_buffs_reaped = 0;
2588
2589         if (!ar->monitor_started)
2590                 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget);
2591         else
2592                 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget,
2593                                                               monitor_mode, napi);
2594
2595         return num_buffs_reaped;
2596 }