1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
11 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
28 "host2reo-re-injection",
30 "host2rxdma-monitor-ring3",
31 "host2rxdma-monitor-ring2",
32 "host2rxdma-monitor-ring1",
34 "wbm2host-rx-release",
36 "reo2host-destination-ring4",
37 "reo2host-destination-ring3",
38 "reo2host-destination-ring2",
39 "reo2host-destination-ring1",
40 "rxdma2host-monitor-destination-mac3",
41 "rxdma2host-monitor-destination-mac2",
42 "rxdma2host-monitor-destination-mac1",
43 "ppdu-end-interrupts-mac3",
44 "ppdu-end-interrupts-mac2",
45 "ppdu-end-interrupts-mac1",
46 "rxdma2host-monitor-status-ring-mac3",
47 "rxdma2host-monitor-status-ring-mac2",
48 "rxdma2host-monitor-status-ring-mac1",
49 "host2rxdma-host-buf-ring-mac3",
50 "host2rxdma-host-buf-ring-mac2",
51 "host2rxdma-host-buf-ring-mac1",
52 "rxdma2host-destination-ring-mac3",
53 "rxdma2host-destination-ring-mac2",
54 "rxdma2host-destination-ring-mac1",
55 "host2tcl-input-ring4",
56 "host2tcl-input-ring3",
57 "host2tcl-input-ring2",
58 "host2tcl-input-ring1",
59 "wbm2host-tx-completions-ring3",
60 "wbm2host-tx-completions-ring2",
61 "wbm2host-tx-completions-ring1",
62 "tcl2host-status-ring",
65 static const struct ath11k_msi_config ath11k_msi_config[] = {
69 .users = (struct ath11k_msi_user[]) {
70 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
71 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
72 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
73 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
75 .hw_rev = ATH11K_HW_QCA6390_HW20,
80 .users = (struct ath11k_msi_user[]) {
81 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
82 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
83 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
85 .hw_rev = ATH11K_HW_QCN9074_HW10,
90 .users = (struct ath11k_msi_user[]) {
91 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
92 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
93 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
94 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
96 .hw_rev = ATH11K_HW_WCN6855_HW20,
101 .users = (struct ath11k_msi_user[]) {
102 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
103 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
104 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
105 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
107 .hw_rev = ATH11K_HW_WCN6855_HW21,
112 .users = (struct ath11k_msi_user[]) {
113 { .name = "CE", .num_vectors = 10, .base_vector = 0 },
114 { .name = "DP", .num_vectors = 18, .base_vector = 10 },
116 .hw_rev = ATH11K_HW_WCN6750_HW10,
120 int ath11k_pcic_init_msi_config(struct ath11k_base *ab)
122 const struct ath11k_msi_config *msi_config;
125 for (i = 0; i < ARRAY_SIZE(ath11k_msi_config); i++) {
126 msi_config = &ath11k_msi_config[i];
128 if (msi_config->hw_rev == ab->hw_rev)
132 if (i == ARRAY_SIZE(ath11k_msi_config)) {
133 ath11k_err(ab, "failed to fetch msi config, unsupported hw version: 0x%x\n",
138 ab->pci.msi.config = msi_config;
141 EXPORT_SYMBOL(ath11k_pcic_init_msi_config);
143 static void __ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
145 if (offset < ATH11K_PCI_WINDOW_START)
146 iowrite32(value, ab->mem + offset);
148 ab->pci.ops->window_write32(ab, offset, value);
151 void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
154 bool wakeup_required;
156 /* for offset beyond BAR + 4K - 32, may
157 * need to wakeup the device to access.
159 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
160 offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF;
161 if (wakeup_required && ab->pci.ops->wakeup)
162 ret = ab->pci.ops->wakeup(ab);
164 __ath11k_pcic_write32(ab, offset, value);
166 if (wakeup_required && !ret && ab->pci.ops->release)
167 ab->pci.ops->release(ab);
169 EXPORT_SYMBOL(ath11k_pcic_write32);
171 static u32 __ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
175 if (offset < ATH11K_PCI_WINDOW_START)
176 val = ioread32(ab->mem + offset);
178 val = ab->pci.ops->window_read32(ab, offset);
183 u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
187 bool wakeup_required;
189 /* for offset beyond BAR + 4K - 32, may
190 * need to wakeup the device to access.
192 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
193 offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF;
194 if (wakeup_required && ab->pci.ops->wakeup)
195 ret = ab->pci.ops->wakeup(ab);
197 val = __ath11k_pcic_read32(ab, offset);
199 if (wakeup_required && !ret && ab->pci.ops->release)
200 ab->pci.ops->release(ab);
204 EXPORT_SYMBOL(ath11k_pcic_read32);
206 int ath11k_pcic_read(struct ath11k_base *ab, void *buf, u32 start, u32 end)
209 bool wakeup_required;
213 /* for offset beyond BAR + 4K - 32, may
214 * need to wakeup the device to access.
216 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
217 end >= ATH11K_PCI_ACCESS_ALWAYS_OFF;
218 if (wakeup_required && ab->pci.ops->wakeup) {
219 ret = ab->pci.ops->wakeup(ab);
222 "wakeup failed, data may be invalid: %d",
224 /* Even though wakeup() failed, continue processing rather
225 * than returning because some parts of the data may still
226 * be valid and useful in some cases, e.g. could give us
227 * some clues on firmware crash.
228 * Mislead due to invalid data could be avoided because we
229 * are aware of the wakeup failure.
234 for (i = start; i < end + 1; i += 4)
235 *data++ = __ath11k_pcic_read32(ab, i);
237 if (wakeup_required && ab->pci.ops->release)
238 ab->pci.ops->release(ab);
242 EXPORT_SYMBOL(ath11k_pcic_read);
244 void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
247 *msi_addr_lo = ab->pci.msi.addr_lo;
248 *msi_addr_hi = ab->pci.msi.addr_hi;
250 EXPORT_SYMBOL(ath11k_pcic_get_msi_address);
252 int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
253 int *num_vectors, u32 *user_base_data,
256 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
259 for (idx = 0; idx < msi_config->total_users; idx++) {
260 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
261 *num_vectors = msi_config->users[idx].num_vectors;
262 *base_vector = msi_config->users[idx].base_vector;
263 *user_base_data = *base_vector + ab->pci.msi.ep_base_data;
265 ath11k_dbg(ab, ATH11K_DBG_PCI,
266 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
267 user_name, *num_vectors, *user_base_data,
274 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
278 EXPORT_SYMBOL(ath11k_pcic_get_user_msi_assignment);
280 void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
284 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
285 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
293 *msi_idx = msi_data_idx;
295 EXPORT_SYMBOL(ath11k_pcic_get_ce_msi_idx);
297 static void ath11k_pcic_free_ext_irq(struct ath11k_base *ab)
301 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
302 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
304 for (j = 0; j < irq_grp->num_irq; j++)
305 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
307 netif_napi_del(&irq_grp->napi);
311 void ath11k_pcic_free_irq(struct ath11k_base *ab)
315 for (i = 0; i < ab->hw_params.ce_count; i++) {
316 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
318 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
319 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
322 ath11k_pcic_free_ext_irq(ab);
324 EXPORT_SYMBOL(ath11k_pcic_free_irq);
326 static void ath11k_pcic_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
330 /* In case of one MSI vector, we handle irq enable/disable in a
331 * uniform way since we only have one irq
333 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
336 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
337 enable_irq(ab->irq_num[irq_idx]);
340 static void ath11k_pcic_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
344 /* In case of one MSI vector, we handle irq enable/disable in a
345 * uniform way since we only have one irq
347 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
350 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
351 disable_irq_nosync(ab->irq_num[irq_idx]);
354 static void ath11k_pcic_ce_irqs_disable(struct ath11k_base *ab)
358 clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
360 for (i = 0; i < ab->hw_params.ce_count; i++) {
361 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
363 ath11k_pcic_ce_irq_disable(ab, i);
367 static void ath11k_pcic_sync_ce_irqs(struct ath11k_base *ab)
372 for (i = 0; i < ab->hw_params.ce_count; i++) {
373 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
376 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
377 synchronize_irq(ab->irq_num[irq_idx]);
381 static void ath11k_pcic_ce_tasklet(struct tasklet_struct *t)
383 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
384 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
386 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
388 enable_irq(ce_pipe->ab->irq_num[irq_idx]);
391 static irqreturn_t ath11k_pcic_ce_interrupt_handler(int irq, void *arg)
393 struct ath11k_ce_pipe *ce_pipe = arg;
394 struct ath11k_base *ab = ce_pipe->ab;
395 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
397 if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
400 /* last interrupt received for this CE */
401 ce_pipe->timestamp = jiffies;
403 disable_irq_nosync(ab->irq_num[irq_idx]);
405 tasklet_schedule(&ce_pipe->intr_tq);
410 static void ath11k_pcic_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
412 struct ath11k_base *ab = irq_grp->ab;
415 /* In case of one MSI vector, we handle irq enable/disable
416 * in a uniform way since we only have one irq
418 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
421 for (i = 0; i < irq_grp->num_irq; i++)
422 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
425 static void __ath11k_pcic_ext_irq_disable(struct ath11k_base *sc)
429 clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &sc->dev_flags);
431 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
432 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
434 ath11k_pcic_ext_grp_disable(irq_grp);
436 if (irq_grp->napi_enabled) {
437 napi_synchronize(&irq_grp->napi);
438 napi_disable(&irq_grp->napi);
439 irq_grp->napi_enabled = false;
444 static void ath11k_pcic_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
446 struct ath11k_base *ab = irq_grp->ab;
449 /* In case of one MSI vector, we handle irq enable/disable in a
450 * uniform way since we only have one irq
452 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
455 for (i = 0; i < irq_grp->num_irq; i++)
456 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
459 void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab)
463 set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
465 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
466 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
468 if (!irq_grp->napi_enabled) {
469 dev_set_threaded(&irq_grp->napi_ndev, true);
470 napi_enable(&irq_grp->napi);
471 irq_grp->napi_enabled = true;
473 ath11k_pcic_ext_grp_enable(irq_grp);
476 EXPORT_SYMBOL(ath11k_pcic_ext_irq_enable);
478 static void ath11k_pcic_sync_ext_irqs(struct ath11k_base *ab)
482 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
483 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
485 for (j = 0; j < irq_grp->num_irq; j++) {
486 irq_idx = irq_grp->irqs[j];
487 synchronize_irq(ab->irq_num[irq_idx]);
492 void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab)
494 __ath11k_pcic_ext_irq_disable(ab);
495 ath11k_pcic_sync_ext_irqs(ab);
497 EXPORT_SYMBOL(ath11k_pcic_ext_irq_disable);
499 static int ath11k_pcic_ext_grp_napi_poll(struct napi_struct *napi, int budget)
501 struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
502 struct ath11k_ext_irq_grp,
504 struct ath11k_base *ab = irq_grp->ab;
508 work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
509 if (work_done < budget) {
510 napi_complete_done(napi, work_done);
511 for (i = 0; i < irq_grp->num_irq; i++)
512 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
515 if (work_done > budget)
521 static irqreturn_t ath11k_pcic_ext_interrupt_handler(int irq, void *arg)
523 struct ath11k_ext_irq_grp *irq_grp = arg;
524 struct ath11k_base *ab = irq_grp->ab;
527 if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
530 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
532 /* last interrupt received for this group */
533 irq_grp->timestamp = jiffies;
535 for (i = 0; i < irq_grp->num_irq; i++)
536 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
538 napi_schedule(&irq_grp->napi);
544 ath11k_pcic_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
546 return ab->pci.ops->get_msi_irq(ab, vector);
549 static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab)
551 int i, j, ret, num_vectors = 0;
552 u32 user_base_data = 0, base_vector = 0;
553 unsigned long irq_flags;
555 ret = ath11k_pcic_get_user_msi_assignment(ab, "DP", &num_vectors,
561 irq_flags = IRQF_SHARED;
562 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
563 irq_flags |= IRQF_NOBALANCING;
565 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
566 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
571 init_dummy_netdev(&irq_grp->napi_ndev);
572 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
573 ath11k_pcic_ext_grp_napi_poll);
575 if (ab->hw_params.ring_mask->tx[i] ||
576 ab->hw_params.ring_mask->rx[i] ||
577 ab->hw_params.ring_mask->rx_err[i] ||
578 ab->hw_params.ring_mask->rx_wbm_rel[i] ||
579 ab->hw_params.ring_mask->reo_status[i] ||
580 ab->hw_params.ring_mask->rxdma2host[i] ||
581 ab->hw_params.ring_mask->host2rxdma[i] ||
582 ab->hw_params.ring_mask->rx_mon_status[i]) {
586 irq_grp->num_irq = num_irq;
587 irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i;
589 for (j = 0; j < irq_grp->num_irq; j++) {
590 int irq_idx = irq_grp->irqs[j];
591 int vector = (i % num_vectors) + base_vector;
592 int irq = ath11k_pcic_get_msi_irq(ab, vector);
597 ab->irq_num[irq_idx] = irq;
599 ath11k_dbg(ab, ATH11K_DBG_PCI,
600 "irq:%d group:%d\n", irq, i);
602 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
603 ret = request_irq(irq, ath11k_pcic_ext_interrupt_handler,
604 irq_flags, "DP_EXT_IRQ", irq_grp);
606 ath11k_err(ab, "failed request irq %d: %d\n",
611 ath11k_pcic_ext_grp_disable(irq_grp);
617 int ath11k_pcic_config_irq(struct ath11k_base *ab)
619 struct ath11k_ce_pipe *ce_pipe;
621 u32 msi_data_count, msi_data_idx;
623 unsigned int msi_data;
624 int irq, i, ret, irq_idx;
625 unsigned long irq_flags;
627 ret = ath11k_pcic_get_user_msi_assignment(ab, "CE", &msi_data_count,
628 &msi_data_start, &msi_irq_start);
632 irq_flags = IRQF_SHARED;
633 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
634 irq_flags |= IRQF_NOBALANCING;
636 /* Configure CE irqs */
637 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
638 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
641 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
642 irq = ath11k_pcic_get_msi_irq(ab, msi_data);
646 ce_pipe = &ab->ce.ce_pipe[i];
648 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
650 tasklet_setup(&ce_pipe->intr_tq, ath11k_pcic_ce_tasklet);
652 ret = request_irq(irq, ath11k_pcic_ce_interrupt_handler,
653 irq_flags, irq_name[irq_idx], ce_pipe);
655 ath11k_err(ab, "failed to request irq %d: %d\n",
660 ab->irq_num[irq_idx] = irq;
663 ath11k_pcic_ce_irq_disable(ab, i);
666 ret = ath11k_pcic_ext_irq_config(ab);
672 EXPORT_SYMBOL(ath11k_pcic_config_irq);
674 void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab)
678 set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
680 for (i = 0; i < ab->hw_params.ce_count; i++) {
681 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
683 ath11k_pcic_ce_irq_enable(ab, i);
686 EXPORT_SYMBOL(ath11k_pcic_ce_irqs_enable);
688 static void ath11k_pcic_kill_tasklets(struct ath11k_base *ab)
692 for (i = 0; i < ab->hw_params.ce_count; i++) {
693 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
695 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
698 tasklet_kill(&ce_pipe->intr_tq);
702 void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab)
704 ath11k_pcic_ce_irqs_disable(ab);
705 ath11k_pcic_sync_ce_irqs(ab);
706 ath11k_pcic_kill_tasklets(ab);
708 EXPORT_SYMBOL(ath11k_pcic_ce_irq_disable_sync);
710 void ath11k_pcic_stop(struct ath11k_base *ab)
712 ath11k_pcic_ce_irq_disable_sync(ab);
713 ath11k_ce_cleanup_pipes(ab);
715 EXPORT_SYMBOL(ath11k_pcic_stop);
717 int ath11k_pcic_start(struct ath11k_base *ab)
719 set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
721 ath11k_pcic_ce_irqs_enable(ab);
722 ath11k_ce_rx_post_buf(ab);
726 EXPORT_SYMBOL(ath11k_pcic_start);
728 int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
729 u8 *ul_pipe, u8 *dl_pipe)
731 const struct service_to_pipe *entry;
732 bool ul_set = false, dl_set = false;
735 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
736 entry = &ab->hw_params.svc_to_ce_map[i];
738 if (__le32_to_cpu(entry->service_id) != service_id)
741 switch (__le32_to_cpu(entry->pipedir)) {
746 *dl_pipe = __le32_to_cpu(entry->pipenum);
751 *ul_pipe = __le32_to_cpu(entry->pipenum);
757 *dl_pipe = __le32_to_cpu(entry->pipenum);
758 *ul_pipe = __le32_to_cpu(entry->pipenum);
765 if (WARN_ON(!ul_set || !dl_set))
770 EXPORT_SYMBOL(ath11k_pcic_map_service_to_pipe);
772 int ath11k_pcic_register_pci_ops(struct ath11k_base *ab,
773 const struct ath11k_pci_ops *pci_ops)
778 /* Return error if mandatory pci_ops callbacks are missing */
779 if (!pci_ops->get_msi_irq || !pci_ops->window_write32 ||
780 !pci_ops->window_read32)
783 ab->pci.ops = pci_ops;
786 EXPORT_SYMBOL(ath11k_pcic_register_pci_ops);
788 void ath11k_pci_enable_ce_irqs_except_wake_irq(struct ath11k_base *ab)
792 for (i = 0; i < ab->hw_params.ce_count; i++) {
793 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR ||
794 i == ATH11K_PCI_CE_WAKE_IRQ)
796 ath11k_pcic_ce_irq_enable(ab, i);
799 EXPORT_SYMBOL(ath11k_pci_enable_ce_irqs_except_wake_irq);
801 void ath11k_pci_disable_ce_irqs_except_wake_irq(struct ath11k_base *ab)
805 struct ath11k_ce_pipe *ce_pipe;
807 for (i = 0; i < ab->hw_params.ce_count; i++) {
808 ce_pipe = &ab->ce.ce_pipe[i];
809 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
811 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR ||
812 i == ATH11K_PCI_CE_WAKE_IRQ)
815 disable_irq_nosync(ab->irq_num[irq_idx]);
816 synchronize_irq(ab->irq_num[irq_idx]);
817 tasklet_kill(&ce_pipe->intr_tq);
820 EXPORT_SYMBOL(ath11k_pci_disable_ce_irqs_except_wake_irq);