1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
10 #include <linux/of_address.h>
11 #include <linux/ioport.h>
19 #define MHI_TIMEOUT_DEFAULT_MS 20000
20 #define RDDM_DUMP_SIZE 0x420000
22 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
31 .doorbell = MHI_DB_BRST_DISABLE,
33 .offload_channel = false,
34 .doorbell_mode_switch = false,
42 .dir = DMA_FROM_DEVICE,
45 .doorbell = MHI_DB_BRST_DISABLE,
47 .offload_channel = false,
48 .doorbell_mode_switch = false,
59 .doorbell = MHI_DB_BRST_DISABLE,
61 .offload_channel = false,
62 .doorbell_mode_switch = false,
70 .dir = DMA_FROM_DEVICE,
73 .doorbell = MHI_DB_BRST_DISABLE,
75 .offload_channel = false,
76 .doorbell_mode_switch = false,
81 static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
84 .irq_moderation_ms = 0,
86 .mode = MHI_DB_BRST_DISABLE,
87 .data_type = MHI_ER_CTRL,
88 .hardware_event = false,
89 .client_managed = false,
90 .offload_channel = false,
94 .irq_moderation_ms = 1,
96 .mode = MHI_DB_BRST_DISABLE,
98 .hardware_event = false,
99 .client_managed = false,
100 .offload_channel = false,
104 static struct mhi_controller_config ath11k_mhi_config_qca6390 = {
107 .use_bounce_buf = false,
109 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
110 .ch_cfg = ath11k_mhi_channels_qca6390,
111 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
112 .event_cfg = ath11k_mhi_events_qca6390,
115 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
121 .dir = DMA_TO_DEVICE,
124 .doorbell = MHI_DB_BRST_DISABLE,
126 .offload_channel = false,
127 .doorbell_mode_switch = false,
135 .dir = DMA_FROM_DEVICE,
138 .doorbell = MHI_DB_BRST_DISABLE,
140 .offload_channel = false,
141 .doorbell_mode_switch = false,
149 .dir = DMA_TO_DEVICE,
152 .doorbell = MHI_DB_BRST_DISABLE,
154 .offload_channel = false,
155 .doorbell_mode_switch = false,
163 .dir = DMA_FROM_DEVICE,
166 .doorbell = MHI_DB_BRST_DISABLE,
168 .offload_channel = false,
169 .doorbell_mode_switch = false,
174 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
177 .irq_moderation_ms = 0,
179 .data_type = MHI_ER_CTRL,
180 .mode = MHI_DB_BRST_DISABLE,
181 .hardware_event = false,
182 .client_managed = false,
183 .offload_channel = false,
187 .irq_moderation_ms = 1,
189 .mode = MHI_DB_BRST_DISABLE,
191 .hardware_event = false,
192 .client_managed = false,
193 .offload_channel = false,
197 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
200 .use_bounce_buf = false,
202 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
203 .ch_cfg = ath11k_mhi_channels_qcn9074,
204 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
205 .event_cfg = ath11k_mhi_events_qcn9074,
208 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
212 val = ath11k_pcic_read32(ab, MHISTATUS);
214 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val);
216 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
217 * has SYSERR bit set and thus need to set MHICTRL_RESET
220 ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
225 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab)
227 ath11k_pcic_write32(ab, PCIE_TXVECDB, 0);
230 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab)
232 ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0);
235 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab)
237 ath11k_pcic_write32(ab, PCIE_RXVECDB, 0);
240 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab)
242 ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0);
245 void ath11k_mhi_clear_vector(struct ath11k_base *ab)
247 ath11k_mhi_reset_txvecdb(ab);
248 ath11k_mhi_reset_txvecstatus(ab);
249 ath11k_mhi_reset_rxvecdb(ab);
250 ath11k_mhi_reset_rxvecstatus(ab);
253 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
255 struct ath11k_base *ab = ab_pci->ab;
256 u32 user_base_data, base_vector;
257 int ret, num_vectors, i;
259 unsigned int msi_data;
261 ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors,
262 &user_base_data, &base_vector);
266 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
267 num_vectors, base_vector);
269 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
273 for (i = 0; i < num_vectors; i++) {
274 msi_data = base_vector;
276 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
279 irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
282 ab_pci->mhi_ctrl->irq = irq;
283 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
288 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
293 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
297 static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason)
301 return "MHI_CB_IDLE";
302 case MHI_CB_PENDING_DATA:
303 return "MHI_CB_PENDING_DATA";
304 case MHI_CB_LPM_ENTER:
305 return "MHI_CB_LPM_ENTER";
306 case MHI_CB_LPM_EXIT:
307 return "MHI_CB_LPM_EXIT";
309 return "MHI_CB_EE_RDDM";
310 case MHI_CB_EE_MISSION_MODE:
311 return "MHI_CB_EE_MISSION_MODE";
312 case MHI_CB_SYS_ERROR:
313 return "MHI_CB_SYS_ERROR";
314 case MHI_CB_FATAL_ERROR:
315 return "MHI_CB_FATAL_ERROR";
317 return "MHI_CB_BW_REQ";
323 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
324 enum mhi_callback cb)
326 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
328 ath11k_dbg(ab, ATH11K_DBG_BOOT, "mhi notify status reason %s\n",
329 ath11k_mhi_op_callback_to_str(cb));
332 case MHI_CB_SYS_ERROR:
333 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
336 if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags)))
337 queue_work(ab->workqueue_aux, &ab->reset_work);
344 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
353 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
360 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
362 struct device_node *np;
366 np = of_find_node_by_type(NULL, "memory");
370 ret = of_address_to_resource(np, 0, &res);
375 mhi_ctrl->iova_start = res.start + 0x1000000;
376 mhi_ctrl->iova_stop = res.end;
381 int ath11k_mhi_register(struct ath11k_pci *ab_pci)
383 struct ath11k_base *ab = ab_pci->ab;
384 struct mhi_controller *mhi_ctrl;
385 struct mhi_controller_config *ath11k_mhi_config;
388 mhi_ctrl = mhi_alloc_controller();
392 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE,
394 sizeof(ab_pci->amss_path));
396 ab_pci->mhi_ctrl = mhi_ctrl;
397 mhi_ctrl->cntrl_dev = ab->dev;
398 mhi_ctrl->fw_image = ab_pci->amss_path;
399 mhi_ctrl->regs = ab->mem;
400 mhi_ctrl->reg_len = ab->mem_len;
402 ret = ath11k_mhi_get_msi(ab_pci);
404 ath11k_err(ab, "failed to get msi for mhi\n");
405 goto free_controller;
408 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
409 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
411 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
412 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
414 goto free_controller;
416 mhi_ctrl->iova_start = 0;
417 mhi_ctrl->iova_stop = 0xFFFFFFFF;
420 mhi_ctrl->rddm_size = RDDM_DUMP_SIZE;
421 mhi_ctrl->sbl_size = SZ_512K;
422 mhi_ctrl->seg_len = SZ_512K;
423 mhi_ctrl->fbc_download = true;
424 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get;
425 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put;
426 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
427 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
428 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
430 switch (ab->hw_rev) {
431 case ATH11K_HW_QCN9074_HW10:
432 ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
434 case ATH11K_HW_QCA6390_HW20:
435 case ATH11K_HW_WCN6855_HW20:
436 case ATH11K_HW_WCN6855_HW21:
437 ath11k_mhi_config = &ath11k_mhi_config_qca6390;
440 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
443 goto free_controller;
446 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
448 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
449 goto free_controller;
455 mhi_free_controller(mhi_ctrl);
456 ab_pci->mhi_ctrl = NULL;
460 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci)
462 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
464 mhi_unregister_controller(mhi_ctrl);
465 kfree(mhi_ctrl->irq);
466 mhi_free_controller(mhi_ctrl);
469 int ath11k_mhi_start(struct ath11k_pci *ab_pci)
471 struct ath11k_base *ab = ab_pci->ab;
474 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
476 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
478 ath11k_warn(ab, "failed to prepare mhi: %d", ret);
482 ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
484 ath11k_warn(ab, "failed to power up mhi: %d", ret);
491 void ath11k_mhi_stop(struct ath11k_pci *ab_pci)
493 mhi_power_down(ab_pci->mhi_ctrl, true);
494 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
497 int ath11k_mhi_suspend(struct ath11k_pci *ab_pci)
499 struct ath11k_base *ab = ab_pci->ab;
502 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
504 ath11k_warn(ab, "failed to suspend mhi: %d", ret);
511 int ath11k_mhi_resume(struct ath11k_pci *ab_pci)
513 struct ath11k_base *ab = ab_pci->ab;
516 /* Do force MHI resume as some devices like QCA6390, WCN6855
517 * are not in M3 state but they are functional. So just ignore
518 * the MHI state while resuming.
520 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl);
522 ath11k_warn(ab, "failed to resume mhi: %d", ret);