drivers/net/wireless/ath/ath11k/dp.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #ifndef ATH11K_DP_H
   8 #define ATH11K_DP_H
   9
  10 #include "hal_rx.h"
  11
  12 #define MAX_RXDMA_PER_PDEV     2
  13
  14 struct ath11k_base;
  15 struct ath11k_peer;
  16 struct ath11k_dp;
  17 struct ath11k_vif;
  18 struct hal_tcl_status_ring;
  19 struct ath11k_ext_irq_grp;
  20
  21 struct dp_rx_tid {
  22         u8 tid;
  23         u32 *vaddr;
  24         dma_addr_t paddr;
  25         u32 size;
  26         u32 ba_win_sz;
  27         bool active;
  28
  29         /* Info related to rx fragments */
  30         u32 cur_sn;
  31         u16 last_frag_no;
  32         u16 rx_frag_bitmap;
  33
  34         struct sk_buff_head rx_frags;
  35         struct hal_reo_dest_ring *dst_ring_desc;
  36
  37         /* Timer info related to fragments */
  38         struct timer_list frag_timer;
  39         struct ath11k_base *ab;
  40 };
  41
  42 #define DP_REO_DESC_FREE_THRESHOLD  64
  43 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
  44 #define DP_MON_PURGE_TIMEOUT_MS     100
  45 #define DP_MON_SERVICE_BUDGET       128
  46
  47 struct dp_reo_cache_flush_elem {
  48         struct list_head list;
  49         struct dp_rx_tid data;
  50         unsigned long ts;
  51 };
  52
  53 struct dp_reo_cmd {
  54         struct list_head list;
  55         struct dp_rx_tid data;
  56         int cmd_num;
  57         void (*handler)(struct ath11k_dp *, void *,
  58                         enum hal_reo_cmd_status status);
  59 };
  60
  61 struct dp_srng {
  62         u32 *vaddr_unaligned;
  63         u32 *vaddr;
  64         dma_addr_t paddr_unaligned;
  65         dma_addr_t paddr;
  66         int size;
  67         u32 ring_id;
  68         u8 cached;
  69 };
  70
  71 struct dp_rxdma_ring {
  72         struct dp_srng refill_buf_ring;
  73         struct idr bufs_idr;
  74         /* Protects bufs_idr */
  75         spinlock_t idr_lock;
  76         int bufs_max;
  77 };
  78
  79 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
  80
  81 struct dp_tx_ring {
  82         u8 tcl_data_ring_id;
  83         struct dp_srng tcl_data_ring;
  84         struct dp_srng tcl_comp_ring;
  85         struct idr txbuf_idr;
  86         /* Protects txbuf_idr and num_pending */
  87         spinlock_t tx_idr_lock;
  88         struct hal_wbm_release_ring *tx_status;
  89         int tx_status_head;
  90         int tx_status_tail;
  91 };
  92
  93 enum dp_mon_status_buf_state {
  94         /* PPDU id matches in dst ring and status ring */
  95         DP_MON_STATUS_MATCH,
  96         /* status ring dma is not done */
  97         DP_MON_STATUS_NO_DMA,
  98         /* status ring is lagging, reap status ring */
  99         DP_MON_STATUS_LAG,
 100         /* status ring is leading, reap dst ring and drop */
 101         DP_MON_STATUS_LEAD,
 102         /* replinish monitor status ring */
 103         DP_MON_STATUS_REPLINISH,
 104 };
 105
 106 struct ath11k_pdev_mon_stats {
 107         u32 status_ppdu_state;
 108         u32 status_ppdu_start;
 109         u32 status_ppdu_end;
 110         u32 status_ppdu_compl;
 111         u32 status_ppdu_start_mis;
 112         u32 status_ppdu_end_mis;
 113         u32 status_ppdu_done;
 114         u32 dest_ppdu_done;
 115         u32 dest_mpdu_done;
 116         u32 dest_mpdu_drop;
 117         u32 dup_mon_linkdesc_cnt;
 118         u32 dup_mon_buf_cnt;
 119         u32 dest_mon_stuck;
 120         u32 dest_mon_not_reaped;
 121 };
 122
 123 struct dp_full_mon_mpdu {
 124         struct list_head list;
 125         struct sk_buff *head;
 126         struct sk_buff *tail;
 127 };
 128
 129 struct dp_link_desc_bank {
 130         void *vaddr_unaligned;
 131         void *vaddr;
 132         dma_addr_t paddr_unaligned;
 133         dma_addr_t paddr;
 134         u32 size;
 135 };
 136
 137 /* Size to enforce scatter idle list mode */
 138 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
 139 #define DP_LINK_DESC_BANKS_MAX 8
 140
 141 #define DP_RX_DESC_COOKIE_INDEX_MAX             0x3ffff
 142 #define DP_RX_DESC_COOKIE_POOL_ID_MAX           0x1c0000
 143 #define DP_RX_DESC_COOKIE_MAX   \
 144         (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
 145 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
 146
 147 enum ath11k_dp_ppdu_state {
 148         DP_PPDU_STATUS_START,
 149         DP_PPDU_STATUS_DONE,
 150 };
 151
 152 struct ath11k_mon_data {
 153         struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
 154         struct hal_rx_mon_ppdu_info mon_ppdu_info;
 155
 156         u32 mon_ppdu_status;
 157         u32 mon_last_buf_cookie;
 158         u64 mon_last_linkdesc_paddr;
 159         u16 chan_noise_floor;
 160         bool hold_mon_dst_ring;
 161         enum dp_mon_status_buf_state buf_state;
 162         dma_addr_t mon_status_paddr;
 163         struct dp_full_mon_mpdu *mon_mpdu;
 164         struct hal_sw_mon_ring_entries sw_mon_entries;
 165         struct ath11k_pdev_mon_stats rx_mon_stats;
 166         /* lock for monitor data */
 167         spinlock_t mon_lock;
 168         struct sk_buff_head rx_status_q;
 169 };
 170
 171 struct ath11k_pdev_dp {
 172         u32 mac_id;
 173         u32 mon_dest_ring_stuck_cnt;
 174         atomic_t num_tx_pending;
 175         wait_queue_head_t tx_empty_waitq;
 176         struct dp_rxdma_ring rx_refill_buf_ring;
 177         struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
 178         struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
 179         struct dp_srng rxdma_mon_dst_ring;
 180         struct dp_srng rxdma_mon_desc_ring;
 181
 182         struct dp_rxdma_ring rxdma_mon_buf_ring;
 183         struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
 184         struct ieee80211_rx_status rx_status;
 185         struct ath11k_mon_data mon_data;
 186 };
 187
 188 #define DP_NUM_CLIENTS_MAX 64
 189 #define DP_AVG_TIDS_PER_CLIENT 2
 190 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
 191 #define DP_AVG_MSDUS_PER_FLOW 128
 192 #define DP_AVG_FLOWS_PER_TID 2
 193 #define DP_AVG_MPDUS_PER_TID_MAX 128
 194 #define DP_AVG_MSDUS_PER_MPDU 4
 195
 196 #define DP_RX_HASH_ENABLE       1 /* Enable hash based Rx steering */
 197
 198 #define DP_BA_WIN_SZ_MAX        256
 199
 200 #define DP_TCL_NUM_RING_MAX     3
 201 #define DP_TCL_NUM_RING_MAX_QCA6390     1
 202
 203 #define DP_IDLE_SCATTER_BUFS_MAX 16
 204
 205 #define DP_WBM_RELEASE_RING_SIZE        64
 206 #define DP_TCL_DATA_RING_SIZE           512
 207 #define DP_TCL_DATA_RING_SIZE_WCN6750   2048
 208 #define DP_TX_COMP_RING_SIZE            32768
 209 #define DP_TX_IDR_SIZE                  DP_TX_COMP_RING_SIZE
 210 #define DP_TCL_CMD_RING_SIZE            32
 211 #define DP_TCL_STATUS_RING_SIZE         32
 212 #define DP_REO_DST_RING_MAX             4
 213 #define DP_REO_DST_RING_SIZE            2048
 214 #define DP_REO_REINJECT_RING_SIZE       32
 215 #define DP_RX_RELEASE_RING_SIZE         1024
 216 #define DP_REO_EXCEPTION_RING_SIZE      128
 217 #define DP_REO_CMD_RING_SIZE            256
 218 #define DP_REO_STATUS_RING_SIZE         2048
 219 #define DP_RXDMA_BUF_RING_SIZE          4096
 220 #define DP_RXDMA_REFILL_RING_SIZE       2048
 221 #define DP_RXDMA_ERR_DST_RING_SIZE      1024
 222 #define DP_RXDMA_MON_STATUS_RING_SIZE   1024
 223 #define DP_RXDMA_MONITOR_BUF_RING_SIZE  4096
 224 #define DP_RXDMA_MONITOR_DST_RING_SIZE  2048
 225 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
 226
 227 #define DP_RX_RELEASE_RING_NUM  3
 228
 229 #define DP_RX_BUFFER_SIZE       2048
 230 #define DP_RX_BUFFER_SIZE_LITE  1024
 231 #define DP_RX_BUFFER_ALIGN_SIZE 128
 232
 233 #define DP_RXDMA_BUF_COOKIE_BUF_ID      GENMASK(17, 0)
 234 #define DP_RXDMA_BUF_COOKIE_PDEV_ID     GENMASK(20, 18)
 235
 236 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
 237 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
 238
 239 #define DP_TX_DESC_ID_MAC_ID  GENMASK(1, 0)
 240 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
 241 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
 242
 243 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
 244 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
 245
 246 struct ath11k_hp_update_timer {
 247         struct timer_list timer;
 248         bool started;
 249         bool init;
 250         u32 tx_num;
 251         u32 timer_tx_num;
 252         u32 ring_id;
 253         u32 interval;
 254         struct ath11k_base *ab;
 255 };
 256
 257 struct ath11k_dp {
 258         struct ath11k_base *ab;
 259         enum ath11k_htc_ep_id eid;
 260         struct completion htt_tgt_version_received;
 261         u8 htt_tgt_ver_major;
 262         u8 htt_tgt_ver_minor;
 263         struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
 264         struct dp_srng wbm_idle_ring;
 265         struct dp_srng wbm_desc_rel_ring;
 266         struct dp_srng tcl_cmd_ring;
 267         struct dp_srng tcl_status_ring;
 268         struct dp_srng reo_reinject_ring;
 269         struct dp_srng rx_rel_ring;
 270         struct dp_srng reo_except_ring;
 271         struct dp_srng reo_cmd_ring;
 272         struct dp_srng reo_status_ring;
 273         struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
 274         struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
 275         struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
 276         struct list_head reo_cmd_list;
 277         struct list_head reo_cmd_cache_flush_list;
 278         struct list_head dp_full_mon_mpdu_list;
 279         u32 reo_cmd_cache_flush_count;
 280         /**
 281          * protects access to below fields,
 282          * - reo_cmd_list
 283          * - reo_cmd_cache_flush_list
 284          * - reo_cmd_cache_flush_count
 285          */
 286         spinlock_t reo_cmd_lock;
 287         struct ath11k_hp_update_timer reo_cmd_timer;
 288         struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
 289 };
 290
 291 /* HTT definitions */
 292
 293 #define HTT_TCL_META_DATA_TYPE                  BIT(0)
 294 #define HTT_TCL_META_DATA_VALID_HTT             BIT(1)
 295
 296 /* vdev meta data */
 297 #define HTT_TCL_META_DATA_VDEV_ID               GENMASK(9, 2)
 298 #define HTT_TCL_META_DATA_PDEV_ID               GENMASK(11, 10)
 299 #define HTT_TCL_META_DATA_HOST_INSPECTED        BIT(12)
 300
 301 /* peer meta data */
 302 #define HTT_TCL_META_DATA_PEER_ID               GENMASK(15, 2)
 303
 304 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
 305
 306 #define HTT_INVALID_PEER_ID     0xffff
 307
 308 /* HTT tx completion is overlaid in wbm_release_ring */
 309 #define HTT_TX_WBM_COMP_INFO0_STATUS            GENMASK(12, 9)
 310 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON   GENMASK(16, 13)
 311 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON   GENMASK(16, 13)
 312
 313 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI          GENMASK(31, 24)
 314 #define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID        GENMASK(15, 0)
 315 #define HTT_TX_WBM_COMP_INFO2_VALID             BIT(21)
 316
 317 struct htt_tx_wbm_completion {
 318         u32 info0;
 319         u32 info1;
 320         u32 info2;
 321         u32 info3;
 322 } __packed;
 323
 324 enum htt_h2t_msg_type {
 325         HTT_H2T_MSG_TYPE_VERSION_REQ            = 0,
 326         HTT_H2T_MSG_TYPE_SRING_SETUP            = 0xb,
 327         HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG  = 0xc,
 328         HTT_H2T_MSG_TYPE_EXT_STATS_CFG          = 0x10,
 329         HTT_H2T_MSG_TYPE_PPDU_STATS_CFG         = 0x11,
 330         HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE   = 0x17,
 331 };
 332
 333 #define HTT_VER_REQ_INFO_MSG_ID         GENMASK(7, 0)
 334
 335 struct htt_ver_req_cmd {
 336         u32 ver_reg_info;
 337 } __packed;
 338
 339 enum htt_srng_ring_type {
 340         HTT_HW_TO_SW_RING,
 341         HTT_SW_TO_HW_RING,
 342         HTT_SW_TO_SW_RING,
 343 };
 344
 345 enum htt_srng_ring_id {
 346         HTT_RXDMA_HOST_BUF_RING,
 347         HTT_RXDMA_MONITOR_STATUS_RING,
 348         HTT_RXDMA_MONITOR_BUF_RING,
 349         HTT_RXDMA_MONITOR_DESC_RING,
 350         HTT_RXDMA_MONITOR_DEST_RING,
 351         HTT_HOST1_TO_FW_RXBUF_RING,
 352         HTT_HOST2_TO_FW_RXBUF_RING,
 353         HTT_RXDMA_NON_MONITOR_DEST_RING,
 354 };
 355
 356 /* host -> target  HTT_SRING_SETUP message
 357  *
 358  * After target is booted up, Host can send SRING setup message for
 359  * each host facing LMAC SRING. Target setups up HW registers based
 360  * on setup message and confirms back to Host if response_required is set.
 361  * Host should wait for confirmation message before sending new SRING
 362  * setup message
 363  *
 364  * The message would appear as follows:
 365  *
 366  * |31            24|23    20|19|18 16|15|14          8|7                0|
 367  * |--------------- +-----------------+----------------+------------------|
 368  * |    ring_type   |      ring_id    |    pdev_id     |     msg_type     |
 369  * |----------------------------------------------------------------------|
 370  * |                          ring_base_addr_lo                           |
 371  * |----------------------------------------------------------------------|
 372  * |                         ring_base_addr_hi                            |
 373  * |----------------------------------------------------------------------|
 374  * |ring_misc_cfg_flag|ring_entry_size|            ring_size              |
 375  * |----------------------------------------------------------------------|
 376  * |                         ring_head_offset32_remote_addr_lo            |
 377  * |----------------------------------------------------------------------|
 378  * |                         ring_head_offset32_remote_addr_hi            |
 379  * |----------------------------------------------------------------------|
 380  * |                         ring_tail_offset32_remote_addr_lo            |
 381  * |----------------------------------------------------------------------|
 382  * |                         ring_tail_offset32_remote_addr_hi            |
 383  * |----------------------------------------------------------------------|
 384  * |                          ring_msi_addr_lo                            |
 385  * |----------------------------------------------------------------------|
 386  * |                          ring_msi_addr_hi                            |
 387  * |----------------------------------------------------------------------|
 388  * |                          ring_msi_data                               |
 389  * |----------------------------------------------------------------------|
 390  * |         intr_timer_th            |IM|      intr_batch_counter_th     |
 391  * |----------------------------------------------------------------------|
 392  * |          reserved        |RR|PTCF|        intr_low_threshold         |
 393  * |----------------------------------------------------------------------|
 394  * Where
 395  *     IM = sw_intr_mode
 396  *     RR = response_required
 397  *     PTCF = prefetch_timer_cfg
 398  *
 399  * The message is interpreted as follows:
 400  * dword0  - b'0:7   - msg_type: This will be set to
 401  *                     HTT_H2T_MSG_TYPE_SRING_SETUP
 402  *           b'8:15  - pdev_id:
 403  *                     0 (for rings at SOC/UMAC level),
 404  *                     1/2/3 mac id (for rings at LMAC level)
 405  *           b'16:23 - ring_id: identify which ring is to setup,
 406  *                     more details can be got from enum htt_srng_ring_id
 407  *           b'24:31 - ring_type: identify type of host rings,
 408  *                     more details can be got from enum htt_srng_ring_type
 409  * dword1  - b'0:31  - ring_base_addr_lo: Lower 32bits of ring base address
 410  * dword2  - b'0:31  - ring_base_addr_hi: Upper 32bits of ring base address
 411  * dword3  - b'0:15  - ring_size: size of the ring in unit of 4-bytes words
 412  *           b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
 413  *           b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
 414  *                     SW_TO_HW_RING.
 415  *                     Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
 416  * dword4  - b'0:31  - ring_head_off32_remote_addr_lo:
 417  *                     Lower 32 bits of memory address of the remote variable
 418  *                     storing the 4-byte word offset that identifies the head
 419  *                     element within the ring.
 420  *                     (The head offset variable has type u32.)
 421  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 422  * dword5  - b'0:31  - ring_head_off32_remote_addr_hi:
 423  *                     Upper 32 bits of memory address of the remote variable
 424  *                     storing the 4-byte word offset that identifies the head
 425  *                     element within the ring.
 426  *                     (The head offset variable has type u32.)
 427  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 428  * dword6  - b'0:31  - ring_tail_off32_remote_addr_lo:
 429  *                     Lower 32 bits of memory address of the remote variable
 430  *                     storing the 4-byte word offset that identifies the tail
 431  *                     element within the ring.
 432  *                     (The tail offset variable has type u32.)
 433  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 434  * dword7  - b'0:31  - ring_tail_off32_remote_addr_hi:
 435  *                     Upper 32 bits of memory address of the remote variable
 436  *                     storing the 4-byte word offset that identifies the tail
 437  *                     element within the ring.
 438  *                     (The tail offset variable has type u32.)
 439  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 440  * dword8  - b'0:31  - ring_msi_addr_lo: Lower 32bits of MSI cfg address
 441  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
 442  * dword9  - b'0:31  - ring_msi_addr_hi: Upper 32bits of MSI cfg address
 443  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
 444  * dword10 - b'0:31  - ring_msi_data: MSI data
 445  *                     Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
 446  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
 447  * dword11 - b'0:14  - intr_batch_counter_th:
 448  *                     batch counter threshold is in units of 4-byte words.
 449  *                     HW internally maintains and increments batch count.
 450  *                     (see SRING spec for detail description).
 451  *                     When batch count reaches threshold value, an interrupt
 452  *                     is generated by HW.
 453  *           b'15    - sw_intr_mode:
 454  *                     This configuration shall be static.
 455  *                     Only programmed at power up.
 456  *                     0: generate pulse style sw interrupts
 457  *                     1: generate level style sw interrupts
 458  *           b'16:31 - intr_timer_th:
 459  *                     The timer init value when timer is idle or is
 460  *                     initialized to start downcounting.
 461  *                     In 8us units (to cover a range of 0 to 524 ms)
 462  * dword12 - b'0:15  - intr_low_threshold:
 463  *                     Used only by Consumer ring to generate ring_sw_int_p.
 464  *                     Ring entries low threshold water mark, that is used
 465  *                     in combination with the interrupt timer as well as
 466  *                     the clearing of the level interrupt.
 467  *           b'16:18 - prefetch_timer_cfg:
 468  *                     Used only by Consumer ring to set timer mode to
 469  *                     support Application prefetch handling.
 470  *                     The external tail offset/pointer will be updated
 471  *                     at following intervals:
 472  *                     3'b000: (Prefetch feature disabled; used only for debug)
 473  *                     3'b001: 1 usec
 474  *                     3'b010: 4 usec
 475  *                     3'b011: 8 usec (default)
 476  *                     3'b100: 16 usec
 477  *                     Others: Reserved
 478  *           b'19    - response_required:
 479  *                     Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
 480  *           b'20:31 - reserved:  reserved for future use
 481  */
 482
 483 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE       GENMASK(7, 0)
 484 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID        GENMASK(15, 8)
 485 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID        GENMASK(23, 16)
 486 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE      GENMASK(31, 24)
 487
 488 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE                      GENMASK(15, 0)
 489 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE                GENMASK(23, 16)
 490 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS              BIT(25)
 491 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP            BIT(27)
 492 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP        BIT(28)
 493 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP            BIT(29)
 494
 495 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH       GENMASK(14, 0)
 496 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE               BIT(15)
 497 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH          GENMASK(31, 16)
 498
 499 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH        GENMASK(15, 0)
 500 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG    BIT(16)
 501 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED      BIT(19)
 502
 503 struct htt_srng_setup_cmd {
 504         u32 info0;
 505         u32 ring_base_addr_lo;
 506         u32 ring_base_addr_hi;
 507         u32 info1;
 508         u32 ring_head_off32_remote_addr_lo;
 509         u32 ring_head_off32_remote_addr_hi;
 510         u32 ring_tail_off32_remote_addr_lo;
 511         u32 ring_tail_off32_remote_addr_hi;
 512         u32 ring_msi_addr_lo;
 513         u32 ring_msi_addr_hi;
 514         u32 msi_data;
 515         u32 intr_info;
 516         u32 info2;
 517 } __packed;
 518
 519 /* host -> target FW  PPDU_STATS config message
 520  *
 521  * @details
 522  * The following field definitions describe the format of the HTT host
 523  * to target FW for PPDU_STATS_CFG msg.
 524  * The message allows the host to configure the PPDU_STATS_IND messages
 525  * produced by the target.
 526  *
 527  * |31          24|23          16|15           8|7            0|
 528  * |-----------------------------------------------------------|
 529  * |    REQ bit mask             |   pdev_mask  |   msg type   |
 530  * |-----------------------------------------------------------|
 531  * Header fields:
 532  *  - MSG_TYPE
 533  *    Bits 7:0
 534  *    Purpose: identifies this is a req to configure ppdu_stats_ind from target
 535  *    Value: 0x11
 536  *  - PDEV_MASK
 537  *    Bits 8:15
 538  *    Purpose: identifies which pdevs this PPDU stats configuration applies to
 539  *    Value: This is a overloaded field, refer to usage and interpretation of
 540  *           PDEV in interface document.
 541  *           Bit   8    :  Reserved for SOC stats
 542  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
 543  *                         Indicates MACID_MASK in DBS
 544  *  - REQ_TLV_BIT_MASK
 545  *    Bits 16:31
 546  *    Purpose: each set bit indicates the corresponding PPDU stats TLV type
 547  *        needs to be included in the target's PPDU_STATS_IND messages.
 548  *    Value: refer htt_ppdu_stats_tlv_tag_t <<<???
 549  *
 550  */
 551
 552 struct htt_ppdu_stats_cfg_cmd {
 553         u32 msg;
 554 } __packed;
 555
 556 #define HTT_PPDU_STATS_CFG_MSG_TYPE             GENMASK(7, 0)
 557 #define HTT_PPDU_STATS_CFG_SOC_STATS            BIT(8)
 558 #define HTT_PPDU_STATS_CFG_PDEV_ID              GENMASK(15, 9)
 559 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK     GENMASK(31, 16)
 560
 561 enum htt_ppdu_stats_tag_type {
 562         HTT_PPDU_STATS_TAG_COMMON,
 563         HTT_PPDU_STATS_TAG_USR_COMMON,
 564         HTT_PPDU_STATS_TAG_USR_RATE,
 565         HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
 566         HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
 567         HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
 568         HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
 569         HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
 570         HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
 571         HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
 572         HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
 573         HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
 574         HTT_PPDU_STATS_TAG_INFO,
 575         HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
 576
 577         /* New TLV's are added above to this line */
 578         HTT_PPDU_STATS_TAG_MAX,
 579 };
 580
 581 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
 582                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
 583                                    | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
 584                                    | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
 585                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
 586                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
 587                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
 588                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
 589
 590 #define HTT_PPDU_STATS_TAG_PKTLOG  (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
 591                                     BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
 592                                     BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
 593                                     BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
 594                                     BIT(HTT_PPDU_STATS_TAG_INFO) | \
 595                                     BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
 596                                     HTT_PPDU_STATS_TAG_DEFAULT)
 597
 598 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
 599  *
 600  * details:
 601  *    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
 602  *    configure RXDMA rings.
 603  *    The configuration is per ring based and includes both packet subtypes
 604  *    and PPDU/MPDU TLVs.
 605  *
 606  *    The message would appear as follows:
 607  *
 608  *    |31       26|25|24|23            16|15             8|7             0|
 609  *    |-----------------+----------------+----------------+---------------|
 610  *    |   rsvd1   |PS|SS|     ring_id    |     pdev_id    |    msg_type   |
 611  *    |-------------------------------------------------------------------|
 612  *    |              rsvd2               |           ring_buffer_size     |
 613  *    |-------------------------------------------------------------------|
 614  *    |                        packet_type_enable_flags_0                 |
 615  *    |-------------------------------------------------------------------|
 616  *    |                        packet_type_enable_flags_1                 |
 617  *    |-------------------------------------------------------------------|
 618  *    |                        packet_type_enable_flags_2                 |
 619  *    |-------------------------------------------------------------------|
 620  *    |                        packet_type_enable_flags_3                 |
 621  *    |-------------------------------------------------------------------|
 622  *    |                         tlv_filter_in_flags                       |
 623  *    |-------------------------------------------------------------------|
 624  * Where:
 625  *     PS = pkt_swap
 626  *     SS = status_swap
 627  * The message is interpreted as follows:
 628  * dword0 - b'0:7   - msg_type: This will be set to
 629  *                    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
 630  *          b'8:15  - pdev_id:
 631  *                    0 (for rings at SOC/UMAC level),
 632  *                    1/2/3 mac id (for rings at LMAC level)
 633  *          b'16:23 - ring_id : Identify the ring to configure.
 634  *                    More details can be got from enum htt_srng_ring_id
 635  *          b'24    - status_swap: 1 is to swap status TLV
 636  *          b'25    - pkt_swap:  1 is to swap packet TLV
 637  *          b'26:31 - rsvd1:  reserved for future use
 638  * dword1 - b'0:16  - ring_buffer_size: size of buffers referenced by rx ring,
 639  *                    in byte units.
 640  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
 641  *        - b'16:31 - rsvd2: Reserved for future use
 642  * dword2 - b'0:31  - packet_type_enable_flags_0:
 643  *                    Enable MGMT packet from 0b0000 to 0b1001
 644  *                    bits from low to high: FP, MD, MO - 3 bits
 645  *                        FP: Filter_Pass
 646  *                        MD: Monitor_Direct
 647  *                        MO: Monitor_Other
 648  *                    10 mgmt subtypes * 3 bits -> 30 bits
 649  *                    Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
 650  * dword3 - b'0:31  - packet_type_enable_flags_1:
 651  *                    Enable MGMT packet from 0b1010 to 0b1111
 652  *                    bits from low to high: FP, MD, MO - 3 bits
 653  *                    Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
 654  * dword4 - b'0:31 -  packet_type_enable_flags_2:
 655  *                    Enable CTRL packet from 0b0000 to 0b1001
 656  *                    bits from low to high: FP, MD, MO - 3 bits
 657  *                    Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
 658  * dword5 - b'0:31  - packet_type_enable_flags_3:
 659  *                    Enable CTRL packet from 0b1010 to 0b1111,
 660  *                    MCAST_DATA, UCAST_DATA, NULL_DATA
 661  *                    bits from low to high: FP, MD, MO - 3 bits
 662  *                    Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
 663  * dword6 - b'0:31 -  tlv_filter_in_flags:
 664  *                    Filter in Attention/MPDU/PPDU/Header/User tlvs
 665  *                    Refer to CFG_TLV_FILTER_IN_FLAG defs
 666  */
 667
 668 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE    GENMASK(7, 0)
 669 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID     GENMASK(15, 8)
 670 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID     GENMASK(23, 16)
 671 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS          BIT(24)
 672 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS          BIT(25)
 673
 674 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE    GENMASK(15, 0)
 675
 676 enum htt_rx_filter_tlv_flags {
 677         HTT_RX_FILTER_TLV_FLAGS_MPDU_START              = BIT(0),
 678         HTT_RX_FILTER_TLV_FLAGS_MSDU_START              = BIT(1),
 679         HTT_RX_FILTER_TLV_FLAGS_RX_PACKET               = BIT(2),
 680         HTT_RX_FILTER_TLV_FLAGS_MSDU_END                = BIT(3),
 681         HTT_RX_FILTER_TLV_FLAGS_MPDU_END                = BIT(4),
 682         HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER           = BIT(5),
 683         HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER         = BIT(6),
 684         HTT_RX_FILTER_TLV_FLAGS_ATTENTION               = BIT(7),
 685         HTT_RX_FILTER_TLV_FLAGS_PPDU_START              = BIT(8),
 686         HTT_RX_FILTER_TLV_FLAGS_PPDU_END                = BIT(9),
 687         HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS     = BIT(10),
 688         HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
 689         HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE    = BIT(12),
 690 };
 691
 692 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
 693         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ          = BIT(0),
 694         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ          = BIT(1),
 695         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ          = BIT(2),
 696         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP         = BIT(3),
 697         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP         = BIT(4),
 698         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP         = BIT(5),
 699         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ        = BIT(6),
 700         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ        = BIT(7),
 701         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ        = BIT(8),
 702         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP       = BIT(9),
 703         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP       = BIT(10),
 704         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP       = BIT(11),
 705         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ          = BIT(12),
 706         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ          = BIT(13),
 707         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ          = BIT(14),
 708         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP         = BIT(15),
 709         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP         = BIT(16),
 710         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP         = BIT(17),
 711         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV   = BIT(18),
 712         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV   = BIT(19),
 713         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV   = BIT(20),
 714         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7         = BIT(21),
 715         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7         = BIT(22),
 716         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7         = BIT(23),
 717         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON             = BIT(24),
 718         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON             = BIT(25),
 719         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON             = BIT(26),
 720         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM               = BIT(27),
 721         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM               = BIT(28),
 722         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM               = BIT(29),
 723 };
 724
 725 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
 726         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC           = BIT(0),
 727         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC           = BIT(1),
 728         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC           = BIT(2),
 729         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH               = BIT(3),
 730         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH               = BIT(4),
 731         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH               = BIT(5),
 732         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH             = BIT(6),
 733         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH             = BIT(7),
 734         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH             = BIT(8),
 735         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION             = BIT(9),
 736         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION             = BIT(10),
 737         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION             = BIT(11),
 738         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK       = BIT(12),
 739         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK       = BIT(13),
 740         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK       = BIT(14),
 741         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15        = BIT(15),
 742         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15        = BIT(16),
 743         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15        = BIT(17),
 744 };
 745
 746 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
 747         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1    = BIT(0),
 748         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1    = BIT(1),
 749         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1    = BIT(2),
 750         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2    = BIT(3),
 751         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2    = BIT(4),
 752         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2    = BIT(5),
 753         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER       = BIT(6),
 754         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER       = BIT(7),
 755         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER       = BIT(8),
 756         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4    = BIT(9),
 757         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4    = BIT(10),
 758         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4    = BIT(11),
 759         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL   = BIT(12),
 760         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL   = BIT(13),
 761         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL   = BIT(14),
 762         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP       = BIT(15),
 763         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP       = BIT(16),
 764         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP       = BIT(17),
 765         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT     = BIT(18),
 766         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT     = BIT(19),
 767         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT     = BIT(20),
 768         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER       = BIT(21),
 769         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER       = BIT(22),
 770         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER       = BIT(23),
 771         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR                = BIT(24),
 772         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR                = BIT(25),
 773         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR                = BIT(26),
 774         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA                 = BIT(27),
 775         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA                 = BIT(28),
 776         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA                 = BIT(29),
 777 };
 778
 779 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
 780         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL             = BIT(0),
 781         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL             = BIT(1),
 782         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL             = BIT(2),
 783         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS                = BIT(3),
 784         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS                = BIT(4),
 785         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS                = BIT(5),
 786         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS                = BIT(6),
 787         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS                = BIT(7),
 788         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS                = BIT(8),
 789         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK                = BIT(9),
 790         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK                = BIT(10),
 791         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK                = BIT(11),
 792         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND              = BIT(12),
 793         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND              = BIT(13),
 794         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND              = BIT(14),
 795         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK          = BIT(15),
 796         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK          = BIT(16),
 797         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK          = BIT(17),
 798 };
 799
 800 enum htt_rx_data_pkt_filter_tlv_flasg3 {
 801         HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST      = BIT(18),
 802         HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST      = BIT(19),
 803         HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST      = BIT(20),
 804         HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST      = BIT(21),
 805         HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST      = BIT(22),
 806         HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST      = BIT(23),
 807         HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA  = BIT(24),
 808         HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA  = BIT(25),
 809         HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA  = BIT(26),
 810 };
 811
 812 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
 813         (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
 814         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
 815         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
 816         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
 817         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
 818         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
 819         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
 820         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
 821         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
 822
 823 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
 824         (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
 825         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
 826         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
 827         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
 828         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
 829         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
 830         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
 831         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
 832         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
 833
 834 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
 835         (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
 836         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
 837         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
 838         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
 839         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
 840         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
 841         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
 842         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
 843         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
 844
 845 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
 846                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
 847                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
 848                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
 849                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
 850
 851 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
 852                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
 853                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
 854                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
 855                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
 856
 857 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
 858                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
 859                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
 860                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
 861                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
 862
 863 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
 864                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
 865                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
 866
 867 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
 868                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
 869                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
 870
 871 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
 872                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
 873                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
 874
 875 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
 876                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
 877                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
 878                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
 879                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
 880                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
 881
 882 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
 883                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
 884                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
 885                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
 886                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
 887                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
 888
 889 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
 890                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
 891                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
 892                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
 893                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
 894                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
 895
 896 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
 897                                      | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
 898                                      | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
 899
 900 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
 901                                      | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
 902                                      | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
 903
 904 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
 905                                      | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
 906                                      | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
 907
 908 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
 909                 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
 910                 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
 911
 912 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
 913                 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
 914                 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
 915
 916 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
 917                 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
 918                 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
 919
 920 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
 921                 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
 922                 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
 923
 924 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
 925                 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
 926                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
 927                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
 928                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
 929                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
 930                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
 931                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
 932                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
 933
 934 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
 935                 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
 936                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
 937                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
 938                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
 939                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
 940                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
 941                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
 942                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
 943
 944 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
 945
 946 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
 947
 948 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
 949
 950 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
 951
 952 #define HTT_RX_MON_FILTER_TLV_FLAGS \
 953                 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
 954                 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
 955                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
 956                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
 957                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
 958                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
 959
 960 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
 961                 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
 962                 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
 963                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
 964                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
 965                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
 966                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
 967
 968 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
 969                 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
 970                 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
 971                 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
 972                 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
 973                 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
 974                 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
 975                 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
 976                 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
 977
 978 struct htt_rx_ring_selection_cfg_cmd {
 979         u32 info0;
 980         u32 info1;
 981         u32 pkt_type_en_flags0;
 982         u32 pkt_type_en_flags1;
 983         u32 pkt_type_en_flags2;
 984         u32 pkt_type_en_flags3;
 985         u32 rx_filter_tlv;
 986 } __packed;
 987
 988 struct htt_rx_ring_tlv_filter {
 989         u32 rx_filter; /* see htt_rx_filter_tlv_flags */
 990         u32 pkt_filter_flags0; /* MGMT */
 991         u32 pkt_filter_flags1; /* MGMT */
 992         u32 pkt_filter_flags2; /* CTRL */
 993         u32 pkt_filter_flags3; /* DATA */
 994 };
 995
 996 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE     GENMASK(7, 0)
 997 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID      GENMASK(15, 8)
 998
 999 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE                 BIT(0)
1000 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END         BIT(1)
1001 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END     BIT(2)
1002 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING           GENMASK(10, 3)
1003
1004 /* Enumeration for full monitor mode destination ring select
1005  * 0 - REO destination ring select
1006  * 1 - FW destination ring select
1007  * 2 - SW destination ring select
1008  * 3 - Release destination ring select
1009  */
1010 enum htt_rx_full_mon_release_ring {
1011         HTT_RX_MON_RING_REO,
1012         HTT_RX_MON_RING_FW,
1013         HTT_RX_MON_RING_SW,
1014         HTT_RX_MON_RING_RELEASE,
1015 };
1016
1017 struct htt_rx_full_monitor_mode_cfg_cmd {
1018         u32 info0;
1019         u32 cfg;
1020 } __packed;
1021
1022 /* HTT message target->host */
1023
1024 enum htt_t2h_msg_type {
1025         HTT_T2H_MSG_TYPE_VERSION_CONF,
1026         HTT_T2H_MSG_TYPE_PEER_MAP       = 0x3,
1027         HTT_T2H_MSG_TYPE_PEER_UNMAP     = 0x4,
1028         HTT_T2H_MSG_TYPE_RX_ADDBA       = 0x5,
1029         HTT_T2H_MSG_TYPE_PKTLOG         = 0x8,
1030         HTT_T2H_MSG_TYPE_SEC_IND        = 0xb,
1031         HTT_T2H_MSG_TYPE_PEER_MAP2      = 0x1e,
1032         HTT_T2H_MSG_TYPE_PEER_UNMAP2    = 0x1f,
1033         HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1034         HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1035         HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1036 };
1037
1038 #define HTT_TARGET_VERSION_MAJOR 3
1039
1040 #define HTT_T2H_MSG_TYPE                GENMASK(7, 0)
1041 #define HTT_T2H_VERSION_CONF_MINOR      GENMASK(15, 8)
1042 #define HTT_T2H_VERSION_CONF_MAJOR      GENMASK(23, 16)
1043
1044 struct htt_t2h_version_conf_msg {
1045         u32 version;
1046 } __packed;
1047
1048 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID   GENMASK(15, 8)
1049 #define HTT_T2H_PEER_MAP_INFO_PEER_ID   GENMASK(31, 16)
1050 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16     GENMASK(15, 0)
1051 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID       GENMASK(31, 16)
1052 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL     GENMASK(15, 0)
1053 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M       BIT(16)
1054 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S       16
1055
1056 struct htt_t2h_peer_map_event {
1057         u32 info;
1058         u32 mac_addr_l32;
1059         u32 info1;
1060         u32 info2;
1061 } __packed;
1062
1063 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1064 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1065 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1066                                         HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1067 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1068 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1069
1070 struct htt_t2h_peer_unmap_event {
1071         u32 info;
1072         u32 mac_addr_l32;
1073         u32 info1;
1074 } __packed;
1075
1076 struct htt_resp_msg {
1077         union {
1078                 struct htt_t2h_version_conf_msg version_msg;
1079                 struct htt_t2h_peer_map_event peer_map_ev;
1080                 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1081         };
1082 } __packed;
1083
1084 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
1085 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
1086 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
1087
1088 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1089 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1090
1091 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0
1092 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1
1093
1094 enum htt_backpressure_umac_ringid {
1095         HTT_SW_RING_IDX_REO_REO2SW1_RING,
1096         HTT_SW_RING_IDX_REO_REO2SW2_RING,
1097         HTT_SW_RING_IDX_REO_REO2SW3_RING,
1098         HTT_SW_RING_IDX_REO_REO2SW4_RING,
1099         HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1100         HTT_SW_RING_IDX_REO_REO2TCL_RING,
1101         HTT_SW_RING_IDX_REO_REO2FW_RING,
1102         HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1103         HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1104         HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1105         HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1106         HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1107         HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1108         HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1109         HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1110         HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1111         HTT_SW_RING_IDX_REO_REO_CMD_RING,
1112         HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1113         HTT_SW_UMAC_RING_IDX_MAX,
1114 };
1115
1116 enum htt_backpressure_lmac_ringid {
1117         HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1118         HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1119         HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1120         HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1121         HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1122         HTT_SW_RING_IDX_RXDMA2FW_RING,
1123         HTT_SW_RING_IDX_RXDMA2SW_RING,
1124         HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1125         HTT_SW_RING_IDX_RXDMA2REO_RING,
1126         HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1127         HTT_SW_RING_IDX_MONITOR_BUF_RING,
1128         HTT_SW_RING_IDX_MONITOR_DESC_RING,
1129         HTT_SW_RING_IDX_MONITOR_DEST_RING,
1130         HTT_SW_LMAC_RING_IDX_MAX,
1131 };
1132
1133 /* ppdu stats
1134  *
1135  * @details
1136  * The following field definitions describe the format of the HTT target
1137  * to host ppdu stats indication message.
1138  *
1139  *
1140  * |31                         16|15   12|11   10|9      8|7            0 |
1141  * |----------------------------------------------------------------------|
1142  * |    payload_size             | rsvd  |pdev_id|mac_id  |    msg type   |
1143  * |----------------------------------------------------------------------|
1144  * |                          ppdu_id                                     |
1145  * |----------------------------------------------------------------------|
1146  * |                        Timestamp in us                               |
1147  * |----------------------------------------------------------------------|
1148  * |                          reserved                                    |
1149  * |----------------------------------------------------------------------|
1150  * |                    type-specific stats info                          |
1151  * |                     (see htt_ppdu_stats.h)                           |
1152  * |----------------------------------------------------------------------|
1153  * Header fields:
1154  *  - MSG_TYPE
1155  *    Bits 7:0
1156  *    Purpose: Identifies this is a PPDU STATS indication
1157  *             message.
1158  *    Value: 0x1d
1159  *  - mac_id
1160  *    Bits 9:8
1161  *    Purpose: mac_id of this ppdu_id
1162  *    Value: 0-3
1163  *  - pdev_id
1164  *    Bits 11:10
1165  *    Purpose: pdev_id of this ppdu_id
1166  *    Value: 0-3
1167  *     0 (for rings at SOC level),
1168  *     1/2/3 PDEV -> 0/1/2
1169  *  - payload_size
1170  *    Bits 31:16
1171  *    Purpose: total tlv size
1172  *    Value: payload_size in bytes
1173  */
1174
1175 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1176 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1177
1178 struct ath11k_htt_ppdu_stats_msg {
1179         u32 info;
1180         u32 ppdu_id;
1181         u32 timestamp;
1182         u32 rsvd;
1183         u8 data[];
1184 } __packed;
1185
1186 struct htt_tlv {
1187         u32 header;
1188         u8 value[];
1189 } __packed;
1190
1191 #define HTT_TLV_TAG                     GENMASK(11, 0)
1192 #define HTT_TLV_LEN                     GENMASK(23, 12)
1193
1194 enum HTT_PPDU_STATS_BW {
1195         HTT_PPDU_STATS_BANDWIDTH_5MHZ   = 0,
1196         HTT_PPDU_STATS_BANDWIDTH_10MHZ  = 1,
1197         HTT_PPDU_STATS_BANDWIDTH_20MHZ  = 2,
1198         HTT_PPDU_STATS_BANDWIDTH_40MHZ  = 3,
1199         HTT_PPDU_STATS_BANDWIDTH_80MHZ  = 4,
1200         HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1201         HTT_PPDU_STATS_BANDWIDTH_DYN    = 6,
1202 };
1203
1204 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M   GENMASK(7, 0)
1205 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M   GENMASK(15, 8)
1206 /* bw - HTT_PPDU_STATS_BW */
1207 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M           GENMASK(19, 16)
1208
1209 struct htt_ppdu_stats_common {
1210         u32 ppdu_id;
1211         u16 sched_cmdid;
1212         u8 ring_id;
1213         u8 num_users;
1214         u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1215         u32 chain_mask;
1216         u32 fes_duration_us; /* frame exchange sequence */
1217         u32 ppdu_sch_eval_start_tstmp_us;
1218         u32 ppdu_sch_end_tstmp_us;
1219         u32 ppdu_start_tstmp_us;
1220         /* BIT [15 :  0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1221          * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1222          */
1223         u16 phy_mode;
1224         u16 bw_mhz;
1225 } __packed;
1226
1227 enum htt_ppdu_stats_gi {
1228         HTT_PPDU_STATS_SGI_0_8_US,
1229         HTT_PPDU_STATS_SGI_0_4_US,
1230         HTT_PPDU_STATS_SGI_1_6_US,
1231         HTT_PPDU_STATS_SGI_3_2_US,
1232 };
1233
1234 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M       GENMASK(3, 0)
1235 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M    GENMASK(11, 4)
1236
1237 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1238 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M      GENMASK(5, 1)
1239
1240 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M       GENMASK(1, 0)
1241 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M           BIT(2)
1242 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M          BIT(3)
1243 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M           GENMASK(7, 4)
1244 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M             GENMASK(11, 8)
1245 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M            GENMASK(15, 12)
1246 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M            GENMASK(19, 16)
1247 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M       GENMASK(23, 20)
1248 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M             GENMASK(27, 24)
1249 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M            BIT(28)
1250 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M           BIT(29)
1251
1252 #define HTT_USR_RATE_PREAMBLE(_val) \
1253                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1254 #define HTT_USR_RATE_BW(_val) \
1255                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1256 #define HTT_USR_RATE_NSS(_val) \
1257                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1258 #define HTT_USR_RATE_MCS(_val) \
1259                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1260 #define HTT_USR_RATE_GI(_val) \
1261                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1262 #define HTT_USR_RATE_DCM(_val) \
1263                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1264
1265 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M          GENMASK(1, 0)
1266 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M              BIT(2)
1267 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M             BIT(3)
1268 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M              GENMASK(7, 4)
1269 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M                GENMASK(11, 8)
1270 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M               GENMASK(15, 12)
1271 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M               GENMASK(19, 16)
1272 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M          GENMASK(23, 20)
1273 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M                GENMASK(27, 24)
1274 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M               BIT(28)
1275 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M              BIT(29)
1276
1277 struct htt_ppdu_stats_user_rate {
1278         u8 tid_num;
1279         u8 reserved0;
1280         u16 sw_peer_id;
1281         u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1282         u16 ru_end;
1283         u16 ru_start;
1284         u16 resp_ru_end;
1285         u16 resp_ru_start;
1286         u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1287         u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1288         /* Note: resp_rate_info is only valid for if resp_type is UL */
1289         u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1290 } __packed;
1291
1292 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M         GENMASK(7, 0)
1293 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M         BIT(8)
1294 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M    GENMASK(10, 9)
1295 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M               GENMASK(13, 11)
1296 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M              BIT(14)
1297 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M           GENMASK(31, 16)
1298
1299 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1300                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1301 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1302                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1303 #define HTT_TX_INFO_RATECODE(_flags) \
1304                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1305 #define HTT_TX_INFO_PEERID(_flags) \
1306                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1307
1308 struct htt_tx_ppdu_stats_info {
1309         struct htt_tlv tlv_hdr;
1310         u32 tx_success_bytes;
1311         u32 tx_retry_bytes;
1312         u32 tx_failed_bytes;
1313         u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1314         u16 tx_success_msdus;
1315         u16 tx_retry_msdus;
1316         u16 tx_failed_msdus;
1317         u16 tx_duration; /* united in us */
1318 } __packed;
1319
1320 enum  htt_ppdu_stats_usr_compln_status {
1321         HTT_PPDU_STATS_USER_STATUS_OK,
1322         HTT_PPDU_STATS_USER_STATUS_FILTERED,
1323         HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1324         HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1325         HTT_PPDU_STATS_USER_STATUS_ABORT,
1326 };
1327
1328 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M        GENMASK(3, 0)
1329 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M       GENMASK(7, 4)
1330 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M          BIT(8)
1331 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M         GENMASK(12, 9)
1332
1333 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1334             FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1335 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1336             FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1337 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1338             FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1339
1340 struct htt_ppdu_stats_usr_cmpltn_cmn {
1341         u8 status;
1342         u8 tid_num;
1343         u16 sw_peer_id;
1344         /* RSSI value of last ack packet (units = dB above noise floor) */
1345         u32 ack_rssi;
1346         u16 mpdu_tried;
1347         u16 mpdu_success;
1348         u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1349 } __packed;
1350
1351 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M   GENMASK(8, 0)
1352 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M   GENMASK(24, 9)
1353 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM      GENMASK(31, 25)
1354
1355 #define HTT_PPDU_STATS_NON_QOS_TID      16
1356
1357 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1358         u32 ppdu_id;
1359         u16 sw_peer_id;
1360         u16 reserved0;
1361         u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1362         u16 current_seq;
1363         u16 start_seq;
1364         u32 success_bytes;
1365 } __packed;
1366
1367 struct htt_ppdu_stats_usr_cmn_array {
1368         struct htt_tlv tlv_hdr;
1369         u32 num_ppdu_stats;
1370         /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info
1371          * elements.
1372          * tx_ppdu_stats_info is variable length, with length =
1373          *     number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
1374          */
1375         struct htt_tx_ppdu_stats_info tx_ppdu_info[];
1376 } __packed;
1377
1378 struct htt_ppdu_user_stats {
1379         u16 peer_id;
1380         u32 tlv_flags;
1381         bool is_valid_peer_id;
1382         struct htt_ppdu_stats_user_rate rate;
1383         struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1384         struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1385 };
1386
1387 #define HTT_PPDU_STATS_MAX_USERS        8
1388 #define HTT_PPDU_DESC_MAX_DEPTH 16
1389
1390 struct htt_ppdu_stats {
1391         struct htt_ppdu_stats_common common;
1392         struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1393 };
1394
1395 struct htt_ppdu_stats_info {
1396         u32 ppdu_id;
1397         struct htt_ppdu_stats ppdu_stats;
1398         struct list_head list;
1399 };
1400
1401 /* @brief target -> host packet log message
1402  *
1403  * @details
1404  * The following field definitions describe the format of the packet log
1405  * message sent from the target to the host.
1406  * The message consists of a 4-octet header,followed by a variable number
1407  * of 32-bit character values.
1408  *
1409  * |31                         16|15  12|11   10|9    8|7            0|
1410  * |------------------------------------------------------------------|
1411  * |        payload_size         | rsvd |pdev_id|mac_id|   msg type   |
1412  * |------------------------------------------------------------------|
1413  * |                              payload                             |
1414  * |------------------------------------------------------------------|
1415  *   - MSG_TYPE
1416  *     Bits 7:0
1417  *     Purpose: identifies this as a pktlog message
1418  *     Value: HTT_T2H_MSG_TYPE_PKTLOG
1419  *   - mac_id
1420  *     Bits 9:8
1421  *     Purpose: identifies which MAC/PHY instance generated this pktlog info
1422  *     Value: 0-3
1423  *   - pdev_id
1424  *     Bits 11:10
1425  *     Purpose: pdev_id
1426  *     Value: 0-3
1427  *     0 (for rings at SOC level),
1428  *     1/2/3 PDEV -> 0/1/2
1429  *   - payload_size
1430  *     Bits 31:16
1431  *     Purpose: explicitly specify the payload size
1432  *     Value: payload size in bytes (payload size is a multiple of 4 bytes)
1433  */
1434 struct htt_pktlog_msg {
1435         u32 hdr;
1436         u8 payload[];
1437 };
1438
1439 /* @brief host -> target FW extended statistics retrieve
1440  *
1441  * @details
1442  * The following field definitions describe the format of the HTT host
1443  * to target FW extended stats retrieve message.
1444  * The message specifies the type of stats the host wants to retrieve.
1445  *
1446  * |31          24|23          16|15           8|7            0|
1447  * |-----------------------------------------------------------|
1448  * |   reserved   | stats type   |   pdev_mask  |   msg type   |
1449  * |-----------------------------------------------------------|
1450  * |                   config param [0]                        |
1451  * |-----------------------------------------------------------|
1452  * |                   config param [1]                        |
1453  * |-----------------------------------------------------------|
1454  * |                   config param [2]                        |
1455  * |-----------------------------------------------------------|
1456  * |                   config param [3]                        |
1457  * |-----------------------------------------------------------|
1458  * |                         reserved                          |
1459  * |-----------------------------------------------------------|
1460  * |                        cookie LSBs                        |
1461  * |-----------------------------------------------------------|
1462  * |                        cookie MSBs                        |
1463  * |-----------------------------------------------------------|
1464  * Header fields:
1465  *  - MSG_TYPE
1466  *    Bits 7:0
1467  *    Purpose: identifies this is a extended stats upload request message
1468  *    Value: 0x10
1469  *  - PDEV_MASK
1470  *    Bits 8:15
1471  *    Purpose: identifies the mask of PDEVs to retrieve stats from
1472  *    Value: This is a overloaded field, refer to usage and interpretation of
1473  *           PDEV in interface document.
1474  *           Bit   8    :  Reserved for SOC stats
1475  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
1476  *                         Indicates MACID_MASK in DBS
1477  *  - STATS_TYPE
1478  *    Bits 23:16
1479  *    Purpose: identifies which FW statistics to upload
1480  *    Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1481  *  - Reserved
1482  *    Bits 31:24
1483  *  - CONFIG_PARAM [0]
1484  *    Bits 31:0
1485  *    Purpose: give an opaque configuration value to the specified stats type
1486  *    Value: stats-type specific configuration value
1487  *           Refer to htt_stats.h for interpretation for each stats sub_type
1488  *  - CONFIG_PARAM [1]
1489  *    Bits 31:0
1490  *    Purpose: give an opaque configuration value to the specified stats type
1491  *    Value: stats-type specific configuration value
1492  *           Refer to htt_stats.h for interpretation for each stats sub_type
1493  *  - CONFIG_PARAM [2]
1494  *    Bits 31:0
1495  *    Purpose: give an opaque configuration value to the specified stats type
1496  *    Value: stats-type specific configuration value
1497  *           Refer to htt_stats.h for interpretation for each stats sub_type
1498  *  - CONFIG_PARAM [3]
1499  *    Bits 31:0
1500  *    Purpose: give an opaque configuration value to the specified stats type
1501  *    Value: stats-type specific configuration value
1502  *           Refer to htt_stats.h for interpretation for each stats sub_type
1503  *  - Reserved [31:0] for future use.
1504  *  - COOKIE_LSBS
1505  *    Bits 31:0
1506  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1507  *        message with its preceding host->target stats request message.
1508  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1509  *  - COOKIE_MSBS
1510  *    Bits 31:0
1511  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1512  *        message with its preceding host->target stats request message.
1513  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1514  */
1515
1516 struct htt_ext_stats_cfg_hdr {
1517         u8 msg_type;
1518         u8 pdev_mask;
1519         u8 stats_type;
1520         u8 reserved;
1521 } __packed;
1522
1523 struct htt_ext_stats_cfg_cmd {
1524         struct htt_ext_stats_cfg_hdr hdr;
1525         u32 cfg_param0;
1526         u32 cfg_param1;
1527         u32 cfg_param2;
1528         u32 cfg_param3;
1529         u32 reserved;
1530         u32 cookie_lsb;
1531         u32 cookie_msb;
1532 } __packed;
1533
1534 /* htt stats config default params */
1535 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1536 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1537 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1538 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1539 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1540 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1541 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1542 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1543
1544 /* HTT_DBG_EXT_STATS_PEER_INFO
1545  * PARAMS:
1546  * @config_param0:
1547  *  [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1548  *  [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1549  *  [Bit31 : Bit16] sw_peer_id
1550  * @config_param1:
1551  *  peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1552  *   0 bit htt_peer_stats_cmn_tlv
1553  *   1 bit htt_peer_details_tlv
1554  *   2 bit htt_tx_peer_rate_stats_tlv
1555  *   3 bit htt_rx_peer_rate_stats_tlv
1556  *   4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1557  *   5 bit htt_rx_tid_stats_tlv
1558  *   6 bit htt_msdu_flow_stats_tlv
1559  * @config_param2: [Bit31 : Bit0] mac_addr31to0
1560  * @config_param3: [Bit15 : Bit0] mac_addr47to32
1561  *                [Bit31 : Bit16] reserved
1562  */
1563 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1564 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1565
1566 /* Used to set different configs to the specified stats type.*/
1567 struct htt_ext_stats_cfg_params {
1568         u32 cfg0;
1569         u32 cfg1;
1570         u32 cfg2;
1571         u32 cfg3;
1572 };
1573
1574 /* @brief target -> host extended statistics upload
1575  *
1576  * @details
1577  * The following field definitions describe the format of the HTT target
1578  * to host stats upload confirmation message.
1579  * The message contains a cookie echoed from the HTT host->target stats
1580  * upload request, which identifies which request the confirmation is
1581  * for, and a single stats can span over multiple HTT stats indication
1582  * due to the HTT message size limitation so every HTT ext stats indication
1583  * will have tag-length-value stats information elements.
1584  * The tag-length header for each HTT stats IND message also includes a
1585  * status field, to indicate whether the request for the stat type in
1586  * question was fully met, partially met, unable to be met, or invalid
1587  * (if the stat type in question is disabled in the target).
1588  * A Done bit 1's indicate the end of the of stats info elements.
1589  *
1590  *
1591  * |31                         16|15    12|11|10 8|7   5|4       0|
1592  * |--------------------------------------------------------------|
1593  * |                   reserved                   |    msg type   |
1594  * |--------------------------------------------------------------|
1595  * |                         cookie LSBs                          |
1596  * |--------------------------------------------------------------|
1597  * |                         cookie MSBs                          |
1598  * |--------------------------------------------------------------|
1599  * |      stats entry length     | rsvd   | D|  S |   stat type   |
1600  * |--------------------------------------------------------------|
1601  * |                   type-specific stats info                   |
1602  * |                      (see htt_stats.h)                       |
1603  * |--------------------------------------------------------------|
1604  * Header fields:
1605  *  - MSG_TYPE
1606  *    Bits 7:0
1607  *    Purpose: Identifies this is a extended statistics upload confirmation
1608  *             message.
1609  *    Value: 0x1c
1610  *  - COOKIE_LSBS
1611  *    Bits 31:0
1612  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1613  *        message with its preceding host->target stats request message.
1614  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1615  *  - COOKIE_MSBS
1616  *    Bits 31:0
1617  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1618  *        message with its preceding host->target stats request message.
1619  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1620  *
1621  * Stats Information Element tag-length header fields:
1622  *  - STAT_TYPE
1623  *    Bits 7:0
1624  *    Purpose: identifies the type of statistics info held in the
1625  *        following information element
1626  *    Value: htt_dbg_ext_stats_type
1627  *  - STATUS
1628  *    Bits 10:8
1629  *    Purpose: indicate whether the requested stats are present
1630  *    Value: htt_dbg_ext_stats_status
1631  *  - DONE
1632  *    Bits 11
1633  *    Purpose:
1634  *        Indicates the completion of the stats entry, this will be the last
1635  *        stats conf HTT segment for the requested stats type.
1636  *    Value:
1637  *        0 -> the stats retrieval is ongoing
1638  *        1 -> the stats retrieval is complete
1639  *  - LENGTH
1640  *    Bits 31:16
1641  *    Purpose: indicate the stats information size
1642  *    Value: This field specifies the number of bytes of stats information
1643  *       that follows the element tag-length header.
1644  *       It is expected but not required that this length is a multiple of
1645  *       4 bytes.
1646  */
1647
1648 #define HTT_T2H_EXT_STATS_INFO1_DONE    BIT(11)
1649 #define HTT_T2H_EXT_STATS_INFO1_LENGTH   GENMASK(31, 16)
1650
1651 struct ath11k_htt_extd_stats_msg {
1652         u32 info0;
1653         u64 cookie;
1654         u32 info1;
1655         u8 data[];
1656 } __packed;
1657
1658 #define HTT_MAC_ADDR_L32_0      GENMASK(7, 0)
1659 #define HTT_MAC_ADDR_L32_1      GENMASK(15, 8)
1660 #define HTT_MAC_ADDR_L32_2      GENMASK(23, 16)
1661 #define HTT_MAC_ADDR_L32_3      GENMASK(31, 24)
1662 #define HTT_MAC_ADDR_H16_0      GENMASK(7, 0)
1663 #define HTT_MAC_ADDR_H16_1      GENMASK(15, 8)
1664
1665 struct htt_mac_addr {
1666         u32 mac_addr_l32;
1667         u32 mac_addr_h16;
1668 };
1669
1670 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1671 {
1672         if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1673                 addr_l32 = swab32(addr_l32);
1674                 addr_h16 = swab16(addr_h16);
1675         }
1676
1677         memcpy(addr, &addr_l32, 4);
1678         memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1679 }
1680
1681 int ath11k_dp_service_srng(struct ath11k_base *ab,
1682                            struct ath11k_ext_irq_grp *irq_grp,
1683                            int budget);
1684 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1685 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1686 void ath11k_dp_free(struct ath11k_base *ab);
1687 int ath11k_dp_alloc(struct ath11k_base *ab);
1688 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1689 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1690 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1691 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1692                                 int mac_id, enum hal_ring_type ring_type);
1693 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1694 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1695 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1696 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1697                          enum hal_ring_type type, int ring_num,
1698                          int mac_id, int num_entries);
1699 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1700                                  struct dp_link_desc_bank *desc_bank,
1701                                  u32 ring_type, struct dp_srng *ring);
1702 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1703                               struct dp_link_desc_bank *link_desc_banks,
1704                               u32 ring_type, struct hal_srng *srng,
1705                               u32 n_link_desc);
1706 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1707                                   struct hal_srng       *srng,
1708                                   struct ath11k_hp_update_timer *update_timer);
1709 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1710                                  struct ath11k_hp_update_timer *update_timer);
1711 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1712                                  struct ath11k_hp_update_timer *update_timer,
1713                                  u32 interval, u32 ring_id);
1714 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab);
1715
1716 #endif