1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
9 #define CE_COUNT_MAX 12
11 /* Byte swap data words */
12 #define CE_ATTR_BYTE_SWAP_DATA 2
14 /* no interrupt on copy completion */
15 #define CE_ATTR_DIS_INTR 8
17 /* Host software's Copy Engine configuration. */
19 #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
21 #define CE_ATTR_FLAGS 0
24 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
25 #define ATH11K_CE_USAGE_THRESHOLD 32
27 void ath11k_ce_byte_swap(void *mem, u32 len);
30 * Directions for interconnect pipe configuration.
31 * These definitions may be used during configuration and are shared
32 * between Host and Target.
34 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
35 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
36 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
37 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
38 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
39 * over the interconnect.
41 #define PIPEDIR_NONE 0
42 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
43 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
44 #define PIPEDIR_INOUT 3 /* bidirectional */
45 #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
48 #define CE_HOST_IE_ADDRESS 0x00A1803C
49 #define CE_HOST_IE_2_ADDRESS 0x00A18040
50 #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS
52 /* CE IE registers are different for IPQ5018 */
53 #define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C
54 #define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050
55 #define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS
57 #define CE_HOST_IE_3_SHIFT 0xC
59 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
61 #define ATH11K_CE_RX_POST_RETRY_JIFFIES 50
66 * Establish a mapping between a service/direction and a pipe.
67 * Configuration information for a Copy Engine pipe and services.
68 * Passed from Host to Target through QMI message and must be in
69 * little endian format.
71 struct service_to_pipe {
78 * Configuration information for a Copy Engine pipe.
79 * Passed from Host to Target through QMI message during startup (one per CE).
81 * NOTE: Structure is shared between Host software and Target firmware!
83 struct ce_pipe_config {
104 /* CE_ATTR_* values */
107 /* #entries in source ring - Must be a power of 2 */
108 unsigned int src_nentries;
111 * Max source send size for this CE.
112 * This is also the minimum size of a destination buffer.
114 unsigned int src_sz_max;
116 /* #entries in destination ring - Must be a power of 2 */
117 unsigned int dest_nentries;
119 void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
120 void (*send_cb)(struct ath11k_base *, struct sk_buff *);
123 #define CE_DESC_RING_ALIGN 8
125 struct ath11k_ce_ring {
126 /* Number of entries in this ring; must be power of 2 */
127 unsigned int nentries;
128 unsigned int nentries_mask;
130 /* For dest ring, this is the next index to be processed
131 * by software after it was/is received into.
133 * For src ring, this is the last descriptor that was sent
134 * and completion processed by software.
136 * Regardless of src or dest ring, this is an invariant
137 * (modulo ring size):
138 * write index >= read index >= sw_index
140 unsigned int sw_index;
142 unsigned int write_index;
144 /* Start of DMA-coherent area reserved for descriptors */
145 /* Host address space */
146 void *base_addr_owner_space_unaligned;
147 /* CE address space */
148 u32 base_addr_ce_space_unaligned;
150 /* Actual start of descriptors.
151 * Aligned to descriptor-size boundary.
152 * Points into reserved DMA-coherent area, above.
154 /* Host address space */
155 void *base_addr_owner_space;
157 /* CE address space */
158 u32 base_addr_ce_space;
164 struct sk_buff *skb[];
167 struct ath11k_ce_pipe {
168 struct ath11k_base *ab;
170 unsigned int attr_flags;
172 unsigned int rx_buf_needed;
174 void (*send_cb)(struct ath11k_base *, struct sk_buff *);
175 void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
177 struct tasklet_struct intr_tq;
178 struct ath11k_ce_ring *src_ring;
179 struct ath11k_ce_ring *dest_ring;
180 struct ath11k_ce_ring *status_ring;
185 struct ath11k_ce_pipe ce_pipe[CE_COUNT_MAX];
186 /* Protects rings of all ce pipes */
188 struct ath11k_hp_update_timer hp_timer[CE_COUNT_MAX];
191 extern const struct ce_attr ath11k_host_ce_config_ipq8074[];
192 extern const struct ce_attr ath11k_host_ce_config_qca6390[];
193 extern const struct ce_attr ath11k_host_ce_config_qcn9074[];
195 void ath11k_ce_cleanup_pipes(struct ath11k_base *ab);
196 void ath11k_ce_rx_replenish_retry(struct timer_list *t);
197 void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id);
198 int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id,
200 void ath11k_ce_rx_post_buf(struct ath11k_base *ab);
201 int ath11k_ce_init_pipes(struct ath11k_base *ab);
202 int ath11k_ce_alloc_pipes(struct ath11k_base *ab);
203 void ath11k_ce_free_pipes(struct ath11k_base *ab);
204 int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id);
205 void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id);
206 int ath11k_ce_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
207 u8 *ul_pipe, u8 *dl_pipe);
208 int ath11k_ce_attr_attach(struct ath11k_base *ab);
209 void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
210 u32 **shadow_cfg, u32 *shadow_cfg_len);
211 void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab);