2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 #define ATH10K_FW_DIR "ath10k"
25 #define QCA988X_2_0_DEVICE_ID (0x003c)
26 #define QCA6164_2_1_DEVICE_ID (0x0041)
27 #define QCA6174_2_1_DEVICE_ID (0x003e)
28 #define QCA99X0_2_0_DEVICE_ID (0x0040)
29 #define QCA9377_1_0_DEVICE_ID (0x0042)
31 /* QCA988X 1.0 definitions (unsupported) */
32 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
34 /* QCA988X 2.0 definitions */
35 #define QCA988X_HW_2_0_VERSION 0x4100016c
36 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
37 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
38 #define QCA988X_HW_2_0_FW_FILE "firmware.bin"
39 #define QCA988X_HW_2_0_OTP_FILE "otp.bin"
40 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
41 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
43 /* QCA6174 target BMI version signatures */
44 #define QCA6174_HW_1_0_VERSION 0x05000000
45 #define QCA6174_HW_1_1_VERSION 0x05000001
46 #define QCA6174_HW_1_3_VERSION 0x05000003
47 #define QCA6174_HW_2_1_VERSION 0x05010000
48 #define QCA6174_HW_3_0_VERSION 0x05020000
49 #define QCA6174_HW_3_2_VERSION 0x05030000
51 /* QCA9377 target BMI version signatures */
52 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000
53 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001
55 enum qca6174_pci_rev {
56 QCA6174_PCI_REV_1_1 = 0x11,
57 QCA6174_PCI_REV_1_3 = 0x13,
58 QCA6174_PCI_REV_2_0 = 0x20,
59 QCA6174_PCI_REV_3_0 = 0x30,
62 enum qca6174_chip_id_rev {
63 QCA6174_HW_1_0_CHIP_ID_REV = 0,
64 QCA6174_HW_1_1_CHIP_ID_REV = 1,
65 QCA6174_HW_1_3_CHIP_ID_REV = 2,
66 QCA6174_HW_2_1_CHIP_ID_REV = 4,
67 QCA6174_HW_2_2_CHIP_ID_REV = 5,
68 QCA6174_HW_3_0_CHIP_ID_REV = 8,
69 QCA6174_HW_3_1_CHIP_ID_REV = 9,
70 QCA6174_HW_3_2_CHIP_ID_REV = 10,
73 enum qca9377_chip_id_rev {
74 QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
75 QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
78 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
79 #define QCA6174_HW_2_1_FW_FILE "firmware.bin"
80 #define QCA6174_HW_2_1_OTP_FILE "otp.bin"
81 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin"
82 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
84 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0"
85 #define QCA6174_HW_3_0_FW_FILE "firmware.bin"
86 #define QCA6174_HW_3_0_OTP_FILE "otp.bin"
87 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin"
88 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
90 /* QCA99X0 1.0 definitions (unsupported) */
91 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0
93 /* QCA99X0 2.0 definitions */
94 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000
95 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1
96 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0"
97 #define QCA99X0_HW_2_0_FW_FILE "firmware.bin"
98 #define QCA99X0_HW_2_0_OTP_FILE "otp.bin"
99 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
100 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
102 /* QCA9377 1.0 definitions */
103 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
104 #define QCA9377_HW_1_0_FW_FILE "firmware.bin"
105 #define QCA9377_HW_1_0_OTP_FILE "otp.bin"
106 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
107 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234
109 #define ATH10K_FW_API2_FILE "firmware-2.bin"
110 #define ATH10K_FW_API3_FILE "firmware-3.bin"
112 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
113 #define ATH10K_FW_API4_FILE "firmware-4.bin"
115 /* HTT id conflict fix for management frames over HTT */
116 #define ATH10K_FW_API5_FILE "firmware-5.bin"
118 #define ATH10K_FW_UTF_FILE "utf.bin"
119 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin"
121 /* includes also the null byte */
122 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
123 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD"
125 #define ATH10K_BOARD_API2_FILE "board-2.bin"
127 #define REG_DUMP_COUNT_QCA988X 60
129 #define QCA988X_CAL_DATA_LEN 2116
131 struct ath10k_fw_ie {
137 enum ath10k_fw_ie_type {
138 ATH10K_FW_IE_FW_VERSION = 0,
139 ATH10K_FW_IE_TIMESTAMP = 1,
140 ATH10K_FW_IE_FEATURES = 2,
141 ATH10K_FW_IE_FW_IMAGE = 3,
142 ATH10K_FW_IE_OTP_IMAGE = 4,
144 /* WMI "operations" interface version, 32 bit value. Supported from
145 * FW API 4 and above.
147 ATH10K_FW_IE_WMI_OP_VERSION = 5,
149 /* HTT "operations" interface version, 32 bit value. Supported from
150 * FW API 5 and above.
152 ATH10K_FW_IE_HTT_OP_VERSION = 6,
154 /* Code swap image for firmware binary */
155 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
158 enum ath10k_fw_wmi_op_version {
159 ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
161 ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
162 ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
163 ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
164 ATH10K_FW_WMI_OP_VERSION_TLV = 4,
165 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
166 ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
169 ATH10K_FW_WMI_OP_VERSION_MAX,
172 enum ath10k_fw_htt_op_version {
173 ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
175 ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
177 /* also used in 10.2 and 10.2.4 branches */
178 ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
180 ATH10K_FW_HTT_OP_VERSION_TLV = 3,
182 ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
185 ATH10K_FW_HTT_OP_VERSION_MAX,
188 enum ath10k_bd_ie_type {
189 /* contains sub IEs of enum ath10k_bd_ie_board_type */
190 ATH10K_BD_IE_BOARD = 0,
193 enum ath10k_bd_ie_board_type {
194 ATH10K_BD_IE_BOARD_NAME = 0,
195 ATH10K_BD_IE_BOARD_DATA = 1,
205 struct ath10k_hw_regs {
206 u32 rtc_state_cold_reset_mask;
207 u32 rtc_soc_base_address;
208 u32 rtc_wmac_base_address;
209 u32 soc_core_base_address;
210 u32 ce_wrapper_base_address;
211 u32 ce0_base_address;
212 u32 ce1_base_address;
213 u32 ce2_base_address;
214 u32 ce3_base_address;
215 u32 ce4_base_address;
216 u32 ce5_base_address;
217 u32 ce6_base_address;
218 u32 ce7_base_address;
219 u32 soc_reset_control_si0_rst_mask;
220 u32 soc_reset_control_ce_rst_mask;
221 u32 soc_chip_id_address;
222 u32 scratch_3_address;
223 u32 fw_indicator_address;
224 u32 pcie_local_base_address;
225 u32 ce_wrap_intr_sum_host_msi_lsb;
226 u32 ce_wrap_intr_sum_host_msi_mask;
227 u32 pcie_intr_fw_mask;
228 u32 pcie_intr_ce_mask_all;
229 u32 pcie_intr_clr_address;
232 extern const struct ath10k_hw_regs qca988x_regs;
233 extern const struct ath10k_hw_regs qca6174_regs;
234 extern const struct ath10k_hw_regs qca99x0_regs;
236 struct ath10k_hw_values {
237 u32 rtc_state_val_on;
239 u8 msi_assign_ce_max;
240 u8 num_target_ce_config_wlan;
241 u16 ce_desc_meta_data_mask;
242 u8 ce_desc_meta_data_lsb;
245 extern const struct ath10k_hw_values qca988x_values;
246 extern const struct ath10k_hw_values qca6174_values;
247 extern const struct ath10k_hw_values qca99x0_values;
249 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
250 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
252 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
253 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
254 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
255 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
257 /* Known pecularities:
258 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
259 * - raw have FCS, nwifi doesn't
260 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
261 * param, llc/snap) are aligned to 4byte boundaries each */
262 enum ath10k_hw_txrx_mode {
263 ATH10K_HW_TXRX_RAW = 0,
265 /* Native Wifi decap mode is used to align IP frames to 4-byte
266 * boundaries and avoid a very expensive re-alignment in mac80211.
268 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
269 ATH10K_HW_TXRX_ETHERNET = 2,
271 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
272 ATH10K_HW_TXRX_MGMT = 3,
275 enum ath10k_mcast2ucast_mode {
276 ATH10K_MCAST2UCAST_DISABLED = 0,
277 ATH10K_MCAST2UCAST_ENABLED = 1,
280 struct ath10k_pktlog_hdr {
289 struct ath10k_pktlog_10_4_hdr {
295 __le32 type_specific_data;
299 enum ath10k_hw_rate_ofdm {
300 ATH10K_HW_RATE_OFDM_48M = 0,
301 ATH10K_HW_RATE_OFDM_24M,
302 ATH10K_HW_RATE_OFDM_12M,
303 ATH10K_HW_RATE_OFDM_6M,
304 ATH10K_HW_RATE_OFDM_54M,
305 ATH10K_HW_RATE_OFDM_36M,
306 ATH10K_HW_RATE_OFDM_18M,
307 ATH10K_HW_RATE_OFDM_9M,
310 enum ath10k_hw_rate_cck {
311 ATH10K_HW_RATE_CCK_LP_11M = 0,
312 ATH10K_HW_RATE_CCK_LP_5_5M,
313 ATH10K_HW_RATE_CCK_LP_2M,
314 ATH10K_HW_RATE_CCK_LP_1M,
315 ATH10K_HW_RATE_CCK_SP_11M,
316 ATH10K_HW_RATE_CCK_SP_5_5M,
317 ATH10K_HW_RATE_CCK_SP_2M,
320 enum ath10k_hw_4addr_pad {
321 ATH10K_HW_4ADDR_PAD_AFTER,
322 ATH10K_HW_4ADDR_PAD_BEFORE,
325 /* Target specific defines for MAIN firmware */
326 #define TARGET_NUM_VDEVS 8
327 #define TARGET_NUM_PEER_AST 2
328 #define TARGET_NUM_WDS_ENTRIES 32
329 #define TARGET_DMA_BURST_SIZE 0
330 #define TARGET_MAC_AGGR_DELIM 0
331 #define TARGET_AST_SKID_LIMIT 16
332 #define TARGET_NUM_STATIONS 16
333 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
335 #define TARGET_NUM_OFFLOAD_PEERS 0
336 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
337 #define TARGET_NUM_PEER_KEYS 2
338 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
339 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
340 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
341 #define TARGET_RX_TIMEOUT_LO_PRI 100
342 #define TARGET_RX_TIMEOUT_HI_PRI 40
344 #define TARGET_SCAN_MAX_PENDING_REQS 4
345 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
346 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
347 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
348 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
349 #define TARGET_NUM_MCAST_GROUPS 0
350 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
351 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
352 #define TARGET_TX_DBG_LOG_SIZE 1024
353 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
354 #define TARGET_VOW_CONFIG 0
355 #define TARGET_NUM_MSDU_DESC (1024 + 400)
356 #define TARGET_MAX_FRAG_ENTRIES 0
358 /* Target specific defines for 10.X firmware */
359 #define TARGET_10X_NUM_VDEVS 16
360 #define TARGET_10X_NUM_PEER_AST 2
361 #define TARGET_10X_NUM_WDS_ENTRIES 32
362 #define TARGET_10X_DMA_BURST_SIZE 0
363 #define TARGET_10X_MAC_AGGR_DELIM 0
364 #define TARGET_10X_AST_SKID_LIMIT 128
365 #define TARGET_10X_NUM_STATIONS 128
366 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
367 (TARGET_10X_NUM_VDEVS))
368 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
369 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
370 #define TARGET_10X_NUM_PEER_KEYS 2
371 #define TARGET_10X_NUM_TIDS_MAX 256
372 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
373 (TARGET_10X_NUM_PEERS) * 2)
374 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
375 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
376 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
377 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
378 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
379 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
380 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
381 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
382 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
383 #define TARGET_10X_NUM_MCAST_GROUPS 0
384 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
385 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
386 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
387 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
388 #define TARGET_10X_VOW_CONFIG 0
389 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
390 #define TARGET_10X_MAX_FRAG_ENTRIES 0
392 /* 10.2 parameters */
393 #define TARGET_10_2_DMA_BURST_SIZE 0
395 /* Target specific defines for WMI-TLV firmware */
396 #define TARGET_TLV_NUM_VDEVS 4
397 #define TARGET_TLV_NUM_STATIONS 32
398 #define TARGET_TLV_NUM_PEERS 35
399 #define TARGET_TLV_NUM_TDLS_VDEVS 1
400 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
401 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
402 #define TARGET_TLV_NUM_WOW_PATTERNS 22
404 /* Diagnostic Window */
405 #define CE_DIAG_PIPE 7
407 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
409 /* Target specific defines for 10.4 firmware */
410 #define TARGET_10_4_NUM_VDEVS 16
411 #define TARGET_10_4_NUM_STATIONS 32
412 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \
413 (TARGET_10_4_NUM_VDEVS))
414 #define TARGET_10_4_ACTIVE_PEERS 0
416 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512
417 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50
418 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0
419 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0
420 #define TARGET_10_4_NUM_PEER_KEYS 2
421 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2)
422 #define TARGET_10_4_AST_SKID_LIMIT 32
423 #define TARGET_10_4_TX_CHAIN_MASK (BIT(0) | BIT(1) | \
425 #define TARGET_10_4_RX_CHAIN_MASK (BIT(0) | BIT(1) | \
428 /* 100 ms for video, best-effort, and background */
429 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100
431 /* 40 ms for voice */
432 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40
434 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
435 #define TARGET_10_4_SCAN_MAX_REQS 4
436 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3
437 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3
438 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8
440 /* Note: mcast to ucast is disabled by default */
441 #define TARGET_10_4_NUM_MCAST_GROUPS 0
442 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0
443 #define TARGET_10_4_MCAST2UCAST_MODE 0
445 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024
446 #define TARGET_10_4_NUM_WDS_ENTRIES 32
447 #define TARGET_10_4_DMA_BURST_SIZE 0
448 #define TARGET_10_4_MAC_AGGR_DELIM 0
449 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
450 #define TARGET_10_4_VOW_CONFIG 0
451 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3
452 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400)
453 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2
454 #define TARGET_10_4_MAX_PEER_EXT_STATS 16
455 #define TARGET_10_4_SMART_ANT_CAP 0
456 #define TARGET_10_4_BK_MIN_FREE 0
457 #define TARGET_10_4_BE_MIN_FREE 0
458 #define TARGET_10_4_VI_MIN_FREE 0
459 #define TARGET_10_4_VO_MIN_FREE 0
460 #define TARGET_10_4_RX_BATCH_MODE 1
461 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0
462 #define TARGET_10_4_ATF_CONFIG 0
463 #define TARGET_10_4_IPHDR_PAD_CONFIG 1
464 #define TARGET_10_4_QWRAP_CONFIG 0
466 /* Number of Copy Engines supported */
467 #define CE_COUNT ar->hw_values->ce_count
470 * Granted MSIs are assigned as follows:
471 * Firmware uses the first
472 * Remaining MSIs, if any, are used by Copy Engines
473 * This mapping is known to both Target firmware and Host software.
474 * It may be changed as long as Host and Target are kept in sync.
476 /* MSI for firmware (errors, etc.) */
477 #define MSI_ASSIGN_FW 0
479 /* MSIs for Copy Engines */
480 #define MSI_ASSIGN_CE_INITIAL 1
481 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max
484 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on
486 #define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask
487 #define RTC_STATE_V_LSB 0
488 #define RTC_STATE_V_MASK 0x00000007
489 #define RTC_STATE_ADDRESS 0x0000
490 #define PCIE_SOC_WAKE_V_MASK 0x00000001
491 #define PCIE_SOC_WAKE_ADDRESS 0x0004
492 #define PCIE_SOC_WAKE_RESET 0x00000000
493 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
495 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
496 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
497 #define MAC_COEX_BASE_ADDRESS 0x00006000
498 #define BT_COEX_BASE_ADDRESS 0x00007000
499 #define SOC_PCIE_BASE_ADDRESS 0x00008000
500 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
501 #define WLAN_UART_BASE_ADDRESS 0x0000c000
502 #define WLAN_SI_BASE_ADDRESS 0x00010000
503 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
504 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
505 #define WLAN_MAC_BASE_ADDRESS 0x00020000
506 #define EFUSE_BASE_ADDRESS 0x00030000
507 #define FPGA_REG_BASE_ADDRESS 0x00039000
508 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
509 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
510 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address
511 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address
512 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address
513 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address
514 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address
515 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address
516 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address
517 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address
518 #define DBI_BASE_ADDRESS 0x00060000
519 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
520 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address
522 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
523 #define SOC_RESET_CONTROL_OFFSET 0x00000000
524 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
525 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
526 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
527 #define SOC_CPU_CLOCK_OFFSET 0x00000020
528 #define SOC_CPU_CLOCK_STANDARD_LSB 0
529 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
530 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
531 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
532 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
533 #define SOC_LPO_CAL_OFFSET 0x000000e0
534 #define SOC_LPO_CAL_ENABLE_LSB 20
535 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
536 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
537 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
539 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
540 #define SOC_CHIP_ID_REV_LSB 8
541 #define SOC_CHIP_ID_REV_MASK 0x00000f00
543 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
544 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
545 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
546 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
548 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
549 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
550 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
551 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
552 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
553 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
554 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
555 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
557 #define CLOCK_GPIO_OFFSET 0xffffffff
558 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
559 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
561 #define SI_CONFIG_OFFSET 0x00000000
562 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
563 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
564 #define SI_CONFIG_I2C_LSB 16
565 #define SI_CONFIG_I2C_MASK 0x00010000
566 #define SI_CONFIG_POS_SAMPLE_LSB 7
567 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
568 #define SI_CONFIG_INACTIVE_DATA_LSB 5
569 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
570 #define SI_CONFIG_INACTIVE_CLK_LSB 4
571 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
572 #define SI_CONFIG_DIVIDER_LSB 0
573 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
574 #define SI_CS_OFFSET 0x00000004
575 #define SI_CS_DONE_ERR_MASK 0x00000400
576 #define SI_CS_DONE_INT_MASK 0x00000200
577 #define SI_CS_START_LSB 8
578 #define SI_CS_START_MASK 0x00000100
579 #define SI_CS_RX_CNT_LSB 4
580 #define SI_CS_RX_CNT_MASK 0x000000f0
581 #define SI_CS_TX_CNT_LSB 0
582 #define SI_CS_TX_CNT_MASK 0x0000000f
584 #define SI_TX_DATA0_OFFSET 0x00000008
585 #define SI_TX_DATA1_OFFSET 0x0000000c
586 #define SI_RX_DATA0_OFFSET 0x00000010
587 #define SI_RX_DATA1_OFFSET 0x00000014
589 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
590 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
591 #define CORE_CTRL_ADDRESS 0x0000
592 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
593 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
594 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address
595 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
596 #define CPU_INTR_ADDRESS 0x0010
598 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
600 /* Firmware indications to the Host via SCRATCH_3 register. */
601 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address
602 #define FW_IND_EVENT_PENDING 1
603 #define FW_IND_INITIALIZED 2
605 /* HOST_REG interrupt from firmware */
606 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask
607 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all
609 #define DRAM_BASE_ADDRESS 0x00400000
611 #define PCIE_BAR_REG_ADDRESS 0x40030
615 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
616 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
617 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
618 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
619 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
620 #define RESET_CONTROL_MBOX_RST_MASK MISSING
621 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
622 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
623 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
624 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
625 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
626 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
627 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
628 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
629 #define LOCAL_SCRATCH_OFFSET 0x18
630 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
631 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
632 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
633 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
634 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
635 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
636 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
637 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
638 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
639 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
640 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
641 #define MBOX_BASE_ADDRESS MISSING
642 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
643 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
644 #define INT_STATUS_ENABLE_CPU_LSB MISSING
645 #define INT_STATUS_ENABLE_CPU_MASK MISSING
646 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
647 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
648 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
649 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
650 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
651 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
652 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
653 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
654 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
655 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
656 #define INT_STATUS_ENABLE_ADDRESS MISSING
657 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
658 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
659 #define HOST_INT_STATUS_ADDRESS MISSING
660 #define CPU_INT_STATUS_ADDRESS MISSING
661 #define ERROR_INT_STATUS_ADDRESS MISSING
662 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
663 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
664 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
665 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
666 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
667 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
668 #define COUNT_DEC_ADDRESS MISSING
669 #define HOST_INT_STATUS_CPU_MASK MISSING
670 #define HOST_INT_STATUS_CPU_LSB MISSING
671 #define HOST_INT_STATUS_ERROR_MASK MISSING
672 #define HOST_INT_STATUS_ERROR_LSB MISSING
673 #define HOST_INT_STATUS_COUNTER_MASK MISSING
674 #define HOST_INT_STATUS_COUNTER_LSB MISSING
675 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
676 #define WINDOW_DATA_ADDRESS MISSING
677 #define WINDOW_READ_ADDR_ADDRESS MISSING
678 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
680 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)