2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/if_ether.h>
23 #include <linux/spinlock.h>
24 #include <net/mac80211.h>
27 * The key cache is used for h/w cipher state and also for
28 * tracking station state such as the current tx antenna.
29 * We also setup a mapping table between key cache slot indices
30 * and station state to short-circuit node lookups on rx.
31 * Different parts have different size key caches. We handle
32 * up to ATH_KEYMAX entries (could dynamically allocate state).
34 #define ATH_KEYMAX 128 /* max key cache size we handle */
36 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
40 unsigned int longcal_timer;
41 unsigned int shortcal_timer;
42 unsigned int resetcal_timer;
43 unsigned int checkani_timer;
44 struct timer_list timer;
47 struct ath_cycle_counters {
54 enum ath_device_state {
65 struct reg_dmn_pair_mapping {
71 struct ath_regulatory {
77 struct reg_dmn_pair_mapping *regpair;
81 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
82 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
89 u8 kv_val[16]; /* TK */
90 u8 kv_mic[8]; /* Michael MIC key */
91 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
92 * supports both MIC keys in the same key cache entry;
93 * in that case, kv_mic is the RX key) */
98 ATH_CIPHER_AES_OCB = 1,
99 ATH_CIPHER_AES_CCM = 2,
107 * struct ath_ops - Register read/write operations
109 * @read: Register read
110 * @multi_read: Multiple register read
111 * @write: Register write
112 * @enable_write_buffer: Enable multiple register writes
113 * @write_flush: flush buffered register writes and disable buffering
116 unsigned int (*read)(void *, u32 reg_offset);
117 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
118 void (*write)(void *, u32 val, u32 reg_offset);
119 void (*enable_write_buffer)(void *);
120 void (*write_flush) (void *);
121 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
130 struct ieee80211_hw *hw;
132 enum ath_device_state state;
138 u8 macaddr[ETH_ALEN];
139 u8 curbssid[ETH_ALEN];
140 u8 bssidmask[ETH_ALEN];
145 DECLARE_BITMAP(keymap, ATH_KEYMAX);
146 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
147 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
148 enum ath_crypt_caps crypt_caps;
150 unsigned int clockrate;
153 struct ath_cycle_counters cc_ani;
154 struct ath_cycle_counters cc_survey;
156 struct ath_regulatory regulatory;
157 struct ath_regulatory reg_world_copy;
158 const struct ath_ops *ops;
159 const struct ath_bus_ops *bus_ops;
163 bool bt_ant_diversity;
168 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
171 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);
173 void ath_hw_setbssidmask(struct ath_common *common);
174 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
175 int ath_key_config(struct ath_common *common,
176 struct ieee80211_vif *vif,
177 struct ieee80211_sta *sta,
178 struct ieee80211_key_conf *key);
179 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
180 void ath_hw_cycle_counters_update(struct ath_common *common);
181 int32_t ath_hw_get_listen_time(struct ath_common *common);
184 void ath_printk(const char *level, const struct ath_common *common,
185 const char *fmt, ...);
187 #define ath_emerg(common, fmt, ...) \
188 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
189 #define ath_alert(common, fmt, ...) \
190 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
191 #define ath_crit(common, fmt, ...) \
192 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
193 #define ath_err(common, fmt, ...) \
194 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
195 #define ath_warn(common, fmt, ...) \
196 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
197 #define ath_notice(common, fmt, ...) \
198 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
199 #define ath_info(common, fmt, ...) \
200 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
203 * enum ath_debug_level - atheros wireless debug level
205 * @ATH_DBG_RESET: reset processing
206 * @ATH_DBG_QUEUE: hardware queue management
207 * @ATH_DBG_EEPROM: eeprom processing
208 * @ATH_DBG_CALIBRATE: periodic calibration
209 * @ATH_DBG_INTERRUPT: interrupt processing
210 * @ATH_DBG_REGULATORY: regulatory processing
211 * @ATH_DBG_ANI: adaptive noise immunitive processing
212 * @ATH_DBG_XMIT: basic xmit operation
213 * @ATH_DBG_BEACON: beacon handling
214 * @ATH_DBG_CONFIG: configuration of the hardware
215 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
216 * @ATH_DBG_PS: power save processing
217 * @ATH_DBG_HWTIMER: hardware timer handling
218 * @ATH_DBG_BTCOEX: bluetooth coexistance
219 * @ATH_DBG_BSTUCK: stuck beacons
220 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
221 * used exclusively for WLAN-BT coexistence starting from
223 * @ATH_DBG_DFS: radar datection
224 * @ATH_DBG_WOW: Wake on Wireless
225 * @ATH_DBG_ANY: enable all debugging
227 * The debug level is used to control the amount and type of debugging output
228 * we want to see. Each driver has its own method for enabling debugging and
229 * modifying debug level states -- but this is typically done through a
230 * module parameter 'debug' along with a respective 'debug' debugfs file
234 ATH_DBG_RESET = 0x00000001,
235 ATH_DBG_QUEUE = 0x00000002,
236 ATH_DBG_EEPROM = 0x00000004,
237 ATH_DBG_CALIBRATE = 0x00000008,
238 ATH_DBG_INTERRUPT = 0x00000010,
239 ATH_DBG_REGULATORY = 0x00000020,
240 ATH_DBG_ANI = 0x00000040,
241 ATH_DBG_XMIT = 0x00000080,
242 ATH_DBG_BEACON = 0x00000100,
243 ATH_DBG_CONFIG = 0x00000200,
244 ATH_DBG_FATAL = 0x00000400,
245 ATH_DBG_PS = 0x00000800,
246 ATH_DBG_BTCOEX = 0x00001000,
247 ATH_DBG_WMI = 0x00002000,
248 ATH_DBG_BSTUCK = 0x00004000,
249 ATH_DBG_MCI = 0x00008000,
250 ATH_DBG_DFS = 0x00010000,
251 ATH_DBG_WOW = 0x00020000,
252 ATH_DBG_ANY = 0xffffffff
255 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
257 #ifdef CONFIG_ATH_DEBUG
259 #define ath_dbg(common, dbg_mask, fmt, ...) \
261 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
262 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
265 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
266 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
270 static inline __attribute__ ((format (printf, 3, 4)))
271 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
272 const char *fmt, ...)
275 #define ath_dbg(common, dbg_mask, fmt, ...) \
276 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
278 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
279 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \
280 int __ret_warn_once = !!(foo); \
281 unlikely(__ret_warn_once); \
284 #endif /* CONFIG_ATH_DEBUG */
286 /** Returns string describing opmode, or NULL if unknown mode. */
287 #ifdef CONFIG_ATH_DEBUG
288 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
290 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)