3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
8 * and used with permission.
10 * Much thanks to Infineon-ADMtek for their support of this driver.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. See README and COPYING for
18 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <linux/crc32.h>
25 #include <linux/eeprom_93cx6.h>
26 #include <net/mac80211.h>
30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
33 MODULE_SUPPORTED_DEVICE("ADM8211");
34 MODULE_LICENSE("GPL");
36 static unsigned int tx_ring_size __read_mostly = 16;
37 static unsigned int rx_ring_size __read_mostly = 16;
39 module_param(tx_ring_size, uint, 0);
40 module_param(rx_ring_size, uint, 0);
42 static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
44 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
45 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
46 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
47 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
51 static struct ieee80211_rate adm8211_rates[] = {
52 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
53 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
54 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
55 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
56 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
59 static const struct ieee80211_channel adm8211_channels[] = {
60 { .center_freq = 2412},
61 { .center_freq = 2417},
62 { .center_freq = 2422},
63 { .center_freq = 2427},
64 { .center_freq = 2432},
65 { .center_freq = 2437},
66 { .center_freq = 2442},
67 { .center_freq = 2447},
68 { .center_freq = 2452},
69 { .center_freq = 2457},
70 { .center_freq = 2462},
71 { .center_freq = 2467},
72 { .center_freq = 2472},
73 { .center_freq = 2484},
77 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
79 struct adm8211_priv *priv = eeprom->data;
80 u32 reg = ADM8211_CSR_READ(SPR);
82 eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
83 eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
84 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
85 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
88 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
90 struct adm8211_priv *priv = eeprom->data;
91 u32 reg = 0x4000 | ADM8211_SPR_SRS;
93 if (eeprom->reg_data_in)
94 reg |= ADM8211_SPR_SDI;
95 if (eeprom->reg_data_out)
96 reg |= ADM8211_SPR_SDO;
97 if (eeprom->reg_data_clock)
98 reg |= ADM8211_SPR_SCLK;
99 if (eeprom->reg_chip_select)
100 reg |= ADM8211_SPR_SCS;
102 ADM8211_CSR_WRITE(SPR, reg);
103 ADM8211_CSR_READ(SPR); /* eeprom_delay */
106 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
108 struct adm8211_priv *priv = dev->priv;
109 unsigned int words, i;
110 struct ieee80211_chan_range chan_range;
112 struct eeprom_93cx6 eeprom = {
114 .register_read = adm8211_eeprom_register_read,
115 .register_write = adm8211_eeprom_register_write
118 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
119 /* 256 * 16-bit = 512 bytes */
120 eeprom.width = PCI_EEPROM_WIDTH_93C66;
123 /* 64 * 16-bit = 128 bytes */
124 eeprom.width = PCI_EEPROM_WIDTH_93C46;
128 priv->eeprom_len = words * 2;
129 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
133 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
135 cr49 = le16_to_cpu(priv->eeprom->cr49);
136 priv->rf_type = (cr49 >> 3) & 0x7;
137 switch (priv->rf_type) {
138 case ADM8211_TYPE_INTERSIL:
139 case ADM8211_TYPE_RFMD:
140 case ADM8211_TYPE_MARVEL:
141 case ADM8211_TYPE_AIROHA:
142 case ADM8211_TYPE_ADMTEK:
146 if (priv->pdev->revision < ADM8211_REV_CA)
147 priv->rf_type = ADM8211_TYPE_RFMD;
149 priv->rf_type = ADM8211_TYPE_AIROHA;
151 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
152 pci_name(priv->pdev), (cr49 >> 3) & 0x7);
155 priv->bbp_type = cr49 & 0x7;
156 switch (priv->bbp_type) {
157 case ADM8211_TYPE_INTERSIL:
158 case ADM8211_TYPE_RFMD:
159 case ADM8211_TYPE_MARVEL:
160 case ADM8211_TYPE_AIROHA:
161 case ADM8211_TYPE_ADMTEK:
164 if (priv->pdev->revision < ADM8211_REV_CA)
165 priv->bbp_type = ADM8211_TYPE_RFMD;
167 priv->bbp_type = ADM8211_TYPE_ADMTEK;
169 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
170 pci_name(priv->pdev), cr49 >> 3);
173 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
174 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
175 pci_name(priv->pdev), priv->eeprom->country_code);
177 chan_range = cranges[2];
179 chan_range = cranges[priv->eeprom->country_code];
181 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
182 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
184 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
186 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
187 priv->band.channels = priv->channels;
188 priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
189 priv->band.bitrates = adm8211_rates;
190 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
192 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
193 if (i < chan_range.min || i > chan_range.max)
194 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
196 switch (priv->eeprom->specific_bbptype) {
197 case ADM8211_BBP_RFMD3000:
198 case ADM8211_BBP_RFMD3002:
199 case ADM8211_BBP_ADM8011:
200 priv->specific_bbptype = priv->eeprom->specific_bbptype;
204 if (priv->pdev->revision < ADM8211_REV_CA)
205 priv->specific_bbptype = ADM8211_BBP_RFMD3000;
207 priv->specific_bbptype = ADM8211_BBP_ADM8011;
209 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
210 pci_name(priv->pdev), priv->eeprom->specific_bbptype);
213 switch (priv->eeprom->specific_rftype) {
214 case ADM8211_RFMD2948:
215 case ADM8211_RFMD2958:
216 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
217 case ADM8211_MAX2820:
218 case ADM8211_AL2210L:
219 priv->transceiver_type = priv->eeprom->specific_rftype;
223 if (priv->pdev->revision == ADM8211_REV_BA)
224 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
225 else if (priv->pdev->revision == ADM8211_REV_CA)
226 priv->transceiver_type = ADM8211_AL2210L;
227 else if (priv->pdev->revision == ADM8211_REV_AB)
228 priv->transceiver_type = ADM8211_RFMD2948;
230 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
231 pci_name(priv->pdev), priv->eeprom->specific_rftype);
236 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
237 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
238 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
243 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
246 struct adm8211_priv *priv = dev->priv;
248 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
249 (priv->pdev->revision < ADM8211_REV_BA ?
250 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
251 ADM8211_CSR_READ(WEPCTL);
254 ADM8211_CSR_WRITE(WESK, data);
255 ADM8211_CSR_READ(WESK);
259 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
260 unsigned int addr, u8 *buf,
263 struct adm8211_priv *priv = dev->priv;
264 u32 reg = ADM8211_CSR_READ(WEPCTL);
267 if (priv->pdev->revision < ADM8211_REV_BA) {
268 for (i = 0; i < len; i += 2) {
269 u16 val = buf[i] | (buf[i + 1] << 8);
270 adm8211_write_sram(dev, addr + i / 2, val);
273 for (i = 0; i < len; i += 4) {
274 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
275 (buf[i + 2] << 16) | (buf[i + 3] << 24);
276 adm8211_write_sram(dev, addr + i / 4, val);
280 ADM8211_CSR_WRITE(WEPCTL, reg);
283 static void adm8211_clear_sram(struct ieee80211_hw *dev)
285 struct adm8211_priv *priv = dev->priv;
286 u32 reg = ADM8211_CSR_READ(WEPCTL);
289 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
290 adm8211_write_sram(dev, addr, 0);
292 ADM8211_CSR_WRITE(WEPCTL, reg);
295 static int adm8211_get_stats(struct ieee80211_hw *dev,
296 struct ieee80211_low_level_stats *stats)
298 struct adm8211_priv *priv = dev->priv;
300 memcpy(stats, &priv->stats, sizeof(*stats));
305 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
307 struct adm8211_priv *priv = dev->priv;
308 unsigned int dirty_tx;
310 spin_lock(&priv->lock);
312 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
313 unsigned int entry = dirty_tx % priv->tx_ring_size;
314 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
315 struct ieee80211_tx_info *txi;
316 struct adm8211_tx_ring_info *info;
319 if (status & TDES0_CONTROL_OWN ||
320 !(status & TDES0_CONTROL_DONE))
323 info = &priv->tx_buffers[entry];
325 txi = IEEE80211_SKB_CB(skb);
327 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
329 pci_unmap_single(priv->pdev, info->mapping,
330 info->skb->len, PCI_DMA_TODEVICE);
332 ieee80211_tx_info_clear_status(txi);
334 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
335 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
336 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
337 !(status & TDES0_STATUS_ES))
338 txi->flags |= IEEE80211_TX_STAT_ACK;
340 ieee80211_tx_status_irqsafe(dev, skb);
345 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
346 ieee80211_wake_queue(dev, 0);
348 priv->dirty_tx = dirty_tx;
349 spin_unlock(&priv->lock);
353 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
355 struct adm8211_priv *priv = dev->priv;
356 unsigned int entry = priv->cur_rx % priv->rx_ring_size;
359 struct sk_buff *skb, *newskb;
360 unsigned int limit = priv->rx_ring_size;
363 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
367 status = le32_to_cpu(priv->rx_ring[entry].status);
368 rate = (status & RDES0_STATUS_RXDR) >> 12;
369 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
372 pktlen = status & RDES0_STATUS_FL;
373 if (pktlen > RX_PKT_SIZE) {
375 printk(KERN_DEBUG "%s: frame too long (%d)\n",
376 wiphy_name(dev->wiphy), pktlen);
377 pktlen = RX_PKT_SIZE;
380 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
381 skb = NULL; /* old buffer will be reused */
382 /* TODO: update RX error stats */
383 /* TODO: check RDES0_STATUS_CRC*E */
384 } else if (pktlen < RX_COPY_BREAK) {
385 skb = dev_alloc_skb(pktlen);
387 pci_dma_sync_single_for_cpu(
389 priv->rx_buffers[entry].mapping,
390 pktlen, PCI_DMA_FROMDEVICE);
391 memcpy(skb_put(skb, pktlen),
392 skb_tail_pointer(priv->rx_buffers[entry].skb),
394 pci_dma_sync_single_for_device(
396 priv->rx_buffers[entry].mapping,
397 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
400 newskb = dev_alloc_skb(RX_PKT_SIZE);
402 skb = priv->rx_buffers[entry].skb;
403 skb_put(skb, pktlen);
406 priv->rx_buffers[entry].mapping,
407 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
408 priv->rx_buffers[entry].skb = newskb;
409 priv->rx_buffers[entry].mapping =
410 pci_map_single(priv->pdev,
411 skb_tail_pointer(newskb),
416 /* TODO: update rx dropped stats */
419 priv->rx_ring[entry].buffer1 =
420 cpu_to_le32(priv->rx_buffers[entry].mapping);
423 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
425 priv->rx_ring[entry].length =
426 cpu_to_le32(RX_PKT_SIZE |
427 (entry == priv->rx_ring_size - 1 ?
428 RDES1_CONTROL_RER : 0));
431 struct ieee80211_rx_status rx_status = {0};
433 if (priv->pdev->revision < ADM8211_REV_CA)
434 rx_status.signal = rssi;
436 rx_status.signal = 100 - rssi;
438 rx_status.rate_idx = rate;
440 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
441 rx_status.band = IEEE80211_BAND_2GHZ;
443 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
444 ieee80211_rx_irqsafe(dev, skb);
447 entry = (++priv->cur_rx) % priv->rx_ring_size;
450 /* TODO: check LPC and update stats? */
454 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
456 #define ADM8211_INT(x) \
458 if (unlikely(stsr & ADM8211_STSR_ ## x)) \
459 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
462 struct ieee80211_hw *dev = dev_id;
463 struct adm8211_priv *priv = dev->priv;
464 u32 stsr = ADM8211_CSR_READ(STSR);
465 ADM8211_CSR_WRITE(STSR, stsr);
466 if (stsr == 0xffffffff)
469 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
472 if (stsr & ADM8211_STSR_RCI)
473 adm8211_interrupt_rci(dev);
474 if (stsr & ADM8211_STSR_TCI)
475 adm8211_interrupt_tci(dev);
500 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
501 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
502 u16 addr, u32 value) { \
503 struct adm8211_priv *priv = dev->priv; \
509 bitbuf = (value << v_shift) | (addr << a_shift); \
511 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
512 ADM8211_CSR_READ(SYNRF); \
513 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
514 ADM8211_CSR_READ(SYNRF); \
517 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
518 ADM8211_CSR_READ(SYNRF); \
521 for (i = 0; i <= bits; i++) { \
522 if (bitbuf & (1 << (bits - i))) \
523 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
525 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
527 ADM8211_CSR_WRITE(SYNRF, reg); \
528 ADM8211_CSR_READ(SYNRF); \
530 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
531 ADM8211_CSR_READ(SYNRF); \
532 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
533 ADM8211_CSR_READ(SYNRF); \
536 if (postwrite == 1) { \
537 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
538 ADM8211_CSR_READ(SYNRF); \
540 if (postwrite == 2) { \
541 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
542 ADM8211_CSR_READ(SYNRF); \
545 ADM8211_CSR_WRITE(SYNRF, 0); \
546 ADM8211_CSR_READ(SYNRF); \
549 WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
550 WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
551 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
552 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
556 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
558 struct adm8211_priv *priv = dev->priv;
559 unsigned int timeout;
563 while (timeout > 0) {
564 reg = ADM8211_CSR_READ(BBPCTL);
565 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
572 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
573 " prewrite (reg=0x%08x)\n",
574 wiphy_name(dev->wiphy), addr, data, reg);
578 switch (priv->bbp_type) {
579 case ADM8211_TYPE_INTERSIL:
580 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
582 case ADM8211_TYPE_RFMD:
583 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
586 case ADM8211_TYPE_ADMTEK:
587 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
591 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
593 ADM8211_CSR_WRITE(BBPCTL, reg);
596 while (timeout > 0) {
597 reg = ADM8211_CSR_READ(BBPCTL);
598 if (!(reg & ADM8211_BBPCTL_WR))
605 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
607 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
608 " postwrite (reg=0x%08x)\n",
609 wiphy_name(dev->wiphy), addr, data, reg);
616 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
618 static const u32 adm8211_rfmd2958_reg5[] =
619 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
620 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
621 static const u32 adm8211_rfmd2958_reg6[] =
622 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
623 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
625 struct adm8211_priv *priv = dev->priv;
626 u8 ant_power = priv->ant_power > 0x3F ?
627 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
628 u8 tx_power = priv->tx_power > 0x3F ?
629 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
630 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
631 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
632 u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
633 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
638 /* Program synthesizer to new channel */
639 switch (priv->transceiver_type) {
640 case ADM8211_RFMD2958:
641 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
642 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
643 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
645 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
646 adm8211_rfmd2958_reg5[chan - 1]);
647 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
648 adm8211_rfmd2958_reg6[chan - 1]);
651 case ADM8211_RFMD2948:
652 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
653 SI4126_MAIN_XINDIV2);
654 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
655 SI4126_POWERDOWN_PDIB |
656 SI4126_POWERDOWN_PDRB);
657 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
658 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
660 2110 : (2033 + (chan * 5))));
661 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
662 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
663 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
666 case ADM8211_MAX2820:
667 adm8211_rf_write_syn_max2820(dev, 0x3,
668 (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
671 case ADM8211_AL2210L:
672 adm8211_rf_write_syn_al2210l(dev, 0x0,
673 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
677 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
678 wiphy_name(dev->wiphy), priv->transceiver_type);
683 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
685 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
686 /* TODO: remove if SMC 2635W doesn't need this */
687 if (priv->transceiver_type == ADM8211_RFMD2948) {
688 reg = ADM8211_CSR_READ(GPIO);
690 reg |= ADM8211_CSR_GPIO_EN0;
692 reg |= ADM8211_CSR_GPIO_O0;
693 ADM8211_CSR_WRITE(GPIO, reg);
696 if (priv->transceiver_type == ADM8211_RFMD2958) {
698 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
699 /* set PCNT1 P_DESIRED/MID_BIAS */
700 reg = le16_to_cpu(priv->eeprom->cr49);
703 reg |= ant_power << 9;
704 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
705 /* set TXRX TX_GAIN */
706 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
707 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
709 reg = ADM8211_CSR_READ(PLCPHD);
711 reg |= tx_power << 18;
712 ADM8211_CSR_WRITE(PLCPHD, reg);
715 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
716 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
717 ADM8211_CSR_READ(SYNRF);
721 if (priv->transceiver_type != ADM8211_RFMD2958)
722 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
724 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
725 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
726 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
727 priv->eeprom->cr28 : 0);
728 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
730 ADM8211_CSR_WRITE(SYNRF, 0);
732 /* Nothing to do for ADMtek BBP */
733 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
734 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
735 wiphy_name(dev->wiphy), priv->bbp_type);
739 /* update current channel for adhoc (and maybe AP mode) */
740 reg = ADM8211_CSR_READ(CAP0);
743 ADM8211_CSR_WRITE(CAP0, reg);
748 static void adm8211_update_mode(struct ieee80211_hw *dev)
750 struct adm8211_priv *priv = dev->priv;
754 priv->soft_rx_crc = 0;
755 switch (priv->mode) {
756 case NL80211_IFTYPE_STATION:
757 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
758 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
760 case NL80211_IFTYPE_ADHOC:
761 priv->nar &= ~ADM8211_NAR_PR;
762 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
764 /* don't trust the error bits on rev 0x20 and up in adhoc */
765 if (priv->pdev->revision >= ADM8211_REV_BA)
766 priv->soft_rx_crc = 1;
768 case NL80211_IFTYPE_MONITOR:
769 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
770 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
777 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
779 struct adm8211_priv *priv = dev->priv;
781 switch (priv->transceiver_type) {
782 case ADM8211_RFMD2958:
783 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
784 /* comments taken from ADMtek vendor driver */
786 /* Reset RF2958 after power on */
787 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
788 /* Initialize RF VCO Core Bias to maximum */
789 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
790 /* Initialize IF PLL */
791 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
792 /* Initialize IF PLL Coarse Tuning */
793 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
794 /* Initialize RF PLL */
795 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
796 /* Initialize RF PLL Coarse Tuning */
797 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
798 /* Initialize TX gain and filter BW (R9) */
799 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
800 (priv->transceiver_type == ADM8211_RFMD2958 ?
802 /* Initialize CAL register */
803 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
806 case ADM8211_MAX2820:
807 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
808 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
809 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
810 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
811 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
814 case ADM8211_AL2210L:
815 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
816 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
817 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
818 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
819 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
820 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
821 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
822 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
823 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
824 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
825 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
826 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
829 case ADM8211_RFMD2948:
835 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
837 struct adm8211_priv *priv = dev->priv;
840 /* write addresses */
841 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
842 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
843 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
844 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
845 } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
846 priv->bbp_type == ADM8211_TYPE_ADMTEK) {
847 /* check specific BBP type */
848 switch (priv->specific_bbptype) {
849 case ADM8211_BBP_RFMD3000:
850 case ADM8211_BBP_RFMD3002:
851 ADM8211_CSR_WRITE(MMIWA, 0x00009101);
852 ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
855 case ADM8211_BBP_ADM8011:
856 ADM8211_CSR_WRITE(MMIWA, 0x00008903);
857 ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
859 reg = ADM8211_CSR_READ(BBPCTL);
860 reg &= ~ADM8211_BBPCTL_TYPE;
862 ADM8211_CSR_WRITE(BBPCTL, reg);
866 switch (priv->pdev->revision) {
868 if (priv->transceiver_type == ADM8211_RFMD2958 ||
869 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
870 priv->transceiver_type == ADM8211_RFMD2948)
871 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
872 else if (priv->transceiver_type == ADM8211_MAX2820 ||
873 priv->transceiver_type == ADM8211_AL2210L)
874 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
878 reg = ADM8211_CSR_READ(MMIRD1);
881 ADM8211_CSR_WRITE(MMIRD1, reg);
887 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
892 ADM8211_CSR_WRITE(MACTEST, 0x800);
895 adm8211_hw_init_syn(dev);
897 /* Set RF Power control IF pin to PE1+PHYRST# */
898 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
899 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
900 ADM8211_CSR_READ(SYNRF);
904 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
909 * 15: 50 (chan 1..13; chan 14: d0)
913 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
914 /* antenna selection: diversity */
915 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
916 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
917 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
918 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
920 if (priv->eeprom->major_version < 2) {
921 adm8211_write_bbp(dev, 0x1c, 0x00);
922 adm8211_write_bbp(dev, 0x1d, 0x80);
924 if (priv->pdev->revision == ADM8211_REV_BA)
925 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
927 adm8211_write_bbp(dev, 0x1c, 0x00);
929 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
931 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
933 adm8211_write_bbp(dev, 0x00, 0xFF);
934 /* antenna selection: diversity */
935 adm8211_write_bbp(dev, 0x07, 0x0A);
937 /* TODO: find documentation for this */
938 switch (priv->transceiver_type) {
939 case ADM8211_RFMD2958:
940 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
941 adm8211_write_bbp(dev, 0x00, 0x00);
942 adm8211_write_bbp(dev, 0x01, 0x00);
943 adm8211_write_bbp(dev, 0x02, 0x00);
944 adm8211_write_bbp(dev, 0x03, 0x00);
945 adm8211_write_bbp(dev, 0x06, 0x0f);
946 adm8211_write_bbp(dev, 0x09, 0x00);
947 adm8211_write_bbp(dev, 0x0a, 0x00);
948 adm8211_write_bbp(dev, 0x0b, 0x00);
949 adm8211_write_bbp(dev, 0x0c, 0x00);
950 adm8211_write_bbp(dev, 0x0f, 0xAA);
951 adm8211_write_bbp(dev, 0x10, 0x8c);
952 adm8211_write_bbp(dev, 0x11, 0x43);
953 adm8211_write_bbp(dev, 0x18, 0x40);
954 adm8211_write_bbp(dev, 0x20, 0x23);
955 adm8211_write_bbp(dev, 0x21, 0x02);
956 adm8211_write_bbp(dev, 0x22, 0x28);
957 adm8211_write_bbp(dev, 0x23, 0x30);
958 adm8211_write_bbp(dev, 0x24, 0x2d);
959 adm8211_write_bbp(dev, 0x28, 0x35);
960 adm8211_write_bbp(dev, 0x2a, 0x8c);
961 adm8211_write_bbp(dev, 0x2b, 0x81);
962 adm8211_write_bbp(dev, 0x2c, 0x44);
963 adm8211_write_bbp(dev, 0x2d, 0x0A);
964 adm8211_write_bbp(dev, 0x29, 0x40);
965 adm8211_write_bbp(dev, 0x60, 0x08);
966 adm8211_write_bbp(dev, 0x64, 0x01);
969 case ADM8211_MAX2820:
970 adm8211_write_bbp(dev, 0x00, 0x00);
971 adm8211_write_bbp(dev, 0x01, 0x00);
972 adm8211_write_bbp(dev, 0x02, 0x00);
973 adm8211_write_bbp(dev, 0x03, 0x00);
974 adm8211_write_bbp(dev, 0x06, 0x0f);
975 adm8211_write_bbp(dev, 0x09, 0x05);
976 adm8211_write_bbp(dev, 0x0a, 0x02);
977 adm8211_write_bbp(dev, 0x0b, 0x00);
978 adm8211_write_bbp(dev, 0x0c, 0x0f);
979 adm8211_write_bbp(dev, 0x0f, 0x55);
980 adm8211_write_bbp(dev, 0x10, 0x8d);
981 adm8211_write_bbp(dev, 0x11, 0x43);
982 adm8211_write_bbp(dev, 0x18, 0x4a);
983 adm8211_write_bbp(dev, 0x20, 0x20);
984 adm8211_write_bbp(dev, 0x21, 0x02);
985 adm8211_write_bbp(dev, 0x22, 0x23);
986 adm8211_write_bbp(dev, 0x23, 0x30);
987 adm8211_write_bbp(dev, 0x24, 0x2d);
988 adm8211_write_bbp(dev, 0x2a, 0x8c);
989 adm8211_write_bbp(dev, 0x2b, 0x81);
990 adm8211_write_bbp(dev, 0x2c, 0x44);
991 adm8211_write_bbp(dev, 0x29, 0x4a);
992 adm8211_write_bbp(dev, 0x60, 0x2b);
993 adm8211_write_bbp(dev, 0x64, 0x01);
996 case ADM8211_AL2210L:
997 adm8211_write_bbp(dev, 0x00, 0x00);
998 adm8211_write_bbp(dev, 0x01, 0x00);
999 adm8211_write_bbp(dev, 0x02, 0x00);
1000 adm8211_write_bbp(dev, 0x03, 0x00);
1001 adm8211_write_bbp(dev, 0x06, 0x0f);
1002 adm8211_write_bbp(dev, 0x07, 0x05);
1003 adm8211_write_bbp(dev, 0x08, 0x03);
1004 adm8211_write_bbp(dev, 0x09, 0x00);
1005 adm8211_write_bbp(dev, 0x0a, 0x00);
1006 adm8211_write_bbp(dev, 0x0b, 0x00);
1007 adm8211_write_bbp(dev, 0x0c, 0x10);
1008 adm8211_write_bbp(dev, 0x0f, 0x55);
1009 adm8211_write_bbp(dev, 0x10, 0x8d);
1010 adm8211_write_bbp(dev, 0x11, 0x43);
1011 adm8211_write_bbp(dev, 0x18, 0x4a);
1012 adm8211_write_bbp(dev, 0x20, 0x20);
1013 adm8211_write_bbp(dev, 0x21, 0x02);
1014 adm8211_write_bbp(dev, 0x22, 0x23);
1015 adm8211_write_bbp(dev, 0x23, 0x30);
1016 adm8211_write_bbp(dev, 0x24, 0x2d);
1017 adm8211_write_bbp(dev, 0x2a, 0xaa);
1018 adm8211_write_bbp(dev, 0x2b, 0x81);
1019 adm8211_write_bbp(dev, 0x2c, 0x44);
1020 adm8211_write_bbp(dev, 0x29, 0xfa);
1021 adm8211_write_bbp(dev, 0x60, 0x2d);
1022 adm8211_write_bbp(dev, 0x64, 0x01);
1025 case ADM8211_RFMD2948:
1029 printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1030 wiphy_name(dev->wiphy), priv->transceiver_type);
1034 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1035 wiphy_name(dev->wiphy), priv->bbp_type);
1037 ADM8211_CSR_WRITE(SYNRF, 0);
1039 /* Set RF CAL control source to MAC control */
1040 reg = ADM8211_CSR_READ(SYNCTL);
1041 reg |= ADM8211_SYNCTL_SELCAL;
1042 ADM8211_CSR_WRITE(SYNCTL, reg);
1047 /* configures hw beacons/probe responses */
1048 static int adm8211_set_rate(struct ieee80211_hw *dev)
1050 struct adm8211_priv *priv = dev->priv;
1053 u8 rate_buf[12] = {0};
1055 /* write supported rates */
1056 if (priv->pdev->revision != ADM8211_REV_BA) {
1057 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1058 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1059 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1061 /* workaround for rev BA specific bug */
1069 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1070 ARRAY_SIZE(adm8211_rates) + 1);
1072 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1073 reg |= 1 << 15; /* short preamble */
1075 ADM8211_CSR_WRITE(PLCPHD, reg);
1077 /* MTMLT = 512 TU (max TX MSDU lifetime)
1078 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1079 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1080 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1085 static void adm8211_hw_init(struct ieee80211_hw *dev)
1087 struct adm8211_priv *priv = dev->priv;
1091 reg = ADM8211_CSR_READ(PAR);
1092 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1093 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1095 if (!pci_set_mwi(priv->pdev)) {
1097 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1100 case 0x8: reg |= (0x1 << 14);
1102 case 0x16: reg |= (0x2 << 14);
1104 case 0x32: reg |= (0x3 << 14);
1106 default: reg |= (0x0 << 14);
1111 ADM8211_CSR_WRITE(PAR, reg);
1113 reg = ADM8211_CSR_READ(CSR_TEST1);
1114 reg &= ~(0xF << 28);
1115 reg |= (1 << 28) | (1 << 31);
1116 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1118 /* lose link after 4 lost beacons */
1119 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1120 ADM8211_CSR_WRITE(WCSR, reg);
1122 /* Disable APM, enable receive FIFO threshold, and set drain receive
1123 * threshold to store-and-forward */
1124 reg = ADM8211_CSR_READ(CMDR);
1125 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1126 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1127 ADM8211_CSR_WRITE(CMDR, reg);
1129 adm8211_set_rate(dev);
1133 * PWR0PAPE = 8 us or 5 us
1134 * PWR1PAPE = 1 us or 3 us
1139 * PWR0TXPE = 8 or 6 */
1140 if (priv->pdev->revision < ADM8211_REV_CA)
1141 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1143 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1145 /* Enable store and forward for transmit */
1146 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1147 ADM8211_CSR_WRITE(NAR, priv->nar);
1150 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1151 ADM8211_CSR_READ(SYNRF);
1153 ADM8211_CSR_WRITE(SYNRF, 0);
1154 ADM8211_CSR_READ(SYNRF);
1157 /* Set CFP Max Duration to 0x10 TU */
1158 reg = ADM8211_CSR_READ(CFPP);
1159 reg &= ~(0xffff << 8);
1161 ADM8211_CSR_WRITE(CFPP, reg);
1163 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1164 * TUCNT = 0x3ff - Tu counter 1024 us */
1165 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1167 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1168 * DIFS=50 us, EIFS=100 us */
1169 if (priv->pdev->revision < ADM8211_REV_CA)
1170 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1173 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1176 /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1177 * RMRD = 2346 * 8 + 1 us (max RX duration) */
1178 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1180 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1181 ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1183 /* Initialize BBP (and SYN) */
1184 adm8211_hw_init_bbp(dev);
1186 /* make sure interrupts are off */
1187 ADM8211_CSR_WRITE(IER, 0);
1189 /* ACK interrupts */
1190 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1192 /* Setup WEP (turns it off for now) */
1193 reg = ADM8211_CSR_READ(MACTEST);
1195 ADM8211_CSR_WRITE(MACTEST, reg);
1197 reg = ADM8211_CSR_READ(WEPCTL);
1198 reg &= ~ADM8211_WEPCTL_WEPENABLE;
1199 reg |= ADM8211_WEPCTL_WEPRXBYP;
1200 ADM8211_CSR_WRITE(WEPCTL, reg);
1202 /* Clear the missed-packet counter. */
1203 ADM8211_CSR_READ(LPC);
1206 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1208 struct adm8211_priv *priv = dev->priv;
1212 /* Power-on issue */
1213 /* TODO: check if this is necessary */
1214 ADM8211_CSR_WRITE(FRCTL, 0);
1216 /* Reset the chip */
1217 tmp = ADM8211_CSR_READ(PAR);
1218 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1220 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1226 ADM8211_CSR_WRITE(PAR, tmp);
1228 if (priv->pdev->revision == ADM8211_REV_BA &&
1229 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1230 priv->transceiver_type == ADM8211_RFMD2958)) {
1231 reg = ADM8211_CSR_READ(CSR_TEST1);
1232 reg |= (1 << 4) | (1 << 5);
1233 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1234 } else if (priv->pdev->revision == ADM8211_REV_CA) {
1235 reg = ADM8211_CSR_READ(CSR_TEST1);
1236 reg &= ~((1 << 4) | (1 << 5));
1237 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1240 ADM8211_CSR_WRITE(FRCTL, 0);
1242 reg = ADM8211_CSR_READ(CSR_TEST0);
1243 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1244 ADM8211_CSR_WRITE(CSR_TEST0, reg);
1246 adm8211_clear_sram(dev);
1251 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1253 struct adm8211_priv *priv = dev->priv;
1257 tsftl = ADM8211_CSR_READ(TSFTL);
1258 tsft = ADM8211_CSR_READ(TSFTH);
1265 static void adm8211_set_interval(struct ieee80211_hw *dev,
1266 unsigned short bi, unsigned short li)
1268 struct adm8211_priv *priv = dev->priv;
1271 /* BP (beacon interval) = data->beacon_interval
1272 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1273 reg = (bi << 16) | li;
1274 ADM8211_CSR_WRITE(BPLI, reg);
1277 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1279 struct adm8211_priv *priv = dev->priv;
1282 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1283 reg = ADM8211_CSR_READ(ABDA1);
1285 reg |= (bssid[4] << 16) | (bssid[5] << 24);
1286 ADM8211_CSR_WRITE(ABDA1, reg);
1289 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1291 struct adm8211_priv *priv = dev->priv;
1292 struct ieee80211_conf *conf = &dev->conf;
1293 int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1295 if (channel != priv->channel) {
1296 priv->channel = channel;
1297 adm8211_rf_set_channel(dev, priv->channel);
1303 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1304 struct ieee80211_vif *vif,
1305 struct ieee80211_bss_conf *conf,
1308 struct adm8211_priv *priv = dev->priv;
1310 if (!(changes & BSS_CHANGED_BSSID))
1313 if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1314 adm8211_set_bssid(dev, conf->bssid);
1315 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1319 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1320 struct netdev_hw_addr_list *mc_list)
1322 unsigned int bit_nr;
1324 struct netdev_hw_addr *ha;
1326 mc_filter[1] = mc_filter[0] = 0;
1328 netdev_hw_addr_list_for_each(ha, mc_list) {
1329 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1332 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1335 return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1338 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1339 unsigned int changed_flags,
1340 unsigned int *total_flags,
1343 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1344 struct adm8211_priv *priv = dev->priv;
1345 unsigned int new_flags;
1348 mc_filter[0] = multicast;
1349 mc_filter[1] = multicast >> 32;
1353 if (*total_flags & FIF_PROMISC_IN_BSS) {
1354 new_flags |= FIF_PROMISC_IN_BSS;
1355 priv->nar |= ADM8211_NAR_PR;
1356 priv->nar &= ~ADM8211_NAR_MM;
1357 mc_filter[1] = mc_filter[0] = ~0;
1358 } else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1359 new_flags |= FIF_ALLMULTI;
1360 priv->nar &= ~ADM8211_NAR_PR;
1361 priv->nar |= ADM8211_NAR_MM;
1362 mc_filter[1] = mc_filter[0] = ~0;
1364 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1369 ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1370 ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1371 ADM8211_CSR_READ(NAR);
1373 if (priv->nar & ADM8211_NAR_PR)
1374 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1376 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1378 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1379 adm8211_set_bssid(dev, bcast);
1381 adm8211_set_bssid(dev, priv->bssid);
1385 *total_flags = new_flags;
1388 static int adm8211_add_interface(struct ieee80211_hw *dev,
1389 struct ieee80211_vif *vif)
1391 struct adm8211_priv *priv = dev->priv;
1392 if (priv->mode != NL80211_IFTYPE_MONITOR)
1395 switch (vif->type) {
1396 case NL80211_IFTYPE_STATION:
1397 priv->mode = vif->type;
1405 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1406 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1408 adm8211_update_mode(dev);
1415 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1416 struct ieee80211_vif *vif)
1418 struct adm8211_priv *priv = dev->priv;
1419 priv->mode = NL80211_IFTYPE_MONITOR;
1422 static int adm8211_init_rings(struct ieee80211_hw *dev)
1424 struct adm8211_priv *priv = dev->priv;
1425 struct adm8211_desc *desc = NULL;
1426 struct adm8211_rx_ring_info *rx_info;
1427 struct adm8211_tx_ring_info *tx_info;
1430 for (i = 0; i < priv->rx_ring_size; i++) {
1431 desc = &priv->rx_ring[i];
1433 desc->length = cpu_to_le32(RX_PKT_SIZE);
1434 priv->rx_buffers[i].skb = NULL;
1436 /* Mark the end of RX ring; hw returns to base address after this
1438 desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1440 for (i = 0; i < priv->rx_ring_size; i++) {
1441 desc = &priv->rx_ring[i];
1442 rx_info = &priv->rx_buffers[i];
1444 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1445 if (rx_info->skb == NULL)
1447 rx_info->mapping = pci_map_single(priv->pdev,
1448 skb_tail_pointer(rx_info->skb),
1450 PCI_DMA_FROMDEVICE);
1451 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1452 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1455 /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1456 for (i = 0; i < priv->tx_ring_size; i++) {
1457 desc = &priv->tx_ring[i];
1458 tx_info = &priv->tx_buffers[i];
1460 tx_info->skb = NULL;
1461 tx_info->mapping = 0;
1464 desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1466 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1467 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1468 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1473 static void adm8211_free_rings(struct ieee80211_hw *dev)
1475 struct adm8211_priv *priv = dev->priv;
1478 for (i = 0; i < priv->rx_ring_size; i++) {
1479 if (!priv->rx_buffers[i].skb)
1484 priv->rx_buffers[i].mapping,
1485 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1487 dev_kfree_skb(priv->rx_buffers[i].skb);
1490 for (i = 0; i < priv->tx_ring_size; i++) {
1491 if (!priv->tx_buffers[i].skb)
1494 pci_unmap_single(priv->pdev,
1495 priv->tx_buffers[i].mapping,
1496 priv->tx_buffers[i].skb->len,
1499 dev_kfree_skb(priv->tx_buffers[i].skb);
1503 static int adm8211_start(struct ieee80211_hw *dev)
1505 struct adm8211_priv *priv = dev->priv;
1508 /* Power up MAC and RF chips */
1509 retval = adm8211_hw_reset(dev);
1511 printk(KERN_ERR "%s: hardware reset failed\n",
1512 wiphy_name(dev->wiphy));
1516 retval = adm8211_init_rings(dev);
1518 printk(KERN_ERR "%s: failed to initialize rings\n",
1519 wiphy_name(dev->wiphy));
1524 adm8211_hw_init(dev);
1525 adm8211_rf_set_channel(dev, priv->channel);
1527 retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1528 IRQF_SHARED, "adm8211", dev);
1530 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1531 wiphy_name(dev->wiphy));
1535 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1536 ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1537 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1538 priv->mode = NL80211_IFTYPE_MONITOR;
1539 adm8211_update_mode(dev);
1540 ADM8211_CSR_WRITE(RDR, 0);
1542 adm8211_set_interval(dev, 100, 10);
1549 static void adm8211_stop(struct ieee80211_hw *dev)
1551 struct adm8211_priv *priv = dev->priv;
1553 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1555 ADM8211_CSR_WRITE(NAR, 0);
1556 ADM8211_CSR_WRITE(IER, 0);
1557 ADM8211_CSR_READ(NAR);
1559 free_irq(priv->pdev->irq, dev);
1561 adm8211_free_rings(dev);
1564 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1565 int plcp_signal, int short_preamble)
1567 /* Alternative calculation from NetBSD: */
1569 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1570 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
1571 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1572 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
1573 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
1574 #define IEEE80211_DUR_DS_SLOW_ACK 112
1575 #define IEEE80211_DUR_DS_FAST_ACK 56
1576 #define IEEE80211_DUR_DS_SLOW_CTS 112
1577 #define IEEE80211_DUR_DS_FAST_CTS 56
1578 #define IEEE80211_DUR_DS_SLOT 20
1579 #define IEEE80211_DUR_DS_SIFS 10
1583 *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1586 if (plcp_signal <= PLCP_SIGNAL_2M)
1587 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1588 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1589 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1590 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1591 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1593 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1594 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1595 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1596 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1597 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1599 /* lengthen duration if long preamble */
1600 if (!short_preamble)
1601 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1602 IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1603 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1604 IEEE80211_DUR_DS_FAST_PLCPHDR);
1607 *plcp = (80 * len) / plcp_signal;
1608 remainder = (80 * len) % plcp_signal;
1609 if (plcp_signal == PLCP_SIGNAL_11M &&
1610 remainder <= 30 && remainder > 0)
1611 *plcp = (*plcp | 0x8000) + 1;
1616 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1617 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1621 struct adm8211_priv *priv = dev->priv;
1622 unsigned long flags;
1627 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1630 spin_lock_irqsave(&priv->lock, flags);
1632 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1633 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1635 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1637 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1638 ieee80211_stop_queue(dev, 0);
1640 entry = priv->cur_tx % priv->tx_ring_size;
1642 priv->tx_buffers[entry].skb = skb;
1643 priv->tx_buffers[entry].mapping = mapping;
1644 priv->tx_buffers[entry].hdrlen = hdrlen;
1645 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1647 if (entry == priv->tx_ring_size - 1)
1648 flag |= TDES1_CONTROL_TER;
1649 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1651 /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1652 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1653 priv->tx_ring[entry].status = cpu_to_le32(flag);
1657 spin_unlock_irqrestore(&priv->lock, flags);
1659 /* Trigger transmit poll */
1660 ADM8211_CSR_WRITE(TDR, 0);
1663 /* Put adm8211_tx_hdr on skb and transmit */
1664 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
1666 struct adm8211_tx_hdr *txhdr;
1667 size_t payload_len, hdrlen;
1668 int plcp, dur, len, plcp_signal, short_preamble;
1669 struct ieee80211_hdr *hdr;
1670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1671 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1674 rc_flags = info->control.rates[0].flags;
1675 short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1676 plcp_signal = txrate->bitrate;
1678 hdr = (struct ieee80211_hdr *)skb->data;
1679 hdrlen = ieee80211_hdrlen(hdr->frame_control);
1680 memcpy(skb->cb, skb->data, hdrlen);
1681 hdr = (struct ieee80211_hdr *)skb->cb;
1682 skb_pull(skb, hdrlen);
1683 payload_len = skb->len;
1685 txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1686 memset(txhdr, 0, sizeof(*txhdr));
1687 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1688 txhdr->signal = plcp_signal;
1689 txhdr->frame_body_size = cpu_to_le16(payload_len);
1690 txhdr->frame_control = hdr->frame_control;
1692 len = hdrlen + payload_len + FCS_LEN;
1694 txhdr->frag = cpu_to_le16(0x0FFF);
1695 adm8211_calc_durations(&dur, &plcp, payload_len,
1696 len, plcp_signal, short_preamble);
1697 txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1698 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1699 txhdr->dur_frag_head = cpu_to_le16(dur);
1700 txhdr->dur_frag_tail = cpu_to_le16(dur);
1702 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1705 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1707 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1708 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1710 txhdr->retry_limit = info->control.rates[0].count;
1712 adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1714 return NETDEV_TX_OK;
1717 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1719 struct adm8211_priv *priv = dev->priv;
1720 unsigned int ring_size;
1722 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1723 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1724 if (!priv->rx_buffers)
1727 priv->tx_buffers = (void *)priv->rx_buffers +
1728 sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1730 /* Allocate TX/RX descriptors */
1731 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1732 sizeof(struct adm8211_desc) * priv->tx_ring_size;
1733 priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1734 &priv->rx_ring_dma);
1736 if (!priv->rx_ring) {
1737 kfree(priv->rx_buffers);
1738 priv->rx_buffers = NULL;
1739 priv->tx_buffers = NULL;
1743 priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1744 priv->rx_ring_size);
1745 priv->tx_ring_dma = priv->rx_ring_dma +
1746 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1751 static const struct ieee80211_ops adm8211_ops = {
1753 .start = adm8211_start,
1754 .stop = adm8211_stop,
1755 .add_interface = adm8211_add_interface,
1756 .remove_interface = adm8211_remove_interface,
1757 .config = adm8211_config,
1758 .bss_info_changed = adm8211_bss_info_changed,
1759 .prepare_multicast = adm8211_prepare_multicast,
1760 .configure_filter = adm8211_configure_filter,
1761 .get_stats = adm8211_get_stats,
1762 .get_tsf = adm8211_get_tsft
1765 static int __devinit adm8211_probe(struct pci_dev *pdev,
1766 const struct pci_device_id *id)
1768 struct ieee80211_hw *dev;
1769 struct adm8211_priv *priv;
1770 unsigned long mem_addr, mem_len;
1771 unsigned int io_addr, io_len;
1774 u8 perm_addr[ETH_ALEN];
1776 err = pci_enable_device(pdev);
1778 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1783 io_addr = pci_resource_start(pdev, 0);
1784 io_len = pci_resource_len(pdev, 0);
1785 mem_addr = pci_resource_start(pdev, 1);
1786 mem_len = pci_resource_len(pdev, 1);
1787 if (io_len < 256 || mem_len < 1024) {
1788 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1790 goto err_disable_pdev;
1794 /* check signature */
1795 pci_read_config_dword(pdev, 0x80 /* CR32 */, ®);
1796 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1797 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1798 pci_name(pdev), reg);
1799 goto err_disable_pdev;
1802 err = pci_request_regions(pdev, "adm8211");
1804 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1806 return err; /* someone else grabbed it? don't disable it */
1809 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1810 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1811 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1816 pci_set_master(pdev);
1818 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1820 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1828 spin_lock_init(&priv->lock);
1830 SET_IEEE80211_DEV(dev, &pdev->dev);
1832 pci_set_drvdata(pdev, dev);
1834 priv->map = pci_iomap(pdev, 1, mem_len);
1836 priv->map = pci_iomap(pdev, 0, io_len);
1839 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1844 priv->rx_ring_size = rx_ring_size;
1845 priv->tx_ring_size = tx_ring_size;
1847 if (adm8211_alloc_rings(dev)) {
1848 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1853 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1854 *(__le16 *)&perm_addr[4] =
1855 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1857 if (!is_valid_ether_addr(perm_addr)) {
1858 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1860 random_ether_addr(perm_addr);
1862 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1864 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1865 /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1866 dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
1867 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1869 dev->channel_change_time = 1000;
1870 dev->max_signal = 100; /* FIXME: find better value */
1872 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1874 priv->retry_limit = 3;
1875 priv->ant_power = 0x40;
1876 priv->tx_power = 0x40;
1877 priv->lpf_cutoff = 0xFF;
1878 priv->lnags_threshold = 0xFF;
1879 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1881 /* Power-on issue. EEPROM won't read correctly without */
1882 if (pdev->revision >= ADM8211_REV_BA) {
1883 ADM8211_CSR_WRITE(FRCTL, 0);
1884 ADM8211_CSR_READ(FRCTL);
1885 ADM8211_CSR_WRITE(FRCTL, 1);
1886 ADM8211_CSR_READ(FRCTL);
1890 err = adm8211_read_eeprom(dev);
1892 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1899 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1901 err = ieee80211_register_hw(dev);
1903 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1908 printk(KERN_INFO "%s: hwaddr %pM, Rev 0x%02x\n",
1909 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1915 pci_free_consistent(pdev,
1916 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1917 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1918 priv->rx_ring, priv->rx_ring_dma);
1919 kfree(priv->rx_buffers);
1922 pci_iounmap(pdev, priv->map);
1925 pci_set_drvdata(pdev, NULL);
1926 ieee80211_free_hw(dev);
1929 pci_release_regions(pdev);
1932 pci_disable_device(pdev);
1937 static void __devexit adm8211_remove(struct pci_dev *pdev)
1939 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1940 struct adm8211_priv *priv;
1945 ieee80211_unregister_hw(dev);
1949 pci_free_consistent(pdev,
1950 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1951 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1952 priv->rx_ring, priv->rx_ring_dma);
1954 kfree(priv->rx_buffers);
1955 kfree(priv->eeprom);
1956 pci_iounmap(pdev, priv->map);
1957 pci_release_regions(pdev);
1958 pci_disable_device(pdev);
1959 ieee80211_free_hw(dev);
1964 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1966 pci_save_state(pdev);
1967 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1971 static int adm8211_resume(struct pci_dev *pdev)
1973 pci_set_power_state(pdev, PCI_D0);
1974 pci_restore_state(pdev);
1977 #endif /* CONFIG_PM */
1980 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1982 /* TODO: implement enable_wake */
1983 static struct pci_driver adm8211_driver = {
1985 .id_table = adm8211_pci_id_table,
1986 .probe = adm8211_probe,
1987 .remove = __devexit_p(adm8211_remove),
1989 .suspend = adm8211_suspend,
1990 .resume = adm8211_resume,
1991 #endif /* CONFIG_PM */
1996 static int __init adm8211_init(void)
1998 return pci_register_driver(&adm8211_driver);
2002 static void __exit adm8211_exit(void)
2004 pci_unregister_driver(&adm8211_driver);
2008 module_init(adm8211_init);
2009 module_exit(adm8211_exit);