2 * Linux driver for VMware's vmxnet3 ethernet NIC.
4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
23 * Maintained by: pv-drivers@vmware.com
27 #ifndef _VMXNET3_DEFS_H_
28 #define _VMXNET3_DEFS_H_
30 #include "upt1_defs.h"
32 /* all registers are 32 bit wide */
35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
39 VMXNET3_REG_CMD = 0x20, /* Command */
40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
43 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
48 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
49 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
50 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
54 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
55 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
57 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
58 #define VMXNET3_REG_ALIGN_MASK 0x7
60 /* I/O Mapped access to registers */
61 #define VMXNET3_IO_TYPE_PT 0
62 #define VMXNET3_IO_TYPE_VD 1
63 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
64 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
65 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
70 VMXNET3_CMD_QUIESCE_DEV,
71 VMXNET3_CMD_RESET_DEV,
72 VMXNET3_CMD_UPDATE_RX_MODE,
73 VMXNET3_CMD_UPDATE_MAC_FILTERS,
74 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
75 VMXNET3_CMD_UPDATE_RSSIDT,
76 VMXNET3_CMD_UPDATE_IML,
77 VMXNET3_CMD_UPDATE_PMCFG,
78 VMXNET3_CMD_UPDATE_FEATURE,
79 VMXNET3_CMD_RESERVED1,
80 VMXNET3_CMD_LOAD_PLUGIN,
81 VMXNET3_CMD_RESERVED2,
82 VMXNET3_CMD_RESERVED3,
83 VMXNET3_CMD_SET_COALESCE,
84 VMXNET3_CMD_REGISTER_MEMREGS,
85 VMXNET3_CMD_SET_RSS_FIELDS,
87 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
88 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
89 VMXNET3_CMD_GET_STATS,
91 VMXNET3_CMD_GET_PERM_MAC_LO,
92 VMXNET3_CMD_GET_PERM_MAC_HI,
93 VMXNET3_CMD_GET_DID_LO,
94 VMXNET3_CMD_GET_DID_HI,
95 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
96 VMXNET3_CMD_GET_CONF_INTR,
97 VMXNET3_CMD_GET_RESERVED1,
98 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
99 VMXNET3_CMD_GET_COALESCE,
100 VMXNET3_CMD_GET_RSS_FIELDS,
104 * Little Endian layout of bitfields -
105 * Byte 0 : 7.....len.....0
106 * Byte 1 : oco gen 13.len.8
107 * Byte 2 : 5.msscof.0 ext1 dtype
108 * Byte 3 : 13...msscof...6
110 * Big Endian layout of bitfields -
111 * Byte 0: 13...msscof...6
112 * Byte 1 : 5.msscof.0 ext1 dtype
113 * Byte 2 : oco gen 13.len.8
114 * Byte 3 : 7.....len.....0
116 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
117 * the bit fields correctly. And cpu_to_le32 will convert bitfields
118 * bit fields written by big endian driver to format required by device.
121 struct Vmxnet3_TxDesc {
124 #ifdef __BIG_ENDIAN_BITFIELD
125 u32 msscof:14; /* MSS, checksum offset, flags */
127 u32 dtype:1; /* descriptor type */
129 u32 gen:1; /* generation bit */
133 u32 gen:1; /* generation bit */
135 u32 dtype:1; /* descriptor type */
137 u32 msscof:14; /* MSS, checksum offset, flags */
138 #endif /* __BIG_ENDIAN_BITFIELD */
140 #ifdef __BIG_ENDIAN_BITFIELD
141 u32 tci:16; /* Tag to Insert */
142 u32 ti:1; /* VLAN Tag Insertion */
144 u32 cq:1; /* completion request */
145 u32 eop:1; /* End Of Packet */
146 u32 om:2; /* offload mode */
147 u32 hlen:10; /* header len */
149 u32 hlen:10; /* header len */
150 u32 om:2; /* offload mode */
151 u32 eop:1; /* End Of Packet */
152 u32 cq:1; /* completion request */
154 u32 ti:1; /* VLAN Tag Insertion */
155 u32 tci:16; /* Tag to Insert */
156 #endif /* __BIG_ENDIAN_BITFIELD */
159 /* TxDesc.OM values */
160 #define VMXNET3_OM_NONE 0
161 #define VMXNET3_OM_ENCAP 1
162 #define VMXNET3_OM_CSUM 2
163 #define VMXNET3_OM_TSO 3
165 /* fields in TxDesc we access w/o using bit fields */
166 #define VMXNET3_TXD_EOP_SHIFT 12
167 #define VMXNET3_TXD_CQ_SHIFT 13
168 #define VMXNET3_TXD_GEN_SHIFT 14
169 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
170 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
172 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
173 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
174 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
176 #define VMXNET3_HDR_COPY_SIZE 128
179 struct Vmxnet3_TxDataDesc {
180 u8 data[VMXNET3_HDR_COPY_SIZE];
183 typedef u8 Vmxnet3_RxDataDesc;
185 #define VMXNET3_TCD_GEN_SHIFT 31
186 #define VMXNET3_TCD_GEN_SIZE 1
187 #define VMXNET3_TCD_TXIDX_SHIFT 0
188 #define VMXNET3_TCD_TXIDX_SIZE 12
189 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
191 struct Vmxnet3_TxCompDesc {
192 u32 txdIdx:12; /* Index of the EOP TxDesc */
199 u32 type:7; /* completion type */
200 u32 gen:1; /* generation bit */
203 struct Vmxnet3_RxDesc {
206 #ifdef __BIG_ENDIAN_BITFIELD
207 u32 gen:1; /* Generation bit */
209 u32 dtype:1; /* Descriptor type */
210 u32 btype:1; /* Buffer Type */
214 u32 btype:1; /* Buffer Type */
215 u32 dtype:1; /* Descriptor type */
217 u32 gen:1; /* Generation bit */
222 /* values of RXD.BTYPE */
223 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
224 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
226 /* fields in RxDesc we access w/o using bit fields */
227 #define VMXNET3_RXD_BTYPE_SHIFT 14
228 #define VMXNET3_RXD_GEN_SHIFT 31
230 #define VMXNET3_RCD_HDR_INNER_SHIFT 13
232 struct Vmxnet3_RxCompDesc {
233 #ifdef __BIG_ENDIAN_BITFIELD
235 u32 cnc:1; /* Checksum Not Calculated */
236 u32 rssType:4; /* RSS hash type used */
237 u32 rqID:10; /* rx queue/ring ID */
238 u32 sop:1; /* Start of Packet */
239 u32 eop:1; /* End of Packet */
241 u32 rxdIdx:12; /* Index of the RxDesc */
243 u32 rxdIdx:12; /* Index of the RxDesc */
245 u32 eop:1; /* End of Packet */
246 u32 sop:1; /* Start of Packet */
247 u32 rqID:10; /* rx queue/ring ID */
248 u32 rssType:4; /* RSS hash type used */
249 u32 cnc:1; /* Checksum Not Calculated */
251 #endif /* __BIG_ENDIAN_BITFIELD */
253 __le32 rssHash; /* RSS hash value */
255 #ifdef __BIG_ENDIAN_BITFIELD
256 u32 tci:16; /* Tag stripped */
257 u32 ts:1; /* Tag is stripped */
258 u32 err:1; /* Error */
259 u32 len:14; /* data length */
261 u32 len:14; /* data length */
262 u32 err:1; /* Error */
263 u32 ts:1; /* Tag is stripped */
264 u32 tci:16; /* Tag stripped */
265 #endif /* __BIG_ENDIAN_BITFIELD */
268 #ifdef __BIG_ENDIAN_BITFIELD
269 u32 gen:1; /* generation bit */
270 u32 type:7; /* completion type */
271 u32 fcs:1; /* Frame CRC correct */
272 u32 frg:1; /* IP Fragment */
275 u32 ipc:1; /* IP Checksum Correct */
276 u32 tcp:1; /* TCP packet */
277 u32 udp:1; /* UDP packet */
278 u32 tuc:1; /* TCP/UDP Checksum Correct */
282 u32 tuc:1; /* TCP/UDP Checksum Correct */
283 u32 udp:1; /* UDP packet */
284 u32 tcp:1; /* TCP packet */
285 u32 ipc:1; /* IP Checksum Correct */
288 u32 frg:1; /* IP Fragment */
289 u32 fcs:1; /* Frame CRC correct */
290 u32 type:7; /* completion type */
291 u32 gen:1; /* generation bit */
292 #endif /* __BIG_ENDIAN_BITFIELD */
295 struct Vmxnet3_RxCompDescExt {
297 u8 segCnt; /* Number of aggregated packets */
298 u8 dupAckCnt; /* Number of duplicate Acks */
299 __le16 tsDelta; /* TCP timestamp difference */
301 #ifdef __BIG_ENDIAN_BITFIELD
302 u32 gen:1; /* generation bit */
303 u32 type:7; /* completion type */
304 u32 fcs:1; /* Frame CRC correct */
305 u32 frg:1; /* IP Fragment */
308 u32 ipc:1; /* IP Checksum Correct */
309 u32 tcp:1; /* TCP packet */
310 u32 udp:1; /* UDP packet */
311 u32 tuc:1; /* TCP/UDP Checksum Correct */
315 u32 tuc:1; /* TCP/UDP Checksum Correct */
316 u32 udp:1; /* UDP packet */
317 u32 tcp:1; /* TCP packet */
318 u32 ipc:1; /* IP Checksum Correct */
321 u32 frg:1; /* IP Fragment */
322 u32 fcs:1; /* Frame CRC correct */
323 u32 type:7; /* completion type */
324 u32 gen:1; /* generation bit */
325 #endif /* __BIG_ENDIAN_BITFIELD */
329 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
330 #define VMXNET3_RCD_TUC_SHIFT 16
331 #define VMXNET3_RCD_IPC_SHIFT 19
333 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
334 #define VMXNET3_RCD_TYPE_SHIFT 56
335 #define VMXNET3_RCD_GEN_SHIFT 63
337 /* csum OK for TCP/UDP pkts over IP */
338 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
339 1 << VMXNET3_RCD_IPC_SHIFT)
340 #define VMXNET3_TXD_GEN_SIZE 1
341 #define VMXNET3_TXD_EOP_SIZE 1
343 /* value of RxCompDesc.rssType */
345 VMXNET3_RCD_RSS_TYPE_NONE = 0,
346 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
347 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
348 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
349 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
353 /* a union for accessing all cmd/completion descriptors */
354 union Vmxnet3_GenericDesc {
358 struct Vmxnet3_TxDesc txd;
359 struct Vmxnet3_RxDesc rxd;
360 struct Vmxnet3_TxCompDesc tcd;
361 struct Vmxnet3_RxCompDesc rcd;
362 struct Vmxnet3_RxCompDescExt rcdExt;
365 #define VMXNET3_INIT_GEN 1
367 /* Max size of a single tx buffer */
368 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
370 /* # of tx desc needed for a tx buffer size */
371 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
372 VMXNET3_MAX_TX_BUF_SIZE)
374 /* max # of tx descs for a non-tso pkt */
375 #define VMXNET3_MAX_TXD_PER_PKT 16
377 /* Max size of a single rx buffer */
378 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
379 /* Minimum size of a type 0 buffer */
380 #define VMXNET3_MIN_T0_BUF_SIZE 128
381 #define VMXNET3_MAX_CSUM_OFFSET 1024
383 /* Ring base address alignment */
384 #define VMXNET3_RING_BA_ALIGN 512
385 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
387 /* Ring size must be a multiple of 32 */
388 #define VMXNET3_RING_SIZE_ALIGN 32
389 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
391 /* Tx Data Ring buffer size must be a multiple of 64 */
392 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
393 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
395 /* Rx Data Ring buffer size must be a multiple of 64 */
396 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
397 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
400 #define VMXNET3_TX_RING_MAX_SIZE 4096
401 #define VMXNET3_TC_RING_MAX_SIZE 4096
402 #define VMXNET3_RX_RING_MAX_SIZE 4096
403 #define VMXNET3_RX_RING2_MAX_SIZE 4096
404 #define VMXNET3_RC_RING_MAX_SIZE 8192
406 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
407 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
409 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
411 /* a list of reasons for queue stop */
414 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
415 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
416 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
417 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
418 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
419 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
420 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
421 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
424 /* completion descriptor types */
425 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
426 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
427 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
430 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
431 VMXNET3_GOS_BITS_32 = 1,
432 VMXNET3_GOS_BITS_64 = 2,
435 #define VMXNET3_GOS_TYPE_LINUX 1
438 struct Vmxnet3_GOSInfo {
439 #ifdef __BIG_ENDIAN_BITFIELD
440 u32 gosMisc:10; /* other info about gos */
441 u32 gosVer:16; /* gos version */
442 u32 gosType:4; /* which guest */
443 u32 gosBits:2; /* 32-bit or 64-bit? */
445 u32 gosBits:2; /* 32-bit or 64-bit? */
446 u32 gosType:4; /* which guest */
447 u32 gosVer:16; /* gos version */
448 u32 gosMisc:10; /* other info about gos */
449 #endif /* __BIG_ENDIAN_BITFIELD */
452 struct Vmxnet3_DriverInfo {
454 struct Vmxnet3_GOSInfo gos;
455 __le32 vmxnet3RevSpt;
460 #define VMXNET3_REV1_MAGIC 3133079265u
463 * QueueDescPA must be 128 bytes aligned. It points to an array of
464 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
465 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
466 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
468 #define VMXNET3_QUEUE_DESC_ALIGN 128
471 struct Vmxnet3_MiscConf {
472 struct Vmxnet3_DriverInfo driverInfo;
474 __le64 ddPA; /* driver data PA */
475 __le64 queueDescPA; /* queue descriptor table PA */
476 __le32 ddLen; /* driver data len */
477 __le32 queueDescLen; /* queue desc. table len in bytes */
486 struct Vmxnet3_TxQueueConf {
488 __le64 dataRingBasePA;
489 __le64 compRingBasePA;
490 __le64 ddPA; /* driver data */
492 __le32 txRingSize; /* # of tx desc */
493 __le32 dataRingSize; /* # of data desc */
494 __le32 compRingSize; /* # of comp desc */
495 __le32 ddLen; /* size of driver data */
498 __le16 txDataRingDescSize;
503 struct Vmxnet3_RxQueueConf {
504 __le64 rxRingBasePA[2];
505 __le64 compRingBasePA;
506 __le64 ddPA; /* driver data */
507 __le64 rxDataRingBasePA;
508 __le32 rxRingSize[2]; /* # of rx desc */
509 __le32 compRingSize; /* # of rx comp desc */
510 __le32 ddLen; /* size of driver data */
513 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
518 enum vmxnet3_intr_mask_mode {
519 VMXNET3_IMM_AUTO = 0,
520 VMXNET3_IMM_ACTIVE = 1,
524 enum vmxnet3_intr_type {
531 #define VMXNET3_MAX_TX_QUEUES 8
532 #define VMXNET3_MAX_RX_QUEUES 16
533 /* addition 1 for events */
534 #define VMXNET3_MAX_INTRS 25
536 /* value of intrCtrl */
537 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
540 struct Vmxnet3_IntrConf {
542 u8 numIntrs; /* # of interrupts */
544 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
550 /* one bit per VLAN ID, the size is in the units of u32 */
551 #define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
554 struct Vmxnet3_QueueStatus {
561 struct Vmxnet3_TxQueueCtrl {
562 __le32 txNumDeferred;
568 struct Vmxnet3_RxQueueCtrl {
575 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
576 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
577 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
578 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
579 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
582 struct Vmxnet3_RxFilterConf {
583 __le32 rxMode; /* VMXNET3_RXM_xxx */
584 __le16 mfTableLen; /* size of the multicast filter table */
586 __le64 mfTablePA; /* PA of the multicast filters table */
587 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
591 #define VMXNET3_PM_MAX_FILTERS 6
592 #define VMXNET3_PM_MAX_PATTERN_SIZE 128
593 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
595 #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
596 #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
600 struct Vmxnet3_PM_PktFilter {
603 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
604 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
609 struct Vmxnet3_PMConf {
610 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
613 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
617 struct Vmxnet3_VariableLenConfDesc {
624 struct Vmxnet3_TxQueueDesc {
625 struct Vmxnet3_TxQueueCtrl ctrl;
626 struct Vmxnet3_TxQueueConf conf;
628 /* Driver read after a GET command */
629 struct Vmxnet3_QueueStatus status;
630 struct UPT1_TxStats stats;
631 u8 _pad[88]; /* 128 aligned */
635 struct Vmxnet3_RxQueueDesc {
636 struct Vmxnet3_RxQueueCtrl ctrl;
637 struct Vmxnet3_RxQueueConf conf;
638 /* Driver read after a GET commad */
639 struct Vmxnet3_QueueStatus status;
640 struct UPT1_RxStats stats;
641 u8 __pad[88]; /* 128 aligned */
644 struct Vmxnet3_SetPolling {
648 #define VMXNET3_COAL_STATIC_MAX_DEPTH 128
649 #define VMXNET3_COAL_RBC_MIN_RATE 100
650 #define VMXNET3_COAL_RBC_MAX_RATE 100000
652 enum Vmxnet3_CoalesceMode {
653 VMXNET3_COALESCE_DISABLED = 0,
654 VMXNET3_COALESCE_ADAPT = 1,
655 VMXNET3_COALESCE_STATIC = 2,
656 VMXNET3_COALESCE_RBC = 3
659 struct Vmxnet3_CoalesceRbc {
663 struct Vmxnet3_CoalesceStatic {
669 struct Vmxnet3_CoalesceScheme {
670 enum Vmxnet3_CoalesceMode coalMode;
672 struct Vmxnet3_CoalesceRbc coalRbc;
673 struct Vmxnet3_CoalesceStatic coalStatic;
677 struct Vmxnet3_MemoryRegion {
684 #define MAX_MEMORY_REGION_PER_QUEUE 16
685 #define MAX_MEMORY_REGION_PER_DEVICE 256
687 struct Vmxnet3_MemRegs {
690 struct Vmxnet3_MemoryRegion memRegs[1];
693 enum Vmxnet3_RSSField {
694 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
695 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
696 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
697 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
698 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
699 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
702 /* If the command data <= 16 bytes, use the shared memory directly.
703 * otherwise, use variable length configuration descriptor.
705 union Vmxnet3_CmdInfo {
706 struct Vmxnet3_VariableLenConfDesc varConf;
707 struct Vmxnet3_SetPolling setPolling;
708 enum Vmxnet3_RSSField setRssFields;
712 struct Vmxnet3_DSDevRead {
713 /* read-only region for device, read by dev in response to a SET cmd */
714 struct Vmxnet3_MiscConf misc;
715 struct Vmxnet3_IntrConf intrConf;
716 struct Vmxnet3_RxFilterConf rxFilterConf;
717 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
718 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
719 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
722 /* All structures in DriverShared are padded to multiples of 8 bytes */
723 struct Vmxnet3_DriverShared {
725 /* make devRead start at 64bit boundaries */
727 struct Vmxnet3_DSDevRead devRead;
732 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of
733 * executing the relevant
740 #define VMXNET3_ECR_RQERR (1 << 0)
741 #define VMXNET3_ECR_TQERR (1 << 1)
742 #define VMXNET3_ECR_LINK (1 << 2)
743 #define VMXNET3_ECR_DIC (1 << 3)
744 #define VMXNET3_ECR_DEBUG (1 << 4)
746 /* flip the gen bit of a ring */
747 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
749 /* only use this if moving the idx won't affect the gen bit */
750 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
753 if (unlikely((idx) == (ring_size))) {\
758 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
759 (vfTable[vid >> 5] |= (1 << (vid & 31)))
760 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
761 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
763 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
764 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
766 #define VMXNET3_MAX_MTU 9000
767 #define VMXNET3_MIN_MTU 60
769 #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
770 #define VMXNET3_LINK_DOWN 0
772 #endif /* _VMXNET3_DEFS_H_ */