1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/acpi.h>
27 /* Information for net-next */
28 #define NETNEXT_VERSION "09"
30 /* Information for net */
31 #define NET_VERSION "10"
33 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
34 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
35 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
36 #define MODULENAME "r8152"
38 #define R8152_PHY_ID 32
40 #define PLA_IDR 0xc000
41 #define PLA_RCR 0xc010
42 #define PLA_RMS 0xc016
43 #define PLA_RXFIFO_CTRL0 0xc0a0
44 #define PLA_RXFIFO_CTRL1 0xc0a4
45 #define PLA_RXFIFO_CTRL2 0xc0a8
46 #define PLA_DMY_REG0 0xc0b0
47 #define PLA_FMC 0xc0b4
48 #define PLA_CFG_WOL 0xc0b6
49 #define PLA_TEREDO_CFG 0xc0bc
50 #define PLA_TEREDO_WAKE_BASE 0xc0c4
51 #define PLA_MAR 0xcd00
52 #define PLA_BACKUP 0xd000
53 #define PLA_BDC_CR 0xd1a0
54 #define PLA_TEREDO_TIMER 0xd2cc
55 #define PLA_REALWOW_TIMER 0xd2e8
56 #define PLA_SUSPEND_FLAG 0xd38a
57 #define PLA_INDICATE_FALG 0xd38c
58 #define PLA_EXTRA_STATUS 0xd398
59 #define PLA_EFUSE_DATA 0xdd00
60 #define PLA_EFUSE_CMD 0xdd02
61 #define PLA_LEDSEL 0xdd90
62 #define PLA_LED_FEATURE 0xdd92
63 #define PLA_PHYAR 0xde00
64 #define PLA_BOOT_CTRL 0xe004
65 #define PLA_GPHY_INTR_IMR 0xe022
66 #define PLA_EEE_CR 0xe040
67 #define PLA_EEEP_CR 0xe080
68 #define PLA_MAC_PWR_CTRL 0xe0c0
69 #define PLA_MAC_PWR_CTRL2 0xe0ca
70 #define PLA_MAC_PWR_CTRL3 0xe0cc
71 #define PLA_MAC_PWR_CTRL4 0xe0ce
72 #define PLA_WDT6_CTRL 0xe428
73 #define PLA_TCR0 0xe610
74 #define PLA_TCR1 0xe612
75 #define PLA_MTPS 0xe615
76 #define PLA_TXFIFO_CTRL 0xe618
77 #define PLA_RSTTALLY 0xe800
79 #define PLA_CRWECR 0xe81c
80 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
81 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
82 #define PLA_CONFIG5 0xe822
83 #define PLA_PHY_PWR 0xe84c
84 #define PLA_OOB_CTRL 0xe84f
85 #define PLA_CPCR 0xe854
86 #define PLA_MISC_0 0xe858
87 #define PLA_MISC_1 0xe85a
88 #define PLA_OCP_GPHY_BASE 0xe86c
89 #define PLA_TALLYCNT 0xe890
90 #define PLA_SFF_STS_7 0xe8de
91 #define PLA_PHYSTATUS 0xe908
92 #define PLA_BP_BA 0xfc26
93 #define PLA_BP_0 0xfc28
94 #define PLA_BP_1 0xfc2a
95 #define PLA_BP_2 0xfc2c
96 #define PLA_BP_3 0xfc2e
97 #define PLA_BP_4 0xfc30
98 #define PLA_BP_5 0xfc32
99 #define PLA_BP_6 0xfc34
100 #define PLA_BP_7 0xfc36
101 #define PLA_BP_EN 0xfc38
103 #define USB_USB2PHY 0xb41e
104 #define USB_SSPHYLINK2 0xb428
105 #define USB_U2P3_CTRL 0xb460
106 #define USB_CSR_DUMMY1 0xb464
107 #define USB_CSR_DUMMY2 0xb466
108 #define USB_DEV_STAT 0xb808
109 #define USB_CONNECT_TIMER 0xcbf8
110 #define USB_MSC_TIMER 0xcbfc
111 #define USB_BURST_SIZE 0xcfc0
112 #define USB_LPM_CONFIG 0xcfd8
113 #define USB_USB_CTRL 0xd406
114 #define USB_PHY_CTRL 0xd408
115 #define USB_TX_AGG 0xd40a
116 #define USB_RX_BUF_TH 0xd40c
117 #define USB_USB_TIMER 0xd428
118 #define USB_RX_EARLY_TIMEOUT 0xd42c
119 #define USB_RX_EARLY_SIZE 0xd42e
120 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
121 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
122 #define USB_TX_DMA 0xd434
123 #define USB_UPT_RXDMA_OWN 0xd437
124 #define USB_TOLERANCE 0xd490
125 #define USB_LPM_CTRL 0xd41a
126 #define USB_BMU_RESET 0xd4b0
127 #define USB_U1U2_TIMER 0xd4da
128 #define USB_UPS_CTRL 0xd800
129 #define USB_POWER_CUT 0xd80a
130 #define USB_MISC_0 0xd81a
131 #define USB_MISC_1 0xd81f
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
216 #define ECM_ALDPS 0x0002
219 #define FMC_FCR_MCU_EN 0x0001
222 #define EEEP_CR_EEEP_TX 0x0002
225 #define WDT6_SET_MODE 0x0010
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
232 #define VERSION_MASK 0x7cf0
235 #define MTPS_JUMBO (12 * 1024 / 64)
236 #define MTPS_DEFAULT (6 * 1024 / 64)
239 #define TALLY_RESET 0x0001
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
259 #define RXDY_GATED_EN 0x0008
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
266 #define CPCR_RX_VLAN 0x0040
269 #define MAGIC_EN 0x0001
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
278 #define ALDPS_PROXY_MODE 0x0001
281 #define EFUSE_READ_CMD BIT(15)
282 #define EFUSE_DATA_BIT16 BIT(7)
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK 0x0700
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO 0x8007
309 #define MAC_CLK_SPDWN_EN BIT(15)
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
333 #define PHYAR_FLAG 0x80000000
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
340 #define AUTOLOAD_DONE 0x0002
342 /* PLA_SUSPEND_FLAG */
343 #define LINK_CHG_EVENT BIT(0)
345 /* PLA_INDICATE_FALG */
346 #define UPCOMING_RUNTIME_D3 BIT(0)
348 /* PLA_EXTRA_STATUS */
349 #define LINK_CHANGE_FLAG BIT(8)
352 #define USB2PHY_SUSPEND 0x0001
353 #define USB2PHY_L1 0x0002
356 #define pwd_dn_scale_mask 0x3ffe
357 #define pwd_dn_scale(x) ((x) << 1)
360 #define DYNAMIC_BURST 0x0001
363 #define EP4_FULL_FC 0x0001
366 #define STAT_SPEED_MASK 0x0006
367 #define STAT_SPEED_HIGH 0x0000
368 #define STAT_SPEED_FULL 0x0002
371 #define LPM_U1U2_EN BIT(0)
374 #define TX_AGG_MAX_THRESHOLD 0x03
377 #define RX_THR_SUPPER 0x0c350180
378 #define RX_THR_HIGH 0x7a120180
379 #define RX_THR_SLOW 0xffff0180
380 #define RX_THR_B 0x00010001
383 #define TEST_MODE_DISABLE 0x00000001
384 #define TX_SIZE_ADJUST1 0x00000100
387 #define BMU_RESET_EP_IN 0x01
388 #define BMU_RESET_EP_OUT 0x02
390 /* USB_UPT_RXDMA_OWN */
391 #define OWN_UPDATE BIT(0)
392 #define OWN_CLEAR BIT(1)
395 #define POWER_CUT 0x0100
397 /* USB_PM_CTRL_STATUS */
398 #define RESUME_INDICATE 0x0001
401 #define RX_AGG_DISABLE 0x0010
402 #define RX_ZERO_EN 0x0080
405 #define U2P3_ENABLE 0x0001
408 #define PWR_EN 0x0001
409 #define PHASE2_EN 0x0008
410 #define UPS_EN BIT(4)
411 #define USP_PREWAKE BIT(5)
414 #define PCUT_STATUS 0x0001
416 /* USB_RX_EARLY_TIMEOUT */
417 #define COALESCE_SUPER 85000U
418 #define COALESCE_HIGH 250000U
419 #define COALESCE_SLOW 524280U
422 #define TIMER11_EN 0x0001
425 /* bit 4 ~ 5: fifo empty boundary */
426 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
427 /* bit 2 ~ 3: LMP timer */
428 #define LPM_TIMER_MASK 0x0c
429 #define LPM_TIMER_500MS 0x04 /* 500 ms */
430 #define LPM_TIMER_500US 0x0c /* 500 us */
431 #define ROK_EXIT_LPM 0x02
434 #define SEN_VAL_MASK 0xf800
435 #define SEN_VAL_NORMAL 0xa000
436 #define SEL_RXIDLE 0x0100
439 #define SAW_CNT_1MS_MASK 0x0fff
442 #define UPS_FLAGS_R_TUNE BIT(0)
443 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
444 #define UPS_FLAGS_250M_CKDIV BIT(2)
445 #define UPS_FLAGS_EN_ALDPS BIT(3)
446 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
447 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
448 #define ups_flags_speed(x) ((x) << 16)
449 #define UPS_FLAGS_EN_EEE BIT(20)
450 #define UPS_FLAGS_EN_500M_EEE BIT(21)
451 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
452 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
453 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
454 #define UPS_FLAGS_EN_GREEN BIT(26)
455 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
469 /* OCP_ALDPS_CONFIG */
470 #define ENPWRSAVE 0x8000
471 #define ENPDNPS 0x0200
472 #define LINKENA 0x0100
473 #define DIS_SDSAVE 0x0010
476 #define PHY_STAT_MASK 0x0007
477 #define PHY_STAT_EXT_INIT 2
478 #define PHY_STAT_LAN_ON 3
479 #define PHY_STAT_PWRDN 5
482 #define PGA_RETURN_EN BIT(1)
485 #define EEE_CLKDIV_EN 0x8000
486 #define EN_ALDPS 0x0004
487 #define EN_10M_PLLOFF 0x0001
489 /* OCP_EEE_CONFIG1 */
490 #define RG_TXLPI_MSK_HFDUP 0x8000
491 #define RG_MATCLR_EN 0x4000
492 #define EEE_10_CAP 0x2000
493 #define EEE_NWAY_EN 0x1000
494 #define TX_QUIET_EN 0x0200
495 #define RX_QUIET_EN 0x0100
496 #define sd_rise_time_mask 0x0070
497 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
498 #define RG_RXLPI_MSK_HFDUP 0x0008
499 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
501 /* OCP_EEE_CONFIG2 */
502 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
503 #define RG_DACQUIET_EN 0x0400
504 #define RG_LDVQUIET_EN 0x0200
505 #define RG_CKRSEL 0x0020
506 #define RG_EEEPRG_EN 0x0010
508 /* OCP_EEE_CONFIG3 */
509 #define fast_snr_mask 0xff80
510 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
511 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
512 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
515 /* bit[15:14] function */
516 #define FUN_ADDR 0x0000
517 #define FUN_DATA 0x4000
518 /* bit[4:0] device addr */
521 #define CTAP_SHORT_EN 0x0040
522 #define EEE10_EN 0x0010
525 #define EN_EEE_CMODE BIT(14)
526 #define EN_EEE_1000 BIT(13)
527 #define EN_EEE_100 BIT(12)
528 #define EN_10M_CLKDIV BIT(11)
529 #define EN_10M_BGOFF 0x0080
532 #define TXDIS_STATE 0x01
533 #define ABD_STATE 0x02
535 /* OCP_PHY_PATCH_STAT */
536 #define PATCH_READY BIT(6)
538 /* OCP_PHY_PATCH_CMD */
539 #define PATCH_REQUEST BIT(4)
542 #define CKADSEL_L 0x0100
543 #define ADC_EN 0x0080
544 #define EN_EMI_L 0x0040
547 #define clk_div_expo(x) (min(x, 5) << 8)
550 #define GREEN_ETH_EN BIT(15)
551 #define R_TUNE_EN BIT(11)
554 #define LPF_AUTO_TUNE 0x8000
557 #define GDAC_IB_UPALL 0x0008
560 #define AMP_DN 0x0200
563 #define RX_DRIVING_MASK 0x6000
566 #define AD_MASK 0xfee0
567 #define BND_MASK 0x0004
568 #define BD_MASK 0x0001
570 #define PASS_THRU_MASK 0x1
572 enum rtl_register_content {
580 #define RTL8152_MAX_TX 4
581 #define RTL8152_MAX_RX 10
586 #define INTR_LINK 0x0004
588 #define RTL8152_REQT_READ 0xc0
589 #define RTL8152_REQT_WRITE 0x40
590 #define RTL8152_REQ_GET_REGS 0x05
591 #define RTL8152_REQ_SET_REGS 0x05
593 #define BYTE_EN_DWORD 0xff
594 #define BYTE_EN_WORD 0x33
595 #define BYTE_EN_BYTE 0x11
596 #define BYTE_EN_SIX_BYTES 0x3f
597 #define BYTE_EN_START_MASK 0x0f
598 #define BYTE_EN_END_MASK 0xf0
600 #define RTL8153_MAX_PACKET 9216 /* 9K */
601 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
603 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
604 #define RTL8153_RMS RTL8153_MAX_PACKET
605 #define RTL8152_TX_TIMEOUT (5 * HZ)
606 #define RTL8152_NAPI_WEIGHT 64
607 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
608 sizeof(struct rx_desc) + RX_ALIGN)
623 /* Define these values to match your device */
624 #define VENDOR_ID_REALTEK 0x0bda
625 #define VENDOR_ID_MICROSOFT 0x045e
626 #define VENDOR_ID_SAMSUNG 0x04e8
627 #define VENDOR_ID_LENOVO 0x17ef
628 #define VENDOR_ID_LINKSYS 0x13b1
629 #define VENDOR_ID_NVIDIA 0x0955
630 #define VENDOR_ID_TPLINK 0x2357
632 #define MCU_TYPE_PLA 0x0100
633 #define MCU_TYPE_USB 0x0000
635 struct tally_counter {
642 __le32 tx_one_collision;
643 __le32 tx_multi_collision;
653 #define RX_LEN_MASK 0x7fff
656 #define RD_UDP_CS BIT(23)
657 #define RD_TCP_CS BIT(22)
658 #define RD_IPV6_CS BIT(20)
659 #define RD_IPV4_CS BIT(19)
662 #define IPF BIT(23) /* IP checksum fail */
663 #define UDPF BIT(22) /* UDP checksum fail */
664 #define TCPF BIT(21) /* TCP checksum fail */
665 #define RX_VLAN_TAG BIT(16)
674 #define TX_FS BIT(31) /* First segment of a packet */
675 #define TX_LS BIT(30) /* Final segment of a packet */
676 #define GTSENDV4 BIT(28)
677 #define GTSENDV6 BIT(27)
678 #define GTTCPHO_SHIFT 18
679 #define GTTCPHO_MAX 0x7fU
680 #define TX_LEN_MAX 0x3ffffU
683 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
684 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
685 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
686 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
688 #define MSS_MAX 0x7ffU
689 #define TCPHO_SHIFT 17
690 #define TCPHO_MAX 0x7ffU
691 #define TX_VLAN_TAG BIT(16)
697 struct list_head list;
699 struct r8152 *context;
705 struct list_head list;
707 struct r8152 *context;
716 struct usb_device *udev;
717 struct napi_struct napi;
718 struct usb_interface *intf;
719 struct net_device *netdev;
720 struct urb *intr_urb;
721 struct tx_agg tx_info[RTL8152_MAX_TX];
722 struct rx_agg rx_info[RTL8152_MAX_RX];
723 struct list_head rx_done, tx_free;
724 struct sk_buff_head tx_queue, rx_queue;
725 spinlock_t rx_lock, tx_lock;
726 struct delayed_work schedule, hw_phy_work;
727 struct mii_if_info mii;
728 struct mutex control; /* use for hw setting */
729 #ifdef CONFIG_PM_SLEEP
730 struct notifier_block pm_notifier;
734 void (*init)(struct r8152 *);
735 int (*enable)(struct r8152 *);
736 void (*disable)(struct r8152 *);
737 void (*up)(struct r8152 *);
738 void (*down)(struct r8152 *);
739 void (*unload)(struct r8152 *);
740 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
741 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
742 bool (*in_nway)(struct r8152 *);
743 void (*hw_phy_cfg)(struct r8152 *);
744 void (*autosuspend_en)(struct r8152 *tp, bool enable);
780 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
781 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
783 static const int multicast_filter_limit = 32;
784 static unsigned int agg_buf_sz = 16384;
786 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
787 VLAN_ETH_HLEN - ETH_FCS_LEN)
790 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
795 tmp = kmalloc(size, GFP_KERNEL);
799 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
800 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
801 value, index, tmp, size, 500);
803 memset(data, 0xff, size);
805 memcpy(data, tmp, size);
813 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
818 tmp = kmemdup(data, size, GFP_KERNEL);
822 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
823 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
824 value, index, tmp, size, 500);
831 static void rtl_set_unplug(struct r8152 *tp)
833 if (tp->udev->state == USB_STATE_NOTATTACHED) {
834 set_bit(RTL8152_UNPLUG, &tp->flags);
835 smp_mb__after_atomic();
839 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
840 void *data, u16 type)
845 if (test_bit(RTL8152_UNPLUG, &tp->flags))
848 /* both size and indix must be 4 bytes align */
849 if ((size & 3) || !size || (index & 3) || !data)
852 if ((u32)index + (u32)size > 0xffff)
857 ret = get_registers(tp, index, type, limit, data);
865 ret = get_registers(tp, index, type, size, data);
882 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
883 u16 size, void *data, u16 type)
886 u16 byteen_start, byteen_end, byen;
889 if (test_bit(RTL8152_UNPLUG, &tp->flags))
892 /* both size and indix must be 4 bytes align */
893 if ((size & 3) || !size || (index & 3) || !data)
896 if ((u32)index + (u32)size > 0xffff)
899 byteen_start = byteen & BYTE_EN_START_MASK;
900 byteen_end = byteen & BYTE_EN_END_MASK;
902 byen = byteen_start | (byteen_start << 4);
903 ret = set_registers(tp, index, type | byen, 4, data);
916 ret = set_registers(tp, index,
917 type | BYTE_EN_DWORD,
926 ret = set_registers(tp, index,
927 type | BYTE_EN_DWORD,
939 byen = byteen_end | (byteen_end >> 4);
940 ret = set_registers(tp, index, type | byen, 4, data);
953 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
955 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
959 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
961 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
965 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
967 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
970 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
974 generic_ocp_read(tp, index, sizeof(data), &data, type);
976 return __le32_to_cpu(data);
979 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
981 __le32 tmp = __cpu_to_le32(data);
983 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
986 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
990 u16 byen = BYTE_EN_WORD;
991 u8 shift = index & 2;
996 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
998 data = __le32_to_cpu(tmp);
999 data >>= (shift * 8);
1005 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1009 u16 byen = BYTE_EN_WORD;
1010 u8 shift = index & 2;
1016 mask <<= (shift * 8);
1017 data <<= (shift * 8);
1021 tmp = __cpu_to_le32(data);
1023 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1026 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1030 u8 shift = index & 3;
1034 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1036 data = __le32_to_cpu(tmp);
1037 data >>= (shift * 8);
1043 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1047 u16 byen = BYTE_EN_BYTE;
1048 u8 shift = index & 3;
1054 mask <<= (shift * 8);
1055 data <<= (shift * 8);
1059 tmp = __cpu_to_le32(data);
1061 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1064 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1066 u16 ocp_base, ocp_index;
1068 ocp_base = addr & 0xf000;
1069 if (ocp_base != tp->ocp_base) {
1070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1071 tp->ocp_base = ocp_base;
1074 ocp_index = (addr & 0x0fff) | 0xb000;
1075 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1078 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1080 u16 ocp_base, ocp_index;
1082 ocp_base = addr & 0xf000;
1083 if (ocp_base != tp->ocp_base) {
1084 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1085 tp->ocp_base = ocp_base;
1088 ocp_index = (addr & 0x0fff) | 0xb000;
1089 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1092 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1094 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1097 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1099 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1102 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1104 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1105 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1108 static u16 sram_read(struct r8152 *tp, u16 addr)
1110 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1111 return ocp_reg_read(tp, OCP_SRAM_DATA);
1114 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1116 struct r8152 *tp = netdev_priv(netdev);
1119 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1122 if (phy_id != R8152_PHY_ID)
1125 ret = r8152_mdio_read(tp, reg);
1131 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1133 struct r8152 *tp = netdev_priv(netdev);
1135 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1138 if (phy_id != R8152_PHY_ID)
1141 r8152_mdio_write(tp, reg, val);
1145 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1147 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1149 struct r8152 *tp = netdev_priv(netdev);
1150 struct sockaddr *addr = p;
1151 int ret = -EADDRNOTAVAIL;
1153 if (!is_valid_ether_addr(addr->sa_data))
1156 ret = usb_autopm_get_interface(tp->intf);
1160 mutex_lock(&tp->control);
1162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1164 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1165 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1166 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1168 mutex_unlock(&tp->control);
1170 usb_autopm_put_interface(tp->intf);
1175 /* Devices containing proper chips can support a persistent
1176 * host system provided MAC address.
1177 * Examples of this are Dell TB15 and Dell WD15 docks
1179 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1182 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1183 union acpi_object *obj;
1186 unsigned char buf[6];
1188 /* test for -AD variant of RTL8153 */
1189 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1190 if ((ocp_data & AD_MASK) == 0x1000) {
1191 /* test for MAC address pass-through bit */
1192 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1193 if ((ocp_data & PASS_THRU_MASK) != 1) {
1194 netif_dbg(tp, probe, tp->netdev,
1195 "No efuse for RTL8153-AD MAC pass through\n");
1199 /* test for RTL8153-BND and RTL8153-BD */
1200 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1201 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1202 netif_dbg(tp, probe, tp->netdev,
1203 "Invalid variant for MAC pass through\n");
1208 /* returns _AUXMAC_#AABBCCDDEEFF# */
1209 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1210 obj = (union acpi_object *)buffer.pointer;
1211 if (!ACPI_SUCCESS(status))
1213 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1214 netif_warn(tp, probe, tp->netdev,
1215 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1216 obj->type, obj->string.length);
1219 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1220 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1221 netif_warn(tp, probe, tp->netdev,
1222 "Invalid header when reading pass-thru MAC addr\n");
1225 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1226 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1227 netif_warn(tp, probe, tp->netdev,
1228 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1233 memcpy(sa->sa_data, buf, 6);
1234 netif_info(tp, probe, tp->netdev,
1235 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1242 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1244 struct net_device *dev = tp->netdev;
1247 sa->sa_family = dev->type;
1249 if (tp->version == RTL_VER_01) {
1250 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1252 /* if device doesn't support MAC pass through this will
1253 * be expected to be non-zero
1255 ret = vendor_mac_passthru_addr_read(tp, sa);
1257 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1261 netif_err(tp, probe, dev, "Get ether addr fail\n");
1262 } else if (!is_valid_ether_addr(sa->sa_data)) {
1263 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1265 eth_hw_addr_random(dev);
1266 ether_addr_copy(sa->sa_data, dev->dev_addr);
1267 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1275 static int set_ethernet_addr(struct r8152 *tp)
1277 struct net_device *dev = tp->netdev;
1281 ret = determine_ethernet_addr(tp, &sa);
1285 if (tp->version == RTL_VER_01)
1286 ether_addr_copy(dev->dev_addr, sa.sa_data);
1288 ret = rtl8152_set_mac_address(dev, &sa);
1293 static void read_bulk_callback(struct urb *urb)
1295 struct net_device *netdev;
1296 int status = urb->status;
1299 unsigned long flags;
1309 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1312 if (!test_bit(WORK_ENABLE, &tp->flags))
1315 netdev = tp->netdev;
1317 /* When link down, the driver would cancel all bulks. */
1318 /* This avoid the re-submitting bulk */
1319 if (!netif_carrier_ok(netdev))
1322 usb_mark_last_busy(tp->udev);
1326 if (urb->actual_length < ETH_ZLEN)
1329 spin_lock_irqsave(&tp->rx_lock, flags);
1330 list_add_tail(&agg->list, &tp->rx_done);
1331 spin_unlock_irqrestore(&tp->rx_lock, flags);
1332 napi_schedule(&tp->napi);
1336 netif_device_detach(tp->netdev);
1339 return; /* the urb is in unlink state */
1341 if (net_ratelimit())
1342 netdev_warn(netdev, "maybe reset is needed?\n");
1345 if (net_ratelimit())
1346 netdev_warn(netdev, "Rx status %d\n", status);
1350 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1353 static void write_bulk_callback(struct urb *urb)
1355 struct net_device_stats *stats;
1356 struct net_device *netdev;
1359 unsigned long flags;
1360 int status = urb->status;
1370 netdev = tp->netdev;
1371 stats = &netdev->stats;
1373 if (net_ratelimit())
1374 netdev_warn(netdev, "Tx status %d\n", status);
1375 stats->tx_errors += agg->skb_num;
1377 stats->tx_packets += agg->skb_num;
1378 stats->tx_bytes += agg->skb_len;
1381 spin_lock_irqsave(&tp->tx_lock, flags);
1382 list_add_tail(&agg->list, &tp->tx_free);
1383 spin_unlock_irqrestore(&tp->tx_lock, flags);
1385 usb_autopm_put_interface_async(tp->intf);
1387 if (!netif_carrier_ok(netdev))
1390 if (!test_bit(WORK_ENABLE, &tp->flags))
1393 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1396 if (!skb_queue_empty(&tp->tx_queue))
1397 napi_schedule(&tp->napi);
1400 static void intr_callback(struct urb *urb)
1404 int status = urb->status;
1411 if (!test_bit(WORK_ENABLE, &tp->flags))
1414 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1418 case 0: /* success */
1420 case -ECONNRESET: /* unlink */
1422 netif_device_detach(tp->netdev);
1426 netif_info(tp, intr, tp->netdev,
1427 "Stop submitting intr, status %d\n", status);
1430 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1432 /* -EPIPE: should clear the halt */
1434 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1438 d = urb->transfer_buffer;
1439 if (INTR_LINK & __le16_to_cpu(d[0])) {
1440 if (!netif_carrier_ok(tp->netdev)) {
1441 set_bit(RTL8152_LINK_CHG, &tp->flags);
1442 schedule_delayed_work(&tp->schedule, 0);
1445 if (netif_carrier_ok(tp->netdev)) {
1446 netif_stop_queue(tp->netdev);
1447 set_bit(RTL8152_LINK_CHG, &tp->flags);
1448 schedule_delayed_work(&tp->schedule, 0);
1453 res = usb_submit_urb(urb, GFP_ATOMIC);
1454 if (res == -ENODEV) {
1456 netif_device_detach(tp->netdev);
1458 netif_err(tp, intr, tp->netdev,
1459 "can't resubmit intr, status %d\n", res);
1463 static inline void *rx_agg_align(void *data)
1465 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1468 static inline void *tx_agg_align(void *data)
1470 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1473 static void free_all_mem(struct r8152 *tp)
1477 for (i = 0; i < RTL8152_MAX_RX; i++) {
1478 usb_free_urb(tp->rx_info[i].urb);
1479 tp->rx_info[i].urb = NULL;
1481 kfree(tp->rx_info[i].buffer);
1482 tp->rx_info[i].buffer = NULL;
1483 tp->rx_info[i].head = NULL;
1486 for (i = 0; i < RTL8152_MAX_TX; i++) {
1487 usb_free_urb(tp->tx_info[i].urb);
1488 tp->tx_info[i].urb = NULL;
1490 kfree(tp->tx_info[i].buffer);
1491 tp->tx_info[i].buffer = NULL;
1492 tp->tx_info[i].head = NULL;
1495 usb_free_urb(tp->intr_urb);
1496 tp->intr_urb = NULL;
1498 kfree(tp->intr_buff);
1499 tp->intr_buff = NULL;
1502 static int alloc_all_mem(struct r8152 *tp)
1504 struct net_device *netdev = tp->netdev;
1505 struct usb_interface *intf = tp->intf;
1506 struct usb_host_interface *alt = intf->cur_altsetting;
1507 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1512 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1514 spin_lock_init(&tp->rx_lock);
1515 spin_lock_init(&tp->tx_lock);
1516 INIT_LIST_HEAD(&tp->tx_free);
1517 INIT_LIST_HEAD(&tp->rx_done);
1518 skb_queue_head_init(&tp->tx_queue);
1519 skb_queue_head_init(&tp->rx_queue);
1521 for (i = 0; i < RTL8152_MAX_RX; i++) {
1522 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1526 if (buf != rx_agg_align(buf)) {
1528 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1534 urb = usb_alloc_urb(0, GFP_KERNEL);
1540 INIT_LIST_HEAD(&tp->rx_info[i].list);
1541 tp->rx_info[i].context = tp;
1542 tp->rx_info[i].urb = urb;
1543 tp->rx_info[i].buffer = buf;
1544 tp->rx_info[i].head = rx_agg_align(buf);
1547 for (i = 0; i < RTL8152_MAX_TX; i++) {
1548 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1552 if (buf != tx_agg_align(buf)) {
1554 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1560 urb = usb_alloc_urb(0, GFP_KERNEL);
1566 INIT_LIST_HEAD(&tp->tx_info[i].list);
1567 tp->tx_info[i].context = tp;
1568 tp->tx_info[i].urb = urb;
1569 tp->tx_info[i].buffer = buf;
1570 tp->tx_info[i].head = tx_agg_align(buf);
1572 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1575 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1579 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1583 tp->intr_interval = (int)ep_intr->desc.bInterval;
1584 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1585 tp->intr_buff, INTBUFSIZE, intr_callback,
1586 tp, tp->intr_interval);
1595 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1597 struct tx_agg *agg = NULL;
1598 unsigned long flags;
1600 if (list_empty(&tp->tx_free))
1603 spin_lock_irqsave(&tp->tx_lock, flags);
1604 if (!list_empty(&tp->tx_free)) {
1605 struct list_head *cursor;
1607 cursor = tp->tx_free.next;
1608 list_del_init(cursor);
1609 agg = list_entry(cursor, struct tx_agg, list);
1611 spin_unlock_irqrestore(&tp->tx_lock, flags);
1616 /* r8152_csum_workaround()
1617 * The hw limites the value the transport offset. When the offset is out of the
1618 * range, calculate the checksum by sw.
1620 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1621 struct sk_buff_head *list)
1623 if (skb_shinfo(skb)->gso_size) {
1624 netdev_features_t features = tp->netdev->features;
1625 struct sk_buff_head seg_list;
1626 struct sk_buff *segs, *nskb;
1628 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1629 segs = skb_gso_segment(skb, features);
1630 if (IS_ERR(segs) || !segs)
1633 __skb_queue_head_init(&seg_list);
1639 __skb_queue_tail(&seg_list, nskb);
1642 skb_queue_splice(&seg_list, list);
1644 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1645 if (skb_checksum_help(skb) < 0)
1648 __skb_queue_head(list, skb);
1650 struct net_device_stats *stats;
1653 stats = &tp->netdev->stats;
1654 stats->tx_dropped++;
1659 /* msdn_giant_send_check()
1660 * According to the document of microsoft, the TCP Pseudo Header excludes the
1661 * packet length for IPv6 TCP large packets.
1663 static int msdn_giant_send_check(struct sk_buff *skb)
1665 const struct ipv6hdr *ipv6h;
1669 ret = skb_cow_head(skb, 0);
1673 ipv6h = ipv6_hdr(skb);
1677 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1682 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1684 if (skb_vlan_tag_present(skb)) {
1687 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1688 desc->opts2 |= cpu_to_le32(opts2);
1692 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1694 u32 opts2 = le32_to_cpu(desc->opts2);
1696 if (opts2 & RX_VLAN_TAG)
1697 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1698 swab16(opts2 & 0xffff));
1701 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1702 struct sk_buff *skb, u32 len, u32 transport_offset)
1704 u32 mss = skb_shinfo(skb)->gso_size;
1705 u32 opts1, opts2 = 0;
1706 int ret = TX_CSUM_SUCCESS;
1708 WARN_ON_ONCE(len > TX_LEN_MAX);
1710 opts1 = len | TX_FS | TX_LS;
1713 if (transport_offset > GTTCPHO_MAX) {
1714 netif_warn(tp, tx_err, tp->netdev,
1715 "Invalid transport offset 0x%x for TSO\n",
1721 switch (vlan_get_protocol(skb)) {
1722 case htons(ETH_P_IP):
1726 case htons(ETH_P_IPV6):
1727 if (msdn_giant_send_check(skb)) {
1739 opts1 |= transport_offset << GTTCPHO_SHIFT;
1740 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1741 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1744 if (transport_offset > TCPHO_MAX) {
1745 netif_warn(tp, tx_err, tp->netdev,
1746 "Invalid transport offset 0x%x\n",
1752 switch (vlan_get_protocol(skb)) {
1753 case htons(ETH_P_IP):
1755 ip_protocol = ip_hdr(skb)->protocol;
1758 case htons(ETH_P_IPV6):
1760 ip_protocol = ipv6_hdr(skb)->nexthdr;
1764 ip_protocol = IPPROTO_RAW;
1768 if (ip_protocol == IPPROTO_TCP)
1770 else if (ip_protocol == IPPROTO_UDP)
1775 opts2 |= transport_offset << TCPHO_SHIFT;
1778 desc->opts2 = cpu_to_le32(opts2);
1779 desc->opts1 = cpu_to_le32(opts1);
1785 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1787 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1791 __skb_queue_head_init(&skb_head);
1792 spin_lock(&tx_queue->lock);
1793 skb_queue_splice_init(tx_queue, &skb_head);
1794 spin_unlock(&tx_queue->lock);
1796 tx_data = agg->head;
1799 remain = agg_buf_sz;
1801 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1802 struct tx_desc *tx_desc;
1803 struct sk_buff *skb;
1807 skb = __skb_dequeue(&skb_head);
1811 len = skb->len + sizeof(*tx_desc);
1814 __skb_queue_head(&skb_head, skb);
1818 tx_data = tx_agg_align(tx_data);
1819 tx_desc = (struct tx_desc *)tx_data;
1821 offset = (u32)skb_transport_offset(skb);
1823 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1824 r8152_csum_workaround(tp, skb, &skb_head);
1828 rtl_tx_vlan_tag(tx_desc, skb);
1830 tx_data += sizeof(*tx_desc);
1833 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1834 struct net_device_stats *stats = &tp->netdev->stats;
1836 stats->tx_dropped++;
1837 dev_kfree_skb_any(skb);
1838 tx_data -= sizeof(*tx_desc);
1843 agg->skb_len += len;
1844 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1846 dev_kfree_skb_any(skb);
1848 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1850 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1854 if (!skb_queue_empty(&skb_head)) {
1855 spin_lock(&tx_queue->lock);
1856 skb_queue_splice(&skb_head, tx_queue);
1857 spin_unlock(&tx_queue->lock);
1860 netif_tx_lock(tp->netdev);
1862 if (netif_queue_stopped(tp->netdev) &&
1863 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1864 netif_wake_queue(tp->netdev);
1866 netif_tx_unlock(tp->netdev);
1868 ret = usb_autopm_get_interface_async(tp->intf);
1872 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1873 agg->head, (int)(tx_data - (u8 *)agg->head),
1874 (usb_complete_t)write_bulk_callback, agg);
1876 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1878 usb_autopm_put_interface_async(tp->intf);
1884 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1886 u8 checksum = CHECKSUM_NONE;
1889 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1892 opts2 = le32_to_cpu(rx_desc->opts2);
1893 opts3 = le32_to_cpu(rx_desc->opts3);
1895 if (opts2 & RD_IPV4_CS) {
1897 checksum = CHECKSUM_NONE;
1898 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1899 checksum = CHECKSUM_UNNECESSARY;
1900 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1901 checksum = CHECKSUM_UNNECESSARY;
1902 } else if (opts2 & RD_IPV6_CS) {
1903 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1904 checksum = CHECKSUM_UNNECESSARY;
1905 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1906 checksum = CHECKSUM_UNNECESSARY;
1913 static int rx_bottom(struct r8152 *tp, int budget)
1915 unsigned long flags;
1916 struct list_head *cursor, *next, rx_queue;
1917 int ret = 0, work_done = 0;
1918 struct napi_struct *napi = &tp->napi;
1920 if (!skb_queue_empty(&tp->rx_queue)) {
1921 while (work_done < budget) {
1922 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1923 struct net_device *netdev = tp->netdev;
1924 struct net_device_stats *stats = &netdev->stats;
1925 unsigned int pkt_len;
1931 napi_gro_receive(napi, skb);
1933 stats->rx_packets++;
1934 stats->rx_bytes += pkt_len;
1938 if (list_empty(&tp->rx_done))
1941 INIT_LIST_HEAD(&rx_queue);
1942 spin_lock_irqsave(&tp->rx_lock, flags);
1943 list_splice_init(&tp->rx_done, &rx_queue);
1944 spin_unlock_irqrestore(&tp->rx_lock, flags);
1946 list_for_each_safe(cursor, next, &rx_queue) {
1947 struct rx_desc *rx_desc;
1953 list_del_init(cursor);
1955 agg = list_entry(cursor, struct rx_agg, list);
1957 if (urb->actual_length < ETH_ZLEN)
1960 rx_desc = agg->head;
1961 rx_data = agg->head;
1962 len_used += sizeof(struct rx_desc);
1964 while (urb->actual_length > len_used) {
1965 struct net_device *netdev = tp->netdev;
1966 struct net_device_stats *stats = &netdev->stats;
1967 unsigned int pkt_len;
1968 struct sk_buff *skb;
1970 /* limite the skb numbers for rx_queue */
1971 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1974 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1975 if (pkt_len < ETH_ZLEN)
1978 len_used += pkt_len;
1979 if (urb->actual_length < len_used)
1982 pkt_len -= ETH_FCS_LEN;
1983 rx_data += sizeof(struct rx_desc);
1985 skb = napi_alloc_skb(napi, pkt_len);
1987 stats->rx_dropped++;
1991 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1992 memcpy(skb->data, rx_data, pkt_len);
1993 skb_put(skb, pkt_len);
1994 skb->protocol = eth_type_trans(skb, netdev);
1995 rtl_rx_vlan_tag(rx_desc, skb);
1996 if (work_done < budget) {
1997 napi_gro_receive(napi, skb);
1999 stats->rx_packets++;
2000 stats->rx_bytes += pkt_len;
2002 __skb_queue_tail(&tp->rx_queue, skb);
2006 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2007 rx_desc = (struct rx_desc *)rx_data;
2008 len_used = (int)(rx_data - (u8 *)agg->head);
2009 len_used += sizeof(struct rx_desc);
2014 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2016 urb->actual_length = 0;
2017 list_add_tail(&agg->list, next);
2021 if (!list_empty(&rx_queue)) {
2022 spin_lock_irqsave(&tp->rx_lock, flags);
2023 list_splice_tail(&rx_queue, &tp->rx_done);
2024 spin_unlock_irqrestore(&tp->rx_lock, flags);
2031 static void tx_bottom(struct r8152 *tp)
2038 if (skb_queue_empty(&tp->tx_queue))
2041 agg = r8152_get_tx_agg(tp);
2045 res = r8152_tx_agg_fill(tp, agg);
2047 struct net_device *netdev = tp->netdev;
2049 if (res == -ENODEV) {
2051 netif_device_detach(netdev);
2053 struct net_device_stats *stats = &netdev->stats;
2054 unsigned long flags;
2056 netif_warn(tp, tx_err, netdev,
2057 "failed tx_urb %d\n", res);
2058 stats->tx_dropped += agg->skb_num;
2060 spin_lock_irqsave(&tp->tx_lock, flags);
2061 list_add_tail(&agg->list, &tp->tx_free);
2062 spin_unlock_irqrestore(&tp->tx_lock, flags);
2068 static void bottom_half(struct r8152 *tp)
2070 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2073 if (!test_bit(WORK_ENABLE, &tp->flags))
2076 /* When link down, the driver would cancel all bulks. */
2077 /* This avoid the re-submitting bulk */
2078 if (!netif_carrier_ok(tp->netdev))
2081 clear_bit(SCHEDULE_NAPI, &tp->flags);
2086 static int r8152_poll(struct napi_struct *napi, int budget)
2088 struct r8152 *tp = container_of(napi, struct r8152, napi);
2091 work_done = rx_bottom(tp, budget);
2094 if (work_done < budget) {
2095 if (!napi_complete_done(napi, work_done))
2097 if (!list_empty(&tp->rx_done))
2098 napi_schedule(napi);
2099 else if (!skb_queue_empty(&tp->tx_queue) &&
2100 !list_empty(&tp->tx_free))
2101 napi_schedule(napi);
2109 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2113 /* The rx would be stopped, so skip submitting */
2114 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2115 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2118 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2119 agg->head, agg_buf_sz,
2120 (usb_complete_t)read_bulk_callback, agg);
2122 ret = usb_submit_urb(agg->urb, mem_flags);
2123 if (ret == -ENODEV) {
2125 netif_device_detach(tp->netdev);
2127 struct urb *urb = agg->urb;
2128 unsigned long flags;
2130 urb->actual_length = 0;
2131 spin_lock_irqsave(&tp->rx_lock, flags);
2132 list_add_tail(&agg->list, &tp->rx_done);
2133 spin_unlock_irqrestore(&tp->rx_lock, flags);
2135 netif_err(tp, rx_err, tp->netdev,
2136 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2138 napi_schedule(&tp->napi);
2144 static void rtl_drop_queued_tx(struct r8152 *tp)
2146 struct net_device_stats *stats = &tp->netdev->stats;
2147 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2148 struct sk_buff *skb;
2150 if (skb_queue_empty(tx_queue))
2153 __skb_queue_head_init(&skb_head);
2154 spin_lock_bh(&tx_queue->lock);
2155 skb_queue_splice_init(tx_queue, &skb_head);
2156 spin_unlock_bh(&tx_queue->lock);
2158 while ((skb = __skb_dequeue(&skb_head))) {
2160 stats->tx_dropped++;
2164 static void rtl8152_tx_timeout(struct net_device *netdev)
2166 struct r8152 *tp = netdev_priv(netdev);
2168 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2170 usb_queue_reset_device(tp->intf);
2173 static void rtl8152_set_rx_mode(struct net_device *netdev)
2175 struct r8152 *tp = netdev_priv(netdev);
2177 if (netif_carrier_ok(netdev)) {
2178 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2179 schedule_delayed_work(&tp->schedule, 0);
2183 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2185 struct r8152 *tp = netdev_priv(netdev);
2186 u32 mc_filter[2]; /* Multicast hash filter */
2190 netif_stop_queue(netdev);
2191 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2192 ocp_data &= ~RCR_ACPT_ALL;
2193 ocp_data |= RCR_AB | RCR_APM;
2195 if (netdev->flags & IFF_PROMISC) {
2196 /* Unconditionally log net taps. */
2197 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2198 ocp_data |= RCR_AM | RCR_AAP;
2199 mc_filter[1] = 0xffffffff;
2200 mc_filter[0] = 0xffffffff;
2201 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2202 (netdev->flags & IFF_ALLMULTI)) {
2203 /* Too many to filter perfectly -- accept all multicasts. */
2205 mc_filter[1] = 0xffffffff;
2206 mc_filter[0] = 0xffffffff;
2208 struct netdev_hw_addr *ha;
2212 netdev_for_each_mc_addr(ha, netdev) {
2213 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2215 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2220 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2221 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2223 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2224 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2225 netif_wake_queue(netdev);
2228 static netdev_features_t
2229 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2230 netdev_features_t features)
2232 u32 mss = skb_shinfo(skb)->gso_size;
2233 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2234 int offset = skb_transport_offset(skb);
2236 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2237 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2238 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2239 features &= ~NETIF_F_GSO_MASK;
2244 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2245 struct net_device *netdev)
2247 struct r8152 *tp = netdev_priv(netdev);
2249 skb_tx_timestamp(skb);
2251 skb_queue_tail(&tp->tx_queue, skb);
2253 if (!list_empty(&tp->tx_free)) {
2254 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2255 set_bit(SCHEDULE_NAPI, &tp->flags);
2256 schedule_delayed_work(&tp->schedule, 0);
2258 usb_mark_last_busy(tp->udev);
2259 napi_schedule(&tp->napi);
2261 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2262 netif_stop_queue(netdev);
2265 return NETDEV_TX_OK;
2268 static void r8152b_reset_packet_filter(struct r8152 *tp)
2272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2273 ocp_data &= ~FMC_FCR_MCU_EN;
2274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2275 ocp_data |= FMC_FCR_MCU_EN;
2276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2279 static void rtl8152_nic_reset(struct r8152 *tp)
2283 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2285 for (i = 0; i < 1000; i++) {
2286 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2288 usleep_range(100, 400);
2292 static void set_tx_qlen(struct r8152 *tp)
2294 struct net_device *netdev = tp->netdev;
2296 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2297 sizeof(struct tx_desc));
2300 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2302 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2305 static void rtl_set_eee_plus(struct r8152 *tp)
2310 speed = rtl8152_get_speed(tp);
2311 if (speed & _10bps) {
2312 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2313 ocp_data |= EEEP_CR_EEEP_TX;
2314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2316 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2317 ocp_data &= ~EEEP_CR_EEEP_TX;
2318 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2322 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2326 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2328 ocp_data |= RXDY_GATED_EN;
2330 ocp_data &= ~RXDY_GATED_EN;
2331 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2334 static int rtl_start_rx(struct r8152 *tp)
2338 INIT_LIST_HEAD(&tp->rx_done);
2339 for (i = 0; i < RTL8152_MAX_RX; i++) {
2340 INIT_LIST_HEAD(&tp->rx_info[i].list);
2341 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2346 if (ret && ++i < RTL8152_MAX_RX) {
2347 struct list_head rx_queue;
2348 unsigned long flags;
2350 INIT_LIST_HEAD(&rx_queue);
2353 struct rx_agg *agg = &tp->rx_info[i++];
2354 struct urb *urb = agg->urb;
2356 urb->actual_length = 0;
2357 list_add_tail(&agg->list, &rx_queue);
2358 } while (i < RTL8152_MAX_RX);
2360 spin_lock_irqsave(&tp->rx_lock, flags);
2361 list_splice_tail(&rx_queue, &tp->rx_done);
2362 spin_unlock_irqrestore(&tp->rx_lock, flags);
2368 static int rtl_stop_rx(struct r8152 *tp)
2372 for (i = 0; i < RTL8152_MAX_RX; i++)
2373 usb_kill_urb(tp->rx_info[i].urb);
2375 while (!skb_queue_empty(&tp->rx_queue))
2376 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2381 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2383 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2384 OWN_UPDATE | OWN_CLEAR);
2387 static int rtl_enable(struct r8152 *tp)
2391 r8152b_reset_packet_filter(tp);
2393 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2394 ocp_data |= CR_RE | CR_TE;
2395 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2397 switch (tp->version) {
2400 r8153b_rx_agg_chg_indicate(tp);
2406 rxdy_gated_en(tp, false);
2411 static int rtl8152_enable(struct r8152 *tp)
2413 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2417 rtl_set_eee_plus(tp);
2419 return rtl_enable(tp);
2422 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2424 u32 ocp_data = tp->coalesce / 8;
2426 switch (tp->version) {
2431 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2437 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2438 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2440 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2442 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2451 static void r8153_set_rx_early_size(struct r8152 *tp)
2453 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2455 switch (tp->version) {
2460 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2465 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2474 static int rtl8153_enable(struct r8152 *tp)
2476 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2480 rtl_set_eee_plus(tp);
2481 r8153_set_rx_early_timeout(tp);
2482 r8153_set_rx_early_size(tp);
2484 return rtl_enable(tp);
2487 static void rtl_disable(struct r8152 *tp)
2492 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2493 rtl_drop_queued_tx(tp);
2497 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2498 ocp_data &= ~RCR_ACPT_ALL;
2499 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2501 rtl_drop_queued_tx(tp);
2503 for (i = 0; i < RTL8152_MAX_TX; i++)
2504 usb_kill_urb(tp->tx_info[i].urb);
2506 rxdy_gated_en(tp, true);
2508 for (i = 0; i < 1000; i++) {
2509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2510 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2512 usleep_range(1000, 2000);
2515 for (i = 0; i < 1000; i++) {
2516 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2518 usleep_range(1000, 2000);
2523 rtl8152_nic_reset(tp);
2526 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2530 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2532 ocp_data |= POWER_CUT;
2534 ocp_data &= ~POWER_CUT;
2535 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2537 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2538 ocp_data &= ~RESUME_INDICATE;
2539 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2542 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2546 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2548 ocp_data |= CPCR_RX_VLAN;
2550 ocp_data &= ~CPCR_RX_VLAN;
2551 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2554 static int rtl8152_set_features(struct net_device *dev,
2555 netdev_features_t features)
2557 netdev_features_t changed = features ^ dev->features;
2558 struct r8152 *tp = netdev_priv(dev);
2561 ret = usb_autopm_get_interface(tp->intf);
2565 mutex_lock(&tp->control);
2567 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2568 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2569 rtl_rx_vlan_en(tp, true);
2571 rtl_rx_vlan_en(tp, false);
2574 mutex_unlock(&tp->control);
2576 usb_autopm_put_interface(tp->intf);
2582 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2584 static u32 __rtl_get_wol(struct r8152 *tp)
2589 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2590 if (ocp_data & LINK_ON_WAKE_EN)
2591 wolopts |= WAKE_PHY;
2593 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2594 if (ocp_data & UWF_EN)
2595 wolopts |= WAKE_UCAST;
2596 if (ocp_data & BWF_EN)
2597 wolopts |= WAKE_BCAST;
2598 if (ocp_data & MWF_EN)
2599 wolopts |= WAKE_MCAST;
2601 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2602 if (ocp_data & MAGIC_EN)
2603 wolopts |= WAKE_MAGIC;
2608 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2612 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2614 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2615 ocp_data &= ~LINK_ON_WAKE_EN;
2616 if (wolopts & WAKE_PHY)
2617 ocp_data |= LINK_ON_WAKE_EN;
2618 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2620 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2621 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2622 if (wolopts & WAKE_UCAST)
2624 if (wolopts & WAKE_BCAST)
2626 if (wolopts & WAKE_MCAST)
2628 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2630 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2632 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2633 ocp_data &= ~MAGIC_EN;
2634 if (wolopts & WAKE_MAGIC)
2635 ocp_data |= MAGIC_EN;
2636 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2638 if (wolopts & WAKE_ANY)
2639 device_set_wakeup_enable(&tp->udev->dev, true);
2641 device_set_wakeup_enable(&tp->udev->dev, false);
2644 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2646 /* MAC clock speed down */
2648 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2650 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2653 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2654 U1U2_SPDWN_EN | L1_SPDWN_EN);
2655 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2656 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2657 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2661 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2663 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2667 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2672 memset(u1u2, 0xff, sizeof(u1u2));
2674 memset(u1u2, 0x00, sizeof(u1u2));
2676 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2679 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2683 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2685 ocp_data |= LPM_U1U2_EN;
2687 ocp_data &= ~LPM_U1U2_EN;
2689 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2692 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2696 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2698 ocp_data |= U2P3_ENABLE;
2700 ocp_data &= ~U2P3_ENABLE;
2701 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2704 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2708 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2711 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2714 static void r8153b_green_en(struct r8152 *tp, bool enable)
2719 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2720 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2721 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2723 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2724 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2725 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2728 data = sram_read(tp, SRAM_GREEN_CFG);
2729 data |= GREEN_ETH_EN;
2730 sram_write(tp, SRAM_GREEN_CFG, data);
2732 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2735 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2740 for (i = 0; i < 500; i++) {
2741 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2742 data &= PHY_STAT_MASK;
2744 if (data == desired)
2746 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2747 data == PHY_STAT_EXT_INIT) {
2757 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2759 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2762 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2763 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2765 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2767 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2771 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2772 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2774 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2775 ocp_data &= ~BIT(0);
2776 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2778 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2779 ocp_data &= ~PCUT_STATUS;
2780 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2782 data = r8153_phy_status(tp, 0);
2785 case PHY_STAT_PWRDN:
2786 case PHY_STAT_EXT_INIT:
2788 test_bit(GREEN_ETHERNET, &tp->flags));
2790 data = r8152_mdio_read(tp, MII_BMCR);
2791 data &= ~BMCR_PDOWN;
2793 r8152_mdio_write(tp, MII_BMCR, data);
2795 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2799 if (data != PHY_STAT_LAN_ON)
2800 netif_warn(tp, link, tp->netdev,
2807 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2811 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2813 ocp_data |= PWR_EN | PHASE2_EN;
2815 ocp_data &= ~(PWR_EN | PHASE2_EN);
2816 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2818 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2819 ocp_data &= ~PCUT_STATUS;
2820 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2823 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2827 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2829 ocp_data |= PWR_EN | PHASE2_EN;
2831 ocp_data &= ~PWR_EN;
2832 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2834 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2835 ocp_data &= ~PCUT_STATUS;
2836 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2839 static void r8153_queue_wake(struct r8152 *tp, bool enable)
2843 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
2845 ocp_data |= UPCOMING_RUNTIME_D3;
2847 ocp_data &= ~UPCOMING_RUNTIME_D3;
2848 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
2850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
2851 ocp_data &= ~LINK_CHG_EVENT;
2852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
2854 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
2855 ocp_data &= ~LINK_CHANGE_FLAG;
2856 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
2859 static bool rtl_can_wakeup(struct r8152 *tp)
2861 struct usb_device *udev = tp->udev;
2863 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2866 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2871 __rtl_set_wol(tp, WAKE_ANY);
2873 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2876 ocp_data |= LINK_OFF_WAKE_EN;
2877 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2879 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2883 __rtl_set_wol(tp, tp->saved_wolopts);
2885 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2888 ocp_data &= ~LINK_OFF_WAKE_EN;
2889 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2891 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2895 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2898 r8153_u1u2en(tp, false);
2899 r8153_u2p3en(tp, false);
2900 r8153_mac_clk_spd(tp, true);
2901 rtl_runtime_suspend_enable(tp, true);
2903 rtl_runtime_suspend_enable(tp, false);
2904 r8153_mac_clk_spd(tp, false);
2906 switch (tp->version) {
2913 r8153_u2p3en(tp, true);
2917 r8153_u1u2en(tp, true);
2921 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2924 r8153_queue_wake(tp, true);
2925 r8153b_u1u2en(tp, false);
2926 r8153_u2p3en(tp, false);
2927 rtl_runtime_suspend_enable(tp, true);
2928 r8153b_ups_en(tp, true);
2930 r8153b_ups_en(tp, false);
2931 r8153_queue_wake(tp, false);
2932 rtl_runtime_suspend_enable(tp, false);
2933 r8153_u2p3en(tp, true);
2934 r8153b_u1u2en(tp, true);
2938 static void r8153_teredo_off(struct r8152 *tp)
2942 switch (tp->version) {
2950 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2951 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2958 /* The bit 0 ~ 7 are relative with teredo settings. They are
2959 * W1C (write 1 to clear), so set all 1 to disable it.
2961 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2968 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2969 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2970 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2973 static void rtl_reset_bmu(struct r8152 *tp)
2977 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2978 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2979 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2980 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2981 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2984 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2987 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2988 LINKENA | DIS_SDSAVE);
2990 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2996 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2998 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2999 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3000 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3003 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3007 r8152_mmd_indirect(tp, dev, reg);
3008 data = ocp_reg_read(tp, OCP_EEE_DATA);
3009 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3014 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3016 r8152_mmd_indirect(tp, dev, reg);
3017 ocp_reg_write(tp, OCP_EEE_DATA, data);
3018 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3021 static void r8152_eee_en(struct r8152 *tp, bool enable)
3023 u16 config1, config2, config3;
3026 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3027 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3028 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3029 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3032 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3033 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3034 config1 |= sd_rise_time(1);
3035 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3036 config3 |= fast_snr(42);
3038 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3039 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3041 config1 |= sd_rise_time(7);
3042 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3043 config3 |= fast_snr(511);
3046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3047 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3048 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3049 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3052 static void r8152b_enable_eee(struct r8152 *tp)
3054 r8152_eee_en(tp, true);
3055 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3058 static void r8152b_enable_fc(struct r8152 *tp)
3062 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3063 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3064 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3067 static void rtl8152_disable(struct r8152 *tp)
3069 r8152_aldps_en(tp, false);
3071 r8152_aldps_en(tp, true);
3074 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3076 r8152b_enable_eee(tp);
3077 r8152_aldps_en(tp, true);
3078 r8152b_enable_fc(tp);
3080 set_bit(PHY_RESET, &tp->flags);
3083 static void r8152b_exit_oob(struct r8152 *tp)
3088 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3089 ocp_data &= ~RCR_ACPT_ALL;
3090 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3092 rxdy_gated_en(tp, true);
3093 r8153_teredo_off(tp);
3094 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3095 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3097 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3098 ocp_data &= ~NOW_IS_OOB;
3099 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3101 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3102 ocp_data &= ~MCU_BORW_EN;
3103 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3105 for (i = 0; i < 1000; i++) {
3106 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3107 if (ocp_data & LINK_LIST_READY)
3109 usleep_range(1000, 2000);
3112 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3113 ocp_data |= RE_INIT_LL;
3114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3116 for (i = 0; i < 1000; i++) {
3117 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3118 if (ocp_data & LINK_LIST_READY)
3120 usleep_range(1000, 2000);
3123 rtl8152_nic_reset(tp);
3125 /* rx share fifo credit full threshold */
3126 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3128 if (tp->udev->speed == USB_SPEED_FULL ||
3129 tp->udev->speed == USB_SPEED_LOW) {
3130 /* rx share fifo credit near full threshold */
3131 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3133 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3136 /* rx share fifo credit near full threshold */
3137 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3139 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3143 /* TX share fifo free credit full threshold */
3144 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3146 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3147 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3148 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3149 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3151 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3153 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3156 ocp_data |= TCR0_AUTO_FIFO;
3157 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3160 static void r8152b_enter_oob(struct r8152 *tp)
3165 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3166 ocp_data &= ~NOW_IS_OOB;
3167 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3169 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3170 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3171 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3175 for (i = 0; i < 1000; i++) {
3176 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3177 if (ocp_data & LINK_LIST_READY)
3179 usleep_range(1000, 2000);
3182 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3183 ocp_data |= RE_INIT_LL;
3184 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3186 for (i = 0; i < 1000; i++) {
3187 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3188 if (ocp_data & LINK_LIST_READY)
3190 usleep_range(1000, 2000);
3193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3195 rtl_rx_vlan_en(tp, true);
3197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
3198 ocp_data |= ALDPS_PROXY_MODE;
3199 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
3201 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3202 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3203 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3205 rxdy_gated_en(tp, false);
3207 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3208 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3209 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3212 static int r8153_patch_request(struct r8152 *tp, bool request)
3217 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3219 data |= PATCH_REQUEST;
3221 data &= ~PATCH_REQUEST;
3222 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3224 for (i = 0; request && i < 5000; i++) {
3225 usleep_range(1000, 2000);
3226 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3230 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3231 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3232 r8153_patch_request(tp, false);
3239 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3243 data = ocp_reg_read(tp, OCP_POWER_CFG);
3246 ocp_reg_write(tp, OCP_POWER_CFG, data);
3251 ocp_reg_write(tp, OCP_POWER_CFG, data);
3252 for (i = 0; i < 20; i++) {
3253 usleep_range(1000, 2000);
3254 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3260 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3262 r8153_aldps_en(tp, enable);
3265 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3267 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3270 static void r8153_eee_en(struct r8152 *tp, bool enable)
3275 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3276 config = ocp_reg_read(tp, OCP_EEE_CFG);
3279 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3282 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3283 config &= ~EEE10_EN;
3286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3287 ocp_reg_write(tp, OCP_EEE_CFG, config);
3290 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3292 r8153_eee_en(tp, enable);
3295 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3297 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3300 static void r8153b_enable_fc(struct r8152 *tp)
3302 r8152b_enable_fc(tp);
3303 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3306 static void r8153_hw_phy_cfg(struct r8152 *tp)
3311 /* disable ALDPS before updating the PHY parameters */
3312 r8153_aldps_en(tp, false);
3314 /* disable EEE before updating the PHY parameters */
3315 r8153_eee_en(tp, false);
3316 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3318 if (tp->version == RTL_VER_03) {
3319 data = ocp_reg_read(tp, OCP_EEE_CFG);
3320 data &= ~CTAP_SHORT_EN;
3321 ocp_reg_write(tp, OCP_EEE_CFG, data);
3324 data = ocp_reg_read(tp, OCP_POWER_CFG);
3325 data |= EEE_CLKDIV_EN;
3326 ocp_reg_write(tp, OCP_POWER_CFG, data);
3328 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3329 data |= EN_10M_BGOFF;
3330 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3331 data = ocp_reg_read(tp, OCP_POWER_CFG);
3332 data |= EN_10M_PLLOFF;
3333 ocp_reg_write(tp, OCP_POWER_CFG, data);
3334 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3336 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3337 ocp_data |= PFM_PWM_SWITCH;
3338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3340 /* Enable LPF corner auto tune */
3341 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3343 /* Adjust 10M Amplitude */
3344 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3345 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3347 r8153_eee_en(tp, true);
3348 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3350 r8153_aldps_en(tp, true);
3351 r8152b_enable_fc(tp);
3353 switch (tp->version) {
3360 r8153_u2p3en(tp, true);
3364 set_bit(PHY_RESET, &tp->flags);
3367 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3371 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3373 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3374 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3379 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3381 u32 ocp_data, ups_flags = 0;
3384 /* disable ALDPS before updating the PHY parameters */
3385 r8153b_aldps_en(tp, false);
3387 /* disable EEE before updating the PHY parameters */
3388 r8153b_eee_en(tp, false);
3389 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3391 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3393 data = sram_read(tp, SRAM_GREEN_CFG);
3395 sram_write(tp, SRAM_GREEN_CFG, data);
3396 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3397 data |= PGA_RETURN_EN;
3398 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3400 /* ADC Bias Calibration:
3401 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3402 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3405 ocp_data = r8152_efuse_read(tp, 0x7d);
3406 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3408 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3410 /* ups mode tx-link-pulse timing adjustment:
3411 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3412 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3414 ocp_data = ocp_reg_read(tp, 0xc426);
3417 u32 swr_cnt_1ms_ini;
3419 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3420 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3421 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3422 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3426 ocp_data |= PFM_PWM_SWITCH;
3427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3430 if (!r8153_patch_request(tp, true)) {
3431 data = ocp_reg_read(tp, OCP_POWER_CFG);
3432 data |= EEE_CLKDIV_EN;
3433 ocp_reg_write(tp, OCP_POWER_CFG, data);
3435 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3436 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3437 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3439 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3440 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3442 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3443 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3444 UPS_FLAGS_EEE_PLLOFF_GIGA;
3446 r8153_patch_request(tp, false);
3449 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3451 r8153b_eee_en(tp, true);
3452 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3454 r8153b_aldps_en(tp, true);
3455 r8153b_enable_fc(tp);
3456 r8153_u2p3en(tp, true);
3458 set_bit(PHY_RESET, &tp->flags);
3461 static void r8153_first_init(struct r8152 *tp)
3466 r8153_mac_clk_spd(tp, false);
3467 rxdy_gated_en(tp, true);
3468 r8153_teredo_off(tp);
3470 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3471 ocp_data &= ~RCR_ACPT_ALL;
3472 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3474 rtl8152_nic_reset(tp);
3477 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3478 ocp_data &= ~NOW_IS_OOB;
3479 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3481 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3482 ocp_data &= ~MCU_BORW_EN;
3483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3485 for (i = 0; i < 1000; i++) {
3486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3487 if (ocp_data & LINK_LIST_READY)
3489 usleep_range(1000, 2000);
3492 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3493 ocp_data |= RE_INIT_LL;
3494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3496 for (i = 0; i < 1000; i++) {
3497 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3498 if (ocp_data & LINK_LIST_READY)
3500 usleep_range(1000, 2000);
3503 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3505 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3507 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3509 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3510 ocp_data |= TCR0_AUTO_FIFO;
3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3513 rtl8152_nic_reset(tp);
3515 /* rx share fifo credit full threshold */
3516 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3519 /* TX share fifo free credit full threshold */
3520 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3523 static void r8153_enter_oob(struct r8152 *tp)
3528 r8153_mac_clk_spd(tp, true);
3530 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3531 ocp_data &= ~NOW_IS_OOB;
3532 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3537 for (i = 0; i < 1000; i++) {
3538 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3539 if (ocp_data & LINK_LIST_READY)
3541 usleep_range(1000, 2000);
3544 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3545 ocp_data |= RE_INIT_LL;
3546 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3548 for (i = 0; i < 1000; i++) {
3549 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3550 if (ocp_data & LINK_LIST_READY)
3552 usleep_range(1000, 2000);
3555 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3558 switch (tp->version) {
3563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3564 ocp_data &= ~TEREDO_WAKE_MASK;
3565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3570 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3571 * type. Set it to zero. bits[7:0] are the W1C bits about
3572 * the events. Set them to all 1 to clear them.
3574 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3581 rtl_rx_vlan_en(tp, true);
3583 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
3584 ocp_data |= ALDPS_PROXY_MODE;
3585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
3587 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3588 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3589 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3591 rxdy_gated_en(tp, false);
3593 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3594 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3595 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3598 static void rtl8153_disable(struct r8152 *tp)
3600 r8153_aldps_en(tp, false);
3603 r8153_aldps_en(tp, true);
3606 static void rtl8153b_disable(struct r8152 *tp)
3608 r8153b_aldps_en(tp, false);
3611 r8153b_aldps_en(tp, true);
3614 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3616 u16 bmcr, anar, gbcr;
3617 enum spd_duplex speed_duplex;
3620 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3621 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3622 ADVERTISE_100HALF | ADVERTISE_100FULL);
3623 if (tp->mii.supports_gmii) {
3624 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3625 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3630 if (autoneg == AUTONEG_DISABLE) {
3631 if (speed == SPEED_10) {
3633 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3634 speed_duplex = FORCE_10M_HALF;
3635 } else if (speed == SPEED_100) {
3636 bmcr = BMCR_SPEED100;
3637 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3638 speed_duplex = FORCE_100M_HALF;
3639 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3640 bmcr = BMCR_SPEED1000;
3641 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3642 speed_duplex = NWAY_1000M_FULL;
3648 if (duplex == DUPLEX_FULL) {
3649 bmcr |= BMCR_FULLDPLX;
3650 if (speed != SPEED_1000)
3654 if (speed == SPEED_10) {
3655 if (duplex == DUPLEX_FULL) {
3656 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3657 speed_duplex = NWAY_10M_FULL;
3659 anar |= ADVERTISE_10HALF;
3660 speed_duplex = NWAY_10M_HALF;
3662 } else if (speed == SPEED_100) {
3663 if (duplex == DUPLEX_FULL) {
3664 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3665 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3666 speed_duplex = NWAY_100M_FULL;
3668 anar |= ADVERTISE_10HALF;
3669 anar |= ADVERTISE_100HALF;
3670 speed_duplex = NWAY_100M_HALF;
3672 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3673 if (duplex == DUPLEX_FULL) {
3674 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3675 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3676 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3678 anar |= ADVERTISE_10HALF;
3679 anar |= ADVERTISE_100HALF;
3680 gbcr |= ADVERTISE_1000HALF;
3682 speed_duplex = NWAY_1000M_FULL;
3688 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3691 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3694 if (tp->mii.supports_gmii)
3695 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3697 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3698 r8152_mdio_write(tp, MII_BMCR, bmcr);
3700 switch (tp->version) {
3703 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3704 UPS_FLAGS_SPEED_MASK);
3711 if (bmcr & BMCR_RESET) {
3714 for (i = 0; i < 50; i++) {
3716 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3725 static void rtl8152_up(struct r8152 *tp)
3727 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3730 r8152_aldps_en(tp, false);
3731 r8152b_exit_oob(tp);
3732 r8152_aldps_en(tp, true);
3735 static void rtl8152_down(struct r8152 *tp)
3737 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3738 rtl_drop_queued_tx(tp);
3742 r8152_power_cut_en(tp, false);
3743 r8152_aldps_en(tp, false);
3744 r8152b_enter_oob(tp);
3745 r8152_aldps_en(tp, true);
3748 static void rtl8153_up(struct r8152 *tp)
3750 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3753 r8153_u1u2en(tp, false);
3754 r8153_u2p3en(tp, false);
3755 r8153_aldps_en(tp, false);
3756 r8153_first_init(tp);
3757 r8153_aldps_en(tp, true);
3759 switch (tp->version) {
3766 r8153_u2p3en(tp, true);
3770 r8153_u1u2en(tp, true);
3773 static void rtl8153_down(struct r8152 *tp)
3775 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3776 rtl_drop_queued_tx(tp);
3780 r8153_u1u2en(tp, false);
3781 r8153_u2p3en(tp, false);
3782 r8153_power_cut_en(tp, false);
3783 r8153_aldps_en(tp, false);
3784 r8153_enter_oob(tp);
3785 r8153_aldps_en(tp, true);
3788 static void rtl8153b_up(struct r8152 *tp)
3790 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3793 r8153b_u1u2en(tp, false);
3794 r8153_u2p3en(tp, false);
3795 r8153b_aldps_en(tp, false);
3797 r8153_first_init(tp);
3798 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3800 r8153b_aldps_en(tp, true);
3801 r8153_u2p3en(tp, true);
3802 r8153b_u1u2en(tp, true);
3805 static void rtl8153b_down(struct r8152 *tp)
3807 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3808 rtl_drop_queued_tx(tp);
3812 r8153b_u1u2en(tp, false);
3813 r8153_u2p3en(tp, false);
3814 r8153b_power_cut_en(tp, false);
3815 r8153b_aldps_en(tp, false);
3816 r8153_enter_oob(tp);
3817 r8153b_aldps_en(tp, true);
3820 static bool rtl8152_in_nway(struct r8152 *tp)
3824 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3825 tp->ocp_base = 0x2000;
3826 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3827 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3829 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3830 if (nway_state & 0xc000)
3836 static bool rtl8153_in_nway(struct r8152 *tp)
3838 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3840 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3846 static void set_carrier(struct r8152 *tp)
3848 struct net_device *netdev = tp->netdev;
3849 struct napi_struct *napi = &tp->napi;
3852 speed = rtl8152_get_speed(tp);
3854 if (speed & LINK_STATUS) {
3855 if (!netif_carrier_ok(netdev)) {
3856 tp->rtl_ops.enable(tp);
3857 netif_stop_queue(netdev);
3859 netif_carrier_on(netdev);
3861 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3862 _rtl8152_set_rx_mode(netdev);
3863 napi_enable(&tp->napi);
3864 netif_wake_queue(netdev);
3865 netif_info(tp, link, netdev, "carrier on\n");
3866 } else if (netif_queue_stopped(netdev) &&
3867 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3868 netif_wake_queue(netdev);
3871 if (netif_carrier_ok(netdev)) {
3872 netif_carrier_off(netdev);
3874 tp->rtl_ops.disable(tp);
3876 netif_info(tp, link, netdev, "carrier off\n");
3881 static void rtl_work_func_t(struct work_struct *work)
3883 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3885 /* If the device is unplugged or !netif_running(), the workqueue
3886 * doesn't need to wake the device, and could return directly.
3888 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3891 if (usb_autopm_get_interface(tp->intf) < 0)
3894 if (!test_bit(WORK_ENABLE, &tp->flags))
3897 if (!mutex_trylock(&tp->control)) {
3898 schedule_delayed_work(&tp->schedule, 0);
3902 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3905 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3906 _rtl8152_set_rx_mode(tp->netdev);
3908 /* don't schedule napi before linking */
3909 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3910 netif_carrier_ok(tp->netdev))
3911 napi_schedule(&tp->napi);
3913 mutex_unlock(&tp->control);
3916 usb_autopm_put_interface(tp->intf);
3919 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3921 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3923 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3926 if (usb_autopm_get_interface(tp->intf) < 0)
3929 mutex_lock(&tp->control);
3931 tp->rtl_ops.hw_phy_cfg(tp);
3933 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3935 mutex_unlock(&tp->control);
3937 usb_autopm_put_interface(tp->intf);
3940 #ifdef CONFIG_PM_SLEEP
3941 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3944 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3947 case PM_HIBERNATION_PREPARE:
3948 case PM_SUSPEND_PREPARE:
3949 usb_autopm_get_interface(tp->intf);
3952 case PM_POST_HIBERNATION:
3953 case PM_POST_SUSPEND:
3954 usb_autopm_put_interface(tp->intf);
3957 case PM_POST_RESTORE:
3958 case PM_RESTORE_PREPARE:
3967 static int rtl8152_open(struct net_device *netdev)
3969 struct r8152 *tp = netdev_priv(netdev);
3972 res = alloc_all_mem(tp);
3976 res = usb_autopm_get_interface(tp->intf);
3980 mutex_lock(&tp->control);
3984 netif_carrier_off(netdev);
3985 netif_start_queue(netdev);
3986 set_bit(WORK_ENABLE, &tp->flags);
3988 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3991 netif_device_detach(tp->netdev);
3992 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3996 napi_enable(&tp->napi);
3998 mutex_unlock(&tp->control);
4000 usb_autopm_put_interface(tp->intf);
4001 #ifdef CONFIG_PM_SLEEP
4002 tp->pm_notifier.notifier_call = rtl_notifier;
4003 register_pm_notifier(&tp->pm_notifier);
4008 mutex_unlock(&tp->control);
4009 usb_autopm_put_interface(tp->intf);
4016 static int rtl8152_close(struct net_device *netdev)
4018 struct r8152 *tp = netdev_priv(netdev);
4021 #ifdef CONFIG_PM_SLEEP
4022 unregister_pm_notifier(&tp->pm_notifier);
4024 napi_disable(&tp->napi);
4025 clear_bit(WORK_ENABLE, &tp->flags);
4026 usb_kill_urb(tp->intr_urb);
4027 cancel_delayed_work_sync(&tp->schedule);
4028 netif_stop_queue(netdev);
4030 res = usb_autopm_get_interface(tp->intf);
4031 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
4032 rtl_drop_queued_tx(tp);
4035 mutex_lock(&tp->control);
4037 tp->rtl_ops.down(tp);
4039 mutex_unlock(&tp->control);
4041 usb_autopm_put_interface(tp->intf);
4049 static void rtl_tally_reset(struct r8152 *tp)
4053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4054 ocp_data |= TALLY_RESET;
4055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4058 static void r8152b_init(struct r8152 *tp)
4063 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4066 data = r8152_mdio_read(tp, MII_BMCR);
4067 if (data & BMCR_PDOWN) {
4068 data &= ~BMCR_PDOWN;
4069 r8152_mdio_write(tp, MII_BMCR, data);
4072 r8152_aldps_en(tp, false);
4074 if (tp->version == RTL_VER_01) {
4075 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4076 ocp_data &= ~LED_MODE_MASK;
4077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4080 r8152_power_cut_en(tp, false);
4082 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4083 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4084 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4085 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4086 ocp_data &= ~MCU_CLK_RATIO_MASK;
4087 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4088 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4089 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4090 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4091 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4093 rtl_tally_reset(tp);
4095 /* enable rx aggregation */
4096 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4097 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4098 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4101 static void r8153_init(struct r8152 *tp)
4107 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4110 r8153_u1u2en(tp, false);
4112 for (i = 0; i < 500; i++) {
4113 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4119 data = r8153_phy_status(tp, 0);
4121 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4122 tp->version == RTL_VER_05)
4123 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4125 data = r8152_mdio_read(tp, MII_BMCR);
4126 if (data & BMCR_PDOWN) {
4127 data &= ~BMCR_PDOWN;
4128 r8152_mdio_write(tp, MII_BMCR, data);
4131 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4133 r8153_u2p3en(tp, false);
4135 if (tp->version == RTL_VER_04) {
4136 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4137 ocp_data &= ~pwd_dn_scale_mask;
4138 ocp_data |= pwd_dn_scale(96);
4139 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4141 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4142 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4143 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4144 } else if (tp->version == RTL_VER_05) {
4145 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4146 ocp_data &= ~ECM_ALDPS;
4147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4149 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4150 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4151 ocp_data &= ~DYNAMIC_BURST;
4153 ocp_data |= DYNAMIC_BURST;
4154 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4155 } else if (tp->version == RTL_VER_06) {
4156 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4157 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4158 ocp_data &= ~DYNAMIC_BURST;
4160 ocp_data |= DYNAMIC_BURST;
4161 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4164 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4165 ocp_data |= EP4_FULL_FC;
4166 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4168 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4169 ocp_data &= ~TIMER11_EN;
4170 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4172 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4173 ocp_data &= ~LED_MODE_MASK;
4174 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4176 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4177 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4178 ocp_data |= LPM_TIMER_500MS;
4180 ocp_data |= LPM_TIMER_500US;
4181 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4183 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4184 ocp_data &= ~SEN_VAL_MASK;
4185 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4186 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4188 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4190 r8153_power_cut_en(tp, false);
4191 r8153_u1u2en(tp, true);
4192 r8153_mac_clk_spd(tp, false);
4193 usb_enable_lpm(tp->udev);
4195 /* rx aggregation */
4196 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4197 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4198 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4199 ocp_data |= RX_AGG_DISABLE;
4201 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4203 rtl_tally_reset(tp);
4205 switch (tp->udev->speed) {
4206 case USB_SPEED_SUPER:
4207 case USB_SPEED_SUPER_PLUS:
4208 tp->coalesce = COALESCE_SUPER;
4210 case USB_SPEED_HIGH:
4211 tp->coalesce = COALESCE_HIGH;
4214 tp->coalesce = COALESCE_SLOW;
4219 static void r8153b_init(struct r8152 *tp)
4225 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4228 r8153b_u1u2en(tp, false);
4230 for (i = 0; i < 500; i++) {
4231 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4237 data = r8153_phy_status(tp, 0);
4239 data = r8152_mdio_read(tp, MII_BMCR);
4240 if (data & BMCR_PDOWN) {
4241 data &= ~BMCR_PDOWN;
4242 r8152_mdio_write(tp, MII_BMCR, data);
4245 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4247 r8153_u2p3en(tp, false);
4249 /* MSC timer = 0xfff * 8ms = 32760 ms */
4250 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4252 /* U1/U2/L1 idle timer. 500 us */
4253 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4255 r8153b_power_cut_en(tp, false);
4256 r8153b_ups_en(tp, false);
4257 r8153_queue_wake(tp, false);
4258 rtl_runtime_suspend_enable(tp, false);
4259 r8153b_u1u2en(tp, true);
4260 usb_enable_lpm(tp->udev);
4262 /* MAC clock speed down */
4263 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4264 ocp_data |= MAC_CLK_SPDWN_EN;
4265 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4267 set_bit(GREEN_ETHERNET, &tp->flags);
4269 /* rx aggregation */
4270 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4271 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4272 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4274 rtl_tally_reset(tp);
4276 tp->coalesce = 15000; /* 15 us */
4279 static int rtl8152_pre_reset(struct usb_interface *intf)
4281 struct r8152 *tp = usb_get_intfdata(intf);
4282 struct net_device *netdev;
4287 netdev = tp->netdev;
4288 if (!netif_running(netdev))
4291 netif_stop_queue(netdev);
4292 napi_disable(&tp->napi);
4293 clear_bit(WORK_ENABLE, &tp->flags);
4294 usb_kill_urb(tp->intr_urb);
4295 cancel_delayed_work_sync(&tp->schedule);
4296 if (netif_carrier_ok(netdev)) {
4297 mutex_lock(&tp->control);
4298 tp->rtl_ops.disable(tp);
4299 mutex_unlock(&tp->control);
4305 static int rtl8152_post_reset(struct usb_interface *intf)
4307 struct r8152 *tp = usb_get_intfdata(intf);
4308 struct net_device *netdev;
4314 /* reset the MAC adddress in case of policy change */
4315 if (determine_ethernet_addr(tp, &sa) >= 0) {
4317 dev_set_mac_address (tp->netdev, &sa, NULL);
4321 netdev = tp->netdev;
4322 if (!netif_running(netdev))
4325 set_bit(WORK_ENABLE, &tp->flags);
4326 if (netif_carrier_ok(netdev)) {
4327 mutex_lock(&tp->control);
4328 tp->rtl_ops.enable(tp);
4330 _rtl8152_set_rx_mode(netdev);
4331 mutex_unlock(&tp->control);
4334 napi_enable(&tp->napi);
4335 netif_wake_queue(netdev);
4336 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4338 if (!list_empty(&tp->rx_done))
4339 napi_schedule(&tp->napi);
4344 static bool delay_autosuspend(struct r8152 *tp)
4346 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4347 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4349 /* This means a linking change occurs and the driver doesn't detect it,
4350 * yet. If the driver has disabled tx/rx and hw is linking on, the
4351 * device wouldn't wake up by receiving any packet.
4353 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4356 /* If the linking down is occurred by nway, the device may miss the
4357 * linking change event. And it wouldn't wake when linking on.
4359 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4361 else if (!skb_queue_empty(&tp->tx_queue))
4367 static int rtl8152_runtime_resume(struct r8152 *tp)
4369 struct net_device *netdev = tp->netdev;
4371 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4372 struct napi_struct *napi = &tp->napi;
4374 tp->rtl_ops.autosuspend_en(tp, false);
4376 set_bit(WORK_ENABLE, &tp->flags);
4378 if (netif_carrier_ok(netdev)) {
4379 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4382 netif_carrier_off(netdev);
4383 tp->rtl_ops.disable(tp);
4384 netif_info(tp, link, netdev, "linking down\n");
4389 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4390 smp_mb__after_atomic();
4392 if (!list_empty(&tp->rx_done))
4393 napi_schedule(&tp->napi);
4395 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4397 if (netdev->flags & IFF_UP)
4398 tp->rtl_ops.autosuspend_en(tp, false);
4400 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4406 static int rtl8152_system_resume(struct r8152 *tp)
4408 struct net_device *netdev = tp->netdev;
4410 netif_device_attach(netdev);
4412 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4414 netif_carrier_off(netdev);
4415 set_bit(WORK_ENABLE, &tp->flags);
4416 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4422 static int rtl8152_runtime_suspend(struct r8152 *tp)
4424 struct net_device *netdev = tp->netdev;
4427 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4428 smp_mb__after_atomic();
4430 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4433 if (netif_carrier_ok(netdev)) {
4436 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4437 ocp_data = rcr & ~RCR_ACPT_ALL;
4438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4439 rxdy_gated_en(tp, true);
4440 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4442 if (!(ocp_data & RXFIFO_EMPTY)) {
4443 rxdy_gated_en(tp, false);
4444 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4445 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4446 smp_mb__after_atomic();
4452 clear_bit(WORK_ENABLE, &tp->flags);
4453 usb_kill_urb(tp->intr_urb);
4455 tp->rtl_ops.autosuspend_en(tp, true);
4457 if (netif_carrier_ok(netdev)) {
4458 struct napi_struct *napi = &tp->napi;
4462 rxdy_gated_en(tp, false);
4463 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4467 if (delay_autosuspend(tp)) {
4468 rtl8152_runtime_resume(tp);
4477 static int rtl8152_system_suspend(struct r8152 *tp)
4479 struct net_device *netdev = tp->netdev;
4481 netif_device_detach(netdev);
4483 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4484 struct napi_struct *napi = &tp->napi;
4486 clear_bit(WORK_ENABLE, &tp->flags);
4487 usb_kill_urb(tp->intr_urb);
4489 cancel_delayed_work_sync(&tp->schedule);
4490 tp->rtl_ops.down(tp);
4497 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4499 struct r8152 *tp = usb_get_intfdata(intf);
4502 mutex_lock(&tp->control);
4504 if (PMSG_IS_AUTO(message))
4505 ret = rtl8152_runtime_suspend(tp);
4507 ret = rtl8152_system_suspend(tp);
4509 mutex_unlock(&tp->control);
4514 static int rtl8152_resume(struct usb_interface *intf)
4516 struct r8152 *tp = usb_get_intfdata(intf);
4519 mutex_lock(&tp->control);
4521 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4522 ret = rtl8152_runtime_resume(tp);
4524 ret = rtl8152_system_resume(tp);
4526 mutex_unlock(&tp->control);
4531 static int rtl8152_reset_resume(struct usb_interface *intf)
4533 struct r8152 *tp = usb_get_intfdata(intf);
4535 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4536 mutex_lock(&tp->control);
4537 tp->rtl_ops.init(tp);
4538 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4539 mutex_unlock(&tp->control);
4540 return rtl8152_resume(intf);
4543 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4545 struct r8152 *tp = netdev_priv(dev);
4547 if (usb_autopm_get_interface(tp->intf) < 0)
4550 if (!rtl_can_wakeup(tp)) {
4554 mutex_lock(&tp->control);
4555 wol->supported = WAKE_ANY;
4556 wol->wolopts = __rtl_get_wol(tp);
4557 mutex_unlock(&tp->control);
4560 usb_autopm_put_interface(tp->intf);
4563 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4565 struct r8152 *tp = netdev_priv(dev);
4568 if (!rtl_can_wakeup(tp))
4571 if (wol->wolopts & ~WAKE_ANY)
4574 ret = usb_autopm_get_interface(tp->intf);
4578 mutex_lock(&tp->control);
4580 __rtl_set_wol(tp, wol->wolopts);
4581 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4583 mutex_unlock(&tp->control);
4585 usb_autopm_put_interface(tp->intf);
4591 static u32 rtl8152_get_msglevel(struct net_device *dev)
4593 struct r8152 *tp = netdev_priv(dev);
4595 return tp->msg_enable;
4598 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4600 struct r8152 *tp = netdev_priv(dev);
4602 tp->msg_enable = value;
4605 static void rtl8152_get_drvinfo(struct net_device *netdev,
4606 struct ethtool_drvinfo *info)
4608 struct r8152 *tp = netdev_priv(netdev);
4610 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4611 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4612 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4616 int rtl8152_get_link_ksettings(struct net_device *netdev,
4617 struct ethtool_link_ksettings *cmd)
4619 struct r8152 *tp = netdev_priv(netdev);
4622 if (!tp->mii.mdio_read)
4625 ret = usb_autopm_get_interface(tp->intf);
4629 mutex_lock(&tp->control);
4631 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4633 mutex_unlock(&tp->control);
4635 usb_autopm_put_interface(tp->intf);
4641 static int rtl8152_set_link_ksettings(struct net_device *dev,
4642 const struct ethtool_link_ksettings *cmd)
4644 struct r8152 *tp = netdev_priv(dev);
4647 ret = usb_autopm_get_interface(tp->intf);
4651 mutex_lock(&tp->control);
4653 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4656 tp->autoneg = cmd->base.autoneg;
4657 tp->speed = cmd->base.speed;
4658 tp->duplex = cmd->base.duplex;
4661 mutex_unlock(&tp->control);
4663 usb_autopm_put_interface(tp->intf);
4669 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4676 "tx_single_collisions",
4677 "tx_multi_collisions",
4685 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4689 return ARRAY_SIZE(rtl8152_gstrings);
4695 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4696 struct ethtool_stats *stats, u64 *data)
4698 struct r8152 *tp = netdev_priv(dev);
4699 struct tally_counter tally;
4701 if (usb_autopm_get_interface(tp->intf) < 0)
4704 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4706 usb_autopm_put_interface(tp->intf);
4708 data[0] = le64_to_cpu(tally.tx_packets);
4709 data[1] = le64_to_cpu(tally.rx_packets);
4710 data[2] = le64_to_cpu(tally.tx_errors);
4711 data[3] = le32_to_cpu(tally.rx_errors);
4712 data[4] = le16_to_cpu(tally.rx_missed);
4713 data[5] = le16_to_cpu(tally.align_errors);
4714 data[6] = le32_to_cpu(tally.tx_one_collision);
4715 data[7] = le32_to_cpu(tally.tx_multi_collision);
4716 data[8] = le64_to_cpu(tally.rx_unicast);
4717 data[9] = le64_to_cpu(tally.rx_broadcast);
4718 data[10] = le32_to_cpu(tally.rx_multicast);
4719 data[11] = le16_to_cpu(tally.tx_aborted);
4720 data[12] = le16_to_cpu(tally.tx_underrun);
4723 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4725 switch (stringset) {
4727 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4732 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4734 u32 ocp_data, lp, adv, supported = 0;
4737 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4738 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4740 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4741 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4743 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4744 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4746 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4747 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4749 eee->eee_enabled = !!ocp_data;
4750 eee->eee_active = !!(supported & adv & lp);
4751 eee->supported = supported;
4752 eee->advertised = adv;
4753 eee->lp_advertised = lp;
4758 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4760 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4762 r8152_eee_en(tp, eee->eee_enabled);
4764 if (!eee->eee_enabled)
4767 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4772 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4774 u32 ocp_data, lp, adv, supported = 0;
4777 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4778 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4780 val = ocp_reg_read(tp, OCP_EEE_ADV);
4781 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4783 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4784 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4786 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4787 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4789 eee->eee_enabled = !!ocp_data;
4790 eee->eee_active = !!(supported & adv & lp);
4791 eee->supported = supported;
4792 eee->advertised = adv;
4793 eee->lp_advertised = lp;
4798 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4800 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4802 r8153_eee_en(tp, eee->eee_enabled);
4804 if (!eee->eee_enabled)
4807 ocp_reg_write(tp, OCP_EEE_ADV, val);
4812 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4814 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4816 r8153b_eee_en(tp, eee->eee_enabled);
4818 if (!eee->eee_enabled)
4821 ocp_reg_write(tp, OCP_EEE_ADV, val);
4827 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4829 struct r8152 *tp = netdev_priv(net);
4832 ret = usb_autopm_get_interface(tp->intf);
4836 mutex_lock(&tp->control);
4838 ret = tp->rtl_ops.eee_get(tp, edata);
4840 mutex_unlock(&tp->control);
4842 usb_autopm_put_interface(tp->intf);
4849 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4851 struct r8152 *tp = netdev_priv(net);
4854 ret = usb_autopm_get_interface(tp->intf);
4858 mutex_lock(&tp->control);
4860 ret = tp->rtl_ops.eee_set(tp, edata);
4862 ret = mii_nway_restart(&tp->mii);
4864 mutex_unlock(&tp->control);
4866 usb_autopm_put_interface(tp->intf);
4872 static int rtl8152_nway_reset(struct net_device *dev)
4874 struct r8152 *tp = netdev_priv(dev);
4877 ret = usb_autopm_get_interface(tp->intf);
4881 mutex_lock(&tp->control);
4883 ret = mii_nway_restart(&tp->mii);
4885 mutex_unlock(&tp->control);
4887 usb_autopm_put_interface(tp->intf);
4893 static int rtl8152_get_coalesce(struct net_device *netdev,
4894 struct ethtool_coalesce *coalesce)
4896 struct r8152 *tp = netdev_priv(netdev);
4898 switch (tp->version) {
4907 coalesce->rx_coalesce_usecs = tp->coalesce;
4912 static int rtl8152_set_coalesce(struct net_device *netdev,
4913 struct ethtool_coalesce *coalesce)
4915 struct r8152 *tp = netdev_priv(netdev);
4918 switch (tp->version) {
4927 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4930 ret = usb_autopm_get_interface(tp->intf);
4934 mutex_lock(&tp->control);
4936 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4937 tp->coalesce = coalesce->rx_coalesce_usecs;
4939 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
4940 netif_stop_queue(netdev);
4941 napi_disable(&tp->napi);
4942 tp->rtl_ops.disable(tp);
4943 tp->rtl_ops.enable(tp);
4945 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
4946 _rtl8152_set_rx_mode(netdev);
4947 napi_enable(&tp->napi);
4948 netif_wake_queue(netdev);
4952 mutex_unlock(&tp->control);
4954 usb_autopm_put_interface(tp->intf);
4959 static const struct ethtool_ops ops = {
4960 .get_drvinfo = rtl8152_get_drvinfo,
4961 .get_link = ethtool_op_get_link,
4962 .nway_reset = rtl8152_nway_reset,
4963 .get_msglevel = rtl8152_get_msglevel,
4964 .set_msglevel = rtl8152_set_msglevel,
4965 .get_wol = rtl8152_get_wol,
4966 .set_wol = rtl8152_set_wol,
4967 .get_strings = rtl8152_get_strings,
4968 .get_sset_count = rtl8152_get_sset_count,
4969 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4970 .get_coalesce = rtl8152_get_coalesce,
4971 .set_coalesce = rtl8152_set_coalesce,
4972 .get_eee = rtl_ethtool_get_eee,
4973 .set_eee = rtl_ethtool_set_eee,
4974 .get_link_ksettings = rtl8152_get_link_ksettings,
4975 .set_link_ksettings = rtl8152_set_link_ksettings,
4978 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4980 struct r8152 *tp = netdev_priv(netdev);
4981 struct mii_ioctl_data *data = if_mii(rq);
4984 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4987 res = usb_autopm_get_interface(tp->intf);
4993 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4997 mutex_lock(&tp->control);
4998 data->val_out = r8152_mdio_read(tp, data->reg_num);
4999 mutex_unlock(&tp->control);
5003 if (!capable(CAP_NET_ADMIN)) {
5007 mutex_lock(&tp->control);
5008 r8152_mdio_write(tp, data->reg_num, data->val_in);
5009 mutex_unlock(&tp->control);
5016 usb_autopm_put_interface(tp->intf);
5022 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
5024 struct r8152 *tp = netdev_priv(dev);
5027 switch (tp->version) {
5037 ret = usb_autopm_get_interface(tp->intf);
5041 mutex_lock(&tp->control);
5045 if (netif_running(dev)) {
5046 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
5050 if (netif_carrier_ok(dev))
5051 r8153_set_rx_early_size(tp);
5054 mutex_unlock(&tp->control);
5056 usb_autopm_put_interface(tp->intf);
5061 static const struct net_device_ops rtl8152_netdev_ops = {
5062 .ndo_open = rtl8152_open,
5063 .ndo_stop = rtl8152_close,
5064 .ndo_do_ioctl = rtl8152_ioctl,
5065 .ndo_start_xmit = rtl8152_start_xmit,
5066 .ndo_tx_timeout = rtl8152_tx_timeout,
5067 .ndo_set_features = rtl8152_set_features,
5068 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5069 .ndo_set_mac_address = rtl8152_set_mac_address,
5070 .ndo_change_mtu = rtl8152_change_mtu,
5071 .ndo_validate_addr = eth_validate_addr,
5072 .ndo_features_check = rtl8152_features_check,
5075 static void rtl8152_unload(struct r8152 *tp)
5077 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5080 if (tp->version != RTL_VER_01)
5081 r8152_power_cut_en(tp, true);
5084 static void rtl8153_unload(struct r8152 *tp)
5086 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5089 r8153_power_cut_en(tp, false);
5092 static void rtl8153b_unload(struct r8152 *tp)
5094 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5097 r8153b_power_cut_en(tp, false);
5100 static int rtl_ops_init(struct r8152 *tp)
5102 struct rtl_ops *ops = &tp->rtl_ops;
5105 switch (tp->version) {
5109 ops->init = r8152b_init;
5110 ops->enable = rtl8152_enable;
5111 ops->disable = rtl8152_disable;
5112 ops->up = rtl8152_up;
5113 ops->down = rtl8152_down;
5114 ops->unload = rtl8152_unload;
5115 ops->eee_get = r8152_get_eee;
5116 ops->eee_set = r8152_set_eee;
5117 ops->in_nway = rtl8152_in_nway;
5118 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5119 ops->autosuspend_en = rtl_runtime_suspend_enable;
5126 ops->init = r8153_init;
5127 ops->enable = rtl8153_enable;
5128 ops->disable = rtl8153_disable;
5129 ops->up = rtl8153_up;
5130 ops->down = rtl8153_down;
5131 ops->unload = rtl8153_unload;
5132 ops->eee_get = r8153_get_eee;
5133 ops->eee_set = r8153_set_eee;
5134 ops->in_nway = rtl8153_in_nway;
5135 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5136 ops->autosuspend_en = rtl8153_runtime_enable;
5141 ops->init = r8153b_init;
5142 ops->enable = rtl8153_enable;
5143 ops->disable = rtl8153b_disable;
5144 ops->up = rtl8153b_up;
5145 ops->down = rtl8153b_down;
5146 ops->unload = rtl8153b_unload;
5147 ops->eee_get = r8153_get_eee;
5148 ops->eee_set = r8153b_set_eee;
5149 ops->in_nway = rtl8153_in_nway;
5150 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5151 ops->autosuspend_en = rtl8153b_runtime_enable;
5156 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5163 static u8 rtl_get_version(struct usb_interface *intf)
5165 struct usb_device *udev = interface_to_usbdev(intf);
5171 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5175 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5176 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5177 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5179 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5185 version = RTL_VER_01;
5188 version = RTL_VER_02;
5191 version = RTL_VER_03;
5194 version = RTL_VER_04;
5197 version = RTL_VER_05;
5200 version = RTL_VER_06;
5203 version = RTL_VER_07;
5206 version = RTL_VER_08;
5209 version = RTL_VER_09;
5212 version = RTL_VER_UNKNOWN;
5213 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5217 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5222 static int rtl8152_probe(struct usb_interface *intf,
5223 const struct usb_device_id *id)
5225 struct usb_device *udev = interface_to_usbdev(intf);
5226 u8 version = rtl_get_version(intf);
5228 struct net_device *netdev;
5231 if (version == RTL_VER_UNKNOWN)
5234 if (udev->actconfig->desc.bConfigurationValue != 1) {
5235 usb_driver_set_configuration(udev, 1);
5239 usb_reset_device(udev);
5240 netdev = alloc_etherdev(sizeof(struct r8152));
5242 dev_err(&intf->dev, "Out of memory\n");
5246 SET_NETDEV_DEV(netdev, &intf->dev);
5247 tp = netdev_priv(netdev);
5248 tp->msg_enable = 0x7FFF;
5251 tp->netdev = netdev;
5253 tp->version = version;
5259 tp->mii.supports_gmii = 0;
5262 tp->mii.supports_gmii = 1;
5266 ret = rtl_ops_init(tp);
5270 mutex_init(&tp->control);
5271 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5272 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5274 netdev->netdev_ops = &rtl8152_netdev_ops;
5275 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5277 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5278 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5279 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5280 NETIF_F_HW_VLAN_CTAG_TX;
5281 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5282 NETIF_F_TSO | NETIF_F_FRAGLIST |
5283 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5284 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5285 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5286 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5287 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5289 if (tp->version == RTL_VER_01) {
5290 netdev->features &= ~NETIF_F_RXCSUM;
5291 netdev->hw_features &= ~NETIF_F_RXCSUM;
5294 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5295 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5296 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5297 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5300 netdev->ethtool_ops = &ops;
5301 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5303 /* MTU range: 68 - 1500 or 9194 */
5304 netdev->min_mtu = ETH_MIN_MTU;
5305 switch (tp->version) {
5308 netdev->max_mtu = ETH_DATA_LEN;
5311 netdev->max_mtu = RTL8153_MAX_MTU;
5315 tp->mii.dev = netdev;
5316 tp->mii.mdio_read = read_mii_word;
5317 tp->mii.mdio_write = write_mii_word;
5318 tp->mii.phy_id_mask = 0x3f;
5319 tp->mii.reg_num_mask = 0x1f;
5320 tp->mii.phy_id = R8152_PHY_ID;
5322 tp->autoneg = AUTONEG_ENABLE;
5323 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5324 tp->duplex = DUPLEX_FULL;
5326 intf->needs_remote_wakeup = 1;
5328 tp->rtl_ops.init(tp);
5329 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5330 set_ethernet_addr(tp);
5332 usb_set_intfdata(intf, tp);
5333 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5335 ret = register_netdev(netdev);
5337 netif_err(tp, probe, netdev, "couldn't register the device\n");
5341 if (!rtl_can_wakeup(tp))
5342 __rtl_set_wol(tp, 0);
5344 tp->saved_wolopts = __rtl_get_wol(tp);
5345 if (tp->saved_wolopts)
5346 device_set_wakeup_enable(&udev->dev, true);
5348 device_set_wakeup_enable(&udev->dev, false);
5350 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5355 usb_set_intfdata(intf, NULL);
5357 free_netdev(netdev);
5361 static void rtl8152_disconnect(struct usb_interface *intf)
5363 struct r8152 *tp = usb_get_intfdata(intf);
5365 usb_set_intfdata(intf, NULL);
5369 unregister_netdev(tp->netdev);
5370 cancel_delayed_work_sync(&tp->hw_phy_work);
5371 tp->rtl_ops.unload(tp);
5372 free_netdev(tp->netdev);
5376 #define REALTEK_USB_DEVICE(vend, prod) \
5377 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5378 USB_DEVICE_ID_MATCH_INT_CLASS, \
5379 .idVendor = (vend), \
5380 .idProduct = (prod), \
5381 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5384 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5385 USB_DEVICE_ID_MATCH_DEVICE, \
5386 .idVendor = (vend), \
5387 .idProduct = (prod), \
5388 .bInterfaceClass = USB_CLASS_COMM, \
5389 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5390 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5392 /* table of devices that work with this driver */
5393 static const struct usb_device_id rtl8152_table[] = {
5394 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5395 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5396 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5397 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5398 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5399 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5400 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5401 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5402 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5403 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5404 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5405 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5406 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5407 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5408 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5412 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5414 static struct usb_driver rtl8152_driver = {
5416 .id_table = rtl8152_table,
5417 .probe = rtl8152_probe,
5418 .disconnect = rtl8152_disconnect,
5419 .suspend = rtl8152_suspend,
5420 .resume = rtl8152_resume,
5421 .reset_resume = rtl8152_reset_resume,
5422 .pre_reset = rtl8152_pre_reset,
5423 .post_reset = rtl8152_post_reset,
5424 .supports_autosuspend = 1,
5425 .disable_hub_initiated_lpm = 1,
5428 module_usb_driver(rtl8152_driver);
5430 MODULE_AUTHOR(DRIVER_AUTHOR);
5431 MODULE_DESCRIPTION(DRIVER_DESC);
5432 MODULE_LICENSE("GPL");
5433 MODULE_VERSION(DRIVER_VERSION);