2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
47 #include <net/checksum.h>
50 #include <asm/system.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
56 #include <asm/idprom.h>
65 #define DRV_MODULE_NAME "tg3"
67 #define TG3_MIN_NUM 117
68 #define DRV_MODULE_VERSION \
69 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE "January 25, 2011"
72 #define TG3_DEF_MAC_MODE 0
73 #define TG3_DEF_RX_MODE 0
74 #define TG3_DEF_TX_MODE 0
75 #define TG3_DEF_MSG_ENABLE \
85 /* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
88 #define TG3_TX_TIMEOUT (5 * HZ)
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU 60
92 #define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
99 #define TG3_RX_STD_RING_SIZE(tp) \
100 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
107 #define TG3_RSS_INDIR_TBL_SIZE 128
109 /* Do not place this n-ring entries value into the tp struct itself,
110 * we really want to expose these constants to GCC so that modulo et
111 * al. operations are done with shifts and masks instead of with
112 * hw multiply/modulo instructions. Another solution would be to
113 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_STD_RING_BYTES(tp) \
120 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_DMA_BYTE_ENAB 64
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146 * that are at least dword aligned when used in PCIX mode. The driver
147 * works around this bug by double copying the packet. This workaround
148 * is built into the normal double copy length check for efficiency.
150 * However, the double copy is only necessary on those architectures
151 * where unaligned memory accesses are inefficient. For those architectures
152 * where unaligned memory accesses incur little penalty, we can reintegrate
153 * the 5701 in the normal rx path. Doing so saves a device structure
154 * dereference by hardcoding the double copy threshold in place.
156 #define TG3_RX_COPY_THRESHOLD 256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
160 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
166 #define TG3_RAW_IP_ALIGN 2
168 /* number of ETHTOOL_GSTATS u64's */
169 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
171 #define TG3_NUM_TEST 6
173 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
175 #define FIRMWARE_TG3 "tigon/tg3.bin"
176 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
177 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
179 static char version[] __devinitdata =
180 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_MODULE_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_TG3);
187 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
190 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
191 module_param(tg3_debug, int, 0);
192 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
268 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
269 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
270 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
271 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
272 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
273 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
274 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
278 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
280 static const struct {
281 const char string[ETH_GSTRING_LEN];
282 } ethtool_stats_keys[TG3_NUM_STATS] = {
285 { "rx_ucast_packets" },
286 { "rx_mcast_packets" },
287 { "rx_bcast_packets" },
289 { "rx_align_errors" },
290 { "rx_xon_pause_rcvd" },
291 { "rx_xoff_pause_rcvd" },
292 { "rx_mac_ctrl_rcvd" },
293 { "rx_xoff_entered" },
294 { "rx_frame_too_long_errors" },
296 { "rx_undersize_packets" },
297 { "rx_in_length_errors" },
298 { "rx_out_length_errors" },
299 { "rx_64_or_less_octet_packets" },
300 { "rx_65_to_127_octet_packets" },
301 { "rx_128_to_255_octet_packets" },
302 { "rx_256_to_511_octet_packets" },
303 { "rx_512_to_1023_octet_packets" },
304 { "rx_1024_to_1522_octet_packets" },
305 { "rx_1523_to_2047_octet_packets" },
306 { "rx_2048_to_4095_octet_packets" },
307 { "rx_4096_to_8191_octet_packets" },
308 { "rx_8192_to_9022_octet_packets" },
315 { "tx_flow_control" },
317 { "tx_single_collisions" },
318 { "tx_mult_collisions" },
320 { "tx_excessive_collisions" },
321 { "tx_late_collisions" },
322 { "tx_collide_2times" },
323 { "tx_collide_3times" },
324 { "tx_collide_4times" },
325 { "tx_collide_5times" },
326 { "tx_collide_6times" },
327 { "tx_collide_7times" },
328 { "tx_collide_8times" },
329 { "tx_collide_9times" },
330 { "tx_collide_10times" },
331 { "tx_collide_11times" },
332 { "tx_collide_12times" },
333 { "tx_collide_13times" },
334 { "tx_collide_14times" },
335 { "tx_collide_15times" },
336 { "tx_ucast_packets" },
337 { "tx_mcast_packets" },
338 { "tx_bcast_packets" },
339 { "tx_carrier_sense_errors" },
343 { "dma_writeq_full" },
344 { "dma_write_prioq_full" },
348 { "rx_threshold_hit" },
350 { "dma_readq_full" },
351 { "dma_read_prioq_full" },
352 { "tx_comp_queue_full" },
354 { "ring_set_send_prod_index" },
355 { "ring_status_update" },
357 { "nic_avoided_irqs" },
358 { "nic_tx_threshold_hit" }
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_test_keys[TG3_NUM_TEST] = {
364 { "nvram test (online) " },
365 { "link test (online) " },
366 { "register test (offline)" },
367 { "memory test (offline)" },
368 { "loopback test (offline)" },
369 { "interrupt test (offline)" },
372 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
374 writel(val, tp->regs + off);
377 static u32 tg3_read32(struct tg3 *tp, u32 off)
379 return readl(tp->regs + off);
382 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
384 writel(val, tp->aperegs + off);
387 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
389 return readl(tp->aperegs + off);
392 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
398 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
399 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
404 writel(val, tp->regs + off);
405 readl(tp->regs + off);
408 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
413 spin_lock_irqsave(&tp->indirect_lock, flags);
414 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
415 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
416 spin_unlock_irqrestore(&tp->indirect_lock, flags);
420 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
424 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
425 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
426 TG3_64BIT_REG_LOW, val);
429 if (off == TG3_RX_STD_PROD_IDX_REG) {
430 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
431 TG3_64BIT_REG_LOW, val);
435 spin_lock_irqsave(&tp->indirect_lock, flags);
436 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
437 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
438 spin_unlock_irqrestore(&tp->indirect_lock, flags);
440 /* In indirect mode when disabling interrupts, we also need
441 * to clear the interrupt bit in the GRC local ctrl register.
443 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
445 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
446 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
450 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
455 spin_lock_irqsave(&tp->indirect_lock, flags);
456 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
457 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
458 spin_unlock_irqrestore(&tp->indirect_lock, flags);
462 /* usec_wait specifies the wait time in usec when writing to certain registers
463 * where it is unsafe to read back the register without some delay.
464 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
465 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
467 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
469 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
470 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 /* Non-posted methods */
472 tp->write32(tp, off, val);
475 tg3_write32(tp, off, val);
480 /* Wait again after the read for the posted method to guarantee that
481 * the wait time is met.
487 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
489 tp->write32_mbox(tp, off, val);
490 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
491 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
492 tp->read32_mbox(tp, off);
495 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
497 void __iomem *mbox = tp->regs + off;
499 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
501 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
505 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
507 return readl(tp->regs + off + GRCMBOX_BASE);
510 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
512 writel(val, tp->regs + off + GRCMBOX_BASE);
515 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
516 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
517 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
518 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
519 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
521 #define tw32(reg, val) tp->write32(tp, reg, val)
522 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
523 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
524 #define tr32(reg) tp->read32(tp, reg)
526 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
530 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
531 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
536 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
539 /* Always leave this as zero. */
540 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
542 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
543 tw32_f(TG3PCI_MEM_WIN_DATA, val);
545 /* Always leave this as zero. */
546 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 spin_unlock_irqrestore(&tp->indirect_lock, flags);
551 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
555 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
556 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
561 spin_lock_irqsave(&tp->indirect_lock, flags);
562 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
563 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
564 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
566 /* Always leave this as zero. */
567 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
569 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
570 *val = tr32(TG3PCI_MEM_WIN_DATA);
572 /* Always leave this as zero. */
573 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
575 spin_unlock_irqrestore(&tp->indirect_lock, flags);
578 static void tg3_ape_lock_init(struct tg3 *tp)
583 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
584 regbase = TG3_APE_LOCK_GRANT;
586 regbase = TG3_APE_PER_LOCK_GRANT;
588 /* Make sure the driver hasn't any stale locks. */
589 for (i = 0; i < 8; i++)
590 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
593 static int tg3_ape_lock(struct tg3 *tp, int locknum)
597 u32 status, req, gnt;
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 case TG3_APE_LOCK_GRC:
604 case TG3_APE_LOCK_MEM:
610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
611 req = TG3_APE_LOCK_REQ;
612 gnt = TG3_APE_LOCK_GRANT;
614 req = TG3_APE_PER_LOCK_REQ;
615 gnt = TG3_APE_PER_LOCK_GRANT;
620 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
622 /* Wait for up to 1 millisecond to acquire lock. */
623 for (i = 0; i < 100; i++) {
624 status = tg3_ape_read32(tp, gnt + off);
625 if (status == APE_LOCK_GRANT_DRIVER)
630 if (status != APE_LOCK_GRANT_DRIVER) {
631 /* Revoke the lock request. */
632 tg3_ape_write32(tp, gnt + off,
633 APE_LOCK_GRANT_DRIVER);
641 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
645 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
649 case TG3_APE_LOCK_GRC:
650 case TG3_APE_LOCK_MEM:
656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
657 gnt = TG3_APE_LOCK_GRANT;
659 gnt = TG3_APE_PER_LOCK_GRANT;
661 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
664 static void tg3_disable_ints(struct tg3 *tp)
668 tw32(TG3PCI_MISC_HOST_CTRL,
669 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
670 for (i = 0; i < tp->irq_max; i++)
671 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
674 static void tg3_enable_ints(struct tg3 *tp)
681 tw32(TG3PCI_MISC_HOST_CTRL,
682 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
684 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
685 for (i = 0; i < tp->irq_cnt; i++) {
686 struct tg3_napi *tnapi = &tp->napi[i];
688 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
689 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
690 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
692 tp->coal_now |= tnapi->coal_now;
695 /* Force an initial interrupt */
696 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
697 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
698 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
700 tw32(HOSTCC_MODE, tp->coal_now);
702 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
705 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
707 struct tg3 *tp = tnapi->tp;
708 struct tg3_hw_status *sblk = tnapi->hw_status;
709 unsigned int work_exists = 0;
711 /* check for phy events */
712 if (!(tp->tg3_flags &
713 (TG3_FLAG_USE_LINKCHG_REG |
714 TG3_FLAG_POLL_SERDES))) {
715 if (sblk->status & SD_STATUS_LINK_CHG)
718 /* check for RX/TX work to do */
719 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
720 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
727 * similar to tg3_enable_ints, but it accurately determines whether there
728 * is new work pending and can return without flushing the PIO write
729 * which reenables interrupts
731 static void tg3_int_reenable(struct tg3_napi *tnapi)
733 struct tg3 *tp = tnapi->tp;
735 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
738 /* When doing tagged status, this work check is unnecessary.
739 * The last_tag we write above tells the chip which piece of
740 * work we've completed.
742 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
744 tw32(HOSTCC_MODE, tp->coalesce_mode |
745 HOSTCC_MODE_ENABLE | tnapi->coal_now);
748 static void tg3_switch_clocks(struct tg3 *tp)
753 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
754 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
757 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
759 orig_clock_ctrl = clock_ctrl;
760 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
761 CLOCK_CTRL_CLKRUN_OENABLE |
763 tp->pci_clock_ctrl = clock_ctrl;
765 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
766 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
770 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
775 tw32_wait_f(TG3PCI_CLOCK_CTRL,
776 clock_ctrl | (CLOCK_CTRL_ALTCLK),
779 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
782 #define PHY_BUSY_LOOPS 5000
784 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
790 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
798 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
799 MI_COM_PHY_ADDR_MASK);
800 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
801 MI_COM_REG_ADDR_MASK);
802 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
804 tw32_f(MAC_MI_COM, frame_val);
806 loops = PHY_BUSY_LOOPS;
809 frame_val = tr32(MAC_MI_COM);
811 if ((frame_val & MI_COM_BUSY) == 0) {
813 frame_val = tr32(MAC_MI_COM);
821 *val = frame_val & MI_COM_DATA_MASK;
825 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
826 tw32_f(MAC_MI_MODE, tp->mi_mode);
833 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
839 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
840 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
845 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
849 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
850 MI_COM_PHY_ADDR_MASK);
851 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
852 MI_COM_REG_ADDR_MASK);
853 frame_val |= (val & MI_COM_DATA_MASK);
854 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
856 tw32_f(MAC_MI_COM, frame_val);
858 loops = PHY_BUSY_LOOPS;
861 frame_val = tr32(MAC_MI_COM);
862 if ((frame_val & MI_COM_BUSY) == 0) {
864 frame_val = tr32(MAC_MI_COM);
874 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
875 tw32_f(MAC_MI_MODE, tp->mi_mode);
882 static int tg3_bmcr_reset(struct tg3 *tp)
887 /* OK, reset it, and poll the BMCR_RESET bit until it
888 * clears or we time out.
890 phy_control = BMCR_RESET;
891 err = tg3_writephy(tp, MII_BMCR, phy_control);
897 err = tg3_readphy(tp, MII_BMCR, &phy_control);
901 if ((phy_control & BMCR_RESET) == 0) {
913 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
915 struct tg3 *tp = bp->priv;
918 spin_lock_bh(&tp->lock);
920 if (tg3_readphy(tp, reg, &val))
923 spin_unlock_bh(&tp->lock);
928 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
930 struct tg3 *tp = bp->priv;
933 spin_lock_bh(&tp->lock);
935 if (tg3_writephy(tp, reg, val))
938 spin_unlock_bh(&tp->lock);
943 static int tg3_mdio_reset(struct mii_bus *bp)
948 static void tg3_mdio_config_5785(struct tg3 *tp)
951 struct phy_device *phydev;
953 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
954 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
955 case PHY_ID_BCM50610:
956 case PHY_ID_BCM50610M:
957 val = MAC_PHYCFG2_50610_LED_MODES;
959 case PHY_ID_BCMAC131:
960 val = MAC_PHYCFG2_AC131_LED_MODES;
962 case PHY_ID_RTL8211C:
963 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
965 case PHY_ID_RTL8201E:
966 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
972 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
973 tw32(MAC_PHYCFG2, val);
975 val = tr32(MAC_PHYCFG1);
976 val &= ~(MAC_PHYCFG1_RGMII_INT |
977 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
978 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
979 tw32(MAC_PHYCFG1, val);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
985 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
986 MAC_PHYCFG2_FMODE_MASK_MASK |
987 MAC_PHYCFG2_GMODE_MASK_MASK |
988 MAC_PHYCFG2_ACT_MASK_MASK |
989 MAC_PHYCFG2_QUAL_MASK_MASK |
990 MAC_PHYCFG2_INBAND_ENABLE;
992 tw32(MAC_PHYCFG2, val);
994 val = tr32(MAC_PHYCFG1);
995 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
996 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
997 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
998 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
999 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1000 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1001 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1004 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1005 tw32(MAC_PHYCFG1, val);
1007 val = tr32(MAC_EXT_RGMII_MODE);
1008 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1009 MAC_RGMII_MODE_RX_QUALITY |
1010 MAC_RGMII_MODE_RX_ACTIVITY |
1011 MAC_RGMII_MODE_RX_ENG_DET |
1012 MAC_RGMII_MODE_TX_ENABLE |
1013 MAC_RGMII_MODE_TX_LOWPWR |
1014 MAC_RGMII_MODE_TX_RESET);
1015 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1016 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1017 val |= MAC_RGMII_MODE_RX_INT_B |
1018 MAC_RGMII_MODE_RX_QUALITY |
1019 MAC_RGMII_MODE_RX_ACTIVITY |
1020 MAC_RGMII_MODE_RX_ENG_DET;
1021 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1022 val |= MAC_RGMII_MODE_TX_ENABLE |
1023 MAC_RGMII_MODE_TX_LOWPWR |
1024 MAC_RGMII_MODE_TX_RESET;
1026 tw32(MAC_EXT_RGMII_MODE, val);
1029 static void tg3_mdio_start(struct tg3 *tp)
1031 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1032 tw32_f(MAC_MI_MODE, tp->mi_mode);
1035 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1037 tg3_mdio_config_5785(tp);
1040 static int tg3_mdio_init(struct tg3 *tp)
1044 struct phy_device *phydev;
1046 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1049 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1051 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1052 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1054 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1055 TG3_CPMU_PHY_STRAP_IS_SERDES;
1059 tp->phy_addr = TG3_PHY_MII_ADDR;
1063 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1064 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067 tp->mdio_bus = mdiobus_alloc();
1068 if (tp->mdio_bus == NULL)
1071 tp->mdio_bus->name = "tg3 mdio bus";
1072 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1073 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1074 tp->mdio_bus->priv = tp;
1075 tp->mdio_bus->parent = &tp->pdev->dev;
1076 tp->mdio_bus->read = &tg3_mdio_read;
1077 tp->mdio_bus->write = &tg3_mdio_write;
1078 tp->mdio_bus->reset = &tg3_mdio_reset;
1079 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1080 tp->mdio_bus->irq = &tp->mdio_irq[0];
1082 for (i = 0; i < PHY_MAX_ADDR; i++)
1083 tp->mdio_bus->irq[i] = PHY_POLL;
1085 /* The bus registration will look for all the PHYs on the mdio bus.
1086 * Unfortunately, it does not ensure the PHY is powered up before
1087 * accessing the PHY ID registers. A chip reset is the
1088 * quickest way to bring the device back to an operational state..
1090 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1093 i = mdiobus_register(tp->mdio_bus);
1095 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1096 mdiobus_free(tp->mdio_bus);
1100 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1102 if (!phydev || !phydev->drv) {
1103 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1104 mdiobus_unregister(tp->mdio_bus);
1105 mdiobus_free(tp->mdio_bus);
1109 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1110 case PHY_ID_BCM57780:
1111 phydev->interface = PHY_INTERFACE_MODE_GMII;
1112 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1114 case PHY_ID_BCM50610:
1115 case PHY_ID_BCM50610M:
1116 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1117 PHY_BRCM_RX_REFCLK_UNUSED |
1118 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1119 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1121 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1122 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1123 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1124 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1125 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1127 case PHY_ID_RTL8211C:
1128 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1130 case PHY_ID_RTL8201E:
1131 case PHY_ID_BCMAC131:
1132 phydev->interface = PHY_INTERFACE_MODE_MII;
1133 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1134 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1138 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1141 tg3_mdio_config_5785(tp);
1146 static void tg3_mdio_fini(struct tg3 *tp)
1148 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1149 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1150 mdiobus_unregister(tp->mdio_bus);
1151 mdiobus_free(tp->mdio_bus);
1155 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1159 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1163 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1167 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1168 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1172 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1178 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1182 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1186 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1190 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1191 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1195 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1201 /* tp->lock is held. */
1202 static inline void tg3_generate_fw_event(struct tg3 *tp)
1206 val = tr32(GRC_RX_CPU_EVENT);
1207 val |= GRC_RX_CPU_DRIVER_EVENT;
1208 tw32_f(GRC_RX_CPU_EVENT, val);
1210 tp->last_event_jiffies = jiffies;
1213 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215 /* tp->lock is held. */
1216 static void tg3_wait_for_event_ack(struct tg3 *tp)
1219 unsigned int delay_cnt;
1222 /* If enough time has passed, no wait is necessary. */
1223 time_remain = (long)(tp->last_event_jiffies + 1 +
1224 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1226 if (time_remain < 0)
1229 /* Check if we can shorten the wait time. */
1230 delay_cnt = jiffies_to_usecs(time_remain);
1231 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1232 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1233 delay_cnt = (delay_cnt >> 3) + 1;
1235 for (i = 0; i < delay_cnt; i++) {
1236 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1242 /* tp->lock is held. */
1243 static void tg3_ump_link_report(struct tg3 *tp)
1248 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1249 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1252 tg3_wait_for_event_ack(tp);
1254 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1256 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1259 if (!tg3_readphy(tp, MII_BMCR, ®))
1261 if (!tg3_readphy(tp, MII_BMSR, ®))
1262 val |= (reg & 0xffff);
1263 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1266 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1268 if (!tg3_readphy(tp, MII_LPA, ®))
1269 val |= (reg & 0xffff);
1270 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1273 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1274 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1276 if (!tg3_readphy(tp, MII_STAT1000, ®))
1277 val |= (reg & 0xffff);
1279 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1281 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1285 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1287 tg3_generate_fw_event(tp);
1290 static void tg3_link_report(struct tg3 *tp)
1292 if (!netif_carrier_ok(tp->dev)) {
1293 netif_info(tp, link, tp->dev, "Link is down\n");
1294 tg3_ump_link_report(tp);
1295 } else if (netif_msg_link(tp)) {
1296 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1297 (tp->link_config.active_speed == SPEED_1000 ?
1299 (tp->link_config.active_speed == SPEED_100 ?
1301 (tp->link_config.active_duplex == DUPLEX_FULL ?
1304 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1305 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1307 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1309 tg3_ump_link_report(tp);
1313 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1317 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1318 miireg = ADVERTISE_PAUSE_CAP;
1319 else if (flow_ctrl & FLOW_CTRL_TX)
1320 miireg = ADVERTISE_PAUSE_ASYM;
1321 else if (flow_ctrl & FLOW_CTRL_RX)
1322 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1329 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1333 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1334 miireg = ADVERTISE_1000XPAUSE;
1335 else if (flow_ctrl & FLOW_CTRL_TX)
1336 miireg = ADVERTISE_1000XPSE_ASYM;
1337 else if (flow_ctrl & FLOW_CTRL_RX)
1338 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1345 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1349 if (lcladv & ADVERTISE_1000XPAUSE) {
1350 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1351 if (rmtadv & LPA_1000XPAUSE)
1352 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1353 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1356 if (rmtadv & LPA_1000XPAUSE)
1357 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1359 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1360 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1367 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1371 u32 old_rx_mode = tp->rx_mode;
1372 u32 old_tx_mode = tp->tx_mode;
1374 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1375 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1377 autoneg = tp->link_config.autoneg;
1379 if (autoneg == AUTONEG_ENABLE &&
1380 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1381 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1382 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1384 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1386 flowctrl = tp->link_config.flowctrl;
1388 tp->link_config.active_flowctrl = flowctrl;
1390 if (flowctrl & FLOW_CTRL_RX)
1391 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1393 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1395 if (old_rx_mode != tp->rx_mode)
1396 tw32_f(MAC_RX_MODE, tp->rx_mode);
1398 if (flowctrl & FLOW_CTRL_TX)
1399 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1401 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1403 if (old_tx_mode != tp->tx_mode)
1404 tw32_f(MAC_TX_MODE, tp->tx_mode);
1407 static void tg3_adjust_link(struct net_device *dev)
1409 u8 oldflowctrl, linkmesg = 0;
1410 u32 mac_mode, lcl_adv, rmt_adv;
1411 struct tg3 *tp = netdev_priv(dev);
1412 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1414 spin_lock_bh(&tp->lock);
1416 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1417 MAC_MODE_HALF_DUPLEX);
1419 oldflowctrl = tp->link_config.active_flowctrl;
1425 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1426 mac_mode |= MAC_MODE_PORT_MODE_MII;
1427 else if (phydev->speed == SPEED_1000 ||
1428 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1429 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1431 mac_mode |= MAC_MODE_PORT_MODE_MII;
1433 if (phydev->duplex == DUPLEX_HALF)
1434 mac_mode |= MAC_MODE_HALF_DUPLEX;
1436 lcl_adv = tg3_advert_flowctrl_1000T(
1437 tp->link_config.flowctrl);
1440 rmt_adv = LPA_PAUSE_CAP;
1441 if (phydev->asym_pause)
1442 rmt_adv |= LPA_PAUSE_ASYM;
1445 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1447 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1449 if (mac_mode != tp->mac_mode) {
1450 tp->mac_mode = mac_mode;
1451 tw32_f(MAC_MODE, tp->mac_mode);
1455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1456 if (phydev->speed == SPEED_10)
1458 MAC_MI_STAT_10MBPS_MODE |
1459 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1464 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1465 tw32(MAC_TX_LENGTHS,
1466 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1467 (6 << TX_LENGTHS_IPG_SHIFT) |
1468 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470 tw32(MAC_TX_LENGTHS,
1471 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1472 (6 << TX_LENGTHS_IPG_SHIFT) |
1473 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1475 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1476 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1477 phydev->speed != tp->link_config.active_speed ||
1478 phydev->duplex != tp->link_config.active_duplex ||
1479 oldflowctrl != tp->link_config.active_flowctrl)
1482 tp->link_config.active_speed = phydev->speed;
1483 tp->link_config.active_duplex = phydev->duplex;
1485 spin_unlock_bh(&tp->lock);
1488 tg3_link_report(tp);
1491 static int tg3_phy_init(struct tg3 *tp)
1493 struct phy_device *phydev;
1495 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1498 /* Bring the PHY back to a known state. */
1501 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503 /* Attach the MAC to the PHY. */
1504 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1505 phydev->dev_flags, phydev->interface);
1506 if (IS_ERR(phydev)) {
1507 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1508 return PTR_ERR(phydev);
1511 /* Mask with MAC supported features. */
1512 switch (phydev->interface) {
1513 case PHY_INTERFACE_MODE_GMII:
1514 case PHY_INTERFACE_MODE_RGMII:
1515 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1516 phydev->supported &= (PHY_GBIT_FEATURES |
1518 SUPPORTED_Asym_Pause);
1522 case PHY_INTERFACE_MODE_MII:
1523 phydev->supported &= (PHY_BASIC_FEATURES |
1525 SUPPORTED_Asym_Pause);
1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1532 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1534 phydev->advertising = phydev->supported;
1539 static void tg3_phy_start(struct tg3 *tp)
1541 struct phy_device *phydev;
1543 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1549 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1550 phydev->speed = tp->link_config.orig_speed;
1551 phydev->duplex = tp->link_config.orig_duplex;
1552 phydev->autoneg = tp->link_config.orig_autoneg;
1553 phydev->advertising = tp->link_config.orig_advertising;
1558 phy_start_aneg(phydev);
1561 static void tg3_phy_stop(struct tg3 *tp)
1563 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1566 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569 static void tg3_phy_fini(struct tg3 *tp)
1571 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1572 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1573 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1577 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1581 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1583 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1588 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1592 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1594 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1599 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 phytest | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1610 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1615 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1619 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1623 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1624 ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1625 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1628 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1629 tg3_phy_fet_toggle_apd(tp, enable);
1633 reg = MII_TG3_MISC_SHDW_WREN |
1634 MII_TG3_MISC_SHDW_SCR5_SEL |
1635 MII_TG3_MISC_SHDW_SCR5_LPED |
1636 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1637 MII_TG3_MISC_SHDW_SCR5_SDTL |
1638 MII_TG3_MISC_SHDW_SCR5_C125OE;
1639 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1640 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1642 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1645 reg = MII_TG3_MISC_SHDW_WREN |
1646 MII_TG3_MISC_SHDW_APD_SEL |
1647 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1649 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1651 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1658 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1659 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1662 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1665 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1666 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1668 tg3_writephy(tp, MII_TG3_FET_TEST,
1669 ephy | MII_TG3_FET_SHADOW_EN);
1670 if (!tg3_readphy(tp, reg, &phy)) {
1672 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1674 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1675 tg3_writephy(tp, reg, phy);
1677 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1680 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1681 MII_TG3_AUXCTL_SHDWSEL_MISC;
1682 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1683 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1685 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1687 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1688 phy |= MII_TG3_AUXCTL_MISC_WREN;
1689 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1694 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1698 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1701 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1702 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1703 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1704 (val | (1 << 15) | (1 << 4)));
1707 static void tg3_phy_apply_otp(struct tg3 *tp)
1716 /* Enable SM_DSP clock and tx 6dB coding. */
1717 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1718 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1719 MII_TG3_AUXCTL_ACTL_TX_6DB;
1720 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1722 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1723 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1724 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1726 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1727 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1728 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1730 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1731 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1732 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1734 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1735 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1737 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1738 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1740 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1741 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1742 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1744 /* Turn off SM_DSP clock. */
1745 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1746 MII_TG3_AUXCTL_ACTL_TX_6DB;
1747 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1750 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1754 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1759 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1760 current_link_up == 1 &&
1761 tp->link_config.active_duplex == DUPLEX_FULL &&
1762 (tp->link_config.active_speed == SPEED_100 ||
1763 tp->link_config.active_speed == SPEED_1000)) {
1766 if (tp->link_config.active_speed == SPEED_1000)
1767 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1769 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1771 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1773 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1774 TG3_CL45_D7_EEERES_STAT, &val);
1777 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1778 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1781 case ASIC_REV_57765:
1782 /* Enable SM_DSP clock and tx 6dB coding. */
1783 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1784 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1785 MII_TG3_AUXCTL_ACTL_TX_6DB;
1786 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1788 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1790 /* Turn off SM_DSP clock. */
1791 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1792 MII_TG3_AUXCTL_ACTL_TX_6DB;
1793 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1796 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1801 if (!tp->setlpicnt) {
1802 val = tr32(TG3_CPMU_EEE_MODE);
1803 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1807 static int tg3_wait_macro_done(struct tg3 *tp)
1814 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1815 if ((tmp32 & 0x1000) == 0)
1825 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1827 static const u32 test_pat[4][6] = {
1828 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1829 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1830 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1831 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1835 for (chan = 0; chan < 4; chan++) {
1838 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1839 (chan * 0x2000) | 0x0200);
1840 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1842 for (i = 0; i < 6; i++)
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1846 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1847 if (tg3_wait_macro_done(tp)) {
1852 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1853 (chan * 0x2000) | 0x0200);
1854 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1855 if (tg3_wait_macro_done(tp)) {
1860 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1861 if (tg3_wait_macro_done(tp)) {
1866 for (i = 0; i < 6; i += 2) {
1869 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1870 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1871 tg3_wait_macro_done(tp)) {
1877 if (low != test_pat[chan][i] ||
1878 high != test_pat[chan][i+1]) {
1879 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1880 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1881 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1891 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1895 for (chan = 0; chan < 4; chan++) {
1898 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1899 (chan * 0x2000) | 0x0200);
1900 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1901 for (i = 0; i < 6; i++)
1902 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1903 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1904 if (tg3_wait_macro_done(tp))
1911 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1913 u32 reg32, phy9_orig;
1914 int retries, do_phy_reset, err;
1920 err = tg3_bmcr_reset(tp);
1926 /* Disable transmitter and interrupt. */
1927 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1931 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1933 /* Set full-duplex, 1000 mbps. */
1934 tg3_writephy(tp, MII_BMCR,
1935 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1937 /* Set to master mode. */
1938 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1941 tg3_writephy(tp, MII_TG3_CTRL,
1942 (MII_TG3_CTRL_AS_MASTER |
1943 MII_TG3_CTRL_ENABLE_AS_MASTER));
1945 /* Enable SM_DSP_CLOCK and 6dB. */
1946 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 /* Block the PHY control access. */
1949 tg3_phydsp_write(tp, 0x8005, 0x0800);
1951 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1954 } while (--retries);
1956 err = tg3_phy_reset_chanpat(tp);
1960 tg3_phydsp_write(tp, 0x8005, 0x0000);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1963 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1967 /* Set Extended packet length bit for jumbo frames */
1968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1973 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1975 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1977 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1984 /* This will reset the tigon3 PHY if there is no valid
1985 * link unless the FORCE argument is non-zero.
1987 static int tg3_phy_reset(struct tg3 *tp)
1992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1993 val = tr32(GRC_MISC_CFG);
1994 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1997 err = tg3_readphy(tp, MII_BMSR, &val);
1998 err |= tg3_readphy(tp, MII_BMSR, &val);
2002 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2003 netif_carrier_off(tp->dev);
2004 tg3_link_report(tp);
2007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2010 err = tg3_phy_reset_5703_4_5(tp);
2017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2018 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2019 cpmuctrl = tr32(TG3_CPMU_CTRL);
2020 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2022 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2025 err = tg3_bmcr_reset(tp);
2029 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2030 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2031 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2033 tw32(TG3_CPMU_CTRL, cpmuctrl);
2036 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2037 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2038 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2039 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2040 CPMU_LSPD_1000MB_MACCLK_12_5) {
2041 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2043 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2047 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2048 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2051 tg3_phy_apply_otp(tp);
2053 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2054 tg3_phy_toggle_apd(tp, true);
2056 tg3_phy_toggle_apd(tp, false);
2059 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2060 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2061 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2062 tg3_phydsp_write(tp, 0x000a, 0x0323);
2063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2065 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2066 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2067 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2069 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2070 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2071 tg3_phydsp_write(tp, 0x000a, 0x310b);
2072 tg3_phydsp_write(tp, 0x201f, 0x9506);
2073 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2074 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2075 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2076 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2077 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2078 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2079 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2080 tg3_writephy(tp, MII_TG3_TEST1,
2081 MII_TG3_TEST1_TRIM_EN | 0x4);
2083 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2084 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2086 /* Set Extended packet length bit (bit 14) on all chips that */
2087 /* support jumbo frames */
2088 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2089 /* Cannot do read-modify-write on 5401 */
2090 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2091 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2092 /* Set bit 14 with read-modify-write to preserve other bits */
2093 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2094 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2095 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2098 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2099 * jumbo frames transmission.
2101 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2102 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2103 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2104 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2108 /* adjust output voltage */
2109 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2112 tg3_phy_toggle_automdix(tp, 1);
2113 tg3_phy_set_wirespeed(tp);
2117 static void tg3_frob_aux_power(struct tg3 *tp)
2119 bool need_vaux = false;
2121 /* The GPIOs do something completely different on 57765. */
2122 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2127 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2131 tp->pdev_peer != tp->pdev) {
2132 struct net_device *dev_peer;
2134 dev_peer = pci_get_drvdata(tp->pdev_peer);
2136 /* remove_one() may have been run on the peer. */
2138 struct tg3 *tp_peer = netdev_priv(dev_peer);
2140 if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2143 if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2144 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2149 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2150 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2155 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2157 (GRC_LCLCTRL_GPIO_OE0 |
2158 GRC_LCLCTRL_GPIO_OE1 |
2159 GRC_LCLCTRL_GPIO_OE2 |
2160 GRC_LCLCTRL_GPIO_OUTPUT0 |
2161 GRC_LCLCTRL_GPIO_OUTPUT1),
2163 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2164 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2165 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2166 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2167 GRC_LCLCTRL_GPIO_OE1 |
2168 GRC_LCLCTRL_GPIO_OE2 |
2169 GRC_LCLCTRL_GPIO_OUTPUT0 |
2170 GRC_LCLCTRL_GPIO_OUTPUT1 |
2172 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2174 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2175 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2177 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2178 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2181 u32 grc_local_ctrl = 0;
2183 /* Workaround to prevent overdrawing Amps. */
2184 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2186 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2187 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2188 grc_local_ctrl, 100);
2191 /* On 5753 and variants, GPIO2 cannot be used. */
2192 no_gpio2 = tp->nic_sram_data_cfg &
2193 NIC_SRAM_DATA_CFG_NO_GPIO2;
2195 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2196 GRC_LCLCTRL_GPIO_OE1 |
2197 GRC_LCLCTRL_GPIO_OE2 |
2198 GRC_LCLCTRL_GPIO_OUTPUT1 |
2199 GRC_LCLCTRL_GPIO_OUTPUT2;
2201 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2202 GRC_LCLCTRL_GPIO_OUTPUT2);
2204 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2205 grc_local_ctrl, 100);
2207 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2209 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2210 grc_local_ctrl, 100);
2213 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2214 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215 grc_local_ctrl, 100);
2219 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2220 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2221 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2222 (GRC_LCLCTRL_GPIO_OE1 |
2223 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2225 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2226 GRC_LCLCTRL_GPIO_OE1, 100);
2228 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2229 (GRC_LCLCTRL_GPIO_OE1 |
2230 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2235 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2237 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2239 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2240 if (speed != SPEED_10)
2242 } else if (speed == SPEED_10)
2248 static int tg3_setup_phy(struct tg3 *, int);
2250 #define RESET_KIND_SHUTDOWN 0
2251 #define RESET_KIND_INIT 1
2252 #define RESET_KIND_SUSPEND 2
2254 static void tg3_write_sig_post_reset(struct tg3 *, int);
2255 static int tg3_halt_cpu(struct tg3 *, u32);
2257 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2261 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2263 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2264 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2267 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2268 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2269 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2276 val = tr32(GRC_MISC_CFG);
2277 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2280 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2282 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2285 tg3_writephy(tp, MII_ADVERTISE, 0);
2286 tg3_writephy(tp, MII_BMCR,
2287 BMCR_ANENABLE | BMCR_ANRESTART);
2289 tg3_writephy(tp, MII_TG3_FET_TEST,
2290 phytest | MII_TG3_FET_SHADOW_EN);
2291 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2292 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2294 MII_TG3_FET_SHDW_AUXMODE4,
2297 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2300 } else if (do_low_power) {
2301 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2302 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2304 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2305 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2306 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2307 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2308 MII_TG3_AUXCTL_PCTL_VREG_11V);
2311 /* The PHY should not be powered down on some chips because
2314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2316 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2317 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2320 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2321 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2322 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2323 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2324 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2325 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2328 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2331 /* tp->lock is held. */
2332 static int tg3_nvram_lock(struct tg3 *tp)
2334 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2337 if (tp->nvram_lock_cnt == 0) {
2338 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2339 for (i = 0; i < 8000; i++) {
2340 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2345 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2349 tp->nvram_lock_cnt++;
2354 /* tp->lock is held. */
2355 static void tg3_nvram_unlock(struct tg3 *tp)
2357 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2358 if (tp->nvram_lock_cnt > 0)
2359 tp->nvram_lock_cnt--;
2360 if (tp->nvram_lock_cnt == 0)
2361 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2365 /* tp->lock is held. */
2366 static void tg3_enable_nvram_access(struct tg3 *tp)
2368 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370 u32 nvaccess = tr32(NVRAM_ACCESS);
2372 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2376 /* tp->lock is held. */
2377 static void tg3_disable_nvram_access(struct tg3 *tp)
2379 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2380 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2381 u32 nvaccess = tr32(NVRAM_ACCESS);
2383 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2387 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2388 u32 offset, u32 *val)
2393 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2396 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2397 EEPROM_ADDR_DEVID_MASK |
2399 tw32(GRC_EEPROM_ADDR,
2401 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2402 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2403 EEPROM_ADDR_ADDR_MASK) |
2404 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2406 for (i = 0; i < 1000; i++) {
2407 tmp = tr32(GRC_EEPROM_ADDR);
2409 if (tmp & EEPROM_ADDR_COMPLETE)
2413 if (!(tmp & EEPROM_ADDR_COMPLETE))
2416 tmp = tr32(GRC_EEPROM_DATA);
2419 * The data will always be opposite the native endian
2420 * format. Perform a blind byteswap to compensate.
2427 #define NVRAM_CMD_TIMEOUT 10000
2429 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2433 tw32(NVRAM_CMD, nvram_cmd);
2434 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2436 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2442 if (i == NVRAM_CMD_TIMEOUT)
2448 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2450 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2451 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2452 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2453 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2454 (tp->nvram_jedecnum == JEDEC_ATMEL))
2456 addr = ((addr / tp->nvram_pagesize) <<
2457 ATMEL_AT45DB0X1B_PAGE_POS) +
2458 (addr % tp->nvram_pagesize);
2463 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2465 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2466 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2467 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2468 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2469 (tp->nvram_jedecnum == JEDEC_ATMEL))
2471 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2472 tp->nvram_pagesize) +
2473 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2478 /* NOTE: Data read in from NVRAM is byteswapped according to
2479 * the byteswapping settings for all other register accesses.
2480 * tg3 devices are BE devices, so on a BE machine, the data
2481 * returned will be exactly as it is seen in NVRAM. On a LE
2482 * machine, the 32-bit value will be byteswapped.
2484 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2488 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2489 return tg3_nvram_read_using_eeprom(tp, offset, val);
2491 offset = tg3_nvram_phys_addr(tp, offset);
2493 if (offset > NVRAM_ADDR_MSK)
2496 ret = tg3_nvram_lock(tp);
2500 tg3_enable_nvram_access(tp);
2502 tw32(NVRAM_ADDR, offset);
2503 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2504 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2507 *val = tr32(NVRAM_RDDATA);
2509 tg3_disable_nvram_access(tp);
2511 tg3_nvram_unlock(tp);
2516 /* Ensures NVRAM data is in bytestream format. */
2517 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2520 int res = tg3_nvram_read(tp, offset, &v);
2522 *val = cpu_to_be32(v);
2526 /* tp->lock is held. */
2527 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2529 u32 addr_high, addr_low;
2532 addr_high = ((tp->dev->dev_addr[0] << 8) |
2533 tp->dev->dev_addr[1]);
2534 addr_low = ((tp->dev->dev_addr[2] << 24) |
2535 (tp->dev->dev_addr[3] << 16) |
2536 (tp->dev->dev_addr[4] << 8) |
2537 (tp->dev->dev_addr[5] << 0));
2538 for (i = 0; i < 4; i++) {
2539 if (i == 1 && skip_mac_1)
2541 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2542 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2547 for (i = 0; i < 12; i++) {
2548 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2549 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2553 addr_high = (tp->dev->dev_addr[0] +
2554 tp->dev->dev_addr[1] +
2555 tp->dev->dev_addr[2] +
2556 tp->dev->dev_addr[3] +
2557 tp->dev->dev_addr[4] +
2558 tp->dev->dev_addr[5]) &
2559 TX_BACKOFF_SEED_MASK;
2560 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2563 static void tg3_enable_register_access(struct tg3 *tp)
2566 * Make sure register accesses (indirect or otherwise) will function
2569 pci_write_config_dword(tp->pdev,
2570 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2573 static int tg3_power_up(struct tg3 *tp)
2575 tg3_enable_register_access(tp);
2577 pci_set_power_state(tp->pdev, PCI_D0);
2579 /* Switch out of Vaux if it is a NIC */
2580 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2581 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2586 static int tg3_power_down_prepare(struct tg3 *tp)
2589 bool device_should_wake, do_low_power;
2591 tg3_enable_register_access(tp);
2593 /* Restore the CLKREQ setting. */
2594 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2597 pci_read_config_word(tp->pdev,
2598 tp->pcie_cap + PCI_EXP_LNKCTL,
2600 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2601 pci_write_config_word(tp->pdev,
2602 tp->pcie_cap + PCI_EXP_LNKCTL,
2606 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2607 tw32(TG3PCI_MISC_HOST_CTRL,
2608 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2610 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2611 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2613 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2614 do_low_power = false;
2615 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2616 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2617 struct phy_device *phydev;
2618 u32 phyid, advertising;
2620 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2622 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2624 tp->link_config.orig_speed = phydev->speed;
2625 tp->link_config.orig_duplex = phydev->duplex;
2626 tp->link_config.orig_autoneg = phydev->autoneg;
2627 tp->link_config.orig_advertising = phydev->advertising;
2629 advertising = ADVERTISED_TP |
2631 ADVERTISED_Autoneg |
2632 ADVERTISED_10baseT_Half;
2634 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2635 device_should_wake) {
2636 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2638 ADVERTISED_100baseT_Half |
2639 ADVERTISED_100baseT_Full |
2640 ADVERTISED_10baseT_Full;
2642 advertising |= ADVERTISED_10baseT_Full;
2645 phydev->advertising = advertising;
2647 phy_start_aneg(phydev);
2649 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2650 if (phyid != PHY_ID_BCMAC131) {
2651 phyid &= PHY_BCM_OUI_MASK;
2652 if (phyid == PHY_BCM_OUI_1 ||
2653 phyid == PHY_BCM_OUI_2 ||
2654 phyid == PHY_BCM_OUI_3)
2655 do_low_power = true;
2659 do_low_power = true;
2661 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2662 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2663 tp->link_config.orig_speed = tp->link_config.speed;
2664 tp->link_config.orig_duplex = tp->link_config.duplex;
2665 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2668 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2669 tp->link_config.speed = SPEED_10;
2670 tp->link_config.duplex = DUPLEX_HALF;
2671 tp->link_config.autoneg = AUTONEG_ENABLE;
2672 tg3_setup_phy(tp, 0);
2676 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2679 val = tr32(GRC_VCPU_EXT_CTRL);
2680 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2681 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2685 for (i = 0; i < 200; i++) {
2686 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2687 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2692 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2693 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2694 WOL_DRV_STATE_SHUTDOWN |
2698 if (device_should_wake) {
2701 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2703 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2707 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2708 mac_mode = MAC_MODE_PORT_MODE_GMII;
2710 mac_mode = MAC_MODE_PORT_MODE_MII;
2712 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2713 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2715 u32 speed = (tp->tg3_flags &
2716 TG3_FLAG_WOL_SPEED_100MB) ?
2717 SPEED_100 : SPEED_10;
2718 if (tg3_5700_link_polarity(tp, speed))
2719 mac_mode |= MAC_MODE_LINK_POLARITY;
2721 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2724 mac_mode = MAC_MODE_PORT_MODE_TBI;
2727 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2728 tw32(MAC_LED_CTRL, tp->led_ctrl);
2730 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2731 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2732 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2733 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2734 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2735 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2737 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2738 mac_mode |= MAC_MODE_APE_TX_EN |
2739 MAC_MODE_APE_RX_EN |
2740 MAC_MODE_TDE_ENABLE;
2742 tw32_f(MAC_MODE, mac_mode);
2745 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2749 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2750 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2751 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2754 base_val = tp->pci_clock_ctrl;
2755 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2756 CLOCK_CTRL_TXCLK_DISABLE);
2758 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2759 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2760 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2761 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2762 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2764 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2765 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2766 u32 newbits1, newbits2;
2768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2769 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2770 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2771 CLOCK_CTRL_TXCLK_DISABLE |
2773 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2774 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2775 newbits1 = CLOCK_CTRL_625_CORE;
2776 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2778 newbits1 = CLOCK_CTRL_ALTCLK;
2779 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2782 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2785 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2788 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2793 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2794 CLOCK_CTRL_TXCLK_DISABLE |
2795 CLOCK_CTRL_44MHZ_CORE);
2797 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2800 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2801 tp->pci_clock_ctrl | newbits3, 40);
2805 if (!(device_should_wake) &&
2806 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2807 tg3_power_down_phy(tp, do_low_power);
2809 tg3_frob_aux_power(tp);
2811 /* Workaround for unstable PLL clock */
2812 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2813 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2814 u32 val = tr32(0x7d00);
2816 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2818 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2821 err = tg3_nvram_lock(tp);
2822 tg3_halt_cpu(tp, RX_CPU_BASE);
2824 tg3_nvram_unlock(tp);
2828 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2833 static void tg3_power_down(struct tg3 *tp)
2835 tg3_power_down_prepare(tp);
2837 pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2838 pci_set_power_state(tp->pdev, PCI_D3hot);
2841 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2843 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2844 case MII_TG3_AUX_STAT_10HALF:
2846 *duplex = DUPLEX_HALF;
2849 case MII_TG3_AUX_STAT_10FULL:
2851 *duplex = DUPLEX_FULL;
2854 case MII_TG3_AUX_STAT_100HALF:
2856 *duplex = DUPLEX_HALF;
2859 case MII_TG3_AUX_STAT_100FULL:
2861 *duplex = DUPLEX_FULL;
2864 case MII_TG3_AUX_STAT_1000HALF:
2865 *speed = SPEED_1000;
2866 *duplex = DUPLEX_HALF;
2869 case MII_TG3_AUX_STAT_1000FULL:
2870 *speed = SPEED_1000;
2871 *duplex = DUPLEX_FULL;
2875 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2876 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2878 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2882 *speed = SPEED_INVALID;
2883 *duplex = DUPLEX_INVALID;
2888 static void tg3_phy_copper_begin(struct tg3 *tp)
2893 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2894 /* Entering low power mode. Disable gigabit and
2895 * 100baseT advertisements.
2897 tg3_writephy(tp, MII_TG3_CTRL, 0);
2899 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2900 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2901 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2902 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2904 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2905 } else if (tp->link_config.speed == SPEED_INVALID) {
2906 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2907 tp->link_config.advertising &=
2908 ~(ADVERTISED_1000baseT_Half |
2909 ADVERTISED_1000baseT_Full);
2911 new_adv = ADVERTISE_CSMA;
2912 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2913 new_adv |= ADVERTISE_10HALF;
2914 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2915 new_adv |= ADVERTISE_10FULL;
2916 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2917 new_adv |= ADVERTISE_100HALF;
2918 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2919 new_adv |= ADVERTISE_100FULL;
2921 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2923 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2925 if (tp->link_config.advertising &
2926 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2928 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2929 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2930 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2931 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2932 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2933 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2934 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2935 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2936 MII_TG3_CTRL_ENABLE_AS_MASTER);
2937 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2939 tg3_writephy(tp, MII_TG3_CTRL, 0);
2942 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2943 new_adv |= ADVERTISE_CSMA;
2945 /* Asking for a specific link mode. */
2946 if (tp->link_config.speed == SPEED_1000) {
2947 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2949 if (tp->link_config.duplex == DUPLEX_FULL)
2950 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2952 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2953 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2954 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2955 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2956 MII_TG3_CTRL_ENABLE_AS_MASTER);
2958 if (tp->link_config.speed == SPEED_100) {
2959 if (tp->link_config.duplex == DUPLEX_FULL)
2960 new_adv |= ADVERTISE_100FULL;
2962 new_adv |= ADVERTISE_100HALF;
2964 if (tp->link_config.duplex == DUPLEX_FULL)
2965 new_adv |= ADVERTISE_10FULL;
2967 new_adv |= ADVERTISE_10HALF;
2969 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2974 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2977 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2980 tw32(TG3_CPMU_EEE_MODE,
2981 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2983 /* Enable SM_DSP clock and tx 6dB coding. */
2984 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2985 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2986 MII_TG3_AUXCTL_ACTL_TX_6DB;
2987 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2989 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2991 case ASIC_REV_57765:
2992 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2993 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2994 MII_TG3_DSP_CH34TP2_HIBW01);
2997 val = MII_TG3_DSP_TAP26_ALNOKO |
2998 MII_TG3_DSP_TAP26_RMRXSTO |
2999 MII_TG3_DSP_TAP26_OPCSINPT;
3000 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3004 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3005 /* Advertise 100-BaseTX EEE ability */
3006 if (tp->link_config.advertising &
3007 ADVERTISED_100baseT_Full)
3008 val |= MDIO_AN_EEE_ADV_100TX;
3009 /* Advertise 1000-BaseT EEE ability */
3010 if (tp->link_config.advertising &
3011 ADVERTISED_1000baseT_Full)
3012 val |= MDIO_AN_EEE_ADV_1000T;
3014 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3016 /* Turn off SM_DSP clock. */
3017 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3018 MII_TG3_AUXCTL_ACTL_TX_6DB;
3019 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3022 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3023 tp->link_config.speed != SPEED_INVALID) {
3024 u32 bmcr, orig_bmcr;
3026 tp->link_config.active_speed = tp->link_config.speed;
3027 tp->link_config.active_duplex = tp->link_config.duplex;
3030 switch (tp->link_config.speed) {
3036 bmcr |= BMCR_SPEED100;
3040 bmcr |= TG3_BMCR_SPEED1000;
3044 if (tp->link_config.duplex == DUPLEX_FULL)
3045 bmcr |= BMCR_FULLDPLX;
3047 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3048 (bmcr != orig_bmcr)) {
3049 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3050 for (i = 0; i < 1500; i++) {
3054 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3055 tg3_readphy(tp, MII_BMSR, &tmp))
3057 if (!(tmp & BMSR_LSTATUS)) {
3062 tg3_writephy(tp, MII_BMCR, bmcr);
3066 tg3_writephy(tp, MII_BMCR,
3067 BMCR_ANENABLE | BMCR_ANRESTART);
3071 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3075 /* Turn off tap power management. */
3076 /* Set Extended packet length bit */
3077 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3079 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3080 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3081 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3082 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3083 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3090 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3092 u32 adv_reg, all_mask = 0;
3094 if (mask & ADVERTISED_10baseT_Half)
3095 all_mask |= ADVERTISE_10HALF;
3096 if (mask & ADVERTISED_10baseT_Full)
3097 all_mask |= ADVERTISE_10FULL;
3098 if (mask & ADVERTISED_100baseT_Half)
3099 all_mask |= ADVERTISE_100HALF;
3100 if (mask & ADVERTISED_100baseT_Full)
3101 all_mask |= ADVERTISE_100FULL;
3103 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3106 if ((adv_reg & all_mask) != all_mask)
3108 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3112 if (mask & ADVERTISED_1000baseT_Half)
3113 all_mask |= ADVERTISE_1000HALF;
3114 if (mask & ADVERTISED_1000baseT_Full)
3115 all_mask |= ADVERTISE_1000FULL;
3117 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3120 if ((tg3_ctrl & all_mask) != all_mask)
3126 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3130 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3133 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3134 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3136 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3137 if (curadv != reqadv)
3140 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3141 tg3_readphy(tp, MII_LPA, rmtadv);
3143 /* Reprogram the advertisement register, even if it
3144 * does not affect the current link. If the link
3145 * gets renegotiated in the future, we can save an
3146 * additional renegotiation cycle by advertising
3147 * it correctly in the first place.
3149 if (curadv != reqadv) {
3150 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3151 ADVERTISE_PAUSE_ASYM);
3152 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3159 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3161 int current_link_up;
3163 u32 lcl_adv, rmt_adv;
3171 (MAC_STATUS_SYNC_CHANGED |
3172 MAC_STATUS_CFG_CHANGED |
3173 MAC_STATUS_MI_COMPLETION |
3174 MAC_STATUS_LNKSTATE_CHANGED));
3177 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3179 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3183 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3185 /* Some third-party PHYs need to be reset on link going
3188 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3191 netif_carrier_ok(tp->dev)) {
3192 tg3_readphy(tp, MII_BMSR, &bmsr);
3193 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3194 !(bmsr & BMSR_LSTATUS))
3200 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3201 tg3_readphy(tp, MII_BMSR, &bmsr);
3202 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3203 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3206 if (!(bmsr & BMSR_LSTATUS)) {
3207 err = tg3_init_5401phy_dsp(tp);
3211 tg3_readphy(tp, MII_BMSR, &bmsr);
3212 for (i = 0; i < 1000; i++) {
3214 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3215 (bmsr & BMSR_LSTATUS)) {
3221 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3222 TG3_PHY_REV_BCM5401_B0 &&
3223 !(bmsr & BMSR_LSTATUS) &&
3224 tp->link_config.active_speed == SPEED_1000) {
3225 err = tg3_phy_reset(tp);
3227 err = tg3_init_5401phy_dsp(tp);
3232 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3233 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3234 /* 5701 {A0,B0} CRC bug workaround */
3235 tg3_writephy(tp, 0x15, 0x0a75);
3236 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3237 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3238 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3241 /* Clear pending interrupts... */
3242 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3243 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3245 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3246 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3247 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3248 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3250 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3252 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3253 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3254 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3256 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3259 current_link_up = 0;
3260 current_speed = SPEED_INVALID;
3261 current_duplex = DUPLEX_INVALID;
3263 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3264 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3265 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3266 if (!(val & (1 << 10))) {
3268 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3274 for (i = 0; i < 100; i++) {
3275 tg3_readphy(tp, MII_BMSR, &bmsr);
3276 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3277 (bmsr & BMSR_LSTATUS))
3282 if (bmsr & BMSR_LSTATUS) {
3285 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3286 for (i = 0; i < 2000; i++) {
3288 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3293 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3298 for (i = 0; i < 200; i++) {
3299 tg3_readphy(tp, MII_BMCR, &bmcr);
3300 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3302 if (bmcr && bmcr != 0x7fff)
3310 tp->link_config.active_speed = current_speed;
3311 tp->link_config.active_duplex = current_duplex;
3313 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3314 if ((bmcr & BMCR_ANENABLE) &&
3315 tg3_copper_is_advertising_all(tp,
3316 tp->link_config.advertising)) {
3317 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3319 current_link_up = 1;
3322 if (!(bmcr & BMCR_ANENABLE) &&
3323 tp->link_config.speed == current_speed &&
3324 tp->link_config.duplex == current_duplex &&
3325 tp->link_config.flowctrl ==
3326 tp->link_config.active_flowctrl) {
3327 current_link_up = 1;
3331 if (current_link_up == 1 &&
3332 tp->link_config.active_duplex == DUPLEX_FULL)
3333 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3337 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3338 tg3_phy_copper_begin(tp);
3340 tg3_readphy(tp, MII_BMSR, &bmsr);
3341 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3342 (bmsr & BMSR_LSTATUS))
3343 current_link_up = 1;
3346 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3347 if (current_link_up == 1) {
3348 if (tp->link_config.active_speed == SPEED_100 ||
3349 tp->link_config.active_speed == SPEED_10)
3350 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3352 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3353 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3354 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3356 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3358 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3359 if (tp->link_config.active_duplex == DUPLEX_HALF)
3360 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3363 if (current_link_up == 1 &&
3364 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3365 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3367 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3370 /* ??? Without this setting Netgear GA302T PHY does not
3371 * ??? send/receive packets...
3373 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3374 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3375 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3376 tw32_f(MAC_MI_MODE, tp->mi_mode);
3380 tw32_f(MAC_MODE, tp->mac_mode);
3383 tg3_phy_eee_adjust(tp, current_link_up);
3385 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3386 /* Polled via timer. */
3387 tw32_f(MAC_EVENT, 0);
3389 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3394 current_link_up == 1 &&
3395 tp->link_config.active_speed == SPEED_1000 &&
3396 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3397 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3400 (MAC_STATUS_SYNC_CHANGED |
3401 MAC_STATUS_CFG_CHANGED));
3404 NIC_SRAM_FIRMWARE_MBOX,
3405 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3408 /* Prevent send BD corruption. */
3409 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3410 u16 oldlnkctl, newlnkctl;
3412 pci_read_config_word(tp->pdev,
3413 tp->pcie_cap + PCI_EXP_LNKCTL,
3415 if (tp->link_config.active_speed == SPEED_100 ||
3416 tp->link_config.active_speed == SPEED_10)
3417 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3419 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3420 if (newlnkctl != oldlnkctl)
3421 pci_write_config_word(tp->pdev,
3422 tp->pcie_cap + PCI_EXP_LNKCTL,
3426 if (current_link_up != netif_carrier_ok(tp->dev)) {
3427 if (current_link_up)
3428 netif_carrier_on(tp->dev);
3430 netif_carrier_off(tp->dev);
3431 tg3_link_report(tp);
3437 struct tg3_fiber_aneginfo {
3439 #define ANEG_STATE_UNKNOWN 0
3440 #define ANEG_STATE_AN_ENABLE 1
3441 #define ANEG_STATE_RESTART_INIT 2
3442 #define ANEG_STATE_RESTART 3
3443 #define ANEG_STATE_DISABLE_LINK_OK 4
3444 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3445 #define ANEG_STATE_ABILITY_DETECT 6
3446 #define ANEG_STATE_ACK_DETECT_INIT 7
3447 #define ANEG_STATE_ACK_DETECT 8
3448 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3449 #define ANEG_STATE_COMPLETE_ACK 10
3450 #define ANEG_STATE_IDLE_DETECT_INIT 11
3451 #define ANEG_STATE_IDLE_DETECT 12
3452 #define ANEG_STATE_LINK_OK 13
3453 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3454 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3457 #define MR_AN_ENABLE 0x00000001
3458 #define MR_RESTART_AN 0x00000002
3459 #define MR_AN_COMPLETE 0x00000004
3460 #define MR_PAGE_RX 0x00000008
3461 #define MR_NP_LOADED 0x00000010
3462 #define MR_TOGGLE_TX 0x00000020
3463 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3464 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3465 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3466 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3467 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3468 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3469 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3470 #define MR_TOGGLE_RX 0x00002000
3471 #define MR_NP_RX 0x00004000
3473 #define MR_LINK_OK 0x80000000
3475 unsigned long link_time, cur_time;
3477 u32 ability_match_cfg;
3478 int ability_match_count;
3480 char ability_match, idle_match, ack_match;
3482 u32 txconfig, rxconfig;
3483 #define ANEG_CFG_NP 0x00000080
3484 #define ANEG_CFG_ACK 0x00000040
3485 #define ANEG_CFG_RF2 0x00000020
3486 #define ANEG_CFG_RF1 0x00000010
3487 #define ANEG_CFG_PS2 0x00000001
3488 #define ANEG_CFG_PS1 0x00008000
3489 #define ANEG_CFG_HD 0x00004000
3490 #define ANEG_CFG_FD 0x00002000
3491 #define ANEG_CFG_INVAL 0x00001f06
3496 #define ANEG_TIMER_ENAB 2
3497 #define ANEG_FAILED -1
3499 #define ANEG_STATE_SETTLE_TIME 10000
3501 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3502 struct tg3_fiber_aneginfo *ap)
3505 unsigned long delta;
3509 if (ap->state == ANEG_STATE_UNKNOWN) {
3513 ap->ability_match_cfg = 0;
3514 ap->ability_match_count = 0;
3515 ap->ability_match = 0;
3521 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3522 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3524 if (rx_cfg_reg != ap->ability_match_cfg) {
3525 ap->ability_match_cfg = rx_cfg_reg;
3526 ap->ability_match = 0;
3527 ap->ability_match_count = 0;
3529 if (++ap->ability_match_count > 1) {
3530 ap->ability_match = 1;
3531 ap->ability_match_cfg = rx_cfg_reg;
3534 if (rx_cfg_reg & ANEG_CFG_ACK)
3542 ap->ability_match_cfg = 0;
3543 ap->ability_match_count = 0;
3544 ap->ability_match = 0;
3550 ap->rxconfig = rx_cfg_reg;
3553 switch (ap->state) {
3554 case ANEG_STATE_UNKNOWN:
3555 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3556 ap->state = ANEG_STATE_AN_ENABLE;
3559 case ANEG_STATE_AN_ENABLE:
3560 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3561 if (ap->flags & MR_AN_ENABLE) {
3564 ap->ability_match_cfg = 0;
3565 ap->ability_match_count = 0;
3566 ap->ability_match = 0;
3570 ap->state = ANEG_STATE_RESTART_INIT;
3572 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3576 case ANEG_STATE_RESTART_INIT:
3577 ap->link_time = ap->cur_time;
3578 ap->flags &= ~(MR_NP_LOADED);
3580 tw32(MAC_TX_AUTO_NEG, 0);
3581 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3582 tw32_f(MAC_MODE, tp->mac_mode);
3585 ret = ANEG_TIMER_ENAB;
3586 ap->state = ANEG_STATE_RESTART;
3589 case ANEG_STATE_RESTART:
3590 delta = ap->cur_time - ap->link_time;
3591 if (delta > ANEG_STATE_SETTLE_TIME)
3592 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3594 ret = ANEG_TIMER_ENAB;
3597 case ANEG_STATE_DISABLE_LINK_OK:
3601 case ANEG_STATE_ABILITY_DETECT_INIT:
3602 ap->flags &= ~(MR_TOGGLE_TX);
3603 ap->txconfig = ANEG_CFG_FD;
3604 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3605 if (flowctrl & ADVERTISE_1000XPAUSE)
3606 ap->txconfig |= ANEG_CFG_PS1;
3607 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3608 ap->txconfig |= ANEG_CFG_PS2;
3609 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3610 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3611 tw32_f(MAC_MODE, tp->mac_mode);
3614 ap->state = ANEG_STATE_ABILITY_DETECT;
3617 case ANEG_STATE_ABILITY_DETECT:
3618 if (ap->ability_match != 0 && ap->rxconfig != 0)
3619 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3622 case ANEG_STATE_ACK_DETECT_INIT:
3623 ap->txconfig |= ANEG_CFG_ACK;
3624 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3625 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3626 tw32_f(MAC_MODE, tp->mac_mode);
3629 ap->state = ANEG_STATE_ACK_DETECT;
3632 case ANEG_STATE_ACK_DETECT:
3633 if (ap->ack_match != 0) {
3634 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3635 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3636 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3638 ap->state = ANEG_STATE_AN_ENABLE;
3640 } else if (ap->ability_match != 0 &&
3641 ap->rxconfig == 0) {
3642 ap->state = ANEG_STATE_AN_ENABLE;
3646 case ANEG_STATE_COMPLETE_ACK_INIT:
3647 if (ap->rxconfig & ANEG_CFG_INVAL) {
3651 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3652 MR_LP_ADV_HALF_DUPLEX |
3653 MR_LP_ADV_SYM_PAUSE |
3654 MR_LP_ADV_ASYM_PAUSE |
3655 MR_LP_ADV_REMOTE_FAULT1 |
3656 MR_LP_ADV_REMOTE_FAULT2 |
3657 MR_LP_ADV_NEXT_PAGE |
3660 if (ap->rxconfig & ANEG_CFG_FD)
3661 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3662 if (ap->rxconfig & ANEG_CFG_HD)
3663 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3664 if (ap->rxconfig & ANEG_CFG_PS1)
3665 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3666 if (ap->rxconfig & ANEG_CFG_PS2)
3667 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3668 if (ap->rxconfig & ANEG_CFG_RF1)
3669 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3670 if (ap->rxconfig & ANEG_CFG_RF2)
3671 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3672 if (ap->rxconfig & ANEG_CFG_NP)
3673 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3675 ap->link_time = ap->cur_time;
3677 ap->flags ^= (MR_TOGGLE_TX);
3678 if (ap->rxconfig & 0x0008)
3679 ap->flags |= MR_TOGGLE_RX;
3680 if (ap->rxconfig & ANEG_CFG_NP)
3681 ap->flags |= MR_NP_RX;
3682 ap->flags |= MR_PAGE_RX;
3684 ap->state = ANEG_STATE_COMPLETE_ACK;
3685 ret = ANEG_TIMER_ENAB;
3688 case ANEG_STATE_COMPLETE_ACK:
3689 if (ap->ability_match != 0 &&
3690 ap->rxconfig == 0) {
3691 ap->state = ANEG_STATE_AN_ENABLE;
3694 delta = ap->cur_time - ap->link_time;
3695 if (delta > ANEG_STATE_SETTLE_TIME) {
3696 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3697 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3699 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3700 !(ap->flags & MR_NP_RX)) {
3701 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3709 case ANEG_STATE_IDLE_DETECT_INIT:
3710 ap->link_time = ap->cur_time;
3711 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3712 tw32_f(MAC_MODE, tp->mac_mode);
3715 ap->state = ANEG_STATE_IDLE_DETECT;
3716 ret = ANEG_TIMER_ENAB;
3719 case ANEG_STATE_IDLE_DETECT:
3720 if (ap->ability_match != 0 &&
3721 ap->rxconfig == 0) {
3722 ap->state = ANEG_STATE_AN_ENABLE;
3725 delta = ap->cur_time - ap->link_time;
3726 if (delta > ANEG_STATE_SETTLE_TIME) {
3727 /* XXX another gem from the Broadcom driver :( */
3728 ap->state = ANEG_STATE_LINK_OK;
3732 case ANEG_STATE_LINK_OK:
3733 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3737 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3738 /* ??? unimplemented */
3741 case ANEG_STATE_NEXT_PAGE_WAIT:
3742 /* ??? unimplemented */
3753 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3756 struct tg3_fiber_aneginfo aninfo;
3757 int status = ANEG_FAILED;
3761 tw32_f(MAC_TX_AUTO_NEG, 0);
3763 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3764 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3767 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3770 memset(&aninfo, 0, sizeof(aninfo));
3771 aninfo.flags |= MR_AN_ENABLE;
3772 aninfo.state = ANEG_STATE_UNKNOWN;
3773 aninfo.cur_time = 0;
3775 while (++tick < 195000) {
3776 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3777 if (status == ANEG_DONE || status == ANEG_FAILED)
3783 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3784 tw32_f(MAC_MODE, tp->mac_mode);
3787 *txflags = aninfo.txconfig;
3788 *rxflags = aninfo.flags;
3790 if (status == ANEG_DONE &&
3791 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3792 MR_LP_ADV_FULL_DUPLEX)))
3798 static void tg3_init_bcm8002(struct tg3 *tp)
3800 u32 mac_status = tr32(MAC_STATUS);
3803 /* Reset when initting first time or we have a link. */
3804 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3805 !(mac_status & MAC_STATUS_PCS_SYNCED))
3808 /* Set PLL lock range. */
3809 tg3_writephy(tp, 0x16, 0x8007);
3812 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3814 /* Wait for reset to complete. */
3815 /* XXX schedule_timeout() ... */
3816 for (i = 0; i < 500; i++)
3819 /* Config mode; select PMA/Ch 1 regs. */
3820 tg3_writephy(tp, 0x10, 0x8411);
3822 /* Enable auto-lock and comdet, select txclk for tx. */
3823 tg3_writephy(tp, 0x11, 0x0a10);
3825 tg3_writephy(tp, 0x18, 0x00a0);
3826 tg3_writephy(tp, 0x16, 0x41ff);
3828 /* Assert and deassert POR. */
3829 tg3_writephy(tp, 0x13, 0x0400);
3831 tg3_writephy(tp, 0x13, 0x0000);
3833 tg3_writephy(tp, 0x11, 0x0a50);
3835 tg3_writephy(tp, 0x11, 0x0a10);
3837 /* Wait for signal to stabilize */
3838 /* XXX schedule_timeout() ... */
3839 for (i = 0; i < 15000; i++)
3842 /* Deselect the channel register so we can read the PHYID
3845 tg3_writephy(tp, 0x10, 0x8011);
3848 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3851 u32 sg_dig_ctrl, sg_dig_status;
3852 u32 serdes_cfg, expected_sg_dig_ctrl;
3853 int workaround, port_a;
3854 int current_link_up;
3857 expected_sg_dig_ctrl = 0;
3860 current_link_up = 0;
3862 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3863 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3865 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3868 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3869 /* preserve bits 20-23 for voltage regulator */
3870 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3873 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3875 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3876 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3878 u32 val = serdes_cfg;
3884 tw32_f(MAC_SERDES_CFG, val);
3887 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3889 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3890 tg3_setup_flow_control(tp, 0, 0);
3891 current_link_up = 1;
3896 /* Want auto-negotiation. */
3897 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3899 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3900 if (flowctrl & ADVERTISE_1000XPAUSE)
3901 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3902 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3903 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3905 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3906 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3907 tp->serdes_counter &&
3908 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3909 MAC_STATUS_RCVD_CFG)) ==
3910 MAC_STATUS_PCS_SYNCED)) {
3911 tp->serdes_counter--;
3912 current_link_up = 1;
3917 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3918 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3920 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3922 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3923 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3924 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3925 MAC_STATUS_SIGNAL_DET)) {
3926 sg_dig_status = tr32(SG_DIG_STATUS);
3927 mac_status = tr32(MAC_STATUS);
3929 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3930 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3931 u32 local_adv = 0, remote_adv = 0;
3933 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3934 local_adv |= ADVERTISE_1000XPAUSE;
3935 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3936 local_adv |= ADVERTISE_1000XPSE_ASYM;
3938 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3939 remote_adv |= LPA_1000XPAUSE;
3940 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3941 remote_adv |= LPA_1000XPAUSE_ASYM;
3943 tg3_setup_flow_control(tp, local_adv, remote_adv);
3944 current_link_up = 1;
3945 tp->serdes_counter = 0;
3946 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3947 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3948 if (tp->serdes_counter)
3949 tp->serdes_counter--;
3952 u32 val = serdes_cfg;
3959 tw32_f(MAC_SERDES_CFG, val);
3962 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3965 /* Link parallel detection - link is up */
3966 /* only if we have PCS_SYNC and not */
3967 /* receiving config code words */
3968 mac_status = tr32(MAC_STATUS);
3969 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3970 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3971 tg3_setup_flow_control(tp, 0, 0);
3972 current_link_up = 1;
3974 TG3_PHYFLG_PARALLEL_DETECT;
3975 tp->serdes_counter =
3976 SERDES_PARALLEL_DET_TIMEOUT;
3978 goto restart_autoneg;
3982 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3983 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3987 return current_link_up;
3990 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3992 int current_link_up = 0;
3994 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3997 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3998 u32 txflags, rxflags;
4001 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4002 u32 local_adv = 0, remote_adv = 0;
4004 if (txflags & ANEG_CFG_PS1)
4005 local_adv |= ADVERTISE_1000XPAUSE;
4006 if (txflags & ANEG_CFG_PS2)
4007 local_adv |= ADVERTISE_1000XPSE_ASYM;
4009 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4010 remote_adv |= LPA_1000XPAUSE;
4011 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4012 remote_adv |= LPA_1000XPAUSE_ASYM;
4014 tg3_setup_flow_control(tp, local_adv, remote_adv);
4016 current_link_up = 1;
4018 for (i = 0; i < 30; i++) {
4021 (MAC_STATUS_SYNC_CHANGED |
4022 MAC_STATUS_CFG_CHANGED));
4024 if ((tr32(MAC_STATUS) &
4025 (MAC_STATUS_SYNC_CHANGED |
4026 MAC_STATUS_CFG_CHANGED)) == 0)
4030 mac_status = tr32(MAC_STATUS);
4031 if (current_link_up == 0 &&
4032 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4033 !(mac_status & MAC_STATUS_RCVD_CFG))
4034 current_link_up = 1;
4036 tg3_setup_flow_control(tp, 0, 0);
4038 /* Forcing 1000FD link up. */
4039 current_link_up = 1;
4041 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4044 tw32_f(MAC_MODE, tp->mac_mode);
4049 return current_link_up;
4052 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4055 u16 orig_active_speed;
4056 u8 orig_active_duplex;
4058 int current_link_up;
4061 orig_pause_cfg = tp->link_config.active_flowctrl;
4062 orig_active_speed = tp->link_config.active_speed;
4063 orig_active_duplex = tp->link_config.active_duplex;
4065 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4066 netif_carrier_ok(tp->dev) &&
4067 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4068 mac_status = tr32(MAC_STATUS);
4069 mac_status &= (MAC_STATUS_PCS_SYNCED |
4070 MAC_STATUS_SIGNAL_DET |
4071 MAC_STATUS_CFG_CHANGED |
4072 MAC_STATUS_RCVD_CFG);
4073 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4074 MAC_STATUS_SIGNAL_DET)) {
4075 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4076 MAC_STATUS_CFG_CHANGED));
4081 tw32_f(MAC_TX_AUTO_NEG, 0);
4083 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4084 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4085 tw32_f(MAC_MODE, tp->mac_mode);
4088 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4089 tg3_init_bcm8002(tp);
4091 /* Enable link change event even when serdes polling. */
4092 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4095 current_link_up = 0;
4096 mac_status = tr32(MAC_STATUS);
4098 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4099 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4101 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4103 tp->napi[0].hw_status->status =
4104 (SD_STATUS_UPDATED |
4105 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4107 for (i = 0; i < 100; i++) {
4108 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4109 MAC_STATUS_CFG_CHANGED));
4111 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4112 MAC_STATUS_CFG_CHANGED |
4113 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4117 mac_status = tr32(MAC_STATUS);
4118 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4119 current_link_up = 0;
4120 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4121 tp->serdes_counter == 0) {
4122 tw32_f(MAC_MODE, (tp->mac_mode |
4123 MAC_MODE_SEND_CONFIGS));
4125 tw32_f(MAC_MODE, tp->mac_mode);
4129 if (current_link_up == 1) {
4130 tp->link_config.active_speed = SPEED_1000;
4131 tp->link_config.active_duplex = DUPLEX_FULL;
4132 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4133 LED_CTRL_LNKLED_OVERRIDE |
4134 LED_CTRL_1000MBPS_ON));
4136 tp->link_config.active_speed = SPEED_INVALID;
4137 tp->link_config.active_duplex = DUPLEX_INVALID;
4138 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4139 LED_CTRL_LNKLED_OVERRIDE |
4140 LED_CTRL_TRAFFIC_OVERRIDE));
4143 if (current_link_up != netif_carrier_ok(tp->dev)) {
4144 if (current_link_up)
4145 netif_carrier_on(tp->dev);
4147 netif_carrier_off(tp->dev);
4148 tg3_link_report(tp);
4150 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4151 if (orig_pause_cfg != now_pause_cfg ||
4152 orig_active_speed != tp->link_config.active_speed ||
4153 orig_active_duplex != tp->link_config.active_duplex)
4154 tg3_link_report(tp);
4160 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4162 int current_link_up, err = 0;
4166 u32 local_adv, remote_adv;
4168 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4169 tw32_f(MAC_MODE, tp->mac_mode);
4175 (MAC_STATUS_SYNC_CHANGED |
4176 MAC_STATUS_CFG_CHANGED |
4177 MAC_STATUS_MI_COMPLETION |
4178 MAC_STATUS_LNKSTATE_CHANGED));
4184 current_link_up = 0;
4185 current_speed = SPEED_INVALID;
4186 current_duplex = DUPLEX_INVALID;
4188 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4189 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4191 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4192 bmsr |= BMSR_LSTATUS;
4194 bmsr &= ~BMSR_LSTATUS;
4197 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4199 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4200 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4201 /* do nothing, just check for link up at the end */
4202 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4205 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4206 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4207 ADVERTISE_1000XPAUSE |
4208 ADVERTISE_1000XPSE_ASYM |
4211 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4213 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4214 new_adv |= ADVERTISE_1000XHALF;
4215 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4216 new_adv |= ADVERTISE_1000XFULL;
4218 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4219 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4220 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4221 tg3_writephy(tp, MII_BMCR, bmcr);
4223 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4224 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4225 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4232 bmcr &= ~BMCR_SPEED1000;
4233 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4235 if (tp->link_config.duplex == DUPLEX_FULL)
4236 new_bmcr |= BMCR_FULLDPLX;
4238 if (new_bmcr != bmcr) {
4239 /* BMCR_SPEED1000 is a reserved bit that needs
4240 * to be set on write.
4242 new_bmcr |= BMCR_SPEED1000;
4244 /* Force a linkdown */
4245 if (netif_carrier_ok(tp->dev)) {
4248 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4249 adv &= ~(ADVERTISE_1000XFULL |
4250 ADVERTISE_1000XHALF |
4252 tg3_writephy(tp, MII_ADVERTISE, adv);
4253 tg3_writephy(tp, MII_BMCR, bmcr |
4257 netif_carrier_off(tp->dev);
4259 tg3_writephy(tp, MII_BMCR, new_bmcr);
4261 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4262 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4263 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4265 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4266 bmsr |= BMSR_LSTATUS;
4268 bmsr &= ~BMSR_LSTATUS;
4270 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4274 if (bmsr & BMSR_LSTATUS) {
4275 current_speed = SPEED_1000;
4276 current_link_up = 1;
4277 if (bmcr & BMCR_FULLDPLX)
4278 current_duplex = DUPLEX_FULL;
4280 current_duplex = DUPLEX_HALF;
4285 if (bmcr & BMCR_ANENABLE) {
4288 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4289 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4290 common = local_adv & remote_adv;
4291 if (common & (ADVERTISE_1000XHALF |
4292 ADVERTISE_1000XFULL)) {
4293 if (common & ADVERTISE_1000XFULL)
4294 current_duplex = DUPLEX_FULL;
4296 current_duplex = DUPLEX_HALF;
4297 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4298 /* Link is up via parallel detect */
4300 current_link_up = 0;
4305 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4306 tg3_setup_flow_control(tp, local_adv, remote_adv);
4308 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4309 if (tp->link_config.active_duplex == DUPLEX_HALF)
4310 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4312 tw32_f(MAC_MODE, tp->mac_mode);
4315 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4317 tp->link_config.active_speed = current_speed;
4318 tp->link_config.active_duplex = current_duplex;
4320 if (current_link_up != netif_carrier_ok(tp->dev)) {
4321 if (current_link_up)
4322 netif_carrier_on(tp->dev);
4324 netif_carrier_off(tp->dev);
4325 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4327 tg3_link_report(tp);
4332 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4334 if (tp->serdes_counter) {
4335 /* Give autoneg time to complete. */
4336 tp->serdes_counter--;
4340 if (!netif_carrier_ok(tp->dev) &&
4341 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4344 tg3_readphy(tp, MII_BMCR, &bmcr);
4345 if (bmcr & BMCR_ANENABLE) {
4348 /* Select shadow register 0x1f */
4349 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4350 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4352 /* Select expansion interrupt status register */
4353 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4354 MII_TG3_DSP_EXP1_INT_STAT);
4355 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4356 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4358 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4359 /* We have signal detect and not receiving
4360 * config code words, link is up by parallel
4364 bmcr &= ~BMCR_ANENABLE;
4365 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4366 tg3_writephy(tp, MII_BMCR, bmcr);
4367 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4370 } else if (netif_carrier_ok(tp->dev) &&
4371 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4372 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4375 /* Select expansion interrupt status register */
4376 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4377 MII_TG3_DSP_EXP1_INT_STAT);
4378 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4382 /* Config code words received, turn on autoneg. */
4383 tg3_readphy(tp, MII_BMCR, &bmcr);
4384 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4386 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4392 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4397 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4398 err = tg3_setup_fiber_phy(tp, force_reset);
4399 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4400 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4402 err = tg3_setup_copper_phy(tp, force_reset);
4404 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4407 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4408 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4410 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4415 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4416 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4417 tw32(GRC_MISC_CFG, val);
4420 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4421 (6 << TX_LENGTHS_IPG_SHIFT);
4422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4423 val |= tr32(MAC_TX_LENGTHS) &
4424 (TX_LENGTHS_JMB_FRM_LEN_MSK |
4425 TX_LENGTHS_CNT_DWN_VAL_MSK);
4427 if (tp->link_config.active_speed == SPEED_1000 &&
4428 tp->link_config.active_duplex == DUPLEX_HALF)
4429 tw32(MAC_TX_LENGTHS, val |
4430 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4432 tw32(MAC_TX_LENGTHS, val |
4433 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4435 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4436 if (netif_carrier_ok(tp->dev)) {
4437 tw32(HOSTCC_STAT_COAL_TICKS,
4438 tp->coal.stats_block_coalesce_usecs);
4440 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4444 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4445 val = tr32(PCIE_PWR_MGMT_THRESH);
4446 if (!netif_carrier_ok(tp->dev))
4447 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4450 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4451 tw32(PCIE_PWR_MGMT_THRESH, val);
4457 static inline int tg3_irq_sync(struct tg3 *tp)
4459 return tp->irq_sync;
4462 /* This is called whenever we suspect that the system chipset is re-
4463 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4464 * is bogus tx completions. We try to recover by setting the
4465 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4468 static void tg3_tx_recover(struct tg3 *tp)
4470 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4471 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4473 netdev_warn(tp->dev,
4474 "The system may be re-ordering memory-mapped I/O "
4475 "cycles to the network device, attempting to recover. "
4476 "Please report the problem to the driver maintainer "
4477 "and include system chipset information.\n");
4479 spin_lock(&tp->lock);
4480 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4481 spin_unlock(&tp->lock);
4484 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4486 /* Tell compiler to fetch tx indices from memory. */
4488 return tnapi->tx_pending -
4489 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4492 /* Tigon3 never reports partial packet sends. So we do not
4493 * need special logic to handle SKBs that have not had all
4494 * of their frags sent yet, like SunGEM does.
4496 static void tg3_tx(struct tg3_napi *tnapi)
4498 struct tg3 *tp = tnapi->tp;
4499 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4500 u32 sw_idx = tnapi->tx_cons;
4501 struct netdev_queue *txq;
4502 int index = tnapi - tp->napi;
4504 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4507 txq = netdev_get_tx_queue(tp->dev, index);
4509 while (sw_idx != hw_idx) {
4510 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4511 struct sk_buff *skb = ri->skb;
4514 if (unlikely(skb == NULL)) {
4519 pci_unmap_single(tp->pdev,
4520 dma_unmap_addr(ri, mapping),
4526 sw_idx = NEXT_TX(sw_idx);
4528 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4529 ri = &tnapi->tx_buffers[sw_idx];
4530 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4533 pci_unmap_page(tp->pdev,
4534 dma_unmap_addr(ri, mapping),
4535 skb_shinfo(skb)->frags[i].size,
4537 sw_idx = NEXT_TX(sw_idx);
4542 if (unlikely(tx_bug)) {
4548 tnapi->tx_cons = sw_idx;
4550 /* Need to make the tx_cons update visible to tg3_start_xmit()
4551 * before checking for netif_queue_stopped(). Without the
4552 * memory barrier, there is a small possibility that tg3_start_xmit()
4553 * will miss it and cause the queue to be stopped forever.
4557 if (unlikely(netif_tx_queue_stopped(txq) &&
4558 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4559 __netif_tx_lock(txq, smp_processor_id());
4560 if (netif_tx_queue_stopped(txq) &&
4561 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4562 netif_tx_wake_queue(txq);
4563 __netif_tx_unlock(txq);
4567 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4572 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4573 map_sz, PCI_DMA_FROMDEVICE);
4574 dev_kfree_skb_any(ri->skb);
4578 /* Returns size of skb allocated or < 0 on error.
4580 * We only need to fill in the address because the other members
4581 * of the RX descriptor are invariant, see tg3_init_rings.
4583 * Note the purposeful assymetry of cpu vs. chip accesses. For
4584 * posting buffers we only dirty the first cache line of the RX
4585 * descriptor (containing the address). Whereas for the RX status
4586 * buffers the cpu only reads the last cacheline of the RX descriptor
4587 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4589 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4590 u32 opaque_key, u32 dest_idx_unmasked)
4592 struct tg3_rx_buffer_desc *desc;
4593 struct ring_info *map;
4594 struct sk_buff *skb;
4596 int skb_size, dest_idx;
4598 switch (opaque_key) {
4599 case RXD_OPAQUE_RING_STD:
4600 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4601 desc = &tpr->rx_std[dest_idx];
4602 map = &tpr->rx_std_buffers[dest_idx];
4603 skb_size = tp->rx_pkt_map_sz;
4606 case RXD_OPAQUE_RING_JUMBO:
4607 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4608 desc = &tpr->rx_jmb[dest_idx].std;
4609 map = &tpr->rx_jmb_buffers[dest_idx];
4610 skb_size = TG3_RX_JMB_MAP_SZ;
4617 /* Do not overwrite any of the map or rp information
4618 * until we are sure we can commit to a new buffer.
4620 * Callers depend upon this behavior and assume that
4621 * we leave everything unchanged if we fail.
4623 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4627 skb_reserve(skb, tp->rx_offset);
4629 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4630 PCI_DMA_FROMDEVICE);
4631 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4637 dma_unmap_addr_set(map, mapping, mapping);
4639 desc->addr_hi = ((u64)mapping >> 32);
4640 desc->addr_lo = ((u64)mapping & 0xffffffff);
4645 /* We only need to move over in the address because the other
4646 * members of the RX descriptor are invariant. See notes above
4647 * tg3_alloc_rx_skb for full details.
4649 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4650 struct tg3_rx_prodring_set *dpr,
4651 u32 opaque_key, int src_idx,
4652 u32 dest_idx_unmasked)
4654 struct tg3 *tp = tnapi->tp;
4655 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4656 struct ring_info *src_map, *dest_map;
4657 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4660 switch (opaque_key) {
4661 case RXD_OPAQUE_RING_STD:
4662 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4663 dest_desc = &dpr->rx_std[dest_idx];
4664 dest_map = &dpr->rx_std_buffers[dest_idx];
4665 src_desc = &spr->rx_std[src_idx];
4666 src_map = &spr->rx_std_buffers[src_idx];
4669 case RXD_OPAQUE_RING_JUMBO:
4670 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4671 dest_desc = &dpr->rx_jmb[dest_idx].std;
4672 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4673 src_desc = &spr->rx_jmb[src_idx].std;
4674 src_map = &spr->rx_jmb_buffers[src_idx];
4681 dest_map->skb = src_map->skb;
4682 dma_unmap_addr_set(dest_map, mapping,
4683 dma_unmap_addr(src_map, mapping));
4684 dest_desc->addr_hi = src_desc->addr_hi;
4685 dest_desc->addr_lo = src_desc->addr_lo;
4687 /* Ensure that the update to the skb happens after the physical
4688 * addresses have been transferred to the new BD location.
4692 src_map->skb = NULL;
4695 /* The RX ring scheme is composed of multiple rings which post fresh
4696 * buffers to the chip, and one special ring the chip uses to report
4697 * status back to the host.
4699 * The special ring reports the status of received packets to the
4700 * host. The chip does not write into the original descriptor the
4701 * RX buffer was obtained from. The chip simply takes the original
4702 * descriptor as provided by the host, updates the status and length
4703 * field, then writes this into the next status ring entry.
4705 * Each ring the host uses to post buffers to the chip is described
4706 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4707 * it is first placed into the on-chip ram. When the packet's length
4708 * is known, it walks down the TG3_BDINFO entries to select the ring.
4709 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4710 * which is within the range of the new packet's length is chosen.
4712 * The "separate ring for rx status" scheme may sound queer, but it makes
4713 * sense from a cache coherency perspective. If only the host writes
4714 * to the buffer post rings, and only the chip writes to the rx status
4715 * rings, then cache lines never move beyond shared-modified state.
4716 * If both the host and chip were to write into the same ring, cache line
4717 * eviction could occur since both entities want it in an exclusive state.
4719 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4721 struct tg3 *tp = tnapi->tp;
4722 u32 work_mask, rx_std_posted = 0;
4723 u32 std_prod_idx, jmb_prod_idx;
4724 u32 sw_idx = tnapi->rx_rcb_ptr;
4727 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4729 hw_idx = *(tnapi->rx_rcb_prod_idx);
4731 * We need to order the read of hw_idx and the read of
4732 * the opaque cookie.
4737 std_prod_idx = tpr->rx_std_prod_idx;
4738 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4739 while (sw_idx != hw_idx && budget > 0) {
4740 struct ring_info *ri;
4741 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4743 struct sk_buff *skb;
4744 dma_addr_t dma_addr;
4745 u32 opaque_key, desc_idx, *post_ptr;
4747 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4748 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4749 if (opaque_key == RXD_OPAQUE_RING_STD) {
4750 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4751 dma_addr = dma_unmap_addr(ri, mapping);
4753 post_ptr = &std_prod_idx;
4755 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4756 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4757 dma_addr = dma_unmap_addr(ri, mapping);
4759 post_ptr = &jmb_prod_idx;
4761 goto next_pkt_nopost;
4763 work_mask |= opaque_key;
4765 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4766 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4768 tg3_recycle_rx(tnapi, tpr, opaque_key,
4769 desc_idx, *post_ptr);
4771 /* Other statistics kept track of by card. */
4776 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4779 if (len > TG3_RX_COPY_THRESH(tp)) {
4782 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4787 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4788 PCI_DMA_FROMDEVICE);
4790 /* Ensure that the update to the skb happens
4791 * after the usage of the old DMA mapping.
4799 struct sk_buff *copy_skb;
4801 tg3_recycle_rx(tnapi, tpr, opaque_key,
4802 desc_idx, *post_ptr);
4804 copy_skb = netdev_alloc_skb(tp->dev, len +
4806 if (copy_skb == NULL)
4807 goto drop_it_no_recycle;
4809 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4810 skb_put(copy_skb, len);
4811 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4812 skb_copy_from_linear_data(skb, copy_skb->data, len);
4813 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4815 /* We'll reuse the original ring buffer. */
4819 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4820 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4821 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4822 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4823 skb->ip_summed = CHECKSUM_UNNECESSARY;
4825 skb_checksum_none_assert(skb);
4827 skb->protocol = eth_type_trans(skb, tp->dev);
4829 if (len > (tp->dev->mtu + ETH_HLEN) &&
4830 skb->protocol != htons(ETH_P_8021Q)) {
4832 goto drop_it_no_recycle;
4835 if (desc->type_flags & RXD_FLAG_VLAN &&
4836 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4837 __vlan_hwaccel_put_tag(skb,
4838 desc->err_vlan & RXD_VLAN_MASK);
4840 napi_gro_receive(&tnapi->napi, skb);
4848 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4849 tpr->rx_std_prod_idx = std_prod_idx &
4850 tp->rx_std_ring_mask;
4851 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4852 tpr->rx_std_prod_idx);
4853 work_mask &= ~RXD_OPAQUE_RING_STD;
4858 sw_idx &= tp->rx_ret_ring_mask;
4860 /* Refresh hw_idx to see if there is new work */
4861 if (sw_idx == hw_idx) {
4862 hw_idx = *(tnapi->rx_rcb_prod_idx);
4867 /* ACK the status ring. */
4868 tnapi->rx_rcb_ptr = sw_idx;
4869 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4871 /* Refill RX ring(s). */
4872 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4873 if (work_mask & RXD_OPAQUE_RING_STD) {
4874 tpr->rx_std_prod_idx = std_prod_idx &
4875 tp->rx_std_ring_mask;
4876 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4877 tpr->rx_std_prod_idx);
4879 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4880 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4881 tp->rx_jmb_ring_mask;
4882 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4883 tpr->rx_jmb_prod_idx);
4886 } else if (work_mask) {
4887 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4888 * updated before the producer indices can be updated.
4892 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4893 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4895 if (tnapi != &tp->napi[1])
4896 napi_schedule(&tp->napi[1].napi);
4902 static void tg3_poll_link(struct tg3 *tp)
4904 /* handle link change and other phy events */
4905 if (!(tp->tg3_flags &
4906 (TG3_FLAG_USE_LINKCHG_REG |
4907 TG3_FLAG_POLL_SERDES))) {
4908 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4910 if (sblk->status & SD_STATUS_LINK_CHG) {
4911 sblk->status = SD_STATUS_UPDATED |
4912 (sblk->status & ~SD_STATUS_LINK_CHG);
4913 spin_lock(&tp->lock);
4914 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4916 (MAC_STATUS_SYNC_CHANGED |
4917 MAC_STATUS_CFG_CHANGED |
4918 MAC_STATUS_MI_COMPLETION |
4919 MAC_STATUS_LNKSTATE_CHANGED));
4922 tg3_setup_phy(tp, 0);
4923 spin_unlock(&tp->lock);
4928 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4929 struct tg3_rx_prodring_set *dpr,
4930 struct tg3_rx_prodring_set *spr)
4932 u32 si, di, cpycnt, src_prod_idx;
4936 src_prod_idx = spr->rx_std_prod_idx;
4938 /* Make sure updates to the rx_std_buffers[] entries and the
4939 * standard producer index are seen in the correct order.
4943 if (spr->rx_std_cons_idx == src_prod_idx)
4946 if (spr->rx_std_cons_idx < src_prod_idx)
4947 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4949 cpycnt = tp->rx_std_ring_mask + 1 -
4950 spr->rx_std_cons_idx;
4952 cpycnt = min(cpycnt,
4953 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4955 si = spr->rx_std_cons_idx;
4956 di = dpr->rx_std_prod_idx;
4958 for (i = di; i < di + cpycnt; i++) {
4959 if (dpr->rx_std_buffers[i].skb) {
4969 /* Ensure that updates to the rx_std_buffers ring and the
4970 * shadowed hardware producer ring from tg3_recycle_skb() are
4971 * ordered correctly WRT the skb check above.
4975 memcpy(&dpr->rx_std_buffers[di],
4976 &spr->rx_std_buffers[si],
4977 cpycnt * sizeof(struct ring_info));
4979 for (i = 0; i < cpycnt; i++, di++, si++) {
4980 struct tg3_rx_buffer_desc *sbd, *dbd;
4981 sbd = &spr->rx_std[si];
4982 dbd = &dpr->rx_std[di];
4983 dbd->addr_hi = sbd->addr_hi;
4984 dbd->addr_lo = sbd->addr_lo;
4987 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4988 tp->rx_std_ring_mask;
4989 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4990 tp->rx_std_ring_mask;
4994 src_prod_idx = spr->rx_jmb_prod_idx;
4996 /* Make sure updates to the rx_jmb_buffers[] entries and
4997 * the jumbo producer index are seen in the correct order.
5001 if (spr->rx_jmb_cons_idx == src_prod_idx)
5004 if (spr->rx_jmb_cons_idx < src_prod_idx)
5005 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5007 cpycnt = tp->rx_jmb_ring_mask + 1 -
5008 spr->rx_jmb_cons_idx;
5010 cpycnt = min(cpycnt,
5011 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5013 si = spr->rx_jmb_cons_idx;
5014 di = dpr->rx_jmb_prod_idx;
5016 for (i = di; i < di + cpycnt; i++) {
5017 if (dpr->rx_jmb_buffers[i].skb) {
5027 /* Ensure that updates to the rx_jmb_buffers ring and the
5028 * shadowed hardware producer ring from tg3_recycle_skb() are
5029 * ordered correctly WRT the skb check above.
5033 memcpy(&dpr->rx_jmb_buffers[di],
5034 &spr->rx_jmb_buffers[si],
5035 cpycnt * sizeof(struct ring_info));
5037 for (i = 0; i < cpycnt; i++, di++, si++) {
5038 struct tg3_rx_buffer_desc *sbd, *dbd;
5039 sbd = &spr->rx_jmb[si].std;
5040 dbd = &dpr->rx_jmb[di].std;
5041 dbd->addr_hi = sbd->addr_hi;
5042 dbd->addr_lo = sbd->addr_lo;
5045 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5046 tp->rx_jmb_ring_mask;
5047 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5048 tp->rx_jmb_ring_mask;
5054 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5056 struct tg3 *tp = tnapi->tp;
5058 /* run TX completion thread */
5059 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5061 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5065 /* run RX thread, within the bounds set by NAPI.
5066 * All RX "locking" is done by ensuring outside
5067 * code synchronizes with tg3->napi.poll()
5069 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5070 work_done += tg3_rx(tnapi, budget - work_done);
5072 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5073 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5075 u32 std_prod_idx = dpr->rx_std_prod_idx;
5076 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5078 for (i = 1; i < tp->irq_cnt; i++)
5079 err |= tg3_rx_prodring_xfer(tp, dpr,
5080 &tp->napi[i].prodring);
5084 if (std_prod_idx != dpr->rx_std_prod_idx)
5085 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5086 dpr->rx_std_prod_idx);
5088 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5089 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5090 dpr->rx_jmb_prod_idx);
5095 tw32_f(HOSTCC_MODE, tp->coal_now);
5101 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5103 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5104 struct tg3 *tp = tnapi->tp;
5106 struct tg3_hw_status *sblk = tnapi->hw_status;
5109 work_done = tg3_poll_work(tnapi, work_done, budget);
5111 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5114 if (unlikely(work_done >= budget))
5117 /* tp->last_tag is used in tg3_int_reenable() below
5118 * to tell the hw how much work has been processed,
5119 * so we must read it before checking for more work.
5121 tnapi->last_tag = sblk->status_tag;
5122 tnapi->last_irq_tag = tnapi->last_tag;
5125 /* check for RX/TX work to do */
5126 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5127 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5128 napi_complete(napi);
5129 /* Reenable interrupts. */
5130 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5139 /* work_done is guaranteed to be less than budget. */
5140 napi_complete(napi);
5141 schedule_work(&tp->reset_task);
5145 static int tg3_poll(struct napi_struct *napi, int budget)
5147 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5148 struct tg3 *tp = tnapi->tp;
5150 struct tg3_hw_status *sblk = tnapi->hw_status;
5155 work_done = tg3_poll_work(tnapi, work_done, budget);
5157 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5160 if (unlikely(work_done >= budget))
5163 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5164 /* tp->last_tag is used in tg3_int_reenable() below
5165 * to tell the hw how much work has been processed,
5166 * so we must read it before checking for more work.
5168 tnapi->last_tag = sblk->status_tag;
5169 tnapi->last_irq_tag = tnapi->last_tag;
5172 sblk->status &= ~SD_STATUS_UPDATED;
5174 if (likely(!tg3_has_work(tnapi))) {
5175 napi_complete(napi);
5176 tg3_int_reenable(tnapi);
5184 /* work_done is guaranteed to be less than budget. */
5185 napi_complete(napi);
5186 schedule_work(&tp->reset_task);
5190 static void tg3_napi_disable(struct tg3 *tp)
5194 for (i = tp->irq_cnt - 1; i >= 0; i--)
5195 napi_disable(&tp->napi[i].napi);
5198 static void tg3_napi_enable(struct tg3 *tp)
5202 for (i = 0; i < tp->irq_cnt; i++)
5203 napi_enable(&tp->napi[i].napi);
5206 static void tg3_napi_init(struct tg3 *tp)
5210 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5211 for (i = 1; i < tp->irq_cnt; i++)
5212 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5215 static void tg3_napi_fini(struct tg3 *tp)
5219 for (i = 0; i < tp->irq_cnt; i++)
5220 netif_napi_del(&tp->napi[i].napi);
5223 static inline void tg3_netif_stop(struct tg3 *tp)
5225 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5226 tg3_napi_disable(tp);
5227 netif_tx_disable(tp->dev);
5230 static inline void tg3_netif_start(struct tg3 *tp)
5232 /* NOTE: unconditional netif_tx_wake_all_queues is only
5233 * appropriate so long as all callers are assured to
5234 * have free tx slots (such as after tg3_init_hw)
5236 netif_tx_wake_all_queues(tp->dev);
5238 tg3_napi_enable(tp);
5239 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5240 tg3_enable_ints(tp);
5243 static void tg3_irq_quiesce(struct tg3 *tp)
5247 BUG_ON(tp->irq_sync);
5252 for (i = 0; i < tp->irq_cnt; i++)
5253 synchronize_irq(tp->napi[i].irq_vec);
5256 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5257 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5258 * with as well. Most of the time, this is not necessary except when
5259 * shutting down the device.
5261 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5263 spin_lock_bh(&tp->lock);
5265 tg3_irq_quiesce(tp);
5268 static inline void tg3_full_unlock(struct tg3 *tp)
5270 spin_unlock_bh(&tp->lock);
5273 /* One-shot MSI handler - Chip automatically disables interrupt
5274 * after sending MSI so driver doesn't have to do it.
5276 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5278 struct tg3_napi *tnapi = dev_id;
5279 struct tg3 *tp = tnapi->tp;
5281 prefetch(tnapi->hw_status);
5283 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5285 if (likely(!tg3_irq_sync(tp)))
5286 napi_schedule(&tnapi->napi);
5291 /* MSI ISR - No need to check for interrupt sharing and no need to
5292 * flush status block and interrupt mailbox. PCI ordering rules
5293 * guarantee that MSI will arrive after the status block.
5295 static irqreturn_t tg3_msi(int irq, void *dev_id)
5297 struct tg3_napi *tnapi = dev_id;
5298 struct tg3 *tp = tnapi->tp;
5300 prefetch(tnapi->hw_status);
5302 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5304 * Writing any value to intr-mbox-0 clears PCI INTA# and
5305 * chip-internal interrupt pending events.
5306 * Writing non-zero to intr-mbox-0 additional tells the
5307 * NIC to stop sending us irqs, engaging "in-intr-handler"
5310 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5311 if (likely(!tg3_irq_sync(tp)))
5312 napi_schedule(&tnapi->napi);
5314 return IRQ_RETVAL(1);
5317 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5319 struct tg3_napi *tnapi = dev_id;
5320 struct tg3 *tp = tnapi->tp;
5321 struct tg3_hw_status *sblk = tnapi->hw_status;
5322 unsigned int handled = 1;
5324 /* In INTx mode, it is possible for the interrupt to arrive at
5325 * the CPU before the status block posted prior to the interrupt.
5326 * Reading the PCI State register will confirm whether the
5327 * interrupt is ours and will flush the status block.
5329 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5330 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5331 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5338 * Writing any value to intr-mbox-0 clears PCI INTA# and
5339 * chip-internal interrupt pending events.
5340 * Writing non-zero to intr-mbox-0 additional tells the
5341 * NIC to stop sending us irqs, engaging "in-intr-handler"
5344 * Flush the mailbox to de-assert the IRQ immediately to prevent
5345 * spurious interrupts. The flush impacts performance but
5346 * excessive spurious interrupts can be worse in some cases.
5348 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5349 if (tg3_irq_sync(tp))
5351 sblk->status &= ~SD_STATUS_UPDATED;
5352 if (likely(tg3_has_work(tnapi))) {
5353 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5354 napi_schedule(&tnapi->napi);
5356 /* No work, shared interrupt perhaps? re-enable
5357 * interrupts, and flush that PCI write
5359 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5363 return IRQ_RETVAL(handled);
5366 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5368 struct tg3_napi *tnapi = dev_id;
5369 struct tg3 *tp = tnapi->tp;
5370 struct tg3_hw_status *sblk = tnapi->hw_status;
5371 unsigned int handled = 1;
5373 /* In INTx mode, it is possible for the interrupt to arrive at
5374 * the CPU before the status block posted prior to the interrupt.
5375 * Reading the PCI State register will confirm whether the
5376 * interrupt is ours and will flush the status block.
5378 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5379 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5380 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5387 * writing any value to intr-mbox-0 clears PCI INTA# and
5388 * chip-internal interrupt pending events.
5389 * writing non-zero to intr-mbox-0 additional tells the
5390 * NIC to stop sending us irqs, engaging "in-intr-handler"
5393 * Flush the mailbox to de-assert the IRQ immediately to prevent
5394 * spurious interrupts. The flush impacts performance but
5395 * excessive spurious interrupts can be worse in some cases.
5397 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5400 * In a shared interrupt configuration, sometimes other devices'
5401 * interrupts will scream. We record the current status tag here
5402 * so that the above check can report that the screaming interrupts
5403 * are unhandled. Eventually they will be silenced.
5405 tnapi->last_irq_tag = sblk->status_tag;
5407 if (tg3_irq_sync(tp))
5410 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5412 napi_schedule(&tnapi->napi);
5415 return IRQ_RETVAL(handled);
5418 /* ISR for interrupt test */
5419 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5421 struct tg3_napi *tnapi = dev_id;
5422 struct tg3 *tp = tnapi->tp;
5423 struct tg3_hw_status *sblk = tnapi->hw_status;
5425 if ((sblk->status & SD_STATUS_UPDATED) ||
5426 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5427 tg3_disable_ints(tp);
5428 return IRQ_RETVAL(1);
5430 return IRQ_RETVAL(0);
5433 static int tg3_init_hw(struct tg3 *, int);
5434 static int tg3_halt(struct tg3 *, int, int);
5436 /* Restart hardware after configuration changes, self-test, etc.
5437 * Invoked with tp->lock held.
5439 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5440 __releases(tp->lock)
5441 __acquires(tp->lock)
5445 err = tg3_init_hw(tp, reset_phy);
5448 "Failed to re-initialize device, aborting\n");
5449 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5450 tg3_full_unlock(tp);
5451 del_timer_sync(&tp->timer);
5453 tg3_napi_enable(tp);
5455 tg3_full_lock(tp, 0);
5460 #ifdef CONFIG_NET_POLL_CONTROLLER
5461 static void tg3_poll_controller(struct net_device *dev)
5464 struct tg3 *tp = netdev_priv(dev);
5466 for (i = 0; i < tp->irq_cnt; i++)
5467 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5471 static void tg3_reset_task(struct work_struct *work)
5473 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5475 unsigned int restart_timer;
5477 tg3_full_lock(tp, 0);
5479 if (!netif_running(tp->dev)) {
5480 tg3_full_unlock(tp);
5484 tg3_full_unlock(tp);
5490 tg3_full_lock(tp, 1);
5492 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5493 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5495 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5496 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5497 tp->write32_rx_mbox = tg3_write_flush_reg32;
5498 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5499 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5502 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5503 err = tg3_init_hw(tp, 1);
5507 tg3_netif_start(tp);
5510 mod_timer(&tp->timer, jiffies + 1);
5513 tg3_full_unlock(tp);
5519 static void tg3_dump_short_state(struct tg3 *tp)
5521 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5522 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5523 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5524 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5527 static void tg3_tx_timeout(struct net_device *dev)
5529 struct tg3 *tp = netdev_priv(dev);
5531 if (netif_msg_tx_err(tp)) {
5532 netdev_err(dev, "transmit timed out, resetting\n");
5533 tg3_dump_short_state(tp);
5536 schedule_work(&tp->reset_task);
5539 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5540 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5542 u32 base = (u32) mapping & 0xffffffff;
5544 return (base > 0xffffdcc0) && (base + len + 8 < base);
5547 /* Test for DMA addresses > 40-bit */
5548 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5551 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5552 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5553 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5560 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5562 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5563 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5564 struct sk_buff *skb, u32 last_plus_one,
5565 u32 *start, u32 base_flags, u32 mss)
5567 struct tg3 *tp = tnapi->tp;
5568 struct sk_buff *new_skb;
5569 dma_addr_t new_addr = 0;
5573 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5574 new_skb = skb_copy(skb, GFP_ATOMIC);
5576 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5578 new_skb = skb_copy_expand(skb,
5579 skb_headroom(skb) + more_headroom,
5580 skb_tailroom(skb), GFP_ATOMIC);
5586 /* New SKB is guaranteed to be linear. */
5588 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5590 /* Make sure the mapping succeeded */
5591 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5593 dev_kfree_skb(new_skb);
5596 /* Make sure new skb does not cross any 4G boundaries.
5597 * Drop the packet if it does.
5599 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5600 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5601 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5604 dev_kfree_skb(new_skb);
5607 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5608 base_flags, 1 | (mss << 1));
5609 *start = NEXT_TX(entry);
5613 /* Now clean up the sw ring entries. */
5615 while (entry != last_plus_one) {
5619 len = skb_headlen(skb);
5621 len = skb_shinfo(skb)->frags[i-1].size;
5623 pci_unmap_single(tp->pdev,
5624 dma_unmap_addr(&tnapi->tx_buffers[entry],
5626 len, PCI_DMA_TODEVICE);
5628 tnapi->tx_buffers[entry].skb = new_skb;
5629 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5632 tnapi->tx_buffers[entry].skb = NULL;
5634 entry = NEXT_TX(entry);
5643 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5644 dma_addr_t mapping, int len, u32 flags,
5647 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5648 int is_end = (mss_and_is_end & 0x1);
5649 u32 mss = (mss_and_is_end >> 1);
5653 flags |= TXD_FLAG_END;
5654 if (flags & TXD_FLAG_VLAN) {
5655 vlan_tag = flags >> 16;
5658 vlan_tag |= (mss << TXD_MSS_SHIFT);
5660 txd->addr_hi = ((u64) mapping >> 32);
5661 txd->addr_lo = ((u64) mapping & 0xffffffff);
5662 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5663 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5666 /* hard_start_xmit for devices that don't have any bugs and
5667 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5669 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5670 struct net_device *dev)
5672 struct tg3 *tp = netdev_priv(dev);
5673 u32 len, entry, base_flags, mss;
5675 struct tg3_napi *tnapi;
5676 struct netdev_queue *txq;
5677 unsigned int i, last;
5679 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5680 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5681 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5684 /* We are running in BH disabled context with netif_tx_lock
5685 * and TX reclaim runs via tp->napi.poll inside of a software
5686 * interrupt. Furthermore, IRQ processing runs lockless so we have
5687 * no IRQ context deadlocks to worry about either. Rejoice!
5689 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5690 if (!netif_tx_queue_stopped(txq)) {
5691 netif_tx_stop_queue(txq);
5693 /* This is a hard error, log it. */
5695 "BUG! Tx Ring full when queue awake!\n");
5697 return NETDEV_TX_BUSY;
5700 entry = tnapi->tx_prod;
5702 mss = skb_shinfo(skb)->gso_size;
5704 int tcp_opt_len, ip_tcp_len;
5707 if (skb_header_cloned(skb) &&
5708 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5713 if (skb_is_gso_v6(skb)) {
5714 hdrlen = skb_headlen(skb) - ETH_HLEN;
5716 struct iphdr *iph = ip_hdr(skb);
5718 tcp_opt_len = tcp_optlen(skb);
5719 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5722 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5723 hdrlen = ip_tcp_len + tcp_opt_len;
5726 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5727 mss |= (hdrlen & 0xc) << 12;
5729 base_flags |= 0x00000010;
5730 base_flags |= (hdrlen & 0x3e0) << 5;
5734 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5735 TXD_FLAG_CPU_POST_DMA);
5737 tcp_hdr(skb)->check = 0;
5739 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5740 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5743 if (vlan_tx_tag_present(skb))
5744 base_flags |= (TXD_FLAG_VLAN |
5745 (vlan_tx_tag_get(skb) << 16));
5747 len = skb_headlen(skb);
5749 /* Queue skb data, a.k.a. the main skb fragment. */
5750 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5751 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5756 tnapi->tx_buffers[entry].skb = skb;
5757 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5759 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5760 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5761 base_flags |= TXD_FLAG_JMB_PKT;
5763 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5764 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5766 entry = NEXT_TX(entry);
5768 /* Now loop through additional data fragments, and queue them. */
5769 if (skb_shinfo(skb)->nr_frags > 0) {
5770 last = skb_shinfo(skb)->nr_frags - 1;
5771 for (i = 0; i <= last; i++) {
5772 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5775 mapping = pci_map_page(tp->pdev,
5778 len, PCI_DMA_TODEVICE);
5779 if (pci_dma_mapping_error(tp->pdev, mapping))
5782 tnapi->tx_buffers[entry].skb = NULL;
5783 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5786 tg3_set_txd(tnapi, entry, mapping, len,
5787 base_flags, (i == last) | (mss << 1));
5789 entry = NEXT_TX(entry);
5793 /* Packets are ready, update Tx producer idx local and on card. */
5794 tw32_tx_mbox(tnapi->prodmbox, entry);
5796 tnapi->tx_prod = entry;
5797 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5798 netif_tx_stop_queue(txq);
5800 /* netif_tx_stop_queue() must be done before checking
5801 * checking tx index in tg3_tx_avail() below, because in
5802 * tg3_tx(), we update tx index before checking for
5803 * netif_tx_queue_stopped().
5806 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5807 netif_tx_wake_queue(txq);
5813 return NETDEV_TX_OK;
5817 entry = tnapi->tx_prod;
5818 tnapi->tx_buffers[entry].skb = NULL;
5819 pci_unmap_single(tp->pdev,
5820 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5823 for (i = 0; i <= last; i++) {
5824 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5825 entry = NEXT_TX(entry);
5827 pci_unmap_page(tp->pdev,
5828 dma_unmap_addr(&tnapi->tx_buffers[entry],
5830 frag->size, PCI_DMA_TODEVICE);
5834 return NETDEV_TX_OK;
5837 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5838 struct net_device *);
5840 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5841 * TSO header is greater than 80 bytes.
5843 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5845 struct sk_buff *segs, *nskb;
5846 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5848 /* Estimate the number of fragments in the worst case */
5849 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5850 netif_stop_queue(tp->dev);
5852 /* netif_tx_stop_queue() must be done before checking
5853 * checking tx index in tg3_tx_avail() below, because in
5854 * tg3_tx(), we update tx index before checking for
5855 * netif_tx_queue_stopped().
5858 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5859 return NETDEV_TX_BUSY;
5861 netif_wake_queue(tp->dev);
5864 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5866 goto tg3_tso_bug_end;
5872 tg3_start_xmit_dma_bug(nskb, tp->dev);
5878 return NETDEV_TX_OK;
5881 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5882 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5884 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5885 struct net_device *dev)
5887 struct tg3 *tp = netdev_priv(dev);
5888 u32 len, entry, base_flags, mss;
5889 int would_hit_hwbug;
5891 struct tg3_napi *tnapi;
5892 struct netdev_queue *txq;
5893 unsigned int i, last;
5895 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5896 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5897 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5900 /* We are running in BH disabled context with netif_tx_lock
5901 * and TX reclaim runs via tp->napi.poll inside of a software
5902 * interrupt. Furthermore, IRQ processing runs lockless so we have
5903 * no IRQ context deadlocks to worry about either. Rejoice!
5905 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5906 if (!netif_tx_queue_stopped(txq)) {
5907 netif_tx_stop_queue(txq);
5909 /* This is a hard error, log it. */
5911 "BUG! Tx Ring full when queue awake!\n");
5913 return NETDEV_TX_BUSY;
5916 entry = tnapi->tx_prod;
5918 if (skb->ip_summed == CHECKSUM_PARTIAL)
5919 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5921 mss = skb_shinfo(skb)->gso_size;
5924 u32 tcp_opt_len, hdr_len;
5926 if (skb_header_cloned(skb) &&
5927 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5933 tcp_opt_len = tcp_optlen(skb);
5935 if (skb_is_gso_v6(skb)) {
5936 hdr_len = skb_headlen(skb) - ETH_HLEN;
5940 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5941 hdr_len = ip_tcp_len + tcp_opt_len;
5944 iph->tot_len = htons(mss + hdr_len);
5947 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5948 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5949 return tg3_tso_bug(tp, skb);
5951 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5952 TXD_FLAG_CPU_POST_DMA);
5954 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5955 tcp_hdr(skb)->check = 0;
5956 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5958 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5963 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5964 mss |= (hdr_len & 0xc) << 12;
5966 base_flags |= 0x00000010;
5967 base_flags |= (hdr_len & 0x3e0) << 5;
5968 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5969 mss |= hdr_len << 9;
5970 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5972 if (tcp_opt_len || iph->ihl > 5) {
5975 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5976 mss |= (tsflags << 11);
5979 if (tcp_opt_len || iph->ihl > 5) {
5982 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5983 base_flags |= tsflags << 12;
5988 if (vlan_tx_tag_present(skb))
5989 base_flags |= (TXD_FLAG_VLAN |
5990 (vlan_tx_tag_get(skb) << 16));
5992 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5993 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5994 base_flags |= TXD_FLAG_JMB_PKT;
5996 len = skb_headlen(skb);
5998 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5999 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6004 tnapi->tx_buffers[entry].skb = skb;
6005 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6007 would_hit_hwbug = 0;
6009 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6010 would_hit_hwbug = 1;
6012 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6013 tg3_4g_overflow_test(mapping, len))
6014 would_hit_hwbug = 1;
6016 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6017 tg3_40bit_overflow_test(tp, mapping, len))
6018 would_hit_hwbug = 1;
6020 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6021 would_hit_hwbug = 1;
6023 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6024 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6026 entry = NEXT_TX(entry);
6028 /* Now loop through additional data fragments, and queue them. */
6029 if (skb_shinfo(skb)->nr_frags > 0) {
6030 last = skb_shinfo(skb)->nr_frags - 1;
6031 for (i = 0; i <= last; i++) {
6032 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6035 mapping = pci_map_page(tp->pdev,
6038 len, PCI_DMA_TODEVICE);
6040 tnapi->tx_buffers[entry].skb = NULL;
6041 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6043 if (pci_dma_mapping_error(tp->pdev, mapping))
6046 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6048 would_hit_hwbug = 1;
6050 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6051 tg3_4g_overflow_test(mapping, len))
6052 would_hit_hwbug = 1;
6054 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6055 tg3_40bit_overflow_test(tp, mapping, len))
6056 would_hit_hwbug = 1;
6058 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6059 tg3_set_txd(tnapi, entry, mapping, len,
6060 base_flags, (i == last)|(mss << 1));
6062 tg3_set_txd(tnapi, entry, mapping, len,
6063 base_flags, (i == last));
6065 entry = NEXT_TX(entry);
6069 if (would_hit_hwbug) {
6070 u32 last_plus_one = entry;
6073 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6074 start &= (TG3_TX_RING_SIZE - 1);
6076 /* If the workaround fails due to memory/mapping
6077 * failure, silently drop this packet.
6079 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6080 &start, base_flags, mss))
6086 /* Packets are ready, update Tx producer idx local and on card. */
6087 tw32_tx_mbox(tnapi->prodmbox, entry);
6089 tnapi->tx_prod = entry;
6090 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6091 netif_tx_stop_queue(txq);
6093 /* netif_tx_stop_queue() must be done before checking
6094 * checking tx index in tg3_tx_avail() below, because in
6095 * tg3_tx(), we update tx index before checking for
6096 * netif_tx_queue_stopped().
6099 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6100 netif_tx_wake_queue(txq);
6106 return NETDEV_TX_OK;
6110 entry = tnapi->tx_prod;
6111 tnapi->tx_buffers[entry].skb = NULL;
6112 pci_unmap_single(tp->pdev,
6113 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6116 for (i = 0; i <= last; i++) {
6117 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6118 entry = NEXT_TX(entry);
6120 pci_unmap_page(tp->pdev,
6121 dma_unmap_addr(&tnapi->tx_buffers[entry],
6123 frag->size, PCI_DMA_TODEVICE);
6127 return NETDEV_TX_OK;
6130 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6132 struct tg3 *tp = netdev_priv(dev);
6134 if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6135 features &= ~NETIF_F_ALL_TSO;
6140 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6145 if (new_mtu > ETH_DATA_LEN) {
6146 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6147 netdev_update_features(dev);
6148 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6150 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6153 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6154 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6155 netdev_update_features(dev);
6157 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6161 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6163 struct tg3 *tp = netdev_priv(dev);
6166 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6169 if (!netif_running(dev)) {
6170 /* We'll just catch it later when the
6173 tg3_set_mtu(dev, tp, new_mtu);
6181 tg3_full_lock(tp, 1);
6183 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6185 tg3_set_mtu(dev, tp, new_mtu);
6187 err = tg3_restart_hw(tp, 0);
6190 tg3_netif_start(tp);
6192 tg3_full_unlock(tp);
6200 static void tg3_rx_prodring_free(struct tg3 *tp,
6201 struct tg3_rx_prodring_set *tpr)
6205 if (tpr != &tp->napi[0].prodring) {
6206 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6207 i = (i + 1) & tp->rx_std_ring_mask)
6208 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6211 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6212 for (i = tpr->rx_jmb_cons_idx;
6213 i != tpr->rx_jmb_prod_idx;
6214 i = (i + 1) & tp->rx_jmb_ring_mask) {
6215 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6223 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6224 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6227 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6228 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6229 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6230 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6235 /* Initialize rx rings for packet processing.
6237 * The chip has been shut down and the driver detached from
6238 * the networking, so no interrupts or new tx packets will
6239 * end up in the driver. tp->{tx,}lock are held and thus
6242 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6243 struct tg3_rx_prodring_set *tpr)
6245 u32 i, rx_pkt_dma_sz;
6247 tpr->rx_std_cons_idx = 0;
6248 tpr->rx_std_prod_idx = 0;
6249 tpr->rx_jmb_cons_idx = 0;
6250 tpr->rx_jmb_prod_idx = 0;
6252 if (tpr != &tp->napi[0].prodring) {
6253 memset(&tpr->rx_std_buffers[0], 0,
6254 TG3_RX_STD_BUFF_RING_SIZE(tp));
6255 if (tpr->rx_jmb_buffers)
6256 memset(&tpr->rx_jmb_buffers[0], 0,
6257 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6261 /* Zero out all descriptors. */
6262 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6264 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6265 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6266 tp->dev->mtu > ETH_DATA_LEN)
6267 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6268 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6270 /* Initialize invariants of the rings, we only set this
6271 * stuff once. This works because the card does not
6272 * write into the rx buffer posting rings.
6274 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6275 struct tg3_rx_buffer_desc *rxd;
6277 rxd = &tpr->rx_std[i];
6278 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6279 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6280 rxd->opaque = (RXD_OPAQUE_RING_STD |
6281 (i << RXD_OPAQUE_INDEX_SHIFT));
6284 /* Now allocate fresh SKBs for each rx ring. */
6285 for (i = 0; i < tp->rx_pending; i++) {
6286 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6287 netdev_warn(tp->dev,
6288 "Using a smaller RX standard ring. Only "
6289 "%d out of %d buffers were allocated "
6290 "successfully\n", i, tp->rx_pending);
6298 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6299 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6302 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6304 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6307 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6308 struct tg3_rx_buffer_desc *rxd;
6310 rxd = &tpr->rx_jmb[i].std;
6311 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6312 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6314 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6315 (i << RXD_OPAQUE_INDEX_SHIFT));
6318 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6319 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6320 netdev_warn(tp->dev,
6321 "Using a smaller RX jumbo ring. Only %d "
6322 "out of %d buffers were allocated "
6323 "successfully\n", i, tp->rx_jumbo_pending);
6326 tp->rx_jumbo_pending = i;
6335 tg3_rx_prodring_free(tp, tpr);
6339 static void tg3_rx_prodring_fini(struct tg3 *tp,
6340 struct tg3_rx_prodring_set *tpr)
6342 kfree(tpr->rx_std_buffers);
6343 tpr->rx_std_buffers = NULL;
6344 kfree(tpr->rx_jmb_buffers);
6345 tpr->rx_jmb_buffers = NULL;
6347 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6348 tpr->rx_std, tpr->rx_std_mapping);
6352 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6353 tpr->rx_jmb, tpr->rx_jmb_mapping);
6358 static int tg3_rx_prodring_init(struct tg3 *tp,
6359 struct tg3_rx_prodring_set *tpr)
6361 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6363 if (!tpr->rx_std_buffers)
6366 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6367 TG3_RX_STD_RING_BYTES(tp),
6368 &tpr->rx_std_mapping,
6373 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6374 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6375 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6377 if (!tpr->rx_jmb_buffers)
6380 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6381 TG3_RX_JMB_RING_BYTES(tp),
6382 &tpr->rx_jmb_mapping,
6391 tg3_rx_prodring_fini(tp, tpr);
6395 /* Free up pending packets in all rx/tx rings.
6397 * The chip has been shut down and the driver detached from
6398 * the networking, so no interrupts or new tx packets will
6399 * end up in the driver. tp->{tx,}lock is not held and we are not
6400 * in an interrupt context and thus may sleep.
6402 static void tg3_free_rings(struct tg3 *tp)
6406 for (j = 0; j < tp->irq_cnt; j++) {
6407 struct tg3_napi *tnapi = &tp->napi[j];
6409 tg3_rx_prodring_free(tp, &tnapi->prodring);
6411 if (!tnapi->tx_buffers)
6414 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6415 struct ring_info *txp;
6416 struct sk_buff *skb;
6419 txp = &tnapi->tx_buffers[i];
6427 pci_unmap_single(tp->pdev,
6428 dma_unmap_addr(txp, mapping),
6435 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6436 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6437 pci_unmap_page(tp->pdev,
6438 dma_unmap_addr(txp, mapping),
6439 skb_shinfo(skb)->frags[k].size,
6444 dev_kfree_skb_any(skb);
6449 /* Initialize tx/rx rings for packet processing.
6451 * The chip has been shut down and the driver detached from
6452 * the networking, so no interrupts or new tx packets will
6453 * end up in the driver. tp->{tx,}lock are held and thus
6456 static int tg3_init_rings(struct tg3 *tp)
6460 /* Free up all the SKBs. */
6463 for (i = 0; i < tp->irq_cnt; i++) {
6464 struct tg3_napi *tnapi = &tp->napi[i];
6466 tnapi->last_tag = 0;
6467 tnapi->last_irq_tag = 0;
6468 tnapi->hw_status->status = 0;
6469 tnapi->hw_status->status_tag = 0;
6470 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6475 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6477 tnapi->rx_rcb_ptr = 0;
6479 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6481 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6491 * Must not be invoked with interrupt sources disabled and
6492 * the hardware shutdown down.
6494 static void tg3_free_consistent(struct tg3 *tp)
6498 for (i = 0; i < tp->irq_cnt; i++) {
6499 struct tg3_napi *tnapi = &tp->napi[i];
6501 if (tnapi->tx_ring) {
6502 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6503 tnapi->tx_ring, tnapi->tx_desc_mapping);
6504 tnapi->tx_ring = NULL;
6507 kfree(tnapi->tx_buffers);
6508 tnapi->tx_buffers = NULL;
6510 if (tnapi->rx_rcb) {
6511 dma_free_coherent(&tp->pdev->dev,
6512 TG3_RX_RCB_RING_BYTES(tp),
6514 tnapi->rx_rcb_mapping);
6515 tnapi->rx_rcb = NULL;
6518 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6520 if (tnapi->hw_status) {
6521 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6523 tnapi->status_mapping);
6524 tnapi->hw_status = NULL;
6529 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6530 tp->hw_stats, tp->stats_mapping);
6531 tp->hw_stats = NULL;
6536 * Must not be invoked with interrupt sources disabled and
6537 * the hardware shutdown down. Can sleep.
6539 static int tg3_alloc_consistent(struct tg3 *tp)
6543 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6544 sizeof(struct tg3_hw_stats),
6550 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6552 for (i = 0; i < tp->irq_cnt; i++) {
6553 struct tg3_napi *tnapi = &tp->napi[i];
6554 struct tg3_hw_status *sblk;
6556 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6558 &tnapi->status_mapping,
6560 if (!tnapi->hw_status)
6563 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6564 sblk = tnapi->hw_status;
6566 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6569 /* If multivector TSS is enabled, vector 0 does not handle
6570 * tx interrupts. Don't allocate any resources for it.
6572 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6573 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6574 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6577 if (!tnapi->tx_buffers)
6580 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6582 &tnapi->tx_desc_mapping,
6584 if (!tnapi->tx_ring)
6589 * When RSS is enabled, the status block format changes
6590 * slightly. The "rx_jumbo_consumer", "reserved",
6591 * and "rx_mini_consumer" members get mapped to the
6592 * other three rx return ring producer indexes.
6596 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6599 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6602 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6605 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6610 * If multivector RSS is enabled, vector 0 does not handle
6611 * rx or tx interrupts. Don't allocate any resources for it.
6613 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6616 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6617 TG3_RX_RCB_RING_BYTES(tp),
6618 &tnapi->rx_rcb_mapping,
6623 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6629 tg3_free_consistent(tp);
6633 #define MAX_WAIT_CNT 1000
6635 /* To stop a block, clear the enable bit and poll till it
6636 * clears. tp->lock is held.
6638 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6643 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6650 /* We can't enable/disable these bits of the
6651 * 5705/5750, just say success.
6664 for (i = 0; i < MAX_WAIT_CNT; i++) {
6667 if ((val & enable_bit) == 0)
6671 if (i == MAX_WAIT_CNT && !silent) {
6672 dev_err(&tp->pdev->dev,
6673 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6681 /* tp->lock is held. */
6682 static int tg3_abort_hw(struct tg3 *tp, int silent)
6686 tg3_disable_ints(tp);
6688 tp->rx_mode &= ~RX_MODE_ENABLE;
6689 tw32_f(MAC_RX_MODE, tp->rx_mode);
6692 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6693 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6694 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6695 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6696 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6697 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6699 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6700 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6701 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6702 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6703 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6704 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6705 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6707 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6708 tw32_f(MAC_MODE, tp->mac_mode);
6711 tp->tx_mode &= ~TX_MODE_ENABLE;
6712 tw32_f(MAC_TX_MODE, tp->tx_mode);
6714 for (i = 0; i < MAX_WAIT_CNT; i++) {
6716 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6719 if (i >= MAX_WAIT_CNT) {
6720 dev_err(&tp->pdev->dev,
6721 "%s timed out, TX_MODE_ENABLE will not clear "
6722 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6726 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6727 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6728 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6730 tw32(FTQ_RESET, 0xffffffff);
6731 tw32(FTQ_RESET, 0x00000000);
6733 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6734 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6736 for (i = 0; i < tp->irq_cnt; i++) {
6737 struct tg3_napi *tnapi = &tp->napi[i];
6738 if (tnapi->hw_status)
6739 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6742 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6747 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6752 /* NCSI does not support APE events */
6753 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6756 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6757 if (apedata != APE_SEG_SIG_MAGIC)
6760 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6761 if (!(apedata & APE_FW_STATUS_READY))
6764 /* Wait for up to 1 millisecond for APE to service previous event. */
6765 for (i = 0; i < 10; i++) {
6766 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6769 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6771 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6772 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6773 event | APE_EVENT_STATUS_EVENT_PENDING);
6775 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6777 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6783 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6784 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6787 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6792 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6796 case RESET_KIND_INIT:
6797 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6798 APE_HOST_SEG_SIG_MAGIC);
6799 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6800 APE_HOST_SEG_LEN_MAGIC);
6801 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6802 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6803 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6804 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6805 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6806 APE_HOST_BEHAV_NO_PHYLOCK);
6807 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6808 TG3_APE_HOST_DRVR_STATE_START);
6810 event = APE_EVENT_STATUS_STATE_START;
6812 case RESET_KIND_SHUTDOWN:
6813 /* With the interface we are currently using,
6814 * APE does not track driver state. Wiping
6815 * out the HOST SEGMENT SIGNATURE forces
6816 * the APE to assume OS absent status.
6818 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6820 if (device_may_wakeup(&tp->pdev->dev) &&
6821 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6822 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6823 TG3_APE_HOST_WOL_SPEED_AUTO);
6824 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6826 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6828 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6830 event = APE_EVENT_STATUS_STATE_UNLOAD;
6832 case RESET_KIND_SUSPEND:
6833 event = APE_EVENT_STATUS_STATE_SUSPEND;
6839 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6841 tg3_ape_send_event(tp, event);
6844 /* tp->lock is held. */
6845 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6847 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6848 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6850 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6852 case RESET_KIND_INIT:
6853 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6857 case RESET_KIND_SHUTDOWN:
6858 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6862 case RESET_KIND_SUSPEND:
6863 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6872 if (kind == RESET_KIND_INIT ||
6873 kind == RESET_KIND_SUSPEND)
6874 tg3_ape_driver_state_change(tp, kind);
6877 /* tp->lock is held. */
6878 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6880 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6882 case RESET_KIND_INIT:
6883 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6884 DRV_STATE_START_DONE);
6887 case RESET_KIND_SHUTDOWN:
6888 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6889 DRV_STATE_UNLOAD_DONE);
6897 if (kind == RESET_KIND_SHUTDOWN)
6898 tg3_ape_driver_state_change(tp, kind);
6901 /* tp->lock is held. */
6902 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6904 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6906 case RESET_KIND_INIT:
6907 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6911 case RESET_KIND_SHUTDOWN:
6912 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6916 case RESET_KIND_SUSPEND:
6917 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6927 static int tg3_poll_fw(struct tg3 *tp)
6932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6933 /* Wait up to 20ms for init done. */
6934 for (i = 0; i < 200; i++) {
6935 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6942 /* Wait for firmware initialization to complete. */
6943 for (i = 0; i < 100000; i++) {
6944 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6945 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6950 /* Chip might not be fitted with firmware. Some Sun onboard
6951 * parts are configured like that. So don't signal the timeout
6952 * of the above loop as an error, but do report the lack of
6953 * running firmware once.
6956 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6957 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6959 netdev_info(tp->dev, "No firmware running\n");
6962 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6963 /* The 57765 A0 needs a little more
6964 * time to do some important work.
6972 /* Save PCI command register before chip reset */
6973 static void tg3_save_pci_state(struct tg3 *tp)
6975 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6978 /* Restore PCI state after chip reset */
6979 static void tg3_restore_pci_state(struct tg3 *tp)
6983 /* Re-enable indirect register accesses. */
6984 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6985 tp->misc_host_ctrl);
6987 /* Set MAX PCI retry to zero. */
6988 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6989 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6990 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6991 val |= PCISTATE_RETRY_SAME_DMA;
6992 /* Allow reads and writes to the APE register and memory space. */
6993 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6994 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6995 PCISTATE_ALLOW_APE_SHMEM_WR |
6996 PCISTATE_ALLOW_APE_PSPACE_WR;
6997 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6999 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7001 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7002 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7003 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7005 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7006 tp->pci_cacheline_sz);
7007 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7012 /* Make sure PCI-X relaxed ordering bit is clear. */
7013 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7016 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7018 pcix_cmd &= ~PCI_X_CMD_ERO;
7019 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7023 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7025 /* Chip reset on 5780 will reset MSI enable bit,
7026 * so need to restore it.
7028 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7031 pci_read_config_word(tp->pdev,
7032 tp->msi_cap + PCI_MSI_FLAGS,
7034 pci_write_config_word(tp->pdev,
7035 tp->msi_cap + PCI_MSI_FLAGS,
7036 ctrl | PCI_MSI_FLAGS_ENABLE);
7037 val = tr32(MSGINT_MODE);
7038 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7043 static void tg3_stop_fw(struct tg3 *);
7045 /* tp->lock is held. */
7046 static int tg3_chip_reset(struct tg3 *tp)
7049 void (*write_op)(struct tg3 *, u32, u32);
7054 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7056 /* No matching tg3_nvram_unlock() after this because
7057 * chip reset below will undo the nvram lock.
7059 tp->nvram_lock_cnt = 0;
7061 /* GRC_MISC_CFG core clock reset will clear the memory
7062 * enable bit in PCI register 4 and the MSI enable bit
7063 * on some chips, so we save relevant registers here.
7065 tg3_save_pci_state(tp);
7067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7068 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7069 tw32(GRC_FASTBOOT_PC, 0);
7072 * We must avoid the readl() that normally takes place.
7073 * It locks machines, causes machine checks, and other
7074 * fun things. So, temporarily disable the 5701
7075 * hardware workaround, while we do the reset.
7077 write_op = tp->write32;
7078 if (write_op == tg3_write_flush_reg32)
7079 tp->write32 = tg3_write32;
7081 /* Prevent the irq handler from reading or writing PCI registers
7082 * during chip reset when the memory enable bit in the PCI command
7083 * register may be cleared. The chip does not generate interrupt
7084 * at this time, but the irq handler may still be called due to irq
7085 * sharing or irqpoll.
7087 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7088 for (i = 0; i < tp->irq_cnt; i++) {
7089 struct tg3_napi *tnapi = &tp->napi[i];
7090 if (tnapi->hw_status) {
7091 tnapi->hw_status->status = 0;
7092 tnapi->hw_status->status_tag = 0;
7094 tnapi->last_tag = 0;
7095 tnapi->last_irq_tag = 0;
7099 for (i = 0; i < tp->irq_cnt; i++)
7100 synchronize_irq(tp->napi[i].irq_vec);
7102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7103 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7104 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7108 val = GRC_MISC_CFG_CORECLK_RESET;
7110 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7111 /* Force PCIe 1.0a mode */
7112 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7113 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
7114 tr32(TG3_PCIE_PHY_TSTCTL) ==
7115 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7116 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7118 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7119 tw32(GRC_MISC_CFG, (1 << 29));
7124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7125 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7126 tw32(GRC_VCPU_EXT_CTRL,
7127 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7130 /* Manage gphy power for all CPMU absent PCIe devices. */
7131 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7132 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7133 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7135 tw32(GRC_MISC_CFG, val);
7137 /* restore 5701 hardware bug workaround write method */
7138 tp->write32 = write_op;
7140 /* Unfortunately, we have to delay before the PCI read back.
7141 * Some 575X chips even will not respond to a PCI cfg access
7142 * when the reset command is given to the chip.
7144 * How do these hardware designers expect things to work
7145 * properly if the PCI write is posted for a long period
7146 * of time? It is always necessary to have some method by
7147 * which a register read back can occur to push the write
7148 * out which does the reset.
7150 * For most tg3 variants the trick below was working.
7155 /* Flush PCI posted writes. The normal MMIO registers
7156 * are inaccessible at this time so this is the only
7157 * way to make this reliably (actually, this is no longer
7158 * the case, see above). I tried to use indirect
7159 * register read/write but this upset some 5701 variants.
7161 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7165 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7168 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7172 /* Wait for link training to complete. */
7173 for (i = 0; i < 5000; i++)
7176 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7177 pci_write_config_dword(tp->pdev, 0xc4,
7178 cfg_val | (1 << 15));
7181 /* Clear the "no snoop" and "relaxed ordering" bits. */
7182 pci_read_config_word(tp->pdev,
7183 tp->pcie_cap + PCI_EXP_DEVCTL,
7185 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7186 PCI_EXP_DEVCTL_NOSNOOP_EN);
7188 * Older PCIe devices only support the 128 byte
7189 * MPS setting. Enforce the restriction.
7191 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7192 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7193 pci_write_config_word(tp->pdev,
7194 tp->pcie_cap + PCI_EXP_DEVCTL,
7197 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7199 /* Clear error status */
7200 pci_write_config_word(tp->pdev,
7201 tp->pcie_cap + PCI_EXP_DEVSTA,
7202 PCI_EXP_DEVSTA_CED |
7203 PCI_EXP_DEVSTA_NFED |
7204 PCI_EXP_DEVSTA_FED |
7205 PCI_EXP_DEVSTA_URD);
7208 tg3_restore_pci_state(tp);
7210 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7213 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7214 val = tr32(MEMARB_MODE);
7215 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7217 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7219 tw32(0x5000, 0x400);
7222 tw32(GRC_MODE, tp->grc_mode);
7224 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7227 tw32(0xc4, val | (1 << 15));
7230 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7232 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7233 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7234 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7235 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7238 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7239 tp->mac_mode = MAC_MODE_APE_TX_EN |
7240 MAC_MODE_APE_RX_EN |
7241 MAC_MODE_TDE_ENABLE;
7243 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7244 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7246 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7247 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7252 tw32_f(MAC_MODE, val);
7255 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7257 err = tg3_poll_fw(tp);
7263 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7264 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7265 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7266 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
7269 tw32(0x7c00, val | (1 << 25));
7272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7273 val = tr32(TG3_CPMU_CLCK_ORIDE);
7274 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7277 /* Reprobe ASF enable state. */
7278 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7279 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7280 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7281 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7284 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7285 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7286 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7287 tp->last_event_jiffies = jiffies;
7288 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7289 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7296 /* tp->lock is held. */
7297 static void tg3_stop_fw(struct tg3 *tp)
7299 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7300 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7301 /* Wait for RX cpu to ACK the previous event. */
7302 tg3_wait_for_event_ack(tp);
7304 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7306 tg3_generate_fw_event(tp);
7308 /* Wait for RX cpu to ACK this event. */
7309 tg3_wait_for_event_ack(tp);
7313 /* tp->lock is held. */
7314 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7320 tg3_write_sig_pre_reset(tp, kind);
7322 tg3_abort_hw(tp, silent);
7323 err = tg3_chip_reset(tp);
7325 __tg3_set_mac_addr(tp, 0);
7327 tg3_write_sig_legacy(tp, kind);
7328 tg3_write_sig_post_reset(tp, kind);
7336 #define RX_CPU_SCRATCH_BASE 0x30000
7337 #define RX_CPU_SCRATCH_SIZE 0x04000
7338 #define TX_CPU_SCRATCH_BASE 0x34000
7339 #define TX_CPU_SCRATCH_SIZE 0x04000
7341 /* tp->lock is held. */
7342 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7346 BUG_ON(offset == TX_CPU_BASE &&
7347 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7350 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7352 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7355 if (offset == RX_CPU_BASE) {
7356 for (i = 0; i < 10000; i++) {
7357 tw32(offset + CPU_STATE, 0xffffffff);
7358 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7359 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7363 tw32(offset + CPU_STATE, 0xffffffff);
7364 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7367 for (i = 0; i < 10000; i++) {
7368 tw32(offset + CPU_STATE, 0xffffffff);
7369 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7370 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7376 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7377 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7381 /* Clear firmware's nvram arbitration. */
7382 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7383 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7388 unsigned int fw_base;
7389 unsigned int fw_len;
7390 const __be32 *fw_data;
7393 /* tp->lock is held. */
7394 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7395 int cpu_scratch_size, struct fw_info *info)
7397 int err, lock_err, i;
7398 void (*write_op)(struct tg3 *, u32, u32);
7400 if (cpu_base == TX_CPU_BASE &&
7401 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7403 "%s: Trying to load TX cpu firmware which is 5705\n",
7408 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7409 write_op = tg3_write_mem;
7411 write_op = tg3_write_indirect_reg32;
7413 /* It is possible that bootcode is still loading at this point.
7414 * Get the nvram lock first before halting the cpu.
7416 lock_err = tg3_nvram_lock(tp);
7417 err = tg3_halt_cpu(tp, cpu_base);
7419 tg3_nvram_unlock(tp);
7423 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7424 write_op(tp, cpu_scratch_base + i, 0);
7425 tw32(cpu_base + CPU_STATE, 0xffffffff);
7426 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7427 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7428 write_op(tp, (cpu_scratch_base +
7429 (info->fw_base & 0xffff) +
7431 be32_to_cpu(info->fw_data[i]));
7439 /* tp->lock is held. */
7440 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7442 struct fw_info info;
7443 const __be32 *fw_data;
7446 fw_data = (void *)tp->fw->data;
7448 /* Firmware blob starts with version numbers, followed by
7449 start address and length. We are setting complete length.
7450 length = end_address_of_bss - start_address_of_text.
7451 Remainder is the blob to be loaded contiguously
7452 from start address. */
7454 info.fw_base = be32_to_cpu(fw_data[1]);
7455 info.fw_len = tp->fw->size - 12;
7456 info.fw_data = &fw_data[3];
7458 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7459 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7464 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7465 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7470 /* Now startup only the RX cpu. */
7471 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7472 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7474 for (i = 0; i < 5; i++) {
7475 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7477 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7478 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7479 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7483 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7484 "should be %08x\n", __func__,
7485 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7488 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7489 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7494 /* 5705 needs a special version of the TSO firmware. */
7496 /* tp->lock is held. */
7497 static int tg3_load_tso_firmware(struct tg3 *tp)
7499 struct fw_info info;
7500 const __be32 *fw_data;
7501 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7504 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7507 fw_data = (void *)tp->fw->data;
7509 /* Firmware blob starts with version numbers, followed by
7510 start address and length. We are setting complete length.
7511 length = end_address_of_bss - start_address_of_text.
7512 Remainder is the blob to be loaded contiguously
7513 from start address. */
7515 info.fw_base = be32_to_cpu(fw_data[1]);
7516 cpu_scratch_size = tp->fw_len;
7517 info.fw_len = tp->fw->size - 12;
7518 info.fw_data = &fw_data[3];
7520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7521 cpu_base = RX_CPU_BASE;
7522 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7524 cpu_base = TX_CPU_BASE;
7525 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7526 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7529 err = tg3_load_firmware_cpu(tp, cpu_base,
7530 cpu_scratch_base, cpu_scratch_size,
7535 /* Now startup the cpu. */
7536 tw32(cpu_base + CPU_STATE, 0xffffffff);
7537 tw32_f(cpu_base + CPU_PC, info.fw_base);
7539 for (i = 0; i < 5; i++) {
7540 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7542 tw32(cpu_base + CPU_STATE, 0xffffffff);
7543 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7544 tw32_f(cpu_base + CPU_PC, info.fw_base);
7549 "%s fails to set CPU PC, is %08x should be %08x\n",
7550 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7553 tw32(cpu_base + CPU_STATE, 0xffffffff);
7554 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7559 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7561 struct tg3 *tp = netdev_priv(dev);
7562 struct sockaddr *addr = p;
7563 int err = 0, skip_mac_1 = 0;
7565 if (!is_valid_ether_addr(addr->sa_data))
7568 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7570 if (!netif_running(dev))
7573 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7574 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7576 addr0_high = tr32(MAC_ADDR_0_HIGH);
7577 addr0_low = tr32(MAC_ADDR_0_LOW);
7578 addr1_high = tr32(MAC_ADDR_1_HIGH);
7579 addr1_low = tr32(MAC_ADDR_1_LOW);
7581 /* Skip MAC addr 1 if ASF is using it. */
7582 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7583 !(addr1_high == 0 && addr1_low == 0))
7586 spin_lock_bh(&tp->lock);
7587 __tg3_set_mac_addr(tp, skip_mac_1);
7588 spin_unlock_bh(&tp->lock);
7593 /* tp->lock is held. */
7594 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7595 dma_addr_t mapping, u32 maxlen_flags,
7599 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7600 ((u64) mapping >> 32));
7602 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7603 ((u64) mapping & 0xffffffff));
7605 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7608 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7610 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7614 static void __tg3_set_rx_mode(struct net_device *);
7615 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7619 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7620 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7621 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7622 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7624 tw32(HOSTCC_TXCOL_TICKS, 0);
7625 tw32(HOSTCC_TXMAX_FRAMES, 0);
7626 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7629 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7630 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7631 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7632 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7634 tw32(HOSTCC_RXCOL_TICKS, 0);
7635 tw32(HOSTCC_RXMAX_FRAMES, 0);
7636 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7639 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7640 u32 val = ec->stats_block_coalesce_usecs;
7642 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7643 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7645 if (!netif_carrier_ok(tp->dev))
7648 tw32(HOSTCC_STAT_COAL_TICKS, val);
7651 for (i = 0; i < tp->irq_cnt - 1; i++) {
7654 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7655 tw32(reg, ec->rx_coalesce_usecs);
7656 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7657 tw32(reg, ec->rx_max_coalesced_frames);
7658 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7659 tw32(reg, ec->rx_max_coalesced_frames_irq);
7661 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7662 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7663 tw32(reg, ec->tx_coalesce_usecs);
7664 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7665 tw32(reg, ec->tx_max_coalesced_frames);
7666 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7667 tw32(reg, ec->tx_max_coalesced_frames_irq);
7671 for (; i < tp->irq_max - 1; i++) {
7672 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7673 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7674 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7676 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7677 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7678 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7679 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7684 /* tp->lock is held. */
7685 static void tg3_rings_reset(struct tg3 *tp)
7688 u32 stblk, txrcb, rxrcb, limit;
7689 struct tg3_napi *tnapi = &tp->napi[0];
7691 /* Disable all transmit rings but the first. */
7692 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7693 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7694 else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7695 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7696 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7697 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7699 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7701 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7702 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7703 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7704 BDINFO_FLAGS_DISABLED);
7707 /* Disable all receive return rings but the first. */
7708 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7709 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7710 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7711 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7712 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7714 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7716 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7718 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7719 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7720 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7721 BDINFO_FLAGS_DISABLED);
7723 /* Disable interrupts */
7724 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7726 /* Zero mailbox registers. */
7727 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7728 for (i = 1; i < tp->irq_max; i++) {
7729 tp->napi[i].tx_prod = 0;
7730 tp->napi[i].tx_cons = 0;
7731 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7732 tw32_mailbox(tp->napi[i].prodmbox, 0);
7733 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7734 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7736 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7737 tw32_mailbox(tp->napi[0].prodmbox, 0);
7739 tp->napi[0].tx_prod = 0;
7740 tp->napi[0].tx_cons = 0;
7741 tw32_mailbox(tp->napi[0].prodmbox, 0);
7742 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7745 /* Make sure the NIC-based send BD rings are disabled. */
7746 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7747 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7748 for (i = 0; i < 16; i++)
7749 tw32_tx_mbox(mbox + i * 8, 0);
7752 txrcb = NIC_SRAM_SEND_RCB;
7753 rxrcb = NIC_SRAM_RCV_RET_RCB;
7755 /* Clear status block in ram. */
7756 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7758 /* Set status block DMA address */
7759 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7760 ((u64) tnapi->status_mapping >> 32));
7761 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7762 ((u64) tnapi->status_mapping & 0xffffffff));
7764 if (tnapi->tx_ring) {
7765 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7766 (TG3_TX_RING_SIZE <<
7767 BDINFO_FLAGS_MAXLEN_SHIFT),
7768 NIC_SRAM_TX_BUFFER_DESC);
7769 txrcb += TG3_BDINFO_SIZE;
7772 if (tnapi->rx_rcb) {
7773 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7774 (tp->rx_ret_ring_mask + 1) <<
7775 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7776 rxrcb += TG3_BDINFO_SIZE;
7779 stblk = HOSTCC_STATBLCK_RING1;
7781 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7782 u64 mapping = (u64)tnapi->status_mapping;
7783 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7784 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7786 /* Clear status block in ram. */
7787 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7789 if (tnapi->tx_ring) {
7790 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7791 (TG3_TX_RING_SIZE <<
7792 BDINFO_FLAGS_MAXLEN_SHIFT),
7793 NIC_SRAM_TX_BUFFER_DESC);
7794 txrcb += TG3_BDINFO_SIZE;
7797 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7798 ((tp->rx_ret_ring_mask + 1) <<
7799 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7802 rxrcb += TG3_BDINFO_SIZE;
7806 /* tp->lock is held. */
7807 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7809 u32 val, rdmac_mode;
7811 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7813 tg3_disable_ints(tp);
7817 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7819 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7820 tg3_abort_hw(tp, 1);
7822 /* Enable MAC control of LPI */
7823 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7824 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7825 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7826 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7828 tw32_f(TG3_CPMU_EEE_CTRL,
7829 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7831 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7832 TG3_CPMU_EEEMD_LPI_IN_TX |
7833 TG3_CPMU_EEEMD_LPI_IN_RX |
7834 TG3_CPMU_EEEMD_EEE_ENABLE;
7836 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7837 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7839 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7840 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7842 tw32_f(TG3_CPMU_EEE_MODE, val);
7844 tw32_f(TG3_CPMU_EEE_DBTMR1,
7845 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7846 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7848 tw32_f(TG3_CPMU_EEE_DBTMR2,
7849 TG3_CPMU_DBTMR2_APE_TX_2047US |
7850 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7856 err = tg3_chip_reset(tp);
7860 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7862 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7863 val = tr32(TG3_CPMU_CTRL);
7864 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7865 tw32(TG3_CPMU_CTRL, val);
7867 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7868 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7869 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7870 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7872 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7873 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7874 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7875 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7877 val = tr32(TG3_CPMU_HST_ACC);
7878 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7879 val |= CPMU_HST_ACC_MACCLK_6_25;
7880 tw32(TG3_CPMU_HST_ACC, val);
7883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7884 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7885 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7886 PCIE_PWR_MGMT_L1_THRESH_4MS;
7887 tw32(PCIE_PWR_MGMT_THRESH, val);
7889 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7890 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7892 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7894 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7895 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7898 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7899 u32 grc_mode = tr32(GRC_MODE);
7901 /* Access the lower 1K of PL PCIE block registers. */
7902 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7903 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7905 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7906 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7907 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7909 tw32(GRC_MODE, grc_mode);
7912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7913 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7914 u32 grc_mode = tr32(GRC_MODE);
7916 /* Access the lower 1K of PL PCIE block registers. */
7917 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7918 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7920 val = tr32(TG3_PCIE_TLDLPL_PORT +
7921 TG3_PCIE_PL_LO_PHYCTL5);
7922 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7923 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7925 tw32(GRC_MODE, grc_mode);
7928 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7929 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7930 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7931 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7934 /* This works around an issue with Athlon chipsets on
7935 * B3 tigon3 silicon. This bit has no effect on any
7936 * other revision. But do not set this on PCI Express
7937 * chips and don't even touch the clocks if the CPMU is present.
7939 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7940 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7941 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7942 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7945 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7946 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7947 val = tr32(TG3PCI_PCISTATE);
7948 val |= PCISTATE_RETRY_SAME_DMA;
7949 tw32(TG3PCI_PCISTATE, val);
7952 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7953 /* Allow reads and writes to the
7954 * APE register and memory space.
7956 val = tr32(TG3PCI_PCISTATE);
7957 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7958 PCISTATE_ALLOW_APE_SHMEM_WR |
7959 PCISTATE_ALLOW_APE_PSPACE_WR;
7960 tw32(TG3PCI_PCISTATE, val);
7963 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7964 /* Enable some hw fixes. */
7965 val = tr32(TG3PCI_MSI_DATA);
7966 val |= (1 << 26) | (1 << 28) | (1 << 29);
7967 tw32(TG3PCI_MSI_DATA, val);
7970 /* Descriptor ring init may make accesses to the
7971 * NIC SRAM area to setup the TX descriptors, so we
7972 * can only do this after the hardware has been
7973 * successfully reset.
7975 err = tg3_init_rings(tp);
7979 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
7980 val = tr32(TG3PCI_DMA_RW_CTRL) &
7981 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7982 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7983 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7984 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7985 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7986 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7987 /* This value is determined during the probe time DMA
7988 * engine test, tg3_test_dma.
7990 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7993 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7994 GRC_MODE_4X_NIC_SEND_RINGS |
7995 GRC_MODE_NO_TX_PHDR_CSUM |
7996 GRC_MODE_NO_RX_PHDR_CSUM);
7997 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7999 /* Pseudo-header checksum is done by hardware logic and not
8000 * the offload processers, so make the chip do the pseudo-
8001 * header checksums on receive. For transmit it is more
8002 * convenient to do the pseudo-header checksum in software
8003 * as Linux does that on transmit for us in all cases.
8005 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8009 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8011 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8012 val = tr32(GRC_MISC_CFG);
8014 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8015 tw32(GRC_MISC_CFG, val);
8017 /* Initialize MBUF/DESC pool. */
8018 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8020 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8021 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8023 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8025 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8026 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8027 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8028 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8031 fw_len = tp->fw_len;
8032 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8033 tw32(BUFMGR_MB_POOL_ADDR,
8034 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8035 tw32(BUFMGR_MB_POOL_SIZE,
8036 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8039 if (tp->dev->mtu <= ETH_DATA_LEN) {
8040 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8041 tp->bufmgr_config.mbuf_read_dma_low_water);
8042 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8043 tp->bufmgr_config.mbuf_mac_rx_low_water);
8044 tw32(BUFMGR_MB_HIGH_WATER,
8045 tp->bufmgr_config.mbuf_high_water);
8047 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8048 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8049 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8050 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8051 tw32(BUFMGR_MB_HIGH_WATER,
8052 tp->bufmgr_config.mbuf_high_water_jumbo);
8054 tw32(BUFMGR_DMA_LOW_WATER,
8055 tp->bufmgr_config.dma_low_water);
8056 tw32(BUFMGR_DMA_HIGH_WATER,
8057 tp->bufmgr_config.dma_high_water);
8059 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8061 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8062 tw32(BUFMGR_MODE, val);
8063 for (i = 0; i < 2000; i++) {
8064 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8069 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8073 /* Setup replenish threshold. */
8074 val = tp->rx_pending / 8;
8077 else if (val > tp->rx_std_max_post)
8078 val = tp->rx_std_max_post;
8079 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8080 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8081 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8083 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8084 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8087 tw32(RCVBDI_STD_THRESH, val);
8089 /* Initialize TG3_BDINFO's at:
8090 * RCVDBDI_STD_BD: standard eth size rx ring
8091 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8092 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8095 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8096 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8097 * ring attribute flags
8098 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8100 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8101 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8103 * The size of each ring is fixed in the firmware, but the location is
8106 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8107 ((u64) tpr->rx_std_mapping >> 32));
8108 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8109 ((u64) tpr->rx_std_mapping & 0xffffffff));
8110 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
8111 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8112 NIC_SRAM_RX_BUFFER_DESC);
8114 /* Disable the mini ring */
8115 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8116 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8117 BDINFO_FLAGS_DISABLED);
8119 /* Program the jumbo buffer descriptor ring control
8120 * blocks on those devices that have them.
8122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8123 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8124 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8125 /* Setup replenish threshold. */
8126 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8128 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8129 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8130 ((u64) tpr->rx_jmb_mapping >> 32));
8131 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8132 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8133 val = TG3_RX_JMB_RING_SIZE(tp) <<
8134 BDINFO_FLAGS_MAXLEN_SHIFT;
8135 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8136 val | BDINFO_FLAGS_USE_EXT_RECV);
8137 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8139 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8140 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8142 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8143 BDINFO_FLAGS_DISABLED);
8146 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8148 val = TG3_RX_STD_MAX_SIZE_5700;
8150 val = TG3_RX_STD_MAX_SIZE_5717;
8151 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8152 val |= (TG3_RX_STD_DMA_SZ << 2);
8154 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8156 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8158 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8160 tpr->rx_std_prod_idx = tp->rx_pending;
8161 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8163 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8164 tp->rx_jumbo_pending : 0;
8165 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8167 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8168 tw32(STD_REPLENISH_LWM, 32);
8169 tw32(JMB_REPLENISH_LWM, 16);
8172 tg3_rings_reset(tp);
8174 /* Initialize MAC address and backoff seed. */
8175 __tg3_set_mac_addr(tp, 0);
8177 /* MTU + ethernet header + FCS + optional VLAN tag */
8178 tw32(MAC_RX_MTU_SIZE,
8179 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8181 /* The slot time is changed by tg3_setup_phy if we
8182 * run at gigabit with half duplex.
8184 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8185 (6 << TX_LENGTHS_IPG_SHIFT) |
8186 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8189 val |= tr32(MAC_TX_LENGTHS) &
8190 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8191 TX_LENGTHS_CNT_DWN_VAL_MSK);
8193 tw32(MAC_TX_LENGTHS, val);
8195 /* Receive rules. */
8196 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8197 tw32(RCVLPC_CONFIG, 0x0181);
8199 /* Calculate RDMAC_MODE setting early, we need it to determine
8200 * the RCVLPC_STATE_ENABLE mask.
8202 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8203 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8204 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8205 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8206 RDMAC_MODE_LNGREAD_ENAB);
8208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8209 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8214 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8215 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8216 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8219 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8220 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8222 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8223 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8224 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8225 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8229 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8230 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8232 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8233 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8235 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8238 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8241 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8244 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8245 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8247 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
8248 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8251 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8252 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8253 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8254 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8255 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8256 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8258 tw32(TG3_RDMA_RSRVCTRL_REG,
8259 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8263 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8264 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8265 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8266 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8267 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8270 /* Receive/send statistics. */
8271 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8272 val = tr32(RCVLPC_STATS_ENABLE);
8273 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8274 tw32(RCVLPC_STATS_ENABLE, val);
8275 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8276 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8277 val = tr32(RCVLPC_STATS_ENABLE);
8278 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8279 tw32(RCVLPC_STATS_ENABLE, val);
8281 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8283 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8284 tw32(SNDDATAI_STATSENAB, 0xffffff);
8285 tw32(SNDDATAI_STATSCTRL,
8286 (SNDDATAI_SCTRL_ENABLE |
8287 SNDDATAI_SCTRL_FASTUPD));
8289 /* Setup host coalescing engine. */
8290 tw32(HOSTCC_MODE, 0);
8291 for (i = 0; i < 2000; i++) {
8292 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8297 __tg3_set_coalesce(tp, &tp->coal);
8299 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8300 /* Status/statistics block address. See tg3_timer,
8301 * the tg3_periodic_fetch_stats call there, and
8302 * tg3_get_stats to see how this works for 5705/5750 chips.
8304 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8305 ((u64) tp->stats_mapping >> 32));
8306 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8307 ((u64) tp->stats_mapping & 0xffffffff));
8308 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8310 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8312 /* Clear statistics and status block memory areas */
8313 for (i = NIC_SRAM_STATS_BLK;
8314 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8316 tg3_write_mem(tp, i, 0);
8321 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8323 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8324 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8325 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8326 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8328 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8329 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8330 /* reset to prevent losing 1st rx packet intermittently */
8331 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8335 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8336 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8339 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8340 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8341 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8342 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8343 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8344 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8345 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8348 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8349 * If TG3_FLG2_IS_NIC is zero, we should read the
8350 * register to preserve the GPIO settings for LOMs. The GPIOs,
8351 * whether used as inputs or outputs, are set by boot code after
8354 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8357 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8358 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8359 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8362 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8363 GRC_LCLCTRL_GPIO_OUTPUT3;
8365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8366 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8368 tp->grc_local_ctrl &= ~gpio_mask;
8369 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8371 /* GPIO1 must be driven high for eeprom write protect */
8372 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8373 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8374 GRC_LCLCTRL_GPIO_OUTPUT1);
8376 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8379 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8381 val = tr32(MSGINT_MODE);
8382 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8383 tw32(MSGINT_MODE, val);
8386 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8387 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8391 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8392 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8393 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8394 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8395 WDMAC_MODE_LNGREAD_ENAB);
8397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8398 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8399 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8400 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8401 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8403 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8404 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8405 val |= WDMAC_MODE_RX_ACCEL;
8409 /* Enable host coalescing bug fix */
8410 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8411 val |= WDMAC_MODE_STATUS_TAG_FIX;
8413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8414 val |= WDMAC_MODE_BURST_ALL_DATA;
8416 tw32_f(WDMAC_MODE, val);
8419 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8422 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8425 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8426 pcix_cmd |= PCI_X_CMD_READ_2K;
8427 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8428 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8429 pcix_cmd |= PCI_X_CMD_READ_2K;
8431 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8435 tw32_f(RDMAC_MODE, rdmac_mode);
8438 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8439 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8440 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8444 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8446 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8448 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8449 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8450 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8451 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
8452 val |= RCVDBDI_MODE_LRG_RING_SZ;
8453 tw32(RCVDBDI_MODE, val);
8454 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8455 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8456 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8457 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8458 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8459 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8460 tw32(SNDBDI_MODE, val);
8461 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8463 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8464 err = tg3_load_5701_a0_firmware_fix(tp);
8469 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8470 err = tg3_load_tso_firmware(tp);
8475 tp->tx_mode = TX_MODE_ENABLE;
8477 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8478 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8479 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8482 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8483 tp->tx_mode &= ~val;
8484 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8487 tw32_f(MAC_TX_MODE, tp->tx_mode);
8490 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8491 u32 reg = MAC_RSS_INDIR_TBL_0;
8492 u8 *ent = (u8 *)&val;
8494 /* Setup the indirection table */
8495 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8496 int idx = i % sizeof(val);
8498 ent[idx] = i % (tp->irq_cnt - 1);
8499 if (idx == sizeof(val) - 1) {
8505 /* Setup the "secret" hash key. */
8506 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8507 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8508 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8509 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8510 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8511 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8512 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8513 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8514 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8515 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8518 tp->rx_mode = RX_MODE_ENABLE;
8519 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8520 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8522 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8523 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8524 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8525 RX_MODE_RSS_IPV6_HASH_EN |
8526 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8527 RX_MODE_RSS_IPV4_HASH_EN |
8528 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8530 tw32_f(MAC_RX_MODE, tp->rx_mode);
8533 tw32(MAC_LED_CTRL, tp->led_ctrl);
8535 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8536 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8537 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8540 tw32_f(MAC_RX_MODE, tp->rx_mode);
8543 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8544 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8545 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8546 /* Set drive transmission level to 1.2V */
8547 /* only if the signal pre-emphasis bit is not set */
8548 val = tr32(MAC_SERDES_CFG);
8551 tw32(MAC_SERDES_CFG, val);
8553 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8554 tw32(MAC_SERDES_CFG, 0x616000);
8557 /* Prevent chip from dropping frames when flow control
8560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8564 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8567 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8568 /* Use hardware link auto-negotiation */
8569 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8572 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8573 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8576 tmp = tr32(SERDES_RX_CTRL);
8577 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8578 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8579 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8580 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8583 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8584 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8585 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8586 tp->link_config.speed = tp->link_config.orig_speed;
8587 tp->link_config.duplex = tp->link_config.orig_duplex;
8588 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8591 err = tg3_setup_phy(tp, 0);
8595 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8596 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8599 /* Clear CRC stats. */
8600 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8601 tg3_writephy(tp, MII_TG3_TEST1,
8602 tmp | MII_TG3_TEST1_CRC_EN);
8603 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8608 __tg3_set_rx_mode(tp->dev);
8610 /* Initialize receive rules. */
8611 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8612 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8613 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8614 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8616 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8617 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8621 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8625 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8627 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8629 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8631 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8633 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8635 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8637 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8639 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8641 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8643 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8645 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8647 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8649 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8651 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8659 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8660 /* Write our heartbeat update interval to APE. */
8661 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8662 APE_HOST_HEARTBEAT_INT_DISABLE);
8664 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8669 /* Called at device open time to get the chip ready for
8670 * packet processing. Invoked with tp->lock held.
8672 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8674 tg3_switch_clocks(tp);
8676 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8678 return tg3_reset_hw(tp, reset_phy);
8681 #define TG3_STAT_ADD32(PSTAT, REG) \
8682 do { u32 __val = tr32(REG); \
8683 (PSTAT)->low += __val; \
8684 if ((PSTAT)->low < __val) \
8685 (PSTAT)->high += 1; \
8688 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8690 struct tg3_hw_stats *sp = tp->hw_stats;
8692 if (!netif_carrier_ok(tp->dev))
8695 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8696 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8697 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8698 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8699 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8700 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8701 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8702 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8703 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8704 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8705 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8706 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8707 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8709 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8710 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8711 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8712 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8713 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8714 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8715 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8716 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8717 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8718 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8719 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8720 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8721 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8722 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8724 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8725 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8726 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8729 static void tg3_timer(unsigned long __opaque)
8731 struct tg3 *tp = (struct tg3 *) __opaque;
8736 spin_lock(&tp->lock);
8738 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8739 /* All of this garbage is because when using non-tagged
8740 * IRQ status the mailbox/status_block protocol the chip
8741 * uses with the cpu is race prone.
8743 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8744 tw32(GRC_LOCAL_CTRL,
8745 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8747 tw32(HOSTCC_MODE, tp->coalesce_mode |
8748 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8751 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8752 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8753 spin_unlock(&tp->lock);
8754 schedule_work(&tp->reset_task);
8759 /* This part only runs once per second. */
8760 if (!--tp->timer_counter) {
8761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8762 tg3_periodic_fetch_stats(tp);
8764 if (tp->setlpicnt && !--tp->setlpicnt) {
8765 u32 val = tr32(TG3_CPMU_EEE_MODE);
8766 tw32(TG3_CPMU_EEE_MODE,
8767 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8770 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8774 mac_stat = tr32(MAC_STATUS);
8777 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8778 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8780 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8784 tg3_setup_phy(tp, 0);
8785 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8786 u32 mac_stat = tr32(MAC_STATUS);
8789 if (netif_carrier_ok(tp->dev) &&
8790 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8793 if (!netif_carrier_ok(tp->dev) &&
8794 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8795 MAC_STATUS_SIGNAL_DET))) {
8799 if (!tp->serdes_counter) {
8802 ~MAC_MODE_PORT_MODE_MASK));
8804 tw32_f(MAC_MODE, tp->mac_mode);
8807 tg3_setup_phy(tp, 0);
8809 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8810 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8811 tg3_serdes_parallel_detect(tp);
8814 tp->timer_counter = tp->timer_multiplier;
8817 /* Heartbeat is only sent once every 2 seconds.
8819 * The heartbeat is to tell the ASF firmware that the host
8820 * driver is still alive. In the event that the OS crashes,
8821 * ASF needs to reset the hardware to free up the FIFO space
8822 * that may be filled with rx packets destined for the host.
8823 * If the FIFO is full, ASF will no longer function properly.
8825 * Unintended resets have been reported on real time kernels
8826 * where the timer doesn't run on time. Netpoll will also have
8829 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8830 * to check the ring condition when the heartbeat is expiring
8831 * before doing the reset. This will prevent most unintended
8834 if (!--tp->asf_counter) {
8835 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8836 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8837 tg3_wait_for_event_ack(tp);
8839 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8840 FWCMD_NICDRV_ALIVE3);
8841 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8842 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8843 TG3_FW_UPDATE_TIMEOUT_SEC);
8845 tg3_generate_fw_event(tp);
8847 tp->asf_counter = tp->asf_multiplier;
8850 spin_unlock(&tp->lock);
8853 tp->timer.expires = jiffies + tp->timer_offset;
8854 add_timer(&tp->timer);
8857 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8860 unsigned long flags;
8862 struct tg3_napi *tnapi = &tp->napi[irq_num];
8864 if (tp->irq_cnt == 1)
8865 name = tp->dev->name;
8867 name = &tnapi->irq_lbl[0];
8868 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8869 name[IFNAMSIZ-1] = 0;
8872 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8874 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8879 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8880 fn = tg3_interrupt_tagged;
8881 flags = IRQF_SHARED;
8884 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8887 static int tg3_test_interrupt(struct tg3 *tp)
8889 struct tg3_napi *tnapi = &tp->napi[0];
8890 struct net_device *dev = tp->dev;
8891 int err, i, intr_ok = 0;
8894 if (!netif_running(dev))
8897 tg3_disable_ints(tp);
8899 free_irq(tnapi->irq_vec, tnapi);
8902 * Turn off MSI one shot mode. Otherwise this test has no
8903 * observable way to know whether the interrupt was delivered.
8905 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
8906 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8907 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8908 tw32(MSGINT_MODE, val);
8911 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8912 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8916 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8917 tg3_enable_ints(tp);
8919 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8922 for (i = 0; i < 5; i++) {
8923 u32 int_mbox, misc_host_ctrl;
8925 int_mbox = tr32_mailbox(tnapi->int_mbox);
8926 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8928 if ((int_mbox != 0) ||
8929 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8937 tg3_disable_ints(tp);
8939 free_irq(tnapi->irq_vec, tnapi);
8941 err = tg3_request_irq(tp, 0);
8947 /* Reenable MSI one shot mode. */
8948 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
8949 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8950 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8951 tw32(MSGINT_MODE, val);
8959 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8960 * successfully restored
8962 static int tg3_test_msi(struct tg3 *tp)
8967 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8970 /* Turn off SERR reporting in case MSI terminates with Master
8973 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8974 pci_write_config_word(tp->pdev, PCI_COMMAND,
8975 pci_cmd & ~PCI_COMMAND_SERR);
8977 err = tg3_test_interrupt(tp);
8979 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8984 /* other failures */
8988 /* MSI test failed, go back to INTx mode */
8989 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8990 "to INTx mode. Please report this failure to the PCI "
8991 "maintainer and include system chipset information\n");
8993 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8995 pci_disable_msi(tp->pdev);
8997 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8998 tp->napi[0].irq_vec = tp->pdev->irq;
9000 err = tg3_request_irq(tp, 0);
9004 /* Need to reset the chip because the MSI cycle may have terminated
9005 * with Master Abort.
9007 tg3_full_lock(tp, 1);
9009 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9010 err = tg3_init_hw(tp, 1);
9012 tg3_full_unlock(tp);
9015 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9020 static int tg3_request_firmware(struct tg3 *tp)
9022 const __be32 *fw_data;
9024 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9025 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9030 fw_data = (void *)tp->fw->data;
9032 /* Firmware blob starts with version numbers, followed by
9033 * start address and _full_ length including BSS sections
9034 * (which must be longer than the actual data, of course
9037 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9038 if (tp->fw_len < (tp->fw->size - 12)) {
9039 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9040 tp->fw_len, tp->fw_needed);
9041 release_firmware(tp->fw);
9046 /* We no longer need firmware; we have it. */
9047 tp->fw_needed = NULL;
9051 static bool tg3_enable_msix(struct tg3 *tp)
9053 int i, rc, cpus = num_online_cpus();
9054 struct msix_entry msix_ent[tp->irq_max];
9057 /* Just fallback to the simpler MSI mode. */
9061 * We want as many rx rings enabled as there are cpus.
9062 * The first MSIX vector only deals with link interrupts, etc,
9063 * so we add one to the number of vectors we are requesting.
9065 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9067 for (i = 0; i < tp->irq_max; i++) {
9068 msix_ent[i].entry = i;
9069 msix_ent[i].vector = 0;
9072 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9075 } else if (rc != 0) {
9076 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9078 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9083 for (i = 0; i < tp->irq_max; i++)
9084 tp->napi[i].irq_vec = msix_ent[i].vector;
9086 netif_set_real_num_tx_queues(tp->dev, 1);
9087 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9088 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9089 pci_disable_msix(tp->pdev);
9093 if (tp->irq_cnt > 1) {
9094 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9098 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9099 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9106 static void tg3_ints_init(struct tg3 *tp)
9108 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9109 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9110 /* All MSI supporting chips should support tagged
9111 * status. Assert that this is the case.
9113 netdev_warn(tp->dev,
9114 "MSI without TAGGED_STATUS? Not using MSI\n");
9118 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9119 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9120 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9121 pci_enable_msi(tp->pdev) == 0)
9122 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9124 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9125 u32 msi_mode = tr32(MSGINT_MODE);
9126 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9128 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9129 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9132 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9134 tp->napi[0].irq_vec = tp->pdev->irq;
9135 netif_set_real_num_tx_queues(tp->dev, 1);
9136 netif_set_real_num_rx_queues(tp->dev, 1);
9140 static void tg3_ints_fini(struct tg3 *tp)
9142 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9143 pci_disable_msix(tp->pdev);
9144 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9145 pci_disable_msi(tp->pdev);
9146 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9147 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9150 static int tg3_open(struct net_device *dev)
9152 struct tg3 *tp = netdev_priv(dev);
9155 if (tp->fw_needed) {
9156 err = tg3_request_firmware(tp);
9157 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9161 netdev_warn(tp->dev, "TSO capability disabled\n");
9162 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9163 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9164 netdev_notice(tp->dev, "TSO capability restored\n");
9165 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9169 netif_carrier_off(tp->dev);
9171 err = tg3_power_up(tp);
9175 tg3_full_lock(tp, 0);
9177 tg3_disable_ints(tp);
9178 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9180 tg3_full_unlock(tp);
9183 * Setup interrupts first so we know how
9184 * many NAPI resources to allocate
9188 /* The placement of this call is tied
9189 * to the setup and use of Host TX descriptors.
9191 err = tg3_alloc_consistent(tp);
9197 tg3_napi_enable(tp);
9199 for (i = 0; i < tp->irq_cnt; i++) {
9200 struct tg3_napi *tnapi = &tp->napi[i];
9201 err = tg3_request_irq(tp, i);
9203 for (i--; i >= 0; i--)
9204 free_irq(tnapi->irq_vec, tnapi);
9212 tg3_full_lock(tp, 0);
9214 err = tg3_init_hw(tp, 1);
9216 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9219 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9220 tp->timer_offset = HZ;
9222 tp->timer_offset = HZ / 10;
9224 BUG_ON(tp->timer_offset > HZ);
9225 tp->timer_counter = tp->timer_multiplier =
9226 (HZ / tp->timer_offset);
9227 tp->asf_counter = tp->asf_multiplier =
9228 ((HZ / tp->timer_offset) * 2);
9230 init_timer(&tp->timer);
9231 tp->timer.expires = jiffies + tp->timer_offset;
9232 tp->timer.data = (unsigned long) tp;
9233 tp->timer.function = tg3_timer;
9236 tg3_full_unlock(tp);
9241 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9242 err = tg3_test_msi(tp);
9245 tg3_full_lock(tp, 0);
9246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9248 tg3_full_unlock(tp);
9253 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9254 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9255 u32 val = tr32(PCIE_TRANSACTION_CFG);
9257 tw32(PCIE_TRANSACTION_CFG,
9258 val | PCIE_TRANS_CFG_1SHOT_MSI);
9264 tg3_full_lock(tp, 0);
9266 add_timer(&tp->timer);
9267 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9268 tg3_enable_ints(tp);
9270 tg3_full_unlock(tp);
9272 netif_tx_start_all_queues(dev);
9277 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9278 struct tg3_napi *tnapi = &tp->napi[i];
9279 free_irq(tnapi->irq_vec, tnapi);
9283 tg3_napi_disable(tp);
9285 tg3_free_consistent(tp);
9292 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9293 struct rtnl_link_stats64 *);
9294 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9296 static int tg3_close(struct net_device *dev)
9299 struct tg3 *tp = netdev_priv(dev);
9301 tg3_napi_disable(tp);
9302 cancel_work_sync(&tp->reset_task);
9304 netif_tx_stop_all_queues(dev);
9306 del_timer_sync(&tp->timer);
9310 tg3_full_lock(tp, 1);
9312 tg3_disable_ints(tp);
9314 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9316 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9318 tg3_full_unlock(tp);
9320 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9321 struct tg3_napi *tnapi = &tp->napi[i];
9322 free_irq(tnapi->irq_vec, tnapi);
9327 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9329 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9330 sizeof(tp->estats_prev));
9334 tg3_free_consistent(tp);
9338 netif_carrier_off(tp->dev);
9343 static inline u64 get_stat64(tg3_stat64_t *val)
9345 return ((u64)val->high << 32) | ((u64)val->low);
9348 static u64 calc_crc_errors(struct tg3 *tp)
9350 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9352 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9353 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9357 spin_lock_bh(&tp->lock);
9358 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9359 tg3_writephy(tp, MII_TG3_TEST1,
9360 val | MII_TG3_TEST1_CRC_EN);
9361 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9364 spin_unlock_bh(&tp->lock);
9366 tp->phy_crc_errors += val;
9368 return tp->phy_crc_errors;
9371 return get_stat64(&hw_stats->rx_fcs_errors);
9374 #define ESTAT_ADD(member) \
9375 estats->member = old_estats->member + \
9376 get_stat64(&hw_stats->member)
9378 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9380 struct tg3_ethtool_stats *estats = &tp->estats;
9381 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9382 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9387 ESTAT_ADD(rx_octets);
9388 ESTAT_ADD(rx_fragments);
9389 ESTAT_ADD(rx_ucast_packets);
9390 ESTAT_ADD(rx_mcast_packets);
9391 ESTAT_ADD(rx_bcast_packets);
9392 ESTAT_ADD(rx_fcs_errors);
9393 ESTAT_ADD(rx_align_errors);
9394 ESTAT_ADD(rx_xon_pause_rcvd);
9395 ESTAT_ADD(rx_xoff_pause_rcvd);
9396 ESTAT_ADD(rx_mac_ctrl_rcvd);
9397 ESTAT_ADD(rx_xoff_entered);
9398 ESTAT_ADD(rx_frame_too_long_errors);
9399 ESTAT_ADD(rx_jabbers);
9400 ESTAT_ADD(rx_undersize_packets);
9401 ESTAT_ADD(rx_in_length_errors);
9402 ESTAT_ADD(rx_out_length_errors);
9403 ESTAT_ADD(rx_64_or_less_octet_packets);
9404 ESTAT_ADD(rx_65_to_127_octet_packets);
9405 ESTAT_ADD(rx_128_to_255_octet_packets);
9406 ESTAT_ADD(rx_256_to_511_octet_packets);
9407 ESTAT_ADD(rx_512_to_1023_octet_packets);
9408 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9409 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9410 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9411 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9412 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9414 ESTAT_ADD(tx_octets);
9415 ESTAT_ADD(tx_collisions);
9416 ESTAT_ADD(tx_xon_sent);
9417 ESTAT_ADD(tx_xoff_sent);
9418 ESTAT_ADD(tx_flow_control);
9419 ESTAT_ADD(tx_mac_errors);
9420 ESTAT_ADD(tx_single_collisions);
9421 ESTAT_ADD(tx_mult_collisions);
9422 ESTAT_ADD(tx_deferred);
9423 ESTAT_ADD(tx_excessive_collisions);
9424 ESTAT_ADD(tx_late_collisions);
9425 ESTAT_ADD(tx_collide_2times);
9426 ESTAT_ADD(tx_collide_3times);
9427 ESTAT_ADD(tx_collide_4times);
9428 ESTAT_ADD(tx_collide_5times);
9429 ESTAT_ADD(tx_collide_6times);
9430 ESTAT_ADD(tx_collide_7times);
9431 ESTAT_ADD(tx_collide_8times);
9432 ESTAT_ADD(tx_collide_9times);
9433 ESTAT_ADD(tx_collide_10times);
9434 ESTAT_ADD(tx_collide_11times);
9435 ESTAT_ADD(tx_collide_12times);
9436 ESTAT_ADD(tx_collide_13times);
9437 ESTAT_ADD(tx_collide_14times);
9438 ESTAT_ADD(tx_collide_15times);
9439 ESTAT_ADD(tx_ucast_packets);
9440 ESTAT_ADD(tx_mcast_packets);
9441 ESTAT_ADD(tx_bcast_packets);
9442 ESTAT_ADD(tx_carrier_sense_errors);
9443 ESTAT_ADD(tx_discards);
9444 ESTAT_ADD(tx_errors);
9446 ESTAT_ADD(dma_writeq_full);
9447 ESTAT_ADD(dma_write_prioq_full);
9448 ESTAT_ADD(rxbds_empty);
9449 ESTAT_ADD(rx_discards);
9450 ESTAT_ADD(rx_errors);
9451 ESTAT_ADD(rx_threshold_hit);
9453 ESTAT_ADD(dma_readq_full);
9454 ESTAT_ADD(dma_read_prioq_full);
9455 ESTAT_ADD(tx_comp_queue_full);
9457 ESTAT_ADD(ring_set_send_prod_index);
9458 ESTAT_ADD(ring_status_update);
9459 ESTAT_ADD(nic_irqs);
9460 ESTAT_ADD(nic_avoided_irqs);
9461 ESTAT_ADD(nic_tx_threshold_hit);
9466 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9467 struct rtnl_link_stats64 *stats)
9469 struct tg3 *tp = netdev_priv(dev);
9470 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9471 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9476 stats->rx_packets = old_stats->rx_packets +
9477 get_stat64(&hw_stats->rx_ucast_packets) +
9478 get_stat64(&hw_stats->rx_mcast_packets) +
9479 get_stat64(&hw_stats->rx_bcast_packets);
9481 stats->tx_packets = old_stats->tx_packets +
9482 get_stat64(&hw_stats->tx_ucast_packets) +
9483 get_stat64(&hw_stats->tx_mcast_packets) +
9484 get_stat64(&hw_stats->tx_bcast_packets);
9486 stats->rx_bytes = old_stats->rx_bytes +
9487 get_stat64(&hw_stats->rx_octets);
9488 stats->tx_bytes = old_stats->tx_bytes +
9489 get_stat64(&hw_stats->tx_octets);
9491 stats->rx_errors = old_stats->rx_errors +
9492 get_stat64(&hw_stats->rx_errors);
9493 stats->tx_errors = old_stats->tx_errors +
9494 get_stat64(&hw_stats->tx_errors) +
9495 get_stat64(&hw_stats->tx_mac_errors) +
9496 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9497 get_stat64(&hw_stats->tx_discards);
9499 stats->multicast = old_stats->multicast +
9500 get_stat64(&hw_stats->rx_mcast_packets);
9501 stats->collisions = old_stats->collisions +
9502 get_stat64(&hw_stats->tx_collisions);
9504 stats->rx_length_errors = old_stats->rx_length_errors +
9505 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9506 get_stat64(&hw_stats->rx_undersize_packets);
9508 stats->rx_over_errors = old_stats->rx_over_errors +
9509 get_stat64(&hw_stats->rxbds_empty);
9510 stats->rx_frame_errors = old_stats->rx_frame_errors +
9511 get_stat64(&hw_stats->rx_align_errors);
9512 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9513 get_stat64(&hw_stats->tx_discards);
9514 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9515 get_stat64(&hw_stats->tx_carrier_sense_errors);
9517 stats->rx_crc_errors = old_stats->rx_crc_errors +
9518 calc_crc_errors(tp);
9520 stats->rx_missed_errors = old_stats->rx_missed_errors +
9521 get_stat64(&hw_stats->rx_discards);
9523 stats->rx_dropped = tp->rx_dropped;
9528 static inline u32 calc_crc(unsigned char *buf, int len)
9536 for (j = 0; j < len; j++) {
9539 for (k = 0; k < 8; k++) {
9552 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9554 /* accept or reject all multicast frames */
9555 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9556 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9557 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9558 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9561 static void __tg3_set_rx_mode(struct net_device *dev)
9563 struct tg3 *tp = netdev_priv(dev);
9566 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9567 RX_MODE_KEEP_VLAN_TAG);
9569 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9570 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9573 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9574 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9577 if (dev->flags & IFF_PROMISC) {
9578 /* Promiscuous mode. */
9579 rx_mode |= RX_MODE_PROMISC;
9580 } else if (dev->flags & IFF_ALLMULTI) {
9581 /* Accept all multicast. */
9582 tg3_set_multi(tp, 1);
9583 } else if (netdev_mc_empty(dev)) {
9584 /* Reject all multicast. */
9585 tg3_set_multi(tp, 0);
9587 /* Accept one or more multicast(s). */
9588 struct netdev_hw_addr *ha;
9589 u32 mc_filter[4] = { 0, };
9594 netdev_for_each_mc_addr(ha, dev) {
9595 crc = calc_crc(ha->addr, ETH_ALEN);
9597 regidx = (bit & 0x60) >> 5;
9599 mc_filter[regidx] |= (1 << bit);
9602 tw32(MAC_HASH_REG_0, mc_filter[0]);
9603 tw32(MAC_HASH_REG_1, mc_filter[1]);
9604 tw32(MAC_HASH_REG_2, mc_filter[2]);
9605 tw32(MAC_HASH_REG_3, mc_filter[3]);
9608 if (rx_mode != tp->rx_mode) {
9609 tp->rx_mode = rx_mode;
9610 tw32_f(MAC_RX_MODE, rx_mode);
9615 static void tg3_set_rx_mode(struct net_device *dev)
9617 struct tg3 *tp = netdev_priv(dev);
9619 if (!netif_running(dev))
9622 tg3_full_lock(tp, 0);
9623 __tg3_set_rx_mode(dev);
9624 tg3_full_unlock(tp);
9627 #define TG3_REGDUMP_LEN (32 * 1024)
9629 static int tg3_get_regs_len(struct net_device *dev)
9631 return TG3_REGDUMP_LEN;
9634 static void tg3_get_regs(struct net_device *dev,
9635 struct ethtool_regs *regs, void *_p)
9638 struct tg3 *tp = netdev_priv(dev);
9644 memset(p, 0, TG3_REGDUMP_LEN);
9646 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9649 tg3_full_lock(tp, 0);
9651 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9652 #define GET_REG32_LOOP(base, len) \
9653 do { p = (u32 *)(orig_p + (base)); \
9654 for (i = 0; i < len; i += 4) \
9655 __GET_REG32((base) + i); \
9657 #define GET_REG32_1(reg) \
9658 do { p = (u32 *)(orig_p + (reg)); \
9659 __GET_REG32((reg)); \
9662 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9663 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9664 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9665 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9666 GET_REG32_1(SNDDATAC_MODE);
9667 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9668 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9669 GET_REG32_1(SNDBDC_MODE);
9670 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9671 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9672 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9673 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9674 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9675 GET_REG32_1(RCVDCC_MODE);
9676 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9677 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9678 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9679 GET_REG32_1(MBFREE_MODE);
9680 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9681 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9682 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9683 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9684 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9685 GET_REG32_1(RX_CPU_MODE);
9686 GET_REG32_1(RX_CPU_STATE);
9687 GET_REG32_1(RX_CPU_PGMCTR);
9688 GET_REG32_1(RX_CPU_HWBKPT);
9689 GET_REG32_1(TX_CPU_MODE);
9690 GET_REG32_1(TX_CPU_STATE);
9691 GET_REG32_1(TX_CPU_PGMCTR);
9692 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9693 GET_REG32_LOOP(FTQ_RESET, 0x120);
9694 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9695 GET_REG32_1(DMAC_MODE);
9696 GET_REG32_LOOP(GRC_MODE, 0x4c);
9697 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9698 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9701 #undef GET_REG32_LOOP
9704 tg3_full_unlock(tp);
9707 static int tg3_get_eeprom_len(struct net_device *dev)
9709 struct tg3 *tp = netdev_priv(dev);
9711 return tp->nvram_size;
9714 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9716 struct tg3 *tp = netdev_priv(dev);
9719 u32 i, offset, len, b_offset, b_count;
9722 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9725 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9728 offset = eeprom->offset;
9732 eeprom->magic = TG3_EEPROM_MAGIC;
9735 /* adjustments to start on required 4 byte boundary */
9736 b_offset = offset & 3;
9737 b_count = 4 - b_offset;
9738 if (b_count > len) {
9739 /* i.e. offset=1 len=2 */
9742 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9745 memcpy(data, ((char *)&val) + b_offset, b_count);
9748 eeprom->len += b_count;
9751 /* read bytes upto the last 4 byte boundary */
9752 pd = &data[eeprom->len];
9753 for (i = 0; i < (len - (len & 3)); i += 4) {
9754 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9759 memcpy(pd + i, &val, 4);
9764 /* read last bytes not ending on 4 byte boundary */
9765 pd = &data[eeprom->len];
9767 b_offset = offset + len - b_count;
9768 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9771 memcpy(pd, &val, b_count);
9772 eeprom->len += b_count;
9777 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9779 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9781 struct tg3 *tp = netdev_priv(dev);
9783 u32 offset, len, b_offset, odd_len;
9787 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9790 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9791 eeprom->magic != TG3_EEPROM_MAGIC)
9794 offset = eeprom->offset;
9797 if ((b_offset = (offset & 3))) {
9798 /* adjustments to start on required 4 byte boundary */
9799 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9810 /* adjustments to end on required 4 byte boundary */
9812 len = (len + 3) & ~3;
9813 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9819 if (b_offset || odd_len) {
9820 buf = kmalloc(len, GFP_KERNEL);
9824 memcpy(buf, &start, 4);
9826 memcpy(buf+len-4, &end, 4);
9827 memcpy(buf + b_offset, data, eeprom->len);
9830 ret = tg3_nvram_write_block(tp, offset, len, buf);
9838 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9840 struct tg3 *tp = netdev_priv(dev);
9842 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9843 struct phy_device *phydev;
9844 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9846 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9847 return phy_ethtool_gset(phydev, cmd);
9850 cmd->supported = (SUPPORTED_Autoneg);
9852 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9853 cmd->supported |= (SUPPORTED_1000baseT_Half |
9854 SUPPORTED_1000baseT_Full);
9856 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9857 cmd->supported |= (SUPPORTED_100baseT_Half |
9858 SUPPORTED_100baseT_Full |
9859 SUPPORTED_10baseT_Half |
9860 SUPPORTED_10baseT_Full |
9862 cmd->port = PORT_TP;
9864 cmd->supported |= SUPPORTED_FIBRE;
9865 cmd->port = PORT_FIBRE;
9868 cmd->advertising = tp->link_config.advertising;
9869 if (netif_running(dev)) {
9870 cmd->speed = tp->link_config.active_speed;
9871 cmd->duplex = tp->link_config.active_duplex;
9873 cmd->speed = SPEED_INVALID;
9874 cmd->duplex = DUPLEX_INVALID;
9876 cmd->phy_address = tp->phy_addr;
9877 cmd->transceiver = XCVR_INTERNAL;
9878 cmd->autoneg = tp->link_config.autoneg;
9884 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9886 struct tg3 *tp = netdev_priv(dev);
9888 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9889 struct phy_device *phydev;
9890 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9892 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9893 return phy_ethtool_sset(phydev, cmd);
9896 if (cmd->autoneg != AUTONEG_ENABLE &&
9897 cmd->autoneg != AUTONEG_DISABLE)
9900 if (cmd->autoneg == AUTONEG_DISABLE &&
9901 cmd->duplex != DUPLEX_FULL &&
9902 cmd->duplex != DUPLEX_HALF)
9905 if (cmd->autoneg == AUTONEG_ENABLE) {
9906 u32 mask = ADVERTISED_Autoneg |
9908 ADVERTISED_Asym_Pause;
9910 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9911 mask |= ADVERTISED_1000baseT_Half |
9912 ADVERTISED_1000baseT_Full;
9914 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9915 mask |= ADVERTISED_100baseT_Half |
9916 ADVERTISED_100baseT_Full |
9917 ADVERTISED_10baseT_Half |
9918 ADVERTISED_10baseT_Full |
9921 mask |= ADVERTISED_FIBRE;
9923 if (cmd->advertising & ~mask)
9926 mask &= (ADVERTISED_1000baseT_Half |
9927 ADVERTISED_1000baseT_Full |
9928 ADVERTISED_100baseT_Half |
9929 ADVERTISED_100baseT_Full |
9930 ADVERTISED_10baseT_Half |
9931 ADVERTISED_10baseT_Full);
9933 cmd->advertising &= mask;
9935 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9936 if (cmd->speed != SPEED_1000)
9939 if (cmd->duplex != DUPLEX_FULL)
9942 if (cmd->speed != SPEED_100 &&
9943 cmd->speed != SPEED_10)
9948 tg3_full_lock(tp, 0);
9950 tp->link_config.autoneg = cmd->autoneg;
9951 if (cmd->autoneg == AUTONEG_ENABLE) {
9952 tp->link_config.advertising = (cmd->advertising |
9953 ADVERTISED_Autoneg);
9954 tp->link_config.speed = SPEED_INVALID;
9955 tp->link_config.duplex = DUPLEX_INVALID;
9957 tp->link_config.advertising = 0;
9958 tp->link_config.speed = cmd->speed;
9959 tp->link_config.duplex = cmd->duplex;
9962 tp->link_config.orig_speed = tp->link_config.speed;
9963 tp->link_config.orig_duplex = tp->link_config.duplex;
9964 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9966 if (netif_running(dev))
9967 tg3_setup_phy(tp, 1);
9969 tg3_full_unlock(tp);
9974 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9976 struct tg3 *tp = netdev_priv(dev);
9978 strcpy(info->driver, DRV_MODULE_NAME);
9979 strcpy(info->version, DRV_MODULE_VERSION);
9980 strcpy(info->fw_version, tp->fw_ver);
9981 strcpy(info->bus_info, pci_name(tp->pdev));
9984 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9986 struct tg3 *tp = netdev_priv(dev);
9988 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9989 device_can_wakeup(&tp->pdev->dev))
9990 wol->supported = WAKE_MAGIC;
9994 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9995 device_can_wakeup(&tp->pdev->dev))
9996 wol->wolopts = WAKE_MAGIC;
9997 memset(&wol->sopass, 0, sizeof(wol->sopass));
10000 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10002 struct tg3 *tp = netdev_priv(dev);
10003 struct device *dp = &tp->pdev->dev;
10005 if (wol->wolopts & ~WAKE_MAGIC)
10007 if ((wol->wolopts & WAKE_MAGIC) &&
10008 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
10011 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10013 spin_lock_bh(&tp->lock);
10014 if (device_may_wakeup(dp))
10015 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10017 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10018 spin_unlock_bh(&tp->lock);
10024 static u32 tg3_get_msglevel(struct net_device *dev)
10026 struct tg3 *tp = netdev_priv(dev);
10027 return tp->msg_enable;
10030 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10032 struct tg3 *tp = netdev_priv(dev);
10033 tp->msg_enable = value;
10036 static int tg3_nway_reset(struct net_device *dev)
10038 struct tg3 *tp = netdev_priv(dev);
10041 if (!netif_running(dev))
10044 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10047 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10048 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10050 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10054 spin_lock_bh(&tp->lock);
10056 tg3_readphy(tp, MII_BMCR, &bmcr);
10057 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10058 ((bmcr & BMCR_ANENABLE) ||
10059 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10060 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10064 spin_unlock_bh(&tp->lock);
10070 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10072 struct tg3 *tp = netdev_priv(dev);
10074 ering->rx_max_pending = tp->rx_std_ring_mask;
10075 ering->rx_mini_max_pending = 0;
10076 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10077 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10079 ering->rx_jumbo_max_pending = 0;
10081 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10083 ering->rx_pending = tp->rx_pending;
10084 ering->rx_mini_pending = 0;
10085 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10086 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10088 ering->rx_jumbo_pending = 0;
10090 ering->tx_pending = tp->napi[0].tx_pending;
10093 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10095 struct tg3 *tp = netdev_priv(dev);
10096 int i, irq_sync = 0, err = 0;
10098 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10099 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10100 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10101 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10102 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10103 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10106 if (netif_running(dev)) {
10108 tg3_netif_stop(tp);
10112 tg3_full_lock(tp, irq_sync);
10114 tp->rx_pending = ering->rx_pending;
10116 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10117 tp->rx_pending > 63)
10118 tp->rx_pending = 63;
10119 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10121 for (i = 0; i < tp->irq_max; i++)
10122 tp->napi[i].tx_pending = ering->tx_pending;
10124 if (netif_running(dev)) {
10125 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10126 err = tg3_restart_hw(tp, 1);
10128 tg3_netif_start(tp);
10131 tg3_full_unlock(tp);
10133 if (irq_sync && !err)
10139 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10141 struct tg3 *tp = netdev_priv(dev);
10143 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10145 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10146 epause->rx_pause = 1;
10148 epause->rx_pause = 0;
10150 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10151 epause->tx_pause = 1;
10153 epause->tx_pause = 0;
10156 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10158 struct tg3 *tp = netdev_priv(dev);
10161 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10163 struct phy_device *phydev;
10165 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10167 if (!(phydev->supported & SUPPORTED_Pause) ||
10168 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10169 (epause->rx_pause != epause->tx_pause)))
10172 tp->link_config.flowctrl = 0;
10173 if (epause->rx_pause) {
10174 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10176 if (epause->tx_pause) {
10177 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10178 newadv = ADVERTISED_Pause;
10180 newadv = ADVERTISED_Pause |
10181 ADVERTISED_Asym_Pause;
10182 } else if (epause->tx_pause) {
10183 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10184 newadv = ADVERTISED_Asym_Pause;
10188 if (epause->autoneg)
10189 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10191 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10193 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10194 u32 oldadv = phydev->advertising &
10195 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10196 if (oldadv != newadv) {
10197 phydev->advertising &=
10198 ~(ADVERTISED_Pause |
10199 ADVERTISED_Asym_Pause);
10200 phydev->advertising |= newadv;
10201 if (phydev->autoneg) {
10203 * Always renegotiate the link to
10204 * inform our link partner of our
10205 * flow control settings, even if the
10206 * flow control is forced. Let
10207 * tg3_adjust_link() do the final
10208 * flow control setup.
10210 return phy_start_aneg(phydev);
10214 if (!epause->autoneg)
10215 tg3_setup_flow_control(tp, 0, 0);
10217 tp->link_config.orig_advertising &=
10218 ~(ADVERTISED_Pause |
10219 ADVERTISED_Asym_Pause);
10220 tp->link_config.orig_advertising |= newadv;
10225 if (netif_running(dev)) {
10226 tg3_netif_stop(tp);
10230 tg3_full_lock(tp, irq_sync);
10232 if (epause->autoneg)
10233 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10235 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10236 if (epause->rx_pause)
10237 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10239 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10240 if (epause->tx_pause)
10241 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10243 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10245 if (netif_running(dev)) {
10246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10247 err = tg3_restart_hw(tp, 1);
10249 tg3_netif_start(tp);
10252 tg3_full_unlock(tp);
10258 static int tg3_get_sset_count(struct net_device *dev, int sset)
10262 return TG3_NUM_TEST;
10264 return TG3_NUM_STATS;
10266 return -EOPNOTSUPP;
10270 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10272 switch (stringset) {
10274 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10277 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10280 WARN_ON(1); /* we need a WARN() */
10285 static int tg3_set_phys_id(struct net_device *dev,
10286 enum ethtool_phys_id_state state)
10288 struct tg3 *tp = netdev_priv(dev);
10290 if (!netif_running(tp->dev))
10294 case ETHTOOL_ID_ACTIVE:
10297 case ETHTOOL_ID_ON:
10298 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10299 LED_CTRL_1000MBPS_ON |
10300 LED_CTRL_100MBPS_ON |
10301 LED_CTRL_10MBPS_ON |
10302 LED_CTRL_TRAFFIC_OVERRIDE |
10303 LED_CTRL_TRAFFIC_BLINK |
10304 LED_CTRL_TRAFFIC_LED);
10307 case ETHTOOL_ID_OFF:
10308 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10309 LED_CTRL_TRAFFIC_OVERRIDE);
10312 case ETHTOOL_ID_INACTIVE:
10313 tw32(MAC_LED_CTRL, tp->led_ctrl);
10320 static void tg3_get_ethtool_stats(struct net_device *dev,
10321 struct ethtool_stats *estats, u64 *tmp_stats)
10323 struct tg3 *tp = netdev_priv(dev);
10324 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10327 #define NVRAM_TEST_SIZE 0x100
10328 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10329 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10330 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10331 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10332 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10334 static int tg3_test_nvram(struct tg3 *tp)
10338 int i, j, k, err = 0, size;
10340 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10343 if (tg3_nvram_read(tp, 0, &magic) != 0)
10346 if (magic == TG3_EEPROM_MAGIC)
10347 size = NVRAM_TEST_SIZE;
10348 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10349 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10350 TG3_EEPROM_SB_FORMAT_1) {
10351 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10352 case TG3_EEPROM_SB_REVISION_0:
10353 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10355 case TG3_EEPROM_SB_REVISION_2:
10356 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10358 case TG3_EEPROM_SB_REVISION_3:
10359 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10366 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10367 size = NVRAM_SELFBOOT_HW_SIZE;
10371 buf = kmalloc(size, GFP_KERNEL);
10376 for (i = 0, j = 0; i < size; i += 4, j++) {
10377 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10384 /* Selfboot format */
10385 magic = be32_to_cpu(buf[0]);
10386 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10387 TG3_EEPROM_MAGIC_FW) {
10388 u8 *buf8 = (u8 *) buf, csum8 = 0;
10390 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10391 TG3_EEPROM_SB_REVISION_2) {
10392 /* For rev 2, the csum doesn't include the MBA. */
10393 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10395 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10398 for (i = 0; i < size; i++)
10411 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10412 TG3_EEPROM_MAGIC_HW) {
10413 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10414 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10415 u8 *buf8 = (u8 *) buf;
10417 /* Separate the parity bits and the data bytes. */
10418 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10419 if ((i == 0) || (i == 8)) {
10423 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10424 parity[k++] = buf8[i] & msk;
10426 } else if (i == 16) {
10430 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10431 parity[k++] = buf8[i] & msk;
10434 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10435 parity[k++] = buf8[i] & msk;
10438 data[j++] = buf8[i];
10442 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10443 u8 hw8 = hweight8(data[i]);
10445 if ((hw8 & 0x1) && parity[i])
10447 else if (!(hw8 & 0x1) && !parity[i])
10456 /* Bootstrap checksum at offset 0x10 */
10457 csum = calc_crc((unsigned char *) buf, 0x10);
10458 if (csum != le32_to_cpu(buf[0x10/4]))
10461 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10462 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10463 if (csum != le32_to_cpu(buf[0xfc/4]))
10466 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
10467 /* The data is in little-endian format in NVRAM.
10468 * Use the big-endian read routines to preserve
10469 * the byte order as it exists in NVRAM.
10471 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
10475 i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10476 PCI_VPD_LRDT_RO_DATA);
10478 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10482 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10485 i += PCI_VPD_LRDT_TAG_SIZE;
10486 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10487 PCI_VPD_RO_KEYWORD_CHKSUM);
10491 j += PCI_VPD_INFO_FLD_HDR_SIZE;
10493 for (i = 0; i <= j; i++)
10494 csum8 += ((u8 *)buf)[i];
10508 #define TG3_SERDES_TIMEOUT_SEC 2
10509 #define TG3_COPPER_TIMEOUT_SEC 6
10511 static int tg3_test_link(struct tg3 *tp)
10515 if (!netif_running(tp->dev))
10518 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10519 max = TG3_SERDES_TIMEOUT_SEC;
10521 max = TG3_COPPER_TIMEOUT_SEC;
10523 for (i = 0; i < max; i++) {
10524 if (netif_carrier_ok(tp->dev))
10527 if (msleep_interruptible(1000))
10534 /* Only test the commonly used registers */
10535 static int tg3_test_registers(struct tg3 *tp)
10537 int i, is_5705, is_5750;
10538 u32 offset, read_mask, write_mask, val, save_val, read_val;
10542 #define TG3_FL_5705 0x1
10543 #define TG3_FL_NOT_5705 0x2
10544 #define TG3_FL_NOT_5788 0x4
10545 #define TG3_FL_NOT_5750 0x8
10549 /* MAC Control Registers */
10550 { MAC_MODE, TG3_FL_NOT_5705,
10551 0x00000000, 0x00ef6f8c },
10552 { MAC_MODE, TG3_FL_5705,
10553 0x00000000, 0x01ef6b8c },
10554 { MAC_STATUS, TG3_FL_NOT_5705,
10555 0x03800107, 0x00000000 },
10556 { MAC_STATUS, TG3_FL_5705,
10557 0x03800100, 0x00000000 },
10558 { MAC_ADDR_0_HIGH, 0x0000,
10559 0x00000000, 0x0000ffff },
10560 { MAC_ADDR_0_LOW, 0x0000,
10561 0x00000000, 0xffffffff },
10562 { MAC_RX_MTU_SIZE, 0x0000,
10563 0x00000000, 0x0000ffff },
10564 { MAC_TX_MODE, 0x0000,
10565 0x00000000, 0x00000070 },
10566 { MAC_TX_LENGTHS, 0x0000,
10567 0x00000000, 0x00003fff },
10568 { MAC_RX_MODE, TG3_FL_NOT_5705,
10569 0x00000000, 0x000007fc },
10570 { MAC_RX_MODE, TG3_FL_5705,
10571 0x00000000, 0x000007dc },
10572 { MAC_HASH_REG_0, 0x0000,
10573 0x00000000, 0xffffffff },
10574 { MAC_HASH_REG_1, 0x0000,
10575 0x00000000, 0xffffffff },
10576 { MAC_HASH_REG_2, 0x0000,
10577 0x00000000, 0xffffffff },
10578 { MAC_HASH_REG_3, 0x0000,
10579 0x00000000, 0xffffffff },
10581 /* Receive Data and Receive BD Initiator Control Registers. */
10582 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10583 0x00000000, 0xffffffff },
10584 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10585 0x00000000, 0xffffffff },
10586 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10587 0x00000000, 0x00000003 },
10588 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10589 0x00000000, 0xffffffff },
10590 { RCVDBDI_STD_BD+0, 0x0000,
10591 0x00000000, 0xffffffff },
10592 { RCVDBDI_STD_BD+4, 0x0000,
10593 0x00000000, 0xffffffff },
10594 { RCVDBDI_STD_BD+8, 0x0000,
10595 0x00000000, 0xffff0002 },
10596 { RCVDBDI_STD_BD+0xc, 0x0000,
10597 0x00000000, 0xffffffff },
10599 /* Receive BD Initiator Control Registers. */
10600 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10601 0x00000000, 0xffffffff },
10602 { RCVBDI_STD_THRESH, TG3_FL_5705,
10603 0x00000000, 0x000003ff },
10604 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10605 0x00000000, 0xffffffff },
10607 /* Host Coalescing Control Registers. */
10608 { HOSTCC_MODE, TG3_FL_NOT_5705,
10609 0x00000000, 0x00000004 },
10610 { HOSTCC_MODE, TG3_FL_5705,
10611 0x00000000, 0x000000f6 },
10612 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10613 0x00000000, 0xffffffff },
10614 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10615 0x00000000, 0x000003ff },
10616 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10617 0x00000000, 0xffffffff },
10618 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10619 0x00000000, 0x000003ff },
10620 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10621 0x00000000, 0xffffffff },
10622 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10623 0x00000000, 0x000000ff },
10624 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10625 0x00000000, 0xffffffff },
10626 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10627 0x00000000, 0x000000ff },
10628 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10629 0x00000000, 0xffffffff },
10630 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10631 0x00000000, 0xffffffff },
10632 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10633 0x00000000, 0xffffffff },
10634 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10635 0x00000000, 0x000000ff },
10636 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10637 0x00000000, 0xffffffff },
10638 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10639 0x00000000, 0x000000ff },
10640 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10641 0x00000000, 0xffffffff },
10642 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10643 0x00000000, 0xffffffff },
10644 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10645 0x00000000, 0xffffffff },
10646 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10647 0x00000000, 0xffffffff },
10648 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10649 0x00000000, 0xffffffff },
10650 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10651 0xffffffff, 0x00000000 },
10652 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10653 0xffffffff, 0x00000000 },
10655 /* Buffer Manager Control Registers. */
10656 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10657 0x00000000, 0x007fff80 },
10658 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10659 0x00000000, 0x007fffff },
10660 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10661 0x00000000, 0x0000003f },
10662 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10663 0x00000000, 0x000001ff },
10664 { BUFMGR_MB_HIGH_WATER, 0x0000,
10665 0x00000000, 0x000001ff },
10666 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10667 0xffffffff, 0x00000000 },
10668 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10669 0xffffffff, 0x00000000 },
10671 /* Mailbox Registers */
10672 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10673 0x00000000, 0x000001ff },
10674 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10675 0x00000000, 0x000001ff },
10676 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10677 0x00000000, 0x000007ff },
10678 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10679 0x00000000, 0x000001ff },
10681 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10684 is_5705 = is_5750 = 0;
10685 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10687 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10691 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10692 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10695 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10698 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10699 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10702 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10705 offset = (u32) reg_tbl[i].offset;
10706 read_mask = reg_tbl[i].read_mask;
10707 write_mask = reg_tbl[i].write_mask;
10709 /* Save the original register content */
10710 save_val = tr32(offset);
10712 /* Determine the read-only value. */
10713 read_val = save_val & read_mask;
10715 /* Write zero to the register, then make sure the read-only bits
10716 * are not changed and the read/write bits are all zeros.
10720 val = tr32(offset);
10722 /* Test the read-only and read/write bits. */
10723 if (((val & read_mask) != read_val) || (val & write_mask))
10726 /* Write ones to all the bits defined by RdMask and WrMask, then
10727 * make sure the read-only bits are not changed and the
10728 * read/write bits are all ones.
10730 tw32(offset, read_mask | write_mask);
10732 val = tr32(offset);
10734 /* Test the read-only bits. */
10735 if ((val & read_mask) != read_val)
10738 /* Test the read/write bits. */
10739 if ((val & write_mask) != write_mask)
10742 tw32(offset, save_val);
10748 if (netif_msg_hw(tp))
10749 netdev_err(tp->dev,
10750 "Register test failed at offset %x\n", offset);
10751 tw32(offset, save_val);
10755 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10757 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10761 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10762 for (j = 0; j < len; j += 4) {
10765 tg3_write_mem(tp, offset + j, test_pattern[i]);
10766 tg3_read_mem(tp, offset + j, &val);
10767 if (val != test_pattern[i])
10774 static int tg3_test_memory(struct tg3 *tp)
10776 static struct mem_entry {
10779 } mem_tbl_570x[] = {
10780 { 0x00000000, 0x00b50},
10781 { 0x00002000, 0x1c000},
10782 { 0xffffffff, 0x00000}
10783 }, mem_tbl_5705[] = {
10784 { 0x00000100, 0x0000c},
10785 { 0x00000200, 0x00008},
10786 { 0x00004000, 0x00800},
10787 { 0x00006000, 0x01000},
10788 { 0x00008000, 0x02000},
10789 { 0x00010000, 0x0e000},
10790 { 0xffffffff, 0x00000}
10791 }, mem_tbl_5755[] = {
10792 { 0x00000200, 0x00008},
10793 { 0x00004000, 0x00800},
10794 { 0x00006000, 0x00800},
10795 { 0x00008000, 0x02000},
10796 { 0x00010000, 0x0c000},
10797 { 0xffffffff, 0x00000}
10798 }, mem_tbl_5906[] = {
10799 { 0x00000200, 0x00008},
10800 { 0x00004000, 0x00400},
10801 { 0x00006000, 0x00400},
10802 { 0x00008000, 0x01000},
10803 { 0x00010000, 0x01000},
10804 { 0xffffffff, 0x00000}
10805 }, mem_tbl_5717[] = {
10806 { 0x00000200, 0x00008},
10807 { 0x00010000, 0x0a000},
10808 { 0x00020000, 0x13c00},
10809 { 0xffffffff, 0x00000}
10810 }, mem_tbl_57765[] = {
10811 { 0x00000200, 0x00008},
10812 { 0x00004000, 0x00800},
10813 { 0x00006000, 0x09800},
10814 { 0x00010000, 0x0a000},
10815 { 0xffffffff, 0x00000}
10817 struct mem_entry *mem_tbl;
10821 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
10822 mem_tbl = mem_tbl_5717;
10823 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10824 mem_tbl = mem_tbl_57765;
10825 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10826 mem_tbl = mem_tbl_5755;
10827 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10828 mem_tbl = mem_tbl_5906;
10829 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10830 mem_tbl = mem_tbl_5705;
10832 mem_tbl = mem_tbl_570x;
10834 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10835 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10843 #define TG3_MAC_LOOPBACK 0
10844 #define TG3_PHY_LOOPBACK 1
10846 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10848 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10849 u32 desc_idx, coal_now;
10850 struct sk_buff *skb, *rx_skb;
10853 int num_pkts, tx_len, rx_len, i, err;
10854 struct tg3_rx_buffer_desc *desc;
10855 struct tg3_napi *tnapi, *rnapi;
10856 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10858 tnapi = &tp->napi[0];
10859 rnapi = &tp->napi[0];
10860 if (tp->irq_cnt > 1) {
10861 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10862 rnapi = &tp->napi[1];
10863 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10864 tnapi = &tp->napi[1];
10866 coal_now = tnapi->coal_now | rnapi->coal_now;
10868 if (loopback_mode == TG3_MAC_LOOPBACK) {
10869 /* HW errata - mac loopback fails in some cases on 5780.
10870 * Normal traffic and PHY loopback are not affected by
10871 * errata. Also, the MAC loopback test is deprecated for
10872 * all newer ASIC revisions.
10874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10875 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
10878 mac_mode = tp->mac_mode &
10879 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10880 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
10881 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10882 mac_mode |= MAC_MODE_LINK_POLARITY;
10883 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10884 mac_mode |= MAC_MODE_PORT_MODE_MII;
10886 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10887 tw32(MAC_MODE, mac_mode);
10888 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10891 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10892 tg3_phy_fet_toggle_apd(tp, false);
10893 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10895 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10897 tg3_phy_toggle_automdix(tp, 0);
10899 tg3_writephy(tp, MII_BMCR, val);
10902 mac_mode = tp->mac_mode &
10903 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10904 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10905 tg3_writephy(tp, MII_TG3_FET_PTEST,
10906 MII_TG3_FET_PTEST_FRC_TX_LINK |
10907 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10908 /* The write needs to be flushed for the AC131 */
10909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10910 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10911 mac_mode |= MAC_MODE_PORT_MODE_MII;
10913 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10915 /* reset to prevent losing 1st rx packet intermittently */
10916 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10917 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10919 tw32_f(MAC_RX_MODE, tp->rx_mode);
10921 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10922 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10923 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10924 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10925 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10926 mac_mode |= MAC_MODE_LINK_POLARITY;
10927 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10928 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10930 tw32(MAC_MODE, mac_mode);
10932 /* Wait for link */
10933 for (i = 0; i < 100; i++) {
10934 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
10945 skb = netdev_alloc_skb(tp->dev, tx_len);
10949 tx_data = skb_put(skb, tx_len);
10950 memcpy(tx_data, tp->dev->dev_addr, 6);
10951 memset(tx_data + 6, 0x0, 8);
10953 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10955 for (i = 14; i < tx_len; i++)
10956 tx_data[i] = (u8) (i & 0xff);
10958 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10959 if (pci_dma_mapping_error(tp->pdev, map)) {
10960 dev_kfree_skb(skb);
10964 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10969 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10973 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10978 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10979 tr32_mailbox(tnapi->prodmbox);
10983 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10984 for (i = 0; i < 35; i++) {
10985 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10990 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10991 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10992 if ((tx_idx == tnapi->tx_prod) &&
10993 (rx_idx == (rx_start_idx + num_pkts)))
10997 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10998 dev_kfree_skb(skb);
11000 if (tx_idx != tnapi->tx_prod)
11003 if (rx_idx != rx_start_idx + num_pkts)
11006 desc = &rnapi->rx_rcb[rx_start_idx];
11007 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11008 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11009 if (opaque_key != RXD_OPAQUE_RING_STD)
11012 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11013 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11016 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11017 if (rx_len != tx_len)
11020 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11022 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11023 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11025 for (i = 14; i < tx_len; i++) {
11026 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11031 /* tg3_free_rings will unmap and free the rx_skb */
11036 #define TG3_MAC_LOOPBACK_FAILED 1
11037 #define TG3_PHY_LOOPBACK_FAILED 2
11038 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11039 TG3_PHY_LOOPBACK_FAILED)
11041 static int tg3_test_loopback(struct tg3 *tp)
11044 u32 eee_cap, cpmuctrl = 0;
11046 if (!netif_running(tp->dev))
11047 return TG3_LOOPBACK_FAILED;
11049 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11050 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11052 err = tg3_reset_hw(tp, 1);
11054 err = TG3_LOOPBACK_FAILED;
11058 /* Turn off gphy autopowerdown. */
11059 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11060 tg3_phy_toggle_apd(tp, false);
11062 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11066 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11068 /* Wait for up to 40 microseconds to acquire lock. */
11069 for (i = 0; i < 4; i++) {
11070 status = tr32(TG3_CPMU_MUTEX_GNT);
11071 if (status == CPMU_MUTEX_GNT_DRIVER)
11076 if (status != CPMU_MUTEX_GNT_DRIVER) {
11077 err = TG3_LOOPBACK_FAILED;
11081 /* Turn off link-based power management. */
11082 cpmuctrl = tr32(TG3_CPMU_CTRL);
11083 tw32(TG3_CPMU_CTRL,
11084 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11085 CPMU_CTRL_LINK_AWARE_MODE));
11088 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11089 err |= TG3_MAC_LOOPBACK_FAILED;
11091 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11092 tw32(TG3_CPMU_CTRL, cpmuctrl);
11094 /* Release the mutex */
11095 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11098 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11099 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11100 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11101 err |= TG3_PHY_LOOPBACK_FAILED;
11104 /* Re-enable gphy autopowerdown. */
11105 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11106 tg3_phy_toggle_apd(tp, true);
11109 tp->phy_flags |= eee_cap;
11114 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11117 struct tg3 *tp = netdev_priv(dev);
11119 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11122 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11124 if (tg3_test_nvram(tp) != 0) {
11125 etest->flags |= ETH_TEST_FL_FAILED;
11128 if (tg3_test_link(tp) != 0) {
11129 etest->flags |= ETH_TEST_FL_FAILED;
11132 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11133 int err, err2 = 0, irq_sync = 0;
11135 if (netif_running(dev)) {
11137 tg3_netif_stop(tp);
11141 tg3_full_lock(tp, irq_sync);
11143 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11144 err = tg3_nvram_lock(tp);
11145 tg3_halt_cpu(tp, RX_CPU_BASE);
11146 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11147 tg3_halt_cpu(tp, TX_CPU_BASE);
11149 tg3_nvram_unlock(tp);
11151 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11154 if (tg3_test_registers(tp) != 0) {
11155 etest->flags |= ETH_TEST_FL_FAILED;
11158 if (tg3_test_memory(tp) != 0) {
11159 etest->flags |= ETH_TEST_FL_FAILED;
11162 if ((data[4] = tg3_test_loopback(tp)) != 0)
11163 etest->flags |= ETH_TEST_FL_FAILED;
11165 tg3_full_unlock(tp);
11167 if (tg3_test_interrupt(tp) != 0) {
11168 etest->flags |= ETH_TEST_FL_FAILED;
11172 tg3_full_lock(tp, 0);
11174 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11175 if (netif_running(dev)) {
11176 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11177 err2 = tg3_restart_hw(tp, 1);
11179 tg3_netif_start(tp);
11182 tg3_full_unlock(tp);
11184 if (irq_sync && !err2)
11187 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11188 tg3_power_down(tp);
11192 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11194 struct mii_ioctl_data *data = if_mii(ifr);
11195 struct tg3 *tp = netdev_priv(dev);
11198 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11199 struct phy_device *phydev;
11200 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11202 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11203 return phy_mii_ioctl(phydev, ifr, cmd);
11208 data->phy_id = tp->phy_addr;
11211 case SIOCGMIIREG: {
11214 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11215 break; /* We have no PHY */
11217 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11218 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11219 !netif_running(dev)))
11222 spin_lock_bh(&tp->lock);
11223 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11224 spin_unlock_bh(&tp->lock);
11226 data->val_out = mii_regval;
11232 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11233 break; /* We have no PHY */
11235 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11236 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11237 !netif_running(dev)))
11240 spin_lock_bh(&tp->lock);
11241 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11242 spin_unlock_bh(&tp->lock);
11250 return -EOPNOTSUPP;
11253 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11255 struct tg3 *tp = netdev_priv(dev);
11257 memcpy(ec, &tp->coal, sizeof(*ec));
11261 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11263 struct tg3 *tp = netdev_priv(dev);
11264 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11265 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11267 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11268 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11269 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11270 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11271 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11274 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11275 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11276 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11277 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11278 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11279 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11280 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11281 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11282 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11283 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11286 /* No rx interrupts will be generated if both are zero */
11287 if ((ec->rx_coalesce_usecs == 0) &&
11288 (ec->rx_max_coalesced_frames == 0))
11291 /* No tx interrupts will be generated if both are zero */
11292 if ((ec->tx_coalesce_usecs == 0) &&
11293 (ec->tx_max_coalesced_frames == 0))
11296 /* Only copy relevant parameters, ignore all others. */
11297 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11298 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11299 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11300 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11301 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11302 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11303 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11304 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11305 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11307 if (netif_running(dev)) {
11308 tg3_full_lock(tp, 0);
11309 __tg3_set_coalesce(tp, &tp->coal);
11310 tg3_full_unlock(tp);
11315 static const struct ethtool_ops tg3_ethtool_ops = {
11316 .get_settings = tg3_get_settings,
11317 .set_settings = tg3_set_settings,
11318 .get_drvinfo = tg3_get_drvinfo,
11319 .get_regs_len = tg3_get_regs_len,
11320 .get_regs = tg3_get_regs,
11321 .get_wol = tg3_get_wol,
11322 .set_wol = tg3_set_wol,
11323 .get_msglevel = tg3_get_msglevel,
11324 .set_msglevel = tg3_set_msglevel,
11325 .nway_reset = tg3_nway_reset,
11326 .get_link = ethtool_op_get_link,
11327 .get_eeprom_len = tg3_get_eeprom_len,
11328 .get_eeprom = tg3_get_eeprom,
11329 .set_eeprom = tg3_set_eeprom,
11330 .get_ringparam = tg3_get_ringparam,
11331 .set_ringparam = tg3_set_ringparam,
11332 .get_pauseparam = tg3_get_pauseparam,
11333 .set_pauseparam = tg3_set_pauseparam,
11334 .self_test = tg3_self_test,
11335 .get_strings = tg3_get_strings,
11336 .set_phys_id = tg3_set_phys_id,
11337 .get_ethtool_stats = tg3_get_ethtool_stats,
11338 .get_coalesce = tg3_get_coalesce,
11339 .set_coalesce = tg3_set_coalesce,
11340 .get_sset_count = tg3_get_sset_count,
11343 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11345 u32 cursize, val, magic;
11347 tp->nvram_size = EEPROM_CHIP_SIZE;
11349 if (tg3_nvram_read(tp, 0, &magic) != 0)
11352 if ((magic != TG3_EEPROM_MAGIC) &&
11353 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11354 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11358 * Size the chip by reading offsets at increasing powers of two.
11359 * When we encounter our validation signature, we know the addressing
11360 * has wrapped around, and thus have our chip size.
11364 while (cursize < tp->nvram_size) {
11365 if (tg3_nvram_read(tp, cursize, &val) != 0)
11374 tp->nvram_size = cursize;
11377 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11381 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11382 tg3_nvram_read(tp, 0, &val) != 0)
11385 /* Selfboot format */
11386 if (val != TG3_EEPROM_MAGIC) {
11387 tg3_get_eeprom_size(tp);
11391 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11393 /* This is confusing. We want to operate on the
11394 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11395 * call will read from NVRAM and byteswap the data
11396 * according to the byteswapping settings for all
11397 * other register accesses. This ensures the data we
11398 * want will always reside in the lower 16-bits.
11399 * However, the data in NVRAM is in LE format, which
11400 * means the data from the NVRAM read will always be
11401 * opposite the endianness of the CPU. The 16-bit
11402 * byteswap then brings the data to CPU endianness.
11404 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11408 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11411 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11415 nvcfg1 = tr32(NVRAM_CFG1);
11416 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11417 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11419 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11420 tw32(NVRAM_CFG1, nvcfg1);
11423 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11424 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11425 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11426 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11427 tp->nvram_jedecnum = JEDEC_ATMEL;
11428 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11429 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11431 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11432 tp->nvram_jedecnum = JEDEC_ATMEL;
11433 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11435 case FLASH_VENDOR_ATMEL_EEPROM:
11436 tp->nvram_jedecnum = JEDEC_ATMEL;
11437 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11438 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11440 case FLASH_VENDOR_ST:
11441 tp->nvram_jedecnum = JEDEC_ST;
11442 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11443 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11445 case FLASH_VENDOR_SAIFUN:
11446 tp->nvram_jedecnum = JEDEC_SAIFUN;
11447 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11449 case FLASH_VENDOR_SST_SMALL:
11450 case FLASH_VENDOR_SST_LARGE:
11451 tp->nvram_jedecnum = JEDEC_SST;
11452 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11456 tp->nvram_jedecnum = JEDEC_ATMEL;
11457 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11458 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11462 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11464 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11465 case FLASH_5752PAGE_SIZE_256:
11466 tp->nvram_pagesize = 256;
11468 case FLASH_5752PAGE_SIZE_512:
11469 tp->nvram_pagesize = 512;
11471 case FLASH_5752PAGE_SIZE_1K:
11472 tp->nvram_pagesize = 1024;
11474 case FLASH_5752PAGE_SIZE_2K:
11475 tp->nvram_pagesize = 2048;
11477 case FLASH_5752PAGE_SIZE_4K:
11478 tp->nvram_pagesize = 4096;
11480 case FLASH_5752PAGE_SIZE_264:
11481 tp->nvram_pagesize = 264;
11483 case FLASH_5752PAGE_SIZE_528:
11484 tp->nvram_pagesize = 528;
11489 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11493 nvcfg1 = tr32(NVRAM_CFG1);
11495 /* NVRAM protection for TPM */
11496 if (nvcfg1 & (1 << 27))
11497 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11499 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11500 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11501 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11502 tp->nvram_jedecnum = JEDEC_ATMEL;
11503 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11505 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11506 tp->nvram_jedecnum = JEDEC_ATMEL;
11507 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11508 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11510 case FLASH_5752VENDOR_ST_M45PE10:
11511 case FLASH_5752VENDOR_ST_M45PE20:
11512 case FLASH_5752VENDOR_ST_M45PE40:
11513 tp->nvram_jedecnum = JEDEC_ST;
11514 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11515 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11519 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11520 tg3_nvram_get_pagesize(tp, nvcfg1);
11522 /* For eeprom, set pagesize to maximum eeprom size */
11523 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11525 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11526 tw32(NVRAM_CFG1, nvcfg1);
11530 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11532 u32 nvcfg1, protect = 0;
11534 nvcfg1 = tr32(NVRAM_CFG1);
11536 /* NVRAM protection for TPM */
11537 if (nvcfg1 & (1 << 27)) {
11538 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11542 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11544 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11545 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11546 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11547 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11548 tp->nvram_jedecnum = JEDEC_ATMEL;
11549 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11550 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11551 tp->nvram_pagesize = 264;
11552 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11553 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11554 tp->nvram_size = (protect ? 0x3e200 :
11555 TG3_NVRAM_SIZE_512KB);
11556 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11557 tp->nvram_size = (protect ? 0x1f200 :
11558 TG3_NVRAM_SIZE_256KB);
11560 tp->nvram_size = (protect ? 0x1f200 :
11561 TG3_NVRAM_SIZE_128KB);
11563 case FLASH_5752VENDOR_ST_M45PE10:
11564 case FLASH_5752VENDOR_ST_M45PE20:
11565 case FLASH_5752VENDOR_ST_M45PE40:
11566 tp->nvram_jedecnum = JEDEC_ST;
11567 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11569 tp->nvram_pagesize = 256;
11570 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11571 tp->nvram_size = (protect ?
11572 TG3_NVRAM_SIZE_64KB :
11573 TG3_NVRAM_SIZE_128KB);
11574 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11575 tp->nvram_size = (protect ?
11576 TG3_NVRAM_SIZE_64KB :
11577 TG3_NVRAM_SIZE_256KB);
11579 tp->nvram_size = (protect ?
11580 TG3_NVRAM_SIZE_128KB :
11581 TG3_NVRAM_SIZE_512KB);
11586 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11590 nvcfg1 = tr32(NVRAM_CFG1);
11592 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11593 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11594 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11595 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11596 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11597 tp->nvram_jedecnum = JEDEC_ATMEL;
11598 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11599 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11601 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11602 tw32(NVRAM_CFG1, nvcfg1);
11604 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11605 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11606 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11607 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11608 tp->nvram_jedecnum = JEDEC_ATMEL;
11609 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11610 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11611 tp->nvram_pagesize = 264;
11613 case FLASH_5752VENDOR_ST_M45PE10:
11614 case FLASH_5752VENDOR_ST_M45PE20:
11615 case FLASH_5752VENDOR_ST_M45PE40:
11616 tp->nvram_jedecnum = JEDEC_ST;
11617 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11618 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11619 tp->nvram_pagesize = 256;
11624 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11626 u32 nvcfg1, protect = 0;
11628 nvcfg1 = tr32(NVRAM_CFG1);
11630 /* NVRAM protection for TPM */
11631 if (nvcfg1 & (1 << 27)) {
11632 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11636 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11638 case FLASH_5761VENDOR_ATMEL_ADB021D:
11639 case FLASH_5761VENDOR_ATMEL_ADB041D:
11640 case FLASH_5761VENDOR_ATMEL_ADB081D:
11641 case FLASH_5761VENDOR_ATMEL_ADB161D:
11642 case FLASH_5761VENDOR_ATMEL_MDB021D:
11643 case FLASH_5761VENDOR_ATMEL_MDB041D:
11644 case FLASH_5761VENDOR_ATMEL_MDB081D:
11645 case FLASH_5761VENDOR_ATMEL_MDB161D:
11646 tp->nvram_jedecnum = JEDEC_ATMEL;
11647 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11648 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11649 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11650 tp->nvram_pagesize = 256;
11652 case FLASH_5761VENDOR_ST_A_M45PE20:
11653 case FLASH_5761VENDOR_ST_A_M45PE40:
11654 case FLASH_5761VENDOR_ST_A_M45PE80:
11655 case FLASH_5761VENDOR_ST_A_M45PE16:
11656 case FLASH_5761VENDOR_ST_M_M45PE20:
11657 case FLASH_5761VENDOR_ST_M_M45PE40:
11658 case FLASH_5761VENDOR_ST_M_M45PE80:
11659 case FLASH_5761VENDOR_ST_M_M45PE16:
11660 tp->nvram_jedecnum = JEDEC_ST;
11661 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11662 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11663 tp->nvram_pagesize = 256;
11668 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11671 case FLASH_5761VENDOR_ATMEL_ADB161D:
11672 case FLASH_5761VENDOR_ATMEL_MDB161D:
11673 case FLASH_5761VENDOR_ST_A_M45PE16:
11674 case FLASH_5761VENDOR_ST_M_M45PE16:
11675 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11677 case FLASH_5761VENDOR_ATMEL_ADB081D:
11678 case FLASH_5761VENDOR_ATMEL_MDB081D:
11679 case FLASH_5761VENDOR_ST_A_M45PE80:
11680 case FLASH_5761VENDOR_ST_M_M45PE80:
11681 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11683 case FLASH_5761VENDOR_ATMEL_ADB041D:
11684 case FLASH_5761VENDOR_ATMEL_MDB041D:
11685 case FLASH_5761VENDOR_ST_A_M45PE40:
11686 case FLASH_5761VENDOR_ST_M_M45PE40:
11687 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11689 case FLASH_5761VENDOR_ATMEL_ADB021D:
11690 case FLASH_5761VENDOR_ATMEL_MDB021D:
11691 case FLASH_5761VENDOR_ST_A_M45PE20:
11692 case FLASH_5761VENDOR_ST_M_M45PE20:
11693 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11699 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11701 tp->nvram_jedecnum = JEDEC_ATMEL;
11702 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11703 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11706 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11710 nvcfg1 = tr32(NVRAM_CFG1);
11712 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11713 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11714 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11715 tp->nvram_jedecnum = JEDEC_ATMEL;
11716 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11717 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11719 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11720 tw32(NVRAM_CFG1, nvcfg1);
11722 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11723 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11724 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11725 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11726 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11727 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11728 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11729 tp->nvram_jedecnum = JEDEC_ATMEL;
11730 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11731 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11733 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11734 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11735 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11736 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11737 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11739 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11740 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11741 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11743 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11744 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11745 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11749 case FLASH_5752VENDOR_ST_M45PE10:
11750 case FLASH_5752VENDOR_ST_M45PE20:
11751 case FLASH_5752VENDOR_ST_M45PE40:
11752 tp->nvram_jedecnum = JEDEC_ST;
11753 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11754 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11756 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11757 case FLASH_5752VENDOR_ST_M45PE10:
11758 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11760 case FLASH_5752VENDOR_ST_M45PE20:
11761 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11763 case FLASH_5752VENDOR_ST_M45PE40:
11764 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11769 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11773 tg3_nvram_get_pagesize(tp, nvcfg1);
11774 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11775 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11779 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11783 nvcfg1 = tr32(NVRAM_CFG1);
11785 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11786 case FLASH_5717VENDOR_ATMEL_EEPROM:
11787 case FLASH_5717VENDOR_MICRO_EEPROM:
11788 tp->nvram_jedecnum = JEDEC_ATMEL;
11789 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11790 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11792 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11793 tw32(NVRAM_CFG1, nvcfg1);
11795 case FLASH_5717VENDOR_ATMEL_MDB011D:
11796 case FLASH_5717VENDOR_ATMEL_ADB011B:
11797 case FLASH_5717VENDOR_ATMEL_ADB011D:
11798 case FLASH_5717VENDOR_ATMEL_MDB021D:
11799 case FLASH_5717VENDOR_ATMEL_ADB021B:
11800 case FLASH_5717VENDOR_ATMEL_ADB021D:
11801 case FLASH_5717VENDOR_ATMEL_45USPT:
11802 tp->nvram_jedecnum = JEDEC_ATMEL;
11803 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11804 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11806 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11807 case FLASH_5717VENDOR_ATMEL_MDB021D:
11808 /* Detect size with tg3_nvram_get_size() */
11810 case FLASH_5717VENDOR_ATMEL_ADB021B:
11811 case FLASH_5717VENDOR_ATMEL_ADB021D:
11812 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11815 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11819 case FLASH_5717VENDOR_ST_M_M25PE10:
11820 case FLASH_5717VENDOR_ST_A_M25PE10:
11821 case FLASH_5717VENDOR_ST_M_M45PE10:
11822 case FLASH_5717VENDOR_ST_A_M45PE10:
11823 case FLASH_5717VENDOR_ST_M_M25PE20:
11824 case FLASH_5717VENDOR_ST_A_M25PE20:
11825 case FLASH_5717VENDOR_ST_M_M45PE20:
11826 case FLASH_5717VENDOR_ST_A_M45PE20:
11827 case FLASH_5717VENDOR_ST_25USPT:
11828 case FLASH_5717VENDOR_ST_45USPT:
11829 tp->nvram_jedecnum = JEDEC_ST;
11830 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11831 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11833 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11834 case FLASH_5717VENDOR_ST_M_M25PE20:
11835 case FLASH_5717VENDOR_ST_M_M45PE20:
11836 /* Detect size with tg3_nvram_get_size() */
11838 case FLASH_5717VENDOR_ST_A_M25PE20:
11839 case FLASH_5717VENDOR_ST_A_M45PE20:
11840 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11843 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11848 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11852 tg3_nvram_get_pagesize(tp, nvcfg1);
11853 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11854 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11857 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
11859 u32 nvcfg1, nvmpinstrp;
11861 nvcfg1 = tr32(NVRAM_CFG1);
11862 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
11864 switch (nvmpinstrp) {
11865 case FLASH_5720_EEPROM_HD:
11866 case FLASH_5720_EEPROM_LD:
11867 tp->nvram_jedecnum = JEDEC_ATMEL;
11868 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11870 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11871 tw32(NVRAM_CFG1, nvcfg1);
11872 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
11873 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11875 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
11877 case FLASH_5720VENDOR_M_ATMEL_DB011D:
11878 case FLASH_5720VENDOR_A_ATMEL_DB011B:
11879 case FLASH_5720VENDOR_A_ATMEL_DB011D:
11880 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11881 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11882 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11883 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11884 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11885 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11886 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11887 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11888 case FLASH_5720VENDOR_ATMEL_45USPT:
11889 tp->nvram_jedecnum = JEDEC_ATMEL;
11890 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11891 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11893 switch (nvmpinstrp) {
11894 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11895 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11896 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11897 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11899 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11900 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11901 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11902 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11904 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11905 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11906 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11909 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11913 case FLASH_5720VENDOR_M_ST_M25PE10:
11914 case FLASH_5720VENDOR_M_ST_M45PE10:
11915 case FLASH_5720VENDOR_A_ST_M25PE10:
11916 case FLASH_5720VENDOR_A_ST_M45PE10:
11917 case FLASH_5720VENDOR_M_ST_M25PE20:
11918 case FLASH_5720VENDOR_M_ST_M45PE20:
11919 case FLASH_5720VENDOR_A_ST_M25PE20:
11920 case FLASH_5720VENDOR_A_ST_M45PE20:
11921 case FLASH_5720VENDOR_M_ST_M25PE40:
11922 case FLASH_5720VENDOR_M_ST_M45PE40:
11923 case FLASH_5720VENDOR_A_ST_M25PE40:
11924 case FLASH_5720VENDOR_A_ST_M45PE40:
11925 case FLASH_5720VENDOR_M_ST_M25PE80:
11926 case FLASH_5720VENDOR_M_ST_M45PE80:
11927 case FLASH_5720VENDOR_A_ST_M25PE80:
11928 case FLASH_5720VENDOR_A_ST_M45PE80:
11929 case FLASH_5720VENDOR_ST_25USPT:
11930 case FLASH_5720VENDOR_ST_45USPT:
11931 tp->nvram_jedecnum = JEDEC_ST;
11932 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11933 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11935 switch (nvmpinstrp) {
11936 case FLASH_5720VENDOR_M_ST_M25PE20:
11937 case FLASH_5720VENDOR_M_ST_M45PE20:
11938 case FLASH_5720VENDOR_A_ST_M25PE20:
11939 case FLASH_5720VENDOR_A_ST_M45PE20:
11940 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11942 case FLASH_5720VENDOR_M_ST_M25PE40:
11943 case FLASH_5720VENDOR_M_ST_M45PE40:
11944 case FLASH_5720VENDOR_A_ST_M25PE40:
11945 case FLASH_5720VENDOR_A_ST_M45PE40:
11946 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11948 case FLASH_5720VENDOR_M_ST_M25PE80:
11949 case FLASH_5720VENDOR_M_ST_M45PE80:
11950 case FLASH_5720VENDOR_A_ST_M25PE80:
11951 case FLASH_5720VENDOR_A_ST_M45PE80:
11952 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11955 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11960 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11964 tg3_nvram_get_pagesize(tp, nvcfg1);
11965 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11966 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11969 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11970 static void __devinit tg3_nvram_init(struct tg3 *tp)
11972 tw32_f(GRC_EEPROM_ADDR,
11973 (EEPROM_ADDR_FSM_RESET |
11974 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11975 EEPROM_ADDR_CLKPERD_SHIFT)));
11979 /* Enable seeprom accesses. */
11980 tw32_f(GRC_LOCAL_CTRL,
11981 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11984 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11985 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11986 tp->tg3_flags |= TG3_FLAG_NVRAM;
11988 if (tg3_nvram_lock(tp)) {
11989 netdev_warn(tp->dev,
11990 "Cannot get nvram lock, %s failed\n",
11994 tg3_enable_nvram_access(tp);
11996 tp->nvram_size = 0;
11998 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11999 tg3_get_5752_nvram_info(tp);
12000 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12001 tg3_get_5755_nvram_info(tp);
12002 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12004 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12005 tg3_get_5787_nvram_info(tp);
12006 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12007 tg3_get_5761_nvram_info(tp);
12008 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12009 tg3_get_5906_nvram_info(tp);
12010 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12012 tg3_get_57780_nvram_info(tp);
12013 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12015 tg3_get_5717_nvram_info(tp);
12016 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12017 tg3_get_5720_nvram_info(tp);
12019 tg3_get_nvram_info(tp);
12021 if (tp->nvram_size == 0)
12022 tg3_get_nvram_size(tp);
12024 tg3_disable_nvram_access(tp);
12025 tg3_nvram_unlock(tp);
12028 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
12030 tg3_get_eeprom_size(tp);
12034 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12035 u32 offset, u32 len, u8 *buf)
12040 for (i = 0; i < len; i += 4) {
12046 memcpy(&data, buf + i, 4);
12049 * The SEEPROM interface expects the data to always be opposite
12050 * the native endian format. We accomplish this by reversing
12051 * all the operations that would have been performed on the
12052 * data from a call to tg3_nvram_read_be32().
12054 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12056 val = tr32(GRC_EEPROM_ADDR);
12057 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12059 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12061 tw32(GRC_EEPROM_ADDR, val |
12062 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12063 (addr & EEPROM_ADDR_ADDR_MASK) |
12064 EEPROM_ADDR_START |
12065 EEPROM_ADDR_WRITE);
12067 for (j = 0; j < 1000; j++) {
12068 val = tr32(GRC_EEPROM_ADDR);
12070 if (val & EEPROM_ADDR_COMPLETE)
12074 if (!(val & EEPROM_ADDR_COMPLETE)) {
12083 /* offset and length are dword aligned */
12084 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12088 u32 pagesize = tp->nvram_pagesize;
12089 u32 pagemask = pagesize - 1;
12093 tmp = kmalloc(pagesize, GFP_KERNEL);
12099 u32 phy_addr, page_off, size;
12101 phy_addr = offset & ~pagemask;
12103 for (j = 0; j < pagesize; j += 4) {
12104 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12105 (__be32 *) (tmp + j));
12112 page_off = offset & pagemask;
12119 memcpy(tmp + page_off, buf, size);
12121 offset = offset + (pagesize - page_off);
12123 tg3_enable_nvram_access(tp);
12126 * Before we can erase the flash page, we need
12127 * to issue a special "write enable" command.
12129 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12131 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12134 /* Erase the target page */
12135 tw32(NVRAM_ADDR, phy_addr);
12137 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12138 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12140 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12143 /* Issue another write enable to start the write. */
12144 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12146 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12149 for (j = 0; j < pagesize; j += 4) {
12152 data = *((__be32 *) (tmp + j));
12154 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12156 tw32(NVRAM_ADDR, phy_addr + j);
12158 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12162 nvram_cmd |= NVRAM_CMD_FIRST;
12163 else if (j == (pagesize - 4))
12164 nvram_cmd |= NVRAM_CMD_LAST;
12166 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12173 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12174 tg3_nvram_exec_cmd(tp, nvram_cmd);
12181 /* offset and length are dword aligned */
12182 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12187 for (i = 0; i < len; i += 4, offset += 4) {
12188 u32 page_off, phy_addr, nvram_cmd;
12191 memcpy(&data, buf + i, 4);
12192 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12194 page_off = offset % tp->nvram_pagesize;
12196 phy_addr = tg3_nvram_phys_addr(tp, offset);
12198 tw32(NVRAM_ADDR, phy_addr);
12200 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12202 if (page_off == 0 || i == 0)
12203 nvram_cmd |= NVRAM_CMD_FIRST;
12204 if (page_off == (tp->nvram_pagesize - 4))
12205 nvram_cmd |= NVRAM_CMD_LAST;
12207 if (i == (len - 4))
12208 nvram_cmd |= NVRAM_CMD_LAST;
12210 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12211 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12212 (tp->nvram_jedecnum == JEDEC_ST) &&
12213 (nvram_cmd & NVRAM_CMD_FIRST)) {
12215 if ((ret = tg3_nvram_exec_cmd(tp,
12216 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12221 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12222 /* We always do complete word writes to eeprom. */
12223 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12226 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12232 /* offset and length are dword aligned */
12233 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12237 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12238 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12239 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12243 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12244 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12248 ret = tg3_nvram_lock(tp);
12252 tg3_enable_nvram_access(tp);
12253 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12254 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12255 tw32(NVRAM_WRITE1, 0x406);
12257 grc_mode = tr32(GRC_MODE);
12258 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12260 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12261 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12263 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12266 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12270 grc_mode = tr32(GRC_MODE);
12271 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12273 tg3_disable_nvram_access(tp);
12274 tg3_nvram_unlock(tp);
12277 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12278 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12285 struct subsys_tbl_ent {
12286 u16 subsys_vendor, subsys_devid;
12290 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12291 /* Broadcom boards. */
12292 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12293 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12294 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12295 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12296 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12297 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12298 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12299 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12300 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12301 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12302 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12303 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12304 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12305 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12306 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12307 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12308 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12309 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12310 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12311 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12312 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12313 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12316 { TG3PCI_SUBVENDOR_ID_3COM,
12317 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12318 { TG3PCI_SUBVENDOR_ID_3COM,
12319 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12320 { TG3PCI_SUBVENDOR_ID_3COM,
12321 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12322 { TG3PCI_SUBVENDOR_ID_3COM,
12323 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12324 { TG3PCI_SUBVENDOR_ID_3COM,
12325 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12328 { TG3PCI_SUBVENDOR_ID_DELL,
12329 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12330 { TG3PCI_SUBVENDOR_ID_DELL,
12331 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12332 { TG3PCI_SUBVENDOR_ID_DELL,
12333 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12334 { TG3PCI_SUBVENDOR_ID_DELL,
12335 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12337 /* Compaq boards. */
12338 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12339 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12340 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12341 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12342 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12343 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12344 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12345 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12346 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12347 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12350 { TG3PCI_SUBVENDOR_ID_IBM,
12351 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12354 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12358 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12359 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12360 tp->pdev->subsystem_vendor) &&
12361 (subsys_id_to_phy_id[i].subsys_devid ==
12362 tp->pdev->subsystem_device))
12363 return &subsys_id_to_phy_id[i];
12368 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12373 /* On some early chips the SRAM cannot be accessed in D3hot state,
12374 * so need make sure we're in D0.
12376 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12377 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12378 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12381 /* Make sure register accesses (indirect or otherwise)
12382 * will function correctly.
12384 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12385 tp->misc_host_ctrl);
12387 /* The memory arbiter has to be enabled in order for SRAM accesses
12388 * to succeed. Normally on powerup the tg3 chip firmware will make
12389 * sure it is enabled, but other entities such as system netboot
12390 * code might disable it.
12392 val = tr32(MEMARB_MODE);
12393 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12395 tp->phy_id = TG3_PHY_ID_INVALID;
12396 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12398 /* Assume an onboard device and WOL capable by default. */
12399 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12401 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12402 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12403 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12404 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12406 val = tr32(VCPU_CFGSHDW);
12407 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12408 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12409 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12410 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12411 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12415 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12416 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12417 u32 nic_cfg, led_cfg;
12418 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12419 int eeprom_phy_serdes = 0;
12421 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12422 tp->nic_sram_data_cfg = nic_cfg;
12424 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12425 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12426 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12427 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12428 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12429 (ver > 0) && (ver < 0x100))
12430 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12433 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12435 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12436 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12437 eeprom_phy_serdes = 1;
12439 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12440 if (nic_phy_id != 0) {
12441 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12442 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12444 eeprom_phy_id = (id1 >> 16) << 10;
12445 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12446 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12450 tp->phy_id = eeprom_phy_id;
12451 if (eeprom_phy_serdes) {
12452 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12453 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12455 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12458 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12459 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12460 SHASTA_EXT_LED_MODE_MASK);
12462 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12466 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12467 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12470 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12471 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12474 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12475 tp->led_ctrl = LED_CTRL_MODE_MAC;
12477 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12478 * read on some older 5700/5701 bootcode.
12480 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12482 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12484 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12488 case SHASTA_EXT_LED_SHARED:
12489 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12490 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12491 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12492 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12493 LED_CTRL_MODE_PHY_2);
12496 case SHASTA_EXT_LED_MAC:
12497 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12500 case SHASTA_EXT_LED_COMBO:
12501 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12502 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12503 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12504 LED_CTRL_MODE_PHY_2);
12509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12511 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12512 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12514 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12515 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12517 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12518 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12519 if ((tp->pdev->subsystem_vendor ==
12520 PCI_VENDOR_ID_ARIMA) &&
12521 (tp->pdev->subsystem_device == 0x205a ||
12522 tp->pdev->subsystem_device == 0x2063))
12523 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12525 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12526 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12529 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12530 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12531 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12532 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12535 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12536 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12537 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12539 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12540 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12541 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12543 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12544 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12545 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12547 if (cfg2 & (1 << 17))
12548 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12550 /* serdes signal pre-emphasis in register 0x590 set by */
12551 /* bootcode if bit 18 is set */
12552 if (cfg2 & (1 << 18))
12553 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12555 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
12556 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12557 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12558 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12559 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12561 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12562 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12563 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
12566 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12567 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12568 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12571 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12572 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12573 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12574 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12575 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12576 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12579 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12580 device_set_wakeup_enable(&tp->pdev->dev,
12581 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12583 device_set_wakeup_capable(&tp->pdev->dev, false);
12586 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12591 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12592 tw32(OTP_CTRL, cmd);
12594 /* Wait for up to 1 ms for command to execute. */
12595 for (i = 0; i < 100; i++) {
12596 val = tr32(OTP_STATUS);
12597 if (val & OTP_STATUS_CMD_DONE)
12602 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12605 /* Read the gphy configuration from the OTP region of the chip. The gphy
12606 * configuration is a 32-bit value that straddles the alignment boundary.
12607 * We do two 32-bit reads and then shift and merge the results.
12609 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12611 u32 bhalf_otp, thalf_otp;
12613 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12615 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12618 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12620 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12623 thalf_otp = tr32(OTP_READ_DATA);
12625 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12627 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12630 bhalf_otp = tr32(OTP_READ_DATA);
12632 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12635 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12637 u32 adv = ADVERTISED_Autoneg |
12640 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12641 adv |= ADVERTISED_1000baseT_Half |
12642 ADVERTISED_1000baseT_Full;
12644 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12645 adv |= ADVERTISED_100baseT_Half |
12646 ADVERTISED_100baseT_Full |
12647 ADVERTISED_10baseT_Half |
12648 ADVERTISED_10baseT_Full |
12651 adv |= ADVERTISED_FIBRE;
12653 tp->link_config.advertising = adv;
12654 tp->link_config.speed = SPEED_INVALID;
12655 tp->link_config.duplex = DUPLEX_INVALID;
12656 tp->link_config.autoneg = AUTONEG_ENABLE;
12657 tp->link_config.active_speed = SPEED_INVALID;
12658 tp->link_config.active_duplex = DUPLEX_INVALID;
12659 tp->link_config.orig_speed = SPEED_INVALID;
12660 tp->link_config.orig_duplex = DUPLEX_INVALID;
12661 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12664 static int __devinit tg3_phy_probe(struct tg3 *tp)
12666 u32 hw_phy_id_1, hw_phy_id_2;
12667 u32 hw_phy_id, hw_phy_id_masked;
12670 /* flow control autonegotiation is default behavior */
12671 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12672 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12674 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12675 return tg3_phy_init(tp);
12677 /* Reading the PHY ID register can conflict with ASF
12678 * firmware access to the PHY hardware.
12681 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12682 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12683 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12685 /* Now read the physical PHY_ID from the chip and verify
12686 * that it is sane. If it doesn't look good, we fall back
12687 * to either the hard-coded table based PHY_ID and failing
12688 * that the value found in the eeprom area.
12690 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12691 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12693 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12694 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12695 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12697 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12700 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12701 tp->phy_id = hw_phy_id;
12702 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12703 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12705 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12707 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12708 /* Do nothing, phy ID already set up in
12709 * tg3_get_eeprom_hw_cfg().
12712 struct subsys_tbl_ent *p;
12714 /* No eeprom signature? Try the hardcoded
12715 * subsys device table.
12717 p = tg3_lookup_by_subsys(tp);
12721 tp->phy_id = p->phy_id;
12723 tp->phy_id == TG3_PHY_ID_BCM8002)
12724 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12728 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12729 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12730 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12731 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12732 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12733 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12735 tg3_phy_init_link_config(tp);
12737 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12738 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12739 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12740 u32 bmsr, adv_reg, tg3_ctrl, mask;
12742 tg3_readphy(tp, MII_BMSR, &bmsr);
12743 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12744 (bmsr & BMSR_LSTATUS))
12745 goto skip_phy_reset;
12747 err = tg3_phy_reset(tp);
12751 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12752 ADVERTISE_100HALF | ADVERTISE_100FULL |
12753 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12755 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12756 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12757 MII_TG3_CTRL_ADV_1000_FULL);
12758 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12760 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12761 MII_TG3_CTRL_ENABLE_AS_MASTER);
12764 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12765 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12766 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12767 if (!tg3_copper_is_advertising_all(tp, mask)) {
12768 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12770 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12771 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12773 tg3_writephy(tp, MII_BMCR,
12774 BMCR_ANENABLE | BMCR_ANRESTART);
12776 tg3_phy_set_wirespeed(tp);
12778 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12779 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12780 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12784 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12785 err = tg3_init_5401phy_dsp(tp);
12789 err = tg3_init_5401phy_dsp(tp);
12795 static void __devinit tg3_read_vpd(struct tg3 *tp)
12798 unsigned int block_end, rosize, len;
12802 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12803 tg3_nvram_read(tp, 0x0, &magic))
12806 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12810 if (magic == TG3_EEPROM_MAGIC) {
12811 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12814 /* The data is in little-endian format in NVRAM.
12815 * Use the big-endian read routines to preserve
12816 * the byte order as it exists in NVRAM.
12818 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12819 goto out_not_found;
12821 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12825 unsigned int pos = 0;
12827 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12828 cnt = pci_read_vpd(tp->pdev, pos,
12829 TG3_NVM_VPD_LEN - pos,
12831 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12834 goto out_not_found;
12836 if (pos != TG3_NVM_VPD_LEN)
12837 goto out_not_found;
12840 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12841 PCI_VPD_LRDT_RO_DATA);
12843 goto out_not_found;
12845 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12846 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12847 i += PCI_VPD_LRDT_TAG_SIZE;
12849 if (block_end > TG3_NVM_VPD_LEN)
12850 goto out_not_found;
12852 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12853 PCI_VPD_RO_KEYWORD_MFR_ID);
12855 len = pci_vpd_info_field_size(&vpd_data[j]);
12857 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12858 if (j + len > block_end || len != 4 ||
12859 memcmp(&vpd_data[j], "1028", 4))
12862 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12863 PCI_VPD_RO_KEYWORD_VENDOR0);
12867 len = pci_vpd_info_field_size(&vpd_data[j]);
12869 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12870 if (j + len > block_end)
12873 memcpy(tp->fw_ver, &vpd_data[j], len);
12874 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12878 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12879 PCI_VPD_RO_KEYWORD_PARTNO);
12881 goto out_not_found;
12883 len = pci_vpd_info_field_size(&vpd_data[i]);
12885 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12886 if (len > TG3_BPN_SIZE ||
12887 (len + i) > TG3_NVM_VPD_LEN)
12888 goto out_not_found;
12890 memcpy(tp->board_part_number, &vpd_data[i], len);
12894 if (tp->board_part_number[0])
12898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12899 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12900 strcpy(tp->board_part_number, "BCM5717");
12901 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12902 strcpy(tp->board_part_number, "BCM5718");
12905 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12906 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12907 strcpy(tp->board_part_number, "BCM57780");
12908 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12909 strcpy(tp->board_part_number, "BCM57760");
12910 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12911 strcpy(tp->board_part_number, "BCM57790");
12912 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12913 strcpy(tp->board_part_number, "BCM57788");
12916 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12917 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12918 strcpy(tp->board_part_number, "BCM57761");
12919 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12920 strcpy(tp->board_part_number, "BCM57765");
12921 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12922 strcpy(tp->board_part_number, "BCM57781");
12923 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12924 strcpy(tp->board_part_number, "BCM57785");
12925 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12926 strcpy(tp->board_part_number, "BCM57791");
12927 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12928 strcpy(tp->board_part_number, "BCM57795");
12931 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12932 strcpy(tp->board_part_number, "BCM95906");
12935 strcpy(tp->board_part_number, "none");
12939 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12943 if (tg3_nvram_read(tp, offset, &val) ||
12944 (val & 0xfc000000) != 0x0c000000 ||
12945 tg3_nvram_read(tp, offset + 4, &val) ||
12952 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12954 u32 val, offset, start, ver_offset;
12956 bool newver = false;
12958 if (tg3_nvram_read(tp, 0xc, &offset) ||
12959 tg3_nvram_read(tp, 0x4, &start))
12962 offset = tg3_nvram_logical_addr(tp, offset);
12964 if (tg3_nvram_read(tp, offset, &val))
12967 if ((val & 0xfc000000) == 0x0c000000) {
12968 if (tg3_nvram_read(tp, offset + 4, &val))
12975 dst_off = strlen(tp->fw_ver);
12978 if (TG3_VER_SIZE - dst_off < 16 ||
12979 tg3_nvram_read(tp, offset + 8, &ver_offset))
12982 offset = offset + ver_offset - start;
12983 for (i = 0; i < 16; i += 4) {
12985 if (tg3_nvram_read_be32(tp, offset + i, &v))
12988 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12993 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12996 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12997 TG3_NVM_BCVER_MAJSFT;
12998 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12999 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13000 "v%d.%02d", major, minor);
13004 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13006 u32 val, major, minor;
13008 /* Use native endian representation */
13009 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13012 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13013 TG3_NVM_HWSB_CFG1_MAJSFT;
13014 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13015 TG3_NVM_HWSB_CFG1_MINSFT;
13017 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13020 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13022 u32 offset, major, minor, build;
13024 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13026 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13029 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13030 case TG3_EEPROM_SB_REVISION_0:
13031 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13033 case TG3_EEPROM_SB_REVISION_2:
13034 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13036 case TG3_EEPROM_SB_REVISION_3:
13037 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13039 case TG3_EEPROM_SB_REVISION_4:
13040 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13042 case TG3_EEPROM_SB_REVISION_5:
13043 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13045 case TG3_EEPROM_SB_REVISION_6:
13046 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13052 if (tg3_nvram_read(tp, offset, &val))
13055 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13056 TG3_EEPROM_SB_EDH_BLD_SHFT;
13057 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13058 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13059 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13061 if (minor > 99 || build > 26)
13064 offset = strlen(tp->fw_ver);
13065 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13066 " v%d.%02d", major, minor);
13069 offset = strlen(tp->fw_ver);
13070 if (offset < TG3_VER_SIZE - 1)
13071 tp->fw_ver[offset] = 'a' + build - 1;
13075 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13077 u32 val, offset, start;
13080 for (offset = TG3_NVM_DIR_START;
13081 offset < TG3_NVM_DIR_END;
13082 offset += TG3_NVM_DIRENT_SIZE) {
13083 if (tg3_nvram_read(tp, offset, &val))
13086 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13090 if (offset == TG3_NVM_DIR_END)
13093 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13094 start = 0x08000000;
13095 else if (tg3_nvram_read(tp, offset - 4, &start))
13098 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13099 !tg3_fw_img_is_valid(tp, offset) ||
13100 tg3_nvram_read(tp, offset + 8, &val))
13103 offset += val - start;
13105 vlen = strlen(tp->fw_ver);
13107 tp->fw_ver[vlen++] = ',';
13108 tp->fw_ver[vlen++] = ' ';
13110 for (i = 0; i < 4; i++) {
13112 if (tg3_nvram_read_be32(tp, offset, &v))
13115 offset += sizeof(v);
13117 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13118 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13122 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13127 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13133 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13134 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13137 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13138 if (apedata != APE_SEG_SIG_MAGIC)
13141 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13142 if (!(apedata & APE_FW_STATUS_READY))
13145 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13147 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13148 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13154 vlen = strlen(tp->fw_ver);
13156 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13158 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13159 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13160 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13161 (apedata & APE_FW_VERSION_BLDMSK));
13164 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13167 bool vpd_vers = false;
13169 if (tp->fw_ver[0] != 0)
13172 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13173 strcat(tp->fw_ver, "sb");
13177 if (tg3_nvram_read(tp, 0, &val))
13180 if (val == TG3_EEPROM_MAGIC)
13181 tg3_read_bc_ver(tp);
13182 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13183 tg3_read_sb_ver(tp, val);
13184 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13185 tg3_read_hwsb_ver(tp);
13189 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13190 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13193 tg3_read_mgmtfw_ver(tp);
13196 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13199 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13201 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13203 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13204 return TG3_RX_RET_MAX_SIZE_5717;
13205 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13206 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13207 return TG3_RX_RET_MAX_SIZE_5700;
13209 return TG3_RX_RET_MAX_SIZE_5705;
13212 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13213 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13214 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13215 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13219 static int __devinit tg3_get_invariants(struct tg3 *tp)
13222 u32 pci_state_reg, grc_misc_cfg;
13227 /* Force memory write invalidate off. If we leave it on,
13228 * then on 5700_BX chips we have to enable a workaround.
13229 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13230 * to match the cacheline size. The Broadcom driver have this
13231 * workaround but turns MWI off all the times so never uses
13232 * it. This seems to suggest that the workaround is insufficient.
13234 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13235 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13236 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13238 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13239 * has the register indirect write enable bit set before
13240 * we try to access any of the MMIO registers. It is also
13241 * critical that the PCI-X hw workaround situation is decided
13242 * before that as well.
13244 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13247 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13248 MISC_HOST_CTRL_CHIPREV_SHIFT);
13249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13250 u32 prod_id_asic_rev;
13252 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13253 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13254 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13255 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13256 pci_read_config_dword(tp->pdev,
13257 TG3PCI_GEN2_PRODID_ASICREV,
13258 &prod_id_asic_rev);
13259 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13260 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13261 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13262 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13263 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13264 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13265 pci_read_config_dword(tp->pdev,
13266 TG3PCI_GEN15_PRODID_ASICREV,
13267 &prod_id_asic_rev);
13269 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13270 &prod_id_asic_rev);
13272 tp->pci_chip_rev_id = prod_id_asic_rev;
13275 /* Wrong chip ID in 5752 A0. This code can be removed later
13276 * as A0 is not in production.
13278 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13279 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13281 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13282 * we need to disable memory and use config. cycles
13283 * only to access all registers. The 5702/03 chips
13284 * can mistakenly decode the special cycles from the
13285 * ICH chipsets as memory write cycles, causing corruption
13286 * of register and memory space. Only certain ICH bridges
13287 * will drive special cycles with non-zero data during the
13288 * address phase which can fall within the 5703's address
13289 * range. This is not an ICH bug as the PCI spec allows
13290 * non-zero address during special cycles. However, only
13291 * these ICH bridges are known to drive non-zero addresses
13292 * during special cycles.
13294 * Since special cycles do not cross PCI bridges, we only
13295 * enable this workaround if the 5703 is on the secondary
13296 * bus of these ICH bridges.
13298 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13299 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13300 static struct tg3_dev_id {
13304 } ich_chipsets[] = {
13305 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13307 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13309 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13311 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13315 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13316 struct pci_dev *bridge = NULL;
13318 while (pci_id->vendor != 0) {
13319 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13325 if (pci_id->rev != PCI_ANY_ID) {
13326 if (bridge->revision > pci_id->rev)
13329 if (bridge->subordinate &&
13330 (bridge->subordinate->number ==
13331 tp->pdev->bus->number)) {
13333 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13334 pci_dev_put(bridge);
13340 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13341 static struct tg3_dev_id {
13344 } bridge_chipsets[] = {
13345 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13346 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13349 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13350 struct pci_dev *bridge = NULL;
13352 while (pci_id->vendor != 0) {
13353 bridge = pci_get_device(pci_id->vendor,
13360 if (bridge->subordinate &&
13361 (bridge->subordinate->number <=
13362 tp->pdev->bus->number) &&
13363 (bridge->subordinate->subordinate >=
13364 tp->pdev->bus->number)) {
13365 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13366 pci_dev_put(bridge);
13372 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13373 * DMA addresses > 40-bit. This bridge may have other additional
13374 * 57xx devices behind it in some 4-port NIC designs for example.
13375 * Any tg3 device found behind the bridge will also need the 40-bit
13378 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13380 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13381 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13382 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13384 struct pci_dev *bridge = NULL;
13387 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13388 PCI_DEVICE_ID_SERVERWORKS_EPB,
13390 if (bridge && bridge->subordinate &&
13391 (bridge->subordinate->number <=
13392 tp->pdev->bus->number) &&
13393 (bridge->subordinate->subordinate >=
13394 tp->pdev->bus->number)) {
13395 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13396 pci_dev_put(bridge);
13402 /* Initialize misc host control in PCI block. */
13403 tp->misc_host_ctrl |= (misc_ctrl_reg &
13404 MISC_HOST_CTRL_CHIPREV);
13405 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13406 tp->misc_host_ctrl);
13408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13412 tp->pdev_peer = tg3_find_peer(tp);
13414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13415 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13417 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13420 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13421 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
13423 /* Intentionally exclude ASIC_REV_5906 */
13424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13430 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13431 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13434 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13435 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13436 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13437 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13438 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13440 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13441 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13442 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13444 /* 5700 B0 chips do not support checksumming correctly due
13445 * to hardware bugs.
13447 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13448 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
13450 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13451 features |= NETIF_F_IPV6_CSUM;
13452 tp->dev->features |= features;
13453 tp->dev->hw_features |= features;
13454 tp->dev->vlan_features |= features;
13457 /* Determine TSO capabilities */
13458 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13459 ; /* Do nothing. HW bug. */
13460 else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
13461 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13462 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13463 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13464 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13465 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13466 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13467 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13468 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13469 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13470 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13471 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13472 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13473 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13475 tp->fw_needed = FIRMWARE_TG3TSO5;
13477 tp->fw_needed = FIRMWARE_TG3TSO;
13482 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13483 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13484 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13485 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13486 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13487 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13488 tp->pdev_peer == tp->pdev))
13489 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13491 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13493 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13496 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
13497 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13498 tp->irq_max = TG3_IRQ_MAX_VECS;
13502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13505 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13506 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13507 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13508 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13511 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13512 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13514 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
13515 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13516 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13518 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13519 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13520 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13521 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13523 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13526 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13527 if (tp->pcie_cap != 0) {
13530 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13532 tp->pcie_readrq = 4096;
13533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13535 tp->pcie_readrq = 2048;
13537 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13539 pci_read_config_word(tp->pdev,
13540 tp->pcie_cap + PCI_EXP_LNKCTL,
13542 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13544 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13547 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13548 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13549 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13550 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13551 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13553 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13554 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13555 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13556 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13557 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13558 if (!tp->pcix_cap) {
13559 dev_err(&tp->pdev->dev,
13560 "Cannot find PCI-X capability, aborting\n");
13564 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13565 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13568 /* If we have an AMD 762 or VIA K8T800 chipset, write
13569 * reordering to the mailbox registers done by the host
13570 * controller can cause major troubles. We read back from
13571 * every mailbox register write to force the writes to be
13572 * posted to the chip in order.
13574 if (pci_dev_present(tg3_write_reorder_chipsets) &&
13575 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13576 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13578 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13579 &tp->pci_cacheline_sz);
13580 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13581 &tp->pci_lat_timer);
13582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13583 tp->pci_lat_timer < 64) {
13584 tp->pci_lat_timer = 64;
13585 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13586 tp->pci_lat_timer);
13589 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13590 /* 5700 BX chips need to have their TX producer index
13591 * mailboxes written twice to workaround a bug.
13593 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13595 /* If we are in PCI-X mode, enable register write workaround.
13597 * The workaround is to use indirect register accesses
13598 * for all chip writes not to mailbox registers.
13600 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13603 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13605 /* The chip can have it's power management PCI config
13606 * space registers clobbered due to this bug.
13607 * So explicitly force the chip into D0 here.
13609 pci_read_config_dword(tp->pdev,
13610 tp->pm_cap + PCI_PM_CTRL,
13612 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13613 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13614 pci_write_config_dword(tp->pdev,
13615 tp->pm_cap + PCI_PM_CTRL,
13618 /* Also, force SERR#/PERR# in PCI command. */
13619 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13620 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13621 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13625 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13626 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13627 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13628 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13630 /* Chip-specific fixup from Broadcom driver */
13631 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13632 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13633 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13634 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13637 /* Default fast path register access methods */
13638 tp->read32 = tg3_read32;
13639 tp->write32 = tg3_write32;
13640 tp->read32_mbox = tg3_read32;
13641 tp->write32_mbox = tg3_write32;
13642 tp->write32_tx_mbox = tg3_write32;
13643 tp->write32_rx_mbox = tg3_write32;
13645 /* Various workaround register access methods */
13646 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13647 tp->write32 = tg3_write_indirect_reg32;
13648 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13649 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13650 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13652 * Back to back register writes can cause problems on these
13653 * chips, the workaround is to read back all reg writes
13654 * except those to mailbox regs.
13656 * See tg3_write_indirect_reg32().
13658 tp->write32 = tg3_write_flush_reg32;
13661 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13662 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13663 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13664 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13665 tp->write32_rx_mbox = tg3_write_flush_reg32;
13668 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13669 tp->read32 = tg3_read_indirect_reg32;
13670 tp->write32 = tg3_write_indirect_reg32;
13671 tp->read32_mbox = tg3_read_indirect_mbox;
13672 tp->write32_mbox = tg3_write_indirect_mbox;
13673 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13674 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13679 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13680 pci_cmd &= ~PCI_COMMAND_MEMORY;
13681 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13684 tp->read32_mbox = tg3_read32_mbox_5906;
13685 tp->write32_mbox = tg3_write32_mbox_5906;
13686 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13687 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13690 if (tp->write32 == tg3_write_indirect_reg32 ||
13691 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13692 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13694 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13696 /* Get eeprom hw config before calling tg3_set_power_state().
13697 * In particular, the TG3_FLG2_IS_NIC flag must be
13698 * determined before calling tg3_set_power_state() so that
13699 * we know whether or not to switch out of Vaux power.
13700 * When the flag is set, it means that GPIO1 is used for eeprom
13701 * write protect and also implies that it is a LOM where GPIOs
13702 * are not used to switch power.
13704 tg3_get_eeprom_hw_cfg(tp);
13706 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13707 /* Allow reads and writes to the
13708 * APE register and memory space.
13710 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13711 PCISTATE_ALLOW_APE_SHMEM_WR |
13712 PCISTATE_ALLOW_APE_PSPACE_WR;
13713 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13717 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13720 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13721 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13722 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13724 /* Set up tp->grc_local_ctrl before calling tg_power_up().
13725 * GPIO1 driven high will bring 5700's external PHY out of reset.
13726 * It is also used as eeprom write protect on LOMs.
13728 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13729 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13730 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13731 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13732 GRC_LCLCTRL_GPIO_OUTPUT1);
13733 /* Unused GPIO3 must be driven as output on 5752 because there
13734 * are no pull-up resistors on unused GPIO pins.
13736 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13737 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13740 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13741 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13742 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13744 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13745 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13746 /* Turn off the debug UART. */
13747 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13748 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13749 /* Keep VMain power. */
13750 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13751 GRC_LCLCTRL_GPIO_OUTPUT0;
13754 /* Force the chip into D0. */
13755 err = tg3_power_up(tp);
13757 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13761 /* Derive initial jumbo mode from MTU assigned in
13762 * ether_setup() via the alloc_etherdev() call
13764 if (tp->dev->mtu > ETH_DATA_LEN &&
13765 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13766 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13768 /* Determine WakeOnLan speed to use. */
13769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13770 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13771 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13772 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13773 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13775 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13779 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13781 /* A few boards don't want Ethernet@WireSpeed phy feature */
13782 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13783 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13784 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13785 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13786 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13787 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13788 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13790 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13791 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13792 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13793 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13794 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13796 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13797 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13798 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13799 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13800 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
13801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13805 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13806 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13807 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13808 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13809 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13811 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13815 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13816 tp->phy_otp = tg3_read_otp_phycfg(tp);
13817 if (tp->phy_otp == 0)
13818 tp->phy_otp = TG3_OTP_DEFAULT;
13821 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13822 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13824 tp->mi_mode = MAC_MI_MODE_BASE;
13826 tp->coalesce_mode = 0;
13827 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13828 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13829 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13832 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13833 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13835 err = tg3_mdio_init(tp);
13839 /* Initialize data/descriptor byte/word swapping. */
13840 val = tr32(GRC_MODE);
13841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13842 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
13843 GRC_MODE_WORD_SWAP_B2HRX_DATA |
13844 GRC_MODE_B2HRX_ENABLE |
13845 GRC_MODE_HTX2B_ENABLE |
13846 GRC_MODE_HOST_STACKUP);
13848 val &= GRC_MODE_HOST_STACKUP;
13850 tw32(GRC_MODE, val | tp->grc_mode);
13852 tg3_switch_clocks(tp);
13854 /* Clear this out for sanity. */
13855 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13857 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13859 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13860 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13861 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13863 if (chiprevid == CHIPREV_ID_5701_A0 ||
13864 chiprevid == CHIPREV_ID_5701_B0 ||
13865 chiprevid == CHIPREV_ID_5701_B2 ||
13866 chiprevid == CHIPREV_ID_5701_B5) {
13867 void __iomem *sram_base;
13869 /* Write some dummy words into the SRAM status block
13870 * area, see if it reads back correctly. If the return
13871 * value is bad, force enable the PCIX workaround.
13873 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13875 writel(0x00000000, sram_base);
13876 writel(0x00000000, sram_base + 4);
13877 writel(0xffffffff, sram_base + 4);
13878 if (readl(sram_base) != 0x00000000)
13879 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13884 tg3_nvram_init(tp);
13886 grc_misc_cfg = tr32(GRC_MISC_CFG);
13887 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13890 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13891 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13892 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13894 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13895 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13896 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13897 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13898 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13899 HOSTCC_MODE_CLRTICK_TXBD);
13901 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13902 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13903 tp->misc_host_ctrl);
13906 /* Preserve the APE MAC_MODE bits */
13907 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13908 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13910 tp->mac_mode = TG3_DEF_MAC_MODE;
13912 /* these are limited to 10/100 only */
13913 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13914 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13915 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13916 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13917 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13918 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13919 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13920 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13921 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13922 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13923 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13924 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13925 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13926 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13927 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13928 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13930 err = tg3_phy_probe(tp);
13932 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13933 /* ... but do not return immediately ... */
13938 tg3_read_fw_ver(tp);
13940 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13941 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13944 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13946 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13949 /* 5700 {AX,BX} chips have a broken status block link
13950 * change bit implementation, so we must use the
13951 * status register in those cases.
13953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13954 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13956 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13958 /* The led_ctrl is set during tg3_phy_probe, here we might
13959 * have to force the link status polling mechanism based
13960 * upon subsystem IDs.
13962 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13964 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13965 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13966 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13969 /* For all SERDES we poll the MAC status register. */
13970 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13971 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13973 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13975 tp->rx_offset = NET_IP_ALIGN;
13976 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13978 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13980 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13981 tp->rx_copy_thresh = ~(u16)0;
13985 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13986 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13987 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13989 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13991 /* Increment the rx prod index on the rx std ring by at most
13992 * 8 for these chips to workaround hw errata.
13994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13997 tp->rx_std_max_post = 8;
13999 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
14000 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14001 PCIE_PWR_MGMT_L1_THRESH_MSK;
14006 #ifdef CONFIG_SPARC
14007 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14009 struct net_device *dev = tp->dev;
14010 struct pci_dev *pdev = tp->pdev;
14011 struct device_node *dp = pci_device_to_OF_node(pdev);
14012 const unsigned char *addr;
14015 addr = of_get_property(dp, "local-mac-address", &len);
14016 if (addr && len == 6) {
14017 memcpy(dev->dev_addr, addr, 6);
14018 memcpy(dev->perm_addr, dev->dev_addr, 6);
14024 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14026 struct net_device *dev = tp->dev;
14028 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14029 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14034 static int __devinit tg3_get_device_address(struct tg3 *tp)
14036 struct net_device *dev = tp->dev;
14037 u32 hi, lo, mac_offset;
14040 #ifdef CONFIG_SPARC
14041 if (!tg3_get_macaddr_sparc(tp))
14046 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14047 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
14048 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14050 if (tg3_nvram_lock(tp))
14051 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14053 tg3_nvram_unlock(tp);
14054 } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14055 if (PCI_FUNC(tp->pdev->devfn) & 1)
14057 if (PCI_FUNC(tp->pdev->devfn) > 1)
14058 mac_offset += 0x18c;
14059 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14062 /* First try to get it from MAC address mailbox. */
14063 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14064 if ((hi >> 16) == 0x484b) {
14065 dev->dev_addr[0] = (hi >> 8) & 0xff;
14066 dev->dev_addr[1] = (hi >> 0) & 0xff;
14068 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14069 dev->dev_addr[2] = (lo >> 24) & 0xff;
14070 dev->dev_addr[3] = (lo >> 16) & 0xff;
14071 dev->dev_addr[4] = (lo >> 8) & 0xff;
14072 dev->dev_addr[5] = (lo >> 0) & 0xff;
14074 /* Some old bootcode may report a 0 MAC address in SRAM */
14075 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14078 /* Next, try NVRAM. */
14079 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
14080 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14081 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14082 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14083 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14085 /* Finally just fetch it out of the MAC control regs. */
14087 hi = tr32(MAC_ADDR_0_HIGH);
14088 lo = tr32(MAC_ADDR_0_LOW);
14090 dev->dev_addr[5] = lo & 0xff;
14091 dev->dev_addr[4] = (lo >> 8) & 0xff;
14092 dev->dev_addr[3] = (lo >> 16) & 0xff;
14093 dev->dev_addr[2] = (lo >> 24) & 0xff;
14094 dev->dev_addr[1] = hi & 0xff;
14095 dev->dev_addr[0] = (hi >> 8) & 0xff;
14099 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14100 #ifdef CONFIG_SPARC
14101 if (!tg3_get_default_macaddr_sparc(tp))
14106 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14110 #define BOUNDARY_SINGLE_CACHELINE 1
14111 #define BOUNDARY_MULTI_CACHELINE 2
14113 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14115 int cacheline_size;
14119 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14121 cacheline_size = 1024;
14123 cacheline_size = (int) byte * 4;
14125 /* On 5703 and later chips, the boundary bits have no
14128 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14129 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14130 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14133 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14134 goal = BOUNDARY_MULTI_CACHELINE;
14136 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14137 goal = BOUNDARY_SINGLE_CACHELINE;
14143 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14144 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14151 /* PCI controllers on most RISC systems tend to disconnect
14152 * when a device tries to burst across a cache-line boundary.
14153 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14155 * Unfortunately, for PCI-E there are only limited
14156 * write-side controls for this, and thus for reads
14157 * we will still get the disconnects. We'll also waste
14158 * these PCI cycles for both read and write for chips
14159 * other than 5700 and 5701 which do not implement the
14162 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14163 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14164 switch (cacheline_size) {
14169 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14170 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14171 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14173 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14174 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14179 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14180 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14184 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14185 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14188 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14189 switch (cacheline_size) {
14193 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14194 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14195 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14201 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14202 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14206 switch (cacheline_size) {
14208 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14209 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14210 DMA_RWCTRL_WRITE_BNDRY_16);
14215 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14216 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14217 DMA_RWCTRL_WRITE_BNDRY_32);
14222 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14223 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14224 DMA_RWCTRL_WRITE_BNDRY_64);
14229 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14230 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14231 DMA_RWCTRL_WRITE_BNDRY_128);
14236 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14237 DMA_RWCTRL_WRITE_BNDRY_256);
14240 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14241 DMA_RWCTRL_WRITE_BNDRY_512);
14245 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14246 DMA_RWCTRL_WRITE_BNDRY_1024);
14255 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14257 struct tg3_internal_buffer_desc test_desc;
14258 u32 sram_dma_descs;
14261 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14263 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14264 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14265 tw32(RDMAC_STATUS, 0);
14266 tw32(WDMAC_STATUS, 0);
14268 tw32(BUFMGR_MODE, 0);
14269 tw32(FTQ_RESET, 0);
14271 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14272 test_desc.addr_lo = buf_dma & 0xffffffff;
14273 test_desc.nic_mbuf = 0x00002100;
14274 test_desc.len = size;
14277 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14278 * the *second* time the tg3 driver was getting loaded after an
14281 * Broadcom tells me:
14282 * ...the DMA engine is connected to the GRC block and a DMA
14283 * reset may affect the GRC block in some unpredictable way...
14284 * The behavior of resets to individual blocks has not been tested.
14286 * Broadcom noted the GRC reset will also reset all sub-components.
14289 test_desc.cqid_sqid = (13 << 8) | 2;
14291 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14294 test_desc.cqid_sqid = (16 << 8) | 7;
14296 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14299 test_desc.flags = 0x00000005;
14301 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14304 val = *(((u32 *)&test_desc) + i);
14305 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14306 sram_dma_descs + (i * sizeof(u32)));
14307 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14309 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14312 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14314 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14317 for (i = 0; i < 40; i++) {
14321 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14323 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14324 if ((val & 0xffff) == sram_dma_descs) {
14335 #define TEST_BUFFER_SIZE 0x2000
14337 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14338 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14342 static int __devinit tg3_test_dma(struct tg3 *tp)
14344 dma_addr_t buf_dma;
14345 u32 *buf, saved_dma_rwctrl;
14348 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14349 &buf_dma, GFP_KERNEL);
14355 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14356 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14358 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14360 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
14363 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14364 /* DMA read watermark not used on PCIE */
14365 tp->dma_rwctrl |= 0x00180000;
14366 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14369 tp->dma_rwctrl |= 0x003f0000;
14371 tp->dma_rwctrl |= 0x003f000f;
14373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14375 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14376 u32 read_water = 0x7;
14378 /* If the 5704 is behind the EPB bridge, we can
14379 * do the less restrictive ONE_DMA workaround for
14380 * better performance.
14382 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14383 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14384 tp->dma_rwctrl |= 0x8000;
14385 else if (ccval == 0x6 || ccval == 0x7)
14386 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14390 /* Set bit 23 to enable PCIX hw bug fix */
14392 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14393 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14395 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14396 /* 5780 always in PCIX mode */
14397 tp->dma_rwctrl |= 0x00144000;
14398 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14399 /* 5714 always in PCIX mode */
14400 tp->dma_rwctrl |= 0x00148000;
14402 tp->dma_rwctrl |= 0x001b000f;
14406 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14408 tp->dma_rwctrl &= 0xfffffff0;
14410 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14412 /* Remove this if it causes problems for some boards. */
14413 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14415 /* On 5700/5701 chips, we need to set this bit.
14416 * Otherwise the chip will issue cacheline transactions
14417 * to streamable DMA memory with not all the byte
14418 * enables turned on. This is an error on several
14419 * RISC PCI controllers, in particular sparc64.
14421 * On 5703/5704 chips, this bit has been reassigned
14422 * a different meaning. In particular, it is used
14423 * on those chips to enable a PCI-X workaround.
14425 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14428 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14431 /* Unneeded, already done by tg3_get_invariants. */
14432 tg3_switch_clocks(tp);
14435 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14436 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14439 /* It is best to perform DMA test with maximum write burst size
14440 * to expose the 5700/5701 write DMA bug.
14442 saved_dma_rwctrl = tp->dma_rwctrl;
14443 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14444 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14449 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14452 /* Send the buffer to the chip. */
14453 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14455 dev_err(&tp->pdev->dev,
14456 "%s: Buffer write failed. err = %d\n",
14462 /* validate data reached card RAM correctly. */
14463 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14465 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14466 if (le32_to_cpu(val) != p[i]) {
14467 dev_err(&tp->pdev->dev,
14468 "%s: Buffer corrupted on device! "
14469 "(%d != %d)\n", __func__, val, i);
14470 /* ret = -ENODEV here? */
14475 /* Now read it back. */
14476 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14478 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14479 "err = %d\n", __func__, ret);
14484 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14488 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14489 DMA_RWCTRL_WRITE_BNDRY_16) {
14490 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14491 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14492 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14495 dev_err(&tp->pdev->dev,
14496 "%s: Buffer corrupted on read back! "
14497 "(%d != %d)\n", __func__, p[i], i);
14503 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14509 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14510 DMA_RWCTRL_WRITE_BNDRY_16) {
14512 /* DMA test passed without adjusting DMA boundary,
14513 * now look for chipsets that are known to expose the
14514 * DMA bug without failing the test.
14516 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14517 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14518 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14520 /* Safe to use the calculated DMA boundary. */
14521 tp->dma_rwctrl = saved_dma_rwctrl;
14524 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14528 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14533 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14535 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14536 tp->bufmgr_config.mbuf_read_dma_low_water =
14537 DEFAULT_MB_RDMA_LOW_WATER_5705;
14538 tp->bufmgr_config.mbuf_mac_rx_low_water =
14539 DEFAULT_MB_MACRX_LOW_WATER_57765;
14540 tp->bufmgr_config.mbuf_high_water =
14541 DEFAULT_MB_HIGH_WATER_57765;
14543 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14544 DEFAULT_MB_RDMA_LOW_WATER_5705;
14545 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14546 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14547 tp->bufmgr_config.mbuf_high_water_jumbo =
14548 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14549 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14550 tp->bufmgr_config.mbuf_read_dma_low_water =
14551 DEFAULT_MB_RDMA_LOW_WATER_5705;
14552 tp->bufmgr_config.mbuf_mac_rx_low_water =
14553 DEFAULT_MB_MACRX_LOW_WATER_5705;
14554 tp->bufmgr_config.mbuf_high_water =
14555 DEFAULT_MB_HIGH_WATER_5705;
14556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14557 tp->bufmgr_config.mbuf_mac_rx_low_water =
14558 DEFAULT_MB_MACRX_LOW_WATER_5906;
14559 tp->bufmgr_config.mbuf_high_water =
14560 DEFAULT_MB_HIGH_WATER_5906;
14563 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14564 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14565 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14566 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14567 tp->bufmgr_config.mbuf_high_water_jumbo =
14568 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14570 tp->bufmgr_config.mbuf_read_dma_low_water =
14571 DEFAULT_MB_RDMA_LOW_WATER;
14572 tp->bufmgr_config.mbuf_mac_rx_low_water =
14573 DEFAULT_MB_MACRX_LOW_WATER;
14574 tp->bufmgr_config.mbuf_high_water =
14575 DEFAULT_MB_HIGH_WATER;
14577 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14578 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14579 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14580 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14581 tp->bufmgr_config.mbuf_high_water_jumbo =
14582 DEFAULT_MB_HIGH_WATER_JUMBO;
14585 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14586 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14589 static char * __devinit tg3_phy_string(struct tg3 *tp)
14591 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14592 case TG3_PHY_ID_BCM5400: return "5400";
14593 case TG3_PHY_ID_BCM5401: return "5401";
14594 case TG3_PHY_ID_BCM5411: return "5411";
14595 case TG3_PHY_ID_BCM5701: return "5701";
14596 case TG3_PHY_ID_BCM5703: return "5703";
14597 case TG3_PHY_ID_BCM5704: return "5704";
14598 case TG3_PHY_ID_BCM5705: return "5705";
14599 case TG3_PHY_ID_BCM5750: return "5750";
14600 case TG3_PHY_ID_BCM5752: return "5752";
14601 case TG3_PHY_ID_BCM5714: return "5714";
14602 case TG3_PHY_ID_BCM5780: return "5780";
14603 case TG3_PHY_ID_BCM5755: return "5755";
14604 case TG3_PHY_ID_BCM5787: return "5787";
14605 case TG3_PHY_ID_BCM5784: return "5784";
14606 case TG3_PHY_ID_BCM5756: return "5722/5756";
14607 case TG3_PHY_ID_BCM5906: return "5906";
14608 case TG3_PHY_ID_BCM5761: return "5761";
14609 case TG3_PHY_ID_BCM5718C: return "5718C";
14610 case TG3_PHY_ID_BCM5718S: return "5718S";
14611 case TG3_PHY_ID_BCM57765: return "57765";
14612 case TG3_PHY_ID_BCM5719C: return "5719C";
14613 case TG3_PHY_ID_BCM5720C: return "5720C";
14614 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14615 case 0: return "serdes";
14616 default: return "unknown";
14620 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14622 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14623 strcpy(str, "PCI Express");
14625 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14626 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14628 strcpy(str, "PCIX:");
14630 if ((clock_ctrl == 7) ||
14631 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14632 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14633 strcat(str, "133MHz");
14634 else if (clock_ctrl == 0)
14635 strcat(str, "33MHz");
14636 else if (clock_ctrl == 2)
14637 strcat(str, "50MHz");
14638 else if (clock_ctrl == 4)
14639 strcat(str, "66MHz");
14640 else if (clock_ctrl == 6)
14641 strcat(str, "100MHz");
14643 strcpy(str, "PCI:");
14644 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14645 strcat(str, "66MHz");
14647 strcat(str, "33MHz");
14649 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14650 strcat(str, ":32-bit");
14652 strcat(str, ":64-bit");
14656 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14658 struct pci_dev *peer;
14659 unsigned int func, devnr = tp->pdev->devfn & ~7;
14661 for (func = 0; func < 8; func++) {
14662 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14663 if (peer && peer != tp->pdev)
14667 /* 5704 can be configured in single-port mode, set peer to
14668 * tp->pdev in that case.
14676 * We don't need to keep the refcount elevated; there's no way
14677 * to remove one half of this device without removing the other
14684 static void __devinit tg3_init_coal(struct tg3 *tp)
14686 struct ethtool_coalesce *ec = &tp->coal;
14688 memset(ec, 0, sizeof(*ec));
14689 ec->cmd = ETHTOOL_GCOALESCE;
14690 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14691 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14692 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14693 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14694 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14695 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14696 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14697 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14698 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14700 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14701 HOSTCC_MODE_CLRTICK_TXBD)) {
14702 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14703 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14704 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14705 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14708 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14709 ec->rx_coalesce_usecs_irq = 0;
14710 ec->tx_coalesce_usecs_irq = 0;
14711 ec->stats_block_coalesce_usecs = 0;
14715 static const struct net_device_ops tg3_netdev_ops = {
14716 .ndo_open = tg3_open,
14717 .ndo_stop = tg3_close,
14718 .ndo_start_xmit = tg3_start_xmit,
14719 .ndo_get_stats64 = tg3_get_stats64,
14720 .ndo_validate_addr = eth_validate_addr,
14721 .ndo_set_multicast_list = tg3_set_rx_mode,
14722 .ndo_set_mac_address = tg3_set_mac_addr,
14723 .ndo_do_ioctl = tg3_ioctl,
14724 .ndo_tx_timeout = tg3_tx_timeout,
14725 .ndo_change_mtu = tg3_change_mtu,
14726 .ndo_fix_features = tg3_fix_features,
14727 #ifdef CONFIG_NET_POLL_CONTROLLER
14728 .ndo_poll_controller = tg3_poll_controller,
14732 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14733 .ndo_open = tg3_open,
14734 .ndo_stop = tg3_close,
14735 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14736 .ndo_get_stats64 = tg3_get_stats64,
14737 .ndo_validate_addr = eth_validate_addr,
14738 .ndo_set_multicast_list = tg3_set_rx_mode,
14739 .ndo_set_mac_address = tg3_set_mac_addr,
14740 .ndo_do_ioctl = tg3_ioctl,
14741 .ndo_tx_timeout = tg3_tx_timeout,
14742 .ndo_change_mtu = tg3_change_mtu,
14743 #ifdef CONFIG_NET_POLL_CONTROLLER
14744 .ndo_poll_controller = tg3_poll_controller,
14748 static int __devinit tg3_init_one(struct pci_dev *pdev,
14749 const struct pci_device_id *ent)
14751 struct net_device *dev;
14753 int i, err, pm_cap;
14754 u32 sndmbx, rcvmbx, intmbx;
14756 u64 dma_mask, persist_dma_mask;
14757 u32 hw_features = 0;
14759 printk_once(KERN_INFO "%s\n", version);
14761 err = pci_enable_device(pdev);
14763 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14767 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14769 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14770 goto err_out_disable_pdev;
14773 pci_set_master(pdev);
14775 /* Find power-management capability. */
14776 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14778 dev_err(&pdev->dev,
14779 "Cannot find Power Management capability, aborting\n");
14781 goto err_out_free_res;
14784 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14786 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14788 goto err_out_free_res;
14791 SET_NETDEV_DEV(dev, &pdev->dev);
14793 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14795 tp = netdev_priv(dev);
14798 tp->pm_cap = pm_cap;
14799 tp->rx_mode = TG3_DEF_RX_MODE;
14800 tp->tx_mode = TG3_DEF_TX_MODE;
14803 tp->msg_enable = tg3_debug;
14805 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14807 /* The word/byte swap controls here control register access byte
14808 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14811 tp->misc_host_ctrl =
14812 MISC_HOST_CTRL_MASK_PCI_INT |
14813 MISC_HOST_CTRL_WORD_SWAP |
14814 MISC_HOST_CTRL_INDIR_ACCESS |
14815 MISC_HOST_CTRL_PCISTATE_RW;
14817 /* The NONFRM (non-frame) byte/word swap controls take effect
14818 * on descriptor entries, anything which isn't packet data.
14820 * The StrongARM chips on the board (one for tx, one for rx)
14821 * are running in big-endian mode.
14823 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14824 GRC_MODE_WSWAP_NONFRM_DATA);
14825 #ifdef __BIG_ENDIAN
14826 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14828 spin_lock_init(&tp->lock);
14829 spin_lock_init(&tp->indirect_lock);
14830 INIT_WORK(&tp->reset_task, tg3_reset_task);
14832 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14834 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14836 goto err_out_free_dev;
14839 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14840 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14842 dev->ethtool_ops = &tg3_ethtool_ops;
14843 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14844 dev->irq = pdev->irq;
14846 err = tg3_get_invariants(tp);
14848 dev_err(&pdev->dev,
14849 "Problem fetching invariants of chip, aborting\n");
14850 goto err_out_iounmap;
14853 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14854 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
14855 dev->netdev_ops = &tg3_netdev_ops;
14857 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14860 /* The EPB bridge inside 5714, 5715, and 5780 and any
14861 * device behind the EPB cannot support DMA addresses > 40-bit.
14862 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14863 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14864 * do DMA address check in tg3_start_xmit().
14866 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14867 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14868 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14869 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14870 #ifdef CONFIG_HIGHMEM
14871 dma_mask = DMA_BIT_MASK(64);
14874 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14876 /* Configure DMA attributes. */
14877 if (dma_mask > DMA_BIT_MASK(32)) {
14878 err = pci_set_dma_mask(pdev, dma_mask);
14880 dev->features |= NETIF_F_HIGHDMA;
14881 err = pci_set_consistent_dma_mask(pdev,
14884 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14885 "DMA for consistent allocations\n");
14886 goto err_out_iounmap;
14890 if (err || dma_mask == DMA_BIT_MASK(32)) {
14891 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14893 dev_err(&pdev->dev,
14894 "No usable DMA configuration, aborting\n");
14895 goto err_out_iounmap;
14899 tg3_init_bufmgr_config(tp);
14901 /* Selectively allow TSO based on operating conditions */
14902 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14903 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14904 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14906 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14907 tp->fw_needed = NULL;
14910 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14911 tp->fw_needed = FIRMWARE_TG3;
14913 /* TSO is on by default on chips that support hardware TSO.
14914 * Firmware TSO on older chips gives lower performance, so it
14915 * is off by default, but can be enabled using ethtool.
14917 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14918 (dev->features & NETIF_F_IP_CSUM))
14919 hw_features |= NETIF_F_TSO;
14920 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14921 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14922 if (dev->features & NETIF_F_IPV6_CSUM)
14923 hw_features |= NETIF_F_TSO6;
14924 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14926 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14927 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14930 hw_features |= NETIF_F_TSO_ECN;
14933 dev->hw_features |= hw_features;
14934 dev->features |= hw_features;
14935 dev->vlan_features |= hw_features;
14937 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14938 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14939 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14940 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14941 tp->rx_pending = 63;
14944 err = tg3_get_device_address(tp);
14946 dev_err(&pdev->dev,
14947 "Could not obtain valid ethernet address, aborting\n");
14948 goto err_out_iounmap;
14951 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14952 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14953 if (!tp->aperegs) {
14954 dev_err(&pdev->dev,
14955 "Cannot map APE registers, aborting\n");
14957 goto err_out_iounmap;
14960 tg3_ape_lock_init(tp);
14962 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14963 tg3_read_dash_ver(tp);
14967 * Reset chip in case UNDI or EFI driver did not shutdown
14968 * DMA self test will enable WDMAC and we'll see (spurious)
14969 * pending DMA on the PCI bus at that point.
14971 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14972 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14973 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14974 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14977 err = tg3_test_dma(tp);
14979 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14980 goto err_out_apeunmap;
14983 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14984 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14985 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14986 for (i = 0; i < tp->irq_max; i++) {
14987 struct tg3_napi *tnapi = &tp->napi[i];
14990 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14992 tnapi->int_mbox = intmbx;
14998 tnapi->consmbox = rcvmbx;
14999 tnapi->prodmbox = sndmbx;
15002 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15004 tnapi->coal_now = HOSTCC_MODE_NOW;
15006 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
15010 * If we support MSIX, we'll be using RSS. If we're using
15011 * RSS, the first vector only handles link interrupts and the
15012 * remaining vectors handle rx and tx interrupts. Reuse the
15013 * mailbox values for the next iteration. The values we setup
15014 * above are still useful for the single vectored mode.
15029 pci_set_drvdata(pdev, dev);
15031 err = register_netdev(dev);
15033 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15034 goto err_out_apeunmap;
15037 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15038 tp->board_part_number,
15039 tp->pci_chip_rev_id,
15040 tg3_bus_string(tp, str),
15043 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15044 struct phy_device *phydev;
15045 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15047 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15048 phydev->drv->name, dev_name(&phydev->dev));
15052 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15053 ethtype = "10/100Base-TX";
15054 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15055 ethtype = "1000Base-SX";
15057 ethtype = "10/100/1000Base-T";
15059 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15060 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
15061 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
15064 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15065 (dev->features & NETIF_F_RXCSUM) != 0,
15066 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
15067 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15068 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
15069 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
15070 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15072 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15073 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15079 iounmap(tp->aperegs);
15080 tp->aperegs = NULL;
15093 pci_release_regions(pdev);
15095 err_out_disable_pdev:
15096 pci_disable_device(pdev);
15097 pci_set_drvdata(pdev, NULL);
15101 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15103 struct net_device *dev = pci_get_drvdata(pdev);
15106 struct tg3 *tp = netdev_priv(dev);
15109 release_firmware(tp->fw);
15111 cancel_work_sync(&tp->reset_task);
15113 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15118 unregister_netdev(dev);
15120 iounmap(tp->aperegs);
15121 tp->aperegs = NULL;
15128 pci_release_regions(pdev);
15129 pci_disable_device(pdev);
15130 pci_set_drvdata(pdev, NULL);
15134 #ifdef CONFIG_PM_SLEEP
15135 static int tg3_suspend(struct device *device)
15137 struct pci_dev *pdev = to_pci_dev(device);
15138 struct net_device *dev = pci_get_drvdata(pdev);
15139 struct tg3 *tp = netdev_priv(dev);
15142 if (!netif_running(dev))
15145 flush_work_sync(&tp->reset_task);
15147 tg3_netif_stop(tp);
15149 del_timer_sync(&tp->timer);
15151 tg3_full_lock(tp, 1);
15152 tg3_disable_ints(tp);
15153 tg3_full_unlock(tp);
15155 netif_device_detach(dev);
15157 tg3_full_lock(tp, 0);
15158 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15159 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15160 tg3_full_unlock(tp);
15162 err = tg3_power_down_prepare(tp);
15166 tg3_full_lock(tp, 0);
15168 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15169 err2 = tg3_restart_hw(tp, 1);
15173 tp->timer.expires = jiffies + tp->timer_offset;
15174 add_timer(&tp->timer);
15176 netif_device_attach(dev);
15177 tg3_netif_start(tp);
15180 tg3_full_unlock(tp);
15189 static int tg3_resume(struct device *device)
15191 struct pci_dev *pdev = to_pci_dev(device);
15192 struct net_device *dev = pci_get_drvdata(pdev);
15193 struct tg3 *tp = netdev_priv(dev);
15196 if (!netif_running(dev))
15199 netif_device_attach(dev);
15201 tg3_full_lock(tp, 0);
15203 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15204 err = tg3_restart_hw(tp, 1);
15208 tp->timer.expires = jiffies + tp->timer_offset;
15209 add_timer(&tp->timer);
15211 tg3_netif_start(tp);
15214 tg3_full_unlock(tp);
15222 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15223 #define TG3_PM_OPS (&tg3_pm_ops)
15227 #define TG3_PM_OPS NULL
15229 #endif /* CONFIG_PM_SLEEP */
15231 static struct pci_driver tg3_driver = {
15232 .name = DRV_MODULE_NAME,
15233 .id_table = tg3_pci_tbl,
15234 .probe = tg3_init_one,
15235 .remove = __devexit_p(tg3_remove_one),
15236 .driver.pm = TG3_PM_OPS,
15239 static int __init tg3_init(void)
15241 return pci_register_driver(&tg3_driver);
15244 static void __exit tg3_cleanup(void)
15246 pci_unregister_driver(&tg3_driver);
15249 module_init(tg3_init);
15250 module_exit(tg3_cleanup);