drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2011 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mdio.h>
  36 #include <linux/mii.h>
  37 #include <linux/phy.h>
  38 #include <linux/brcmphy.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/ip.h>
  41 #include <linux/tcp.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/firmware.h>
  46
  47 #include <net/checksum.h>
  48 #include <net/ip.h>
  49
  50 #include <asm/system.h>
  51 #include <linux/io.h>
  52 #include <asm/byteorder.h>
  53 #include <linux/uaccess.h>
  54
  55 #ifdef CONFIG_SPARC
  56 #include <asm/idprom.h>
  57 #include <asm/prom.h>
  58 #endif
  59
  60 #define BAR_0   0
  61 #define BAR_2   2
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define TG3_MAJ_NUM                     3
  67 #define TG3_MIN_NUM                     117
  68 #define DRV_MODULE_VERSION      \
  69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  70 #define DRV_MODULE_RELDATE      "January 25, 2011"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_STD_RING_SIZE(tp) \
 100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JMB_RING_SIZE(tp) \
 104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 107 #define TG3_RSS_INDIR_TBL_SIZE          128
 108
 109 /* Do not place this n-ring entries value into the tp struct itself,
 110  * we really want to expose these constants to GCC so that modulo et
 111  * al.  operations are done with shifts and masks instead of with
 112  * hw multiply/modulo instructions.  Another solution would be to
 113  * replace things like '% foo' with '& (foo - 1)'.
 114  */
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_STD_RING_BYTES(tp) \
 120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 121 #define TG3_RX_JMB_RING_BYTES(tp) \
 122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 123 #define TG3_RX_RCB_RING_BYTES(tp) \
 124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 141
 142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 144
 145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 146  * that are at least dword aligned when used in PCIX mode.  The driver
 147  * works around this bug by double copying the packet.  This workaround
 148  * is built into the normal double copy length check for efficiency.
 149  *
 150  * However, the double copy is only necessary on those architectures
 151  * where unaligned memory accesses are inefficient.  For those architectures
 152  * where unaligned memory accesses incur little penalty, we can reintegrate
 153  * the 5701 in the normal rx path.  Doing so saves a device structure
 154  * dereference by hardcoding the double copy threshold in place.
 155  */
 156 #define TG3_RX_COPY_THRESHOLD           256
 157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 159 #else
 160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 161 #endif
 162
 163 /* minimum number of free TX descriptors required to wake up TX process */
 164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 165
 166 #define TG3_RAW_IP_ALIGN 2
 167
 168 /* number of ETHTOOL_GSTATS u64's */
 169 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 170
 171 #define TG3_NUM_TEST            6
 172
 173 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 174
 175 #define FIRMWARE_TG3            "tigon/tg3.bin"
 176 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 177 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 178
 179 static char version[] __devinitdata =
 180         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 181
 182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 184 MODULE_LICENSE("GPL");
 185 MODULE_VERSION(DRV_MODULE_VERSION);
 186 MODULE_FIRMWARE(FIRMWARE_TG3);
 187 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 189
 190 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 191 module_param(tg3_debug, int, 0);
 192 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 193
 194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 274         {}
 275 };
 276
 277 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 278
 279 static const struct {
 280         const char string[ETH_GSTRING_LEN];
 281 } ethtool_stats_keys[TG3_NUM_STATS] = {
 282         { "rx_octets" },
 283         { "rx_fragments" },
 284         { "rx_ucast_packets" },
 285         { "rx_mcast_packets" },
 286         { "rx_bcast_packets" },
 287         { "rx_fcs_errors" },
 288         { "rx_align_errors" },
 289         { "rx_xon_pause_rcvd" },
 290         { "rx_xoff_pause_rcvd" },
 291         { "rx_mac_ctrl_rcvd" },
 292         { "rx_xoff_entered" },
 293         { "rx_frame_too_long_errors" },
 294         { "rx_jabbers" },
 295         { "rx_undersize_packets" },
 296         { "rx_in_length_errors" },
 297         { "rx_out_length_errors" },
 298         { "rx_64_or_less_octet_packets" },
 299         { "rx_65_to_127_octet_packets" },
 300         { "rx_128_to_255_octet_packets" },
 301         { "rx_256_to_511_octet_packets" },
 302         { "rx_512_to_1023_octet_packets" },
 303         { "rx_1024_to_1522_octet_packets" },
 304         { "rx_1523_to_2047_octet_packets" },
 305         { "rx_2048_to_4095_octet_packets" },
 306         { "rx_4096_to_8191_octet_packets" },
 307         { "rx_8192_to_9022_octet_packets" },
 308
 309         { "tx_octets" },
 310         { "tx_collisions" },
 311
 312         { "tx_xon_sent" },
 313         { "tx_xoff_sent" },
 314         { "tx_flow_control" },
 315         { "tx_mac_errors" },
 316         { "tx_single_collisions" },
 317         { "tx_mult_collisions" },
 318         { "tx_deferred" },
 319         { "tx_excessive_collisions" },
 320         { "tx_late_collisions" },
 321         { "tx_collide_2times" },
 322         { "tx_collide_3times" },
 323         { "tx_collide_4times" },
 324         { "tx_collide_5times" },
 325         { "tx_collide_6times" },
 326         { "tx_collide_7times" },
 327         { "tx_collide_8times" },
 328         { "tx_collide_9times" },
 329         { "tx_collide_10times" },
 330         { "tx_collide_11times" },
 331         { "tx_collide_12times" },
 332         { "tx_collide_13times" },
 333         { "tx_collide_14times" },
 334         { "tx_collide_15times" },
 335         { "tx_ucast_packets" },
 336         { "tx_mcast_packets" },
 337         { "tx_bcast_packets" },
 338         { "tx_carrier_sense_errors" },
 339         { "tx_discards" },
 340         { "tx_errors" },
 341
 342         { "dma_writeq_full" },
 343         { "dma_write_prioq_full" },
 344         { "rxbds_empty" },
 345         { "rx_discards" },
 346         { "rx_errors" },
 347         { "rx_threshold_hit" },
 348
 349         { "dma_readq_full" },
 350         { "dma_read_prioq_full" },
 351         { "tx_comp_queue_full" },
 352
 353         { "ring_set_send_prod_index" },
 354         { "ring_status_update" },
 355         { "nic_irqs" },
 356         { "nic_avoided_irqs" },
 357         { "nic_tx_threshold_hit" }
 358 };
 359
 360 static const struct {
 361         const char string[ETH_GSTRING_LEN];
 362 } ethtool_test_keys[TG3_NUM_TEST] = {
 363         { "nvram test     (online) " },
 364         { "link test      (online) " },
 365         { "register test  (offline)" },
 366         { "memory test    (offline)" },
 367         { "loopback test  (offline)" },
 368         { "interrupt test (offline)" },
 369 };
 370
 371 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         writel(val, tp->regs + off);
 374 }
 375
 376 static u32 tg3_read32(struct tg3 *tp, u32 off)
 377 {
 378         return readl(tp->regs + off);
 379 }
 380
 381 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->aperegs + off);
 384 }
 385
 386 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 387 {
 388         return readl(tp->aperegs + off);
 389 }
 390
 391 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 392 {
 393         unsigned long flags;
 394
 395         spin_lock_irqsave(&tp->indirect_lock, flags);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 398         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 399 }
 400
 401 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         writel(val, tp->regs + off);
 404         readl(tp->regs + off);
 405 }
 406
 407 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 408 {
 409         unsigned long flags;
 410         u32 val;
 411
 412         spin_lock_irqsave(&tp->indirect_lock, flags);
 413         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 414         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 415         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 416         return val;
 417 }
 418
 419 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 420 {
 421         unsigned long flags;
 422
 423         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 425                                        TG3_64BIT_REG_LOW, val);
 426                 return;
 427         }
 428         if (off == TG3_RX_STD_PROD_IDX_REG) {
 429                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 430                                        TG3_64BIT_REG_LOW, val);
 431                 return;
 432         }
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438
 439         /* In indirect mode when disabling interrupts, we also need
 440          * to clear the interrupt bit in the GRC local ctrl register.
 441          */
 442         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 443             (val == 0x1)) {
 444                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 445                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 446         }
 447 }
 448
 449 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 450 {
 451         unsigned long flags;
 452         u32 val;
 453
 454         spin_lock_irqsave(&tp->indirect_lock, flags);
 455         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 456         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 457         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 458         return val;
 459 }
 460
 461 /* usec_wait specifies the wait time in usec when writing to certain registers
 462  * where it is unsafe to read back the register without some delay.
 463  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 464  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 465  */
 466 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 467 {
 468         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 469             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 470                 /* Non-posted methods */
 471                 tp->write32(tp, off, val);
 472         else {
 473                 /* Posted method */
 474                 tg3_write32(tp, off, val);
 475                 if (usec_wait)
 476                         udelay(usec_wait);
 477                 tp->read32(tp, off);
 478         }
 479         /* Wait again after the read for the posted method to guarantee that
 480          * the wait time is met.
 481          */
 482         if (usec_wait)
 483                 udelay(usec_wait);
 484 }
 485
 486 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 487 {
 488         tp->write32_mbox(tp, off, val);
 489         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 490             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 491                 tp->read32_mbox(tp, off);
 492 }
 493
 494 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         void __iomem *mbox = tp->regs + off;
 497         writel(val, mbox);
 498         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 499                 writel(val, mbox);
 500         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 501                 readl(mbox);
 502 }
 503
 504 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 505 {
 506         return readl(tp->regs + off + GRCMBOX_BASE);
 507 }
 508
 509 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 510 {
 511         writel(val, tp->regs + off + GRCMBOX_BASE);
 512 }
 513
 514 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 515 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 516 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 517 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 518 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 519
 520 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 521 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 522 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 523 #define tr32(reg)                       tp->read32(tp, reg)
 524
 525 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 526 {
 527         unsigned long flags;
 528
 529         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 530             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 531                 return;
 532
 533         spin_lock_irqsave(&tp->indirect_lock, flags);
 534         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 535                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 536                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 537
 538                 /* Always leave this as zero. */
 539                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 540         } else {
 541                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 542                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 543
 544                 /* Always leave this as zero. */
 545                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 546         }
 547         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 548 }
 549
 550 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 551 {
 552         unsigned long flags;
 553
 554         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 555             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 556                 *val = 0;
 557                 return;
 558         }
 559
 560         spin_lock_irqsave(&tp->indirect_lock, flags);
 561         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 562                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 563                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 564
 565                 /* Always leave this as zero. */
 566                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 567         } else {
 568                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 569                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 570
 571                 /* Always leave this as zero. */
 572                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 573         }
 574         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 575 }
 576
 577 static void tg3_ape_lock_init(struct tg3 *tp)
 578 {
 579         int i;
 580         u32 regbase;
 581
 582         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 583                 regbase = TG3_APE_LOCK_GRANT;
 584         else
 585                 regbase = TG3_APE_PER_LOCK_GRANT;
 586
 587         /* Make sure the driver hasn't any stale locks. */
 588         for (i = 0; i < 8; i++)
 589                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 590 }
 591
 592 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 593 {
 594         int i, off;
 595         int ret = 0;
 596         u32 status, req, gnt;
 597
 598         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 599                 return 0;
 600
 601         switch (locknum) {
 602         case TG3_APE_LOCK_GRC:
 603         case TG3_APE_LOCK_MEM:
 604                 break;
 605         default:
 606                 return -EINVAL;
 607         }
 608
 609         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 610                 req = TG3_APE_LOCK_REQ;
 611                 gnt = TG3_APE_LOCK_GRANT;
 612         } else {
 613                 req = TG3_APE_PER_LOCK_REQ;
 614                 gnt = TG3_APE_PER_LOCK_GRANT;
 615         }
 616
 617         off = 4 * locknum;
 618
 619         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 620
 621         /* Wait for up to 1 millisecond to acquire lock. */
 622         for (i = 0; i < 100; i++) {
 623                 status = tg3_ape_read32(tp, gnt + off);
 624                 if (status == APE_LOCK_GRANT_DRIVER)
 625                         break;
 626                 udelay(10);
 627         }
 628
 629         if (status != APE_LOCK_GRANT_DRIVER) {
 630                 /* Revoke the lock request. */
 631                 tg3_ape_write32(tp, gnt + off,
 632                                 APE_LOCK_GRANT_DRIVER);
 633
 634                 ret = -EBUSY;
 635         }
 636
 637         return ret;
 638 }
 639
 640 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 641 {
 642         u32 gnt;
 643
 644         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 645                 return;
 646
 647         switch (locknum) {
 648         case TG3_APE_LOCK_GRC:
 649         case TG3_APE_LOCK_MEM:
 650                 break;
 651         default:
 652                 return;
 653         }
 654
 655         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 656                 gnt = TG3_APE_LOCK_GRANT;
 657         else
 658                 gnt = TG3_APE_PER_LOCK_GRANT;
 659
 660         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 661 }
 662
 663 static void tg3_disable_ints(struct tg3 *tp)
 664 {
 665         int i;
 666
 667         tw32(TG3PCI_MISC_HOST_CTRL,
 668              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 669         for (i = 0; i < tp->irq_max; i++)
 670                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 671 }
 672
 673 static void tg3_enable_ints(struct tg3 *tp)
 674 {
 675         int i;
 676
 677         tp->irq_sync = 0;
 678         wmb();
 679
 680         tw32(TG3PCI_MISC_HOST_CTRL,
 681              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 682
 683         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 684         for (i = 0; i < tp->irq_cnt; i++) {
 685                 struct tg3_napi *tnapi = &tp->napi[i];
 686
 687                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 688                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 689                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 690
 691                 tp->coal_now |= tnapi->coal_now;
 692         }
 693
 694         /* Force an initial interrupt */
 695         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 696             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 697                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 698         else
 699                 tw32(HOSTCC_MODE, tp->coal_now);
 700
 701         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 702 }
 703
 704 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 705 {
 706         struct tg3 *tp = tnapi->tp;
 707         struct tg3_hw_status *sblk = tnapi->hw_status;
 708         unsigned int work_exists = 0;
 709
 710         /* check for phy events */
 711         if (!(tp->tg3_flags &
 712               (TG3_FLAG_USE_LINKCHG_REG |
 713                TG3_FLAG_POLL_SERDES))) {
 714                 if (sblk->status & SD_STATUS_LINK_CHG)
 715                         work_exists = 1;
 716         }
 717         /* check for RX/TX work to do */
 718         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 719             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 720                 work_exists = 1;
 721
 722         return work_exists;
 723 }
 724
 725 /* tg3_int_reenable
 726  *  similar to tg3_enable_ints, but it accurately determines whether there
 727  *  is new work pending and can return without flushing the PIO write
 728  *  which reenables interrupts
 729  */
 730 static void tg3_int_reenable(struct tg3_napi *tnapi)
 731 {
 732         struct tg3 *tp = tnapi->tp;
 733
 734         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 735         mmiowb();
 736
 737         /* When doing tagged status, this work check is unnecessary.
 738          * The last_tag we write above tells the chip which piece of
 739          * work we've completed.
 740          */
 741         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 742             tg3_has_work(tnapi))
 743                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 744                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 745 }
 746
 747 static void tg3_switch_clocks(struct tg3 *tp)
 748 {
 749         u32 clock_ctrl;
 750         u32 orig_clock_ctrl;
 751
 752         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 753             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 754                 return;
 755
 756         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 757
 758         orig_clock_ctrl = clock_ctrl;
 759         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 760                        CLOCK_CTRL_CLKRUN_OENABLE |
 761                        0x1f);
 762         tp->pci_clock_ctrl = clock_ctrl;
 763
 764         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 765                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 766                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 767                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 768                 }
 769         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 770                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 771                             clock_ctrl |
 772                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 773                             40);
 774                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 775                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 776                             40);
 777         }
 778         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 779 }
 780
 781 #define PHY_BUSY_LOOPS  5000
 782
 783 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 784 {
 785         u32 frame_val;
 786         unsigned int loops;
 787         int ret;
 788
 789         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 790                 tw32_f(MAC_MI_MODE,
 791                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 792                 udelay(80);
 793         }
 794
 795         *val = 0x0;
 796
 797         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 798                       MI_COM_PHY_ADDR_MASK);
 799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 800                       MI_COM_REG_ADDR_MASK);
 801         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 802
 803         tw32_f(MAC_MI_COM, frame_val);
 804
 805         loops = PHY_BUSY_LOOPS;
 806         while (loops != 0) {
 807                 udelay(10);
 808                 frame_val = tr32(MAC_MI_COM);
 809
 810                 if ((frame_val & MI_COM_BUSY) == 0) {
 811                         udelay(5);
 812                         frame_val = tr32(MAC_MI_COM);
 813                         break;
 814                 }
 815                 loops -= 1;
 816         }
 817
 818         ret = -EBUSY;
 819         if (loops != 0) {
 820                 *val = frame_val & MI_COM_DATA_MASK;
 821                 ret = 0;
 822         }
 823
 824         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 825                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 826                 udelay(80);
 827         }
 828
 829         return ret;
 830 }
 831
 832 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 833 {
 834         u32 frame_val;
 835         unsigned int loops;
 836         int ret;
 837
 838         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 839             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 840                 return 0;
 841
 842         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 843                 tw32_f(MAC_MI_MODE,
 844                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 845                 udelay(80);
 846         }
 847
 848         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 849                       MI_COM_PHY_ADDR_MASK);
 850         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 851                       MI_COM_REG_ADDR_MASK);
 852         frame_val |= (val & MI_COM_DATA_MASK);
 853         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 854
 855         tw32_f(MAC_MI_COM, frame_val);
 856
 857         loops = PHY_BUSY_LOOPS;
 858         while (loops != 0) {
 859                 udelay(10);
 860                 frame_val = tr32(MAC_MI_COM);
 861                 if ((frame_val & MI_COM_BUSY) == 0) {
 862                         udelay(5);
 863                         frame_val = tr32(MAC_MI_COM);
 864                         break;
 865                 }
 866                 loops -= 1;
 867         }
 868
 869         ret = -EBUSY;
 870         if (loops != 0)
 871                 ret = 0;
 872
 873         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 874                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 875                 udelay(80);
 876         }
 877
 878         return ret;
 879 }
 880
 881 static int tg3_bmcr_reset(struct tg3 *tp)
 882 {
 883         u32 phy_control;
 884         int limit, err;
 885
 886         /* OK, reset it, and poll the BMCR_RESET bit until it
 887          * clears or we time out.
 888          */
 889         phy_control = BMCR_RESET;
 890         err = tg3_writephy(tp, MII_BMCR, phy_control);
 891         if (err != 0)
 892                 return -EBUSY;
 893
 894         limit = 5000;
 895         while (limit--) {
 896                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 897                 if (err != 0)
 898                         return -EBUSY;
 899
 900                 if ((phy_control & BMCR_RESET) == 0) {
 901                         udelay(40);
 902                         break;
 903                 }
 904                 udelay(10);
 905         }
 906         if (limit < 0)
 907                 return -EBUSY;
 908
 909         return 0;
 910 }
 911
 912 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 913 {
 914         struct tg3 *tp = bp->priv;
 915         u32 val;
 916
 917         spin_lock_bh(&tp->lock);
 918
 919         if (tg3_readphy(tp, reg, &val))
 920                 val = -EIO;
 921
 922         spin_unlock_bh(&tp->lock);
 923
 924         return val;
 925 }
 926
 927 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 928 {
 929         struct tg3 *tp = bp->priv;
 930         u32 ret = 0;
 931
 932         spin_lock_bh(&tp->lock);
 933
 934         if (tg3_writephy(tp, reg, val))
 935                 ret = -EIO;
 936
 937         spin_unlock_bh(&tp->lock);
 938
 939         return ret;
 940 }
 941
 942 static int tg3_mdio_reset(struct mii_bus *bp)
 943 {
 944         return 0;
 945 }
 946
 947 static void tg3_mdio_config_5785(struct tg3 *tp)
 948 {
 949         u32 val;
 950         struct phy_device *phydev;
 951
 952         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 953         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 954         case PHY_ID_BCM50610:
 955         case PHY_ID_BCM50610M:
 956                 val = MAC_PHYCFG2_50610_LED_MODES;
 957                 break;
 958         case PHY_ID_BCMAC131:
 959                 val = MAC_PHYCFG2_AC131_LED_MODES;
 960                 break;
 961         case PHY_ID_RTL8211C:
 962                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 963                 break;
 964         case PHY_ID_RTL8201E:
 965                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 966                 break;
 967         default:
 968                 return;
 969         }
 970
 971         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 972                 tw32(MAC_PHYCFG2, val);
 973
 974                 val = tr32(MAC_PHYCFG1);
 975                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 976                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 977                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 978                 tw32(MAC_PHYCFG1, val);
 979
 980                 return;
 981         }
 982
 983         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 984                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 985                        MAC_PHYCFG2_FMODE_MASK_MASK |
 986                        MAC_PHYCFG2_GMODE_MASK_MASK |
 987                        MAC_PHYCFG2_ACT_MASK_MASK   |
 988                        MAC_PHYCFG2_QUAL_MASK_MASK |
 989                        MAC_PHYCFG2_INBAND_ENABLE;
 990
 991         tw32(MAC_PHYCFG2, val);
 992
 993         val = tr32(MAC_PHYCFG1);
 994         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 995                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 996         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
 997                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 998                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1001         }
1002         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1003                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1004         tw32(MAC_PHYCFG1, val);
1005
1006         val = tr32(MAC_EXT_RGMII_MODE);
1007         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1008                  MAC_RGMII_MODE_RX_QUALITY |
1009                  MAC_RGMII_MODE_RX_ACTIVITY |
1010                  MAC_RGMII_MODE_RX_ENG_DET |
1011                  MAC_RGMII_MODE_TX_ENABLE |
1012                  MAC_RGMII_MODE_TX_LOWPWR |
1013                  MAC_RGMII_MODE_TX_RESET);
1014         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1015                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1016                         val |= MAC_RGMII_MODE_RX_INT_B |
1017                                MAC_RGMII_MODE_RX_QUALITY |
1018                                MAC_RGMII_MODE_RX_ACTIVITY |
1019                                MAC_RGMII_MODE_RX_ENG_DET;
1020                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1021                         val |= MAC_RGMII_MODE_TX_ENABLE |
1022                                MAC_RGMII_MODE_TX_LOWPWR |
1023                                MAC_RGMII_MODE_TX_RESET;
1024         }
1025         tw32(MAC_EXT_RGMII_MODE, val);
1026 }
1027
1028 static void tg3_mdio_start(struct tg3 *tp)
1029 {
1030         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1031         tw32_f(MAC_MI_MODE, tp->mi_mode);
1032         udelay(80);
1033
1034         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1036                 tg3_mdio_config_5785(tp);
1037 }
1038
1039 static int tg3_mdio_init(struct tg3 *tp)
1040 {
1041         int i;
1042         u32 reg;
1043         struct phy_device *phydev;
1044
1045         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1046                 u32 is_serdes;
1047
1048                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1049
1050                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1051                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1052                 else
1053                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1054                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1055                 if (is_serdes)
1056                         tp->phy_addr += 7;
1057         } else
1058                 tp->phy_addr = TG3_PHY_MII_ADDR;
1059
1060         tg3_mdio_start(tp);
1061
1062         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1063             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1064                 return 0;
1065
1066         tp->mdio_bus = mdiobus_alloc();
1067         if (tp->mdio_bus == NULL)
1068                 return -ENOMEM;
1069
1070         tp->mdio_bus->name     = "tg3 mdio bus";
1071         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1072                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1073         tp->mdio_bus->priv     = tp;
1074         tp->mdio_bus->parent   = &tp->pdev->dev;
1075         tp->mdio_bus->read     = &tg3_mdio_read;
1076         tp->mdio_bus->write    = &tg3_mdio_write;
1077         tp->mdio_bus->reset    = &tg3_mdio_reset;
1078         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1079         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1080
1081         for (i = 0; i < PHY_MAX_ADDR; i++)
1082                 tp->mdio_bus->irq[i] = PHY_POLL;
1083
1084         /* The bus registration will look for all the PHYs on the mdio bus.
1085          * Unfortunately, it does not ensure the PHY is powered up before
1086          * accessing the PHY ID registers.  A chip reset is the
1087          * quickest way to bring the device back to an operational state..
1088          */
1089         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1090                 tg3_bmcr_reset(tp);
1091
1092         i = mdiobus_register(tp->mdio_bus);
1093         if (i) {
1094                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1095                 mdiobus_free(tp->mdio_bus);
1096                 return i;
1097         }
1098
1099         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1100
1101         if (!phydev || !phydev->drv) {
1102                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1103                 mdiobus_unregister(tp->mdio_bus);
1104                 mdiobus_free(tp->mdio_bus);
1105                 return -ENODEV;
1106         }
1107
1108         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1109         case PHY_ID_BCM57780:
1110                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1111                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1112                 break;
1113         case PHY_ID_BCM50610:
1114         case PHY_ID_BCM50610M:
1115                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1116                                      PHY_BRCM_RX_REFCLK_UNUSED |
1117                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1118                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1120                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1123                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1124                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1125                 /* fallthru */
1126         case PHY_ID_RTL8211C:
1127                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1128                 break;
1129         case PHY_ID_RTL8201E:
1130         case PHY_ID_BCMAC131:
1131                 phydev->interface = PHY_INTERFACE_MODE_MII;
1132                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1133                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1134                 break;
1135         }
1136
1137         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1138
1139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1140                 tg3_mdio_config_5785(tp);
1141
1142         return 0;
1143 }
1144
1145 static void tg3_mdio_fini(struct tg3 *tp)
1146 {
1147         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1148                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1149                 mdiobus_unregister(tp->mdio_bus);
1150                 mdiobus_free(tp->mdio_bus);
1151         }
1152 }
1153
1154 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1155 {
1156         int err;
1157
1158         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1159         if (err)
1160                 goto done;
1161
1162         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1163         if (err)
1164                 goto done;
1165
1166         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1167                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1168         if (err)
1169                 goto done;
1170
1171         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1172
1173 done:
1174         return err;
1175 }
1176
1177 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1178 {
1179         int err;
1180
1181         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1182         if (err)
1183                 goto done;
1184
1185         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1186         if (err)
1187                 goto done;
1188
1189         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1190                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1191         if (err)
1192                 goto done;
1193
1194         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1195
1196 done:
1197         return err;
1198 }
1199
1200 /* tp->lock is held. */
1201 static inline void tg3_generate_fw_event(struct tg3 *tp)
1202 {
1203         u32 val;
1204
1205         val = tr32(GRC_RX_CPU_EVENT);
1206         val |= GRC_RX_CPU_DRIVER_EVENT;
1207         tw32_f(GRC_RX_CPU_EVENT, val);
1208
1209         tp->last_event_jiffies = jiffies;
1210 }
1211
1212 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1213
1214 /* tp->lock is held. */
1215 static void tg3_wait_for_event_ack(struct tg3 *tp)
1216 {
1217         int i;
1218         unsigned int delay_cnt;
1219         long time_remain;
1220
1221         /* If enough time has passed, no wait is necessary. */
1222         time_remain = (long)(tp->last_event_jiffies + 1 +
1223                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1224                       (long)jiffies;
1225         if (time_remain < 0)
1226                 return;
1227
1228         /* Check if we can shorten the wait time. */
1229         delay_cnt = jiffies_to_usecs(time_remain);
1230         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1231                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1232         delay_cnt = (delay_cnt >> 3) + 1;
1233
1234         for (i = 0; i < delay_cnt; i++) {
1235                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1236                         break;
1237                 udelay(8);
1238         }
1239 }
1240
1241 /* tp->lock is held. */
1242 static void tg3_ump_link_report(struct tg3 *tp)
1243 {
1244         u32 reg;
1245         u32 val;
1246
1247         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1248             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1249                 return;
1250
1251         tg3_wait_for_event_ack(tp);
1252
1253         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1256
1257         val = 0;
1258         if (!tg3_readphy(tp, MII_BMCR, &reg))
1259                 val = reg << 16;
1260         if (!tg3_readphy(tp, MII_BMSR, &reg))
1261                 val |= (reg & 0xffff);
1262         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1263
1264         val = 0;
1265         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1266                 val = reg << 16;
1267         if (!tg3_readphy(tp, MII_LPA, &reg))
1268                 val |= (reg & 0xffff);
1269         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1270
1271         val = 0;
1272         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1273                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1274                         val = reg << 16;
1275                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1276                         val |= (reg & 0xffff);
1277         }
1278         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1279
1280         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1281                 val = reg << 16;
1282         else
1283                 val = 0;
1284         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1285
1286         tg3_generate_fw_event(tp);
1287 }
1288
1289 static void tg3_link_report(struct tg3 *tp)
1290 {
1291         if (!netif_carrier_ok(tp->dev)) {
1292                 netif_info(tp, link, tp->dev, "Link is down\n");
1293                 tg3_ump_link_report(tp);
1294         } else if (netif_msg_link(tp)) {
1295                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1296                             (tp->link_config.active_speed == SPEED_1000 ?
1297                              1000 :
1298                              (tp->link_config.active_speed == SPEED_100 ?
1299                               100 : 10)),
1300                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1301                              "full" : "half"));
1302
1303                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1304                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1305                             "on" : "off",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1307                             "on" : "off");
1308                 tg3_ump_link_report(tp);
1309         }
1310 }
1311
1312 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1313 {
1314         u16 miireg;
1315
1316         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1317                 miireg = ADVERTISE_PAUSE_CAP;
1318         else if (flow_ctrl & FLOW_CTRL_TX)
1319                 miireg = ADVERTISE_PAUSE_ASYM;
1320         else if (flow_ctrl & FLOW_CTRL_RX)
1321                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1322         else
1323                 miireg = 0;
1324
1325         return miireg;
1326 }
1327
1328 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1329 {
1330         u16 miireg;
1331
1332         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1333                 miireg = ADVERTISE_1000XPAUSE;
1334         else if (flow_ctrl & FLOW_CTRL_TX)
1335                 miireg = ADVERTISE_1000XPSE_ASYM;
1336         else if (flow_ctrl & FLOW_CTRL_RX)
1337                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1338         else
1339                 miireg = 0;
1340
1341         return miireg;
1342 }
1343
1344 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1345 {
1346         u8 cap = 0;
1347
1348         if (lcladv & ADVERTISE_1000XPAUSE) {
1349                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1350                         if (rmtadv & LPA_1000XPAUSE)
1351                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1352                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1353                                 cap = FLOW_CTRL_RX;
1354                 } else {
1355                         if (rmtadv & LPA_1000XPAUSE)
1356                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1357                 }
1358         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1359                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1360                         cap = FLOW_CTRL_TX;
1361         }
1362
1363         return cap;
1364 }
1365
1366 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1367 {
1368         u8 autoneg;
1369         u8 flowctrl = 0;
1370         u32 old_rx_mode = tp->rx_mode;
1371         u32 old_tx_mode = tp->tx_mode;
1372
1373         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1374                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1375         else
1376                 autoneg = tp->link_config.autoneg;
1377
1378         if (autoneg == AUTONEG_ENABLE &&
1379             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1380                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1381                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1382                 else
1383                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1384         } else
1385                 flowctrl = tp->link_config.flowctrl;
1386
1387         tp->link_config.active_flowctrl = flowctrl;
1388
1389         if (flowctrl & FLOW_CTRL_RX)
1390                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1391         else
1392                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1393
1394         if (old_rx_mode != tp->rx_mode)
1395                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1396
1397         if (flowctrl & FLOW_CTRL_TX)
1398                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1399         else
1400                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1401
1402         if (old_tx_mode != tp->tx_mode)
1403                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1404 }
1405
1406 static void tg3_adjust_link(struct net_device *dev)
1407 {
1408         u8 oldflowctrl, linkmesg = 0;
1409         u32 mac_mode, lcl_adv, rmt_adv;
1410         struct tg3 *tp = netdev_priv(dev);
1411         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1412
1413         spin_lock_bh(&tp->lock);
1414
1415         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1416                                     MAC_MODE_HALF_DUPLEX);
1417
1418         oldflowctrl = tp->link_config.active_flowctrl;
1419
1420         if (phydev->link) {
1421                 lcl_adv = 0;
1422                 rmt_adv = 0;
1423
1424                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1425                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1426                 else if (phydev->speed == SPEED_1000 ||
1427                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1428                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1429                 else
1430                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1431
1432                 if (phydev->duplex == DUPLEX_HALF)
1433                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1434                 else {
1435                         lcl_adv = tg3_advert_flowctrl_1000T(
1436                                   tp->link_config.flowctrl);
1437
1438                         if (phydev->pause)
1439                                 rmt_adv = LPA_PAUSE_CAP;
1440                         if (phydev->asym_pause)
1441                                 rmt_adv |= LPA_PAUSE_ASYM;
1442                 }
1443
1444                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1445         } else
1446                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1447
1448         if (mac_mode != tp->mac_mode) {
1449                 tp->mac_mode = mac_mode;
1450                 tw32_f(MAC_MODE, tp->mac_mode);
1451                 udelay(40);
1452         }
1453
1454         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1455                 if (phydev->speed == SPEED_10)
1456                         tw32(MAC_MI_STAT,
1457                              MAC_MI_STAT_10MBPS_MODE |
1458                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459                 else
1460                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461         }
1462
1463         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1464                 tw32(MAC_TX_LENGTHS,
1465                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1466                       (6 << TX_LENGTHS_IPG_SHIFT) |
1467                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1468         else
1469                 tw32(MAC_TX_LENGTHS,
1470                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1471                       (6 << TX_LENGTHS_IPG_SHIFT) |
1472                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1473
1474         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1475             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1476             phydev->speed != tp->link_config.active_speed ||
1477             phydev->duplex != tp->link_config.active_duplex ||
1478             oldflowctrl != tp->link_config.active_flowctrl)
1479                 linkmesg = 1;
1480
1481         tp->link_config.active_speed = phydev->speed;
1482         tp->link_config.active_duplex = phydev->duplex;
1483
1484         spin_unlock_bh(&tp->lock);
1485
1486         if (linkmesg)
1487                 tg3_link_report(tp);
1488 }
1489
1490 static int tg3_phy_init(struct tg3 *tp)
1491 {
1492         struct phy_device *phydev;
1493
1494         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1495                 return 0;
1496
1497         /* Bring the PHY back to a known state. */
1498         tg3_bmcr_reset(tp);
1499
1500         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1501
1502         /* Attach the MAC to the PHY. */
1503         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1504                              phydev->dev_flags, phydev->interface);
1505         if (IS_ERR(phydev)) {
1506                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1507                 return PTR_ERR(phydev);
1508         }
1509
1510         /* Mask with MAC supported features. */
1511         switch (phydev->interface) {
1512         case PHY_INTERFACE_MODE_GMII:
1513         case PHY_INTERFACE_MODE_RGMII:
1514                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1515                         phydev->supported &= (PHY_GBIT_FEATURES |
1516                                               SUPPORTED_Pause |
1517                                               SUPPORTED_Asym_Pause);
1518                         break;
1519                 }
1520                 /* fallthru */
1521         case PHY_INTERFACE_MODE_MII:
1522                 phydev->supported &= (PHY_BASIC_FEATURES |
1523                                       SUPPORTED_Pause |
1524                                       SUPPORTED_Asym_Pause);
1525                 break;
1526         default:
1527                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528                 return -EINVAL;
1529         }
1530
1531         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1532
1533         phydev->advertising = phydev->supported;
1534
1535         return 0;
1536 }
1537
1538 static void tg3_phy_start(struct tg3 *tp)
1539 {
1540         struct phy_device *phydev;
1541
1542         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1543                 return;
1544
1545         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1546
1547         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1548                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1549                 phydev->speed = tp->link_config.orig_speed;
1550                 phydev->duplex = tp->link_config.orig_duplex;
1551                 phydev->autoneg = tp->link_config.orig_autoneg;
1552                 phydev->advertising = tp->link_config.orig_advertising;
1553         }
1554
1555         phy_start(phydev);
1556
1557         phy_start_aneg(phydev);
1558 }
1559
1560 static void tg3_phy_stop(struct tg3 *tp)
1561 {
1562         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1563                 return;
1564
1565         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1566 }
1567
1568 static void tg3_phy_fini(struct tg3 *tp)
1569 {
1570         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1571                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1572                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1573         }
1574 }
1575
1576 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1577 {
1578         int err;
1579
1580         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1581         if (!err)
1582                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1583
1584         return err;
1585 }
1586
1587 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1599 {
1600         u32 phytest;
1601
1602         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1603                 u32 phy;
1604
1605                 tg3_writephy(tp, MII_TG3_FET_TEST,
1606                              phytest | MII_TG3_FET_SHADOW_EN);
1607                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1608                         if (enable)
1609                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1610                         else
1611                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1613                 }
1614                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1615         }
1616 }
1617
1618 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1619 {
1620         u32 reg;
1621
1622         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1623             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1624              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1625                 return;
1626
1627         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1628                 tg3_phy_fet_toggle_apd(tp, enable);
1629                 return;
1630         }
1631
1632         reg = MII_TG3_MISC_SHDW_WREN |
1633               MII_TG3_MISC_SHDW_SCR5_SEL |
1634               MII_TG3_MISC_SHDW_SCR5_LPED |
1635               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1636               MII_TG3_MISC_SHDW_SCR5_SDTL |
1637               MII_TG3_MISC_SHDW_SCR5_C125OE;
1638         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1639                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1640
1641         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1642
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_APD_SEL |
1646               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1647         if (enable)
1648                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1649
1650         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1651 }
1652
1653 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1654 {
1655         u32 phy;
1656
1657         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1658             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1659                 return;
1660
1661         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1662                 u32 ephy;
1663
1664                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1665                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1666
1667                         tg3_writephy(tp, MII_TG3_FET_TEST,
1668                                      ephy | MII_TG3_FET_SHADOW_EN);
1669                         if (!tg3_readphy(tp, reg, &phy)) {
1670                                 if (enable)
1671                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1672                                 else
1673                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1674                                 tg3_writephy(tp, reg, phy);
1675                         }
1676                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1677                 }
1678         } else {
1679                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1680                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1681                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1682                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1683                         if (enable)
1684                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1685                         else
1686                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1687                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1688                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1689                 }
1690         }
1691 }
1692
1693 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1694 {
1695         u32 val;
1696
1697         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1698                 return;
1699
1700         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1701             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1702                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1703                              (val | (1 << 15) | (1 << 4)));
1704 }
1705
1706 static void tg3_phy_apply_otp(struct tg3 *tp)
1707 {
1708         u32 otp, phy;
1709
1710         if (!tp->phy_otp)
1711                 return;
1712
1713         otp = tp->phy_otp;
1714
1715         /* Enable SM_DSP clock and tx 6dB coding. */
1716         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1717               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1718               MII_TG3_AUXCTL_ACTL_TX_6DB;
1719         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1720
1721         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1722         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1723         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1724
1725         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1726               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1727         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1728
1729         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1730         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1731         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1732
1733         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1734         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1735
1736         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1737         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1738
1739         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1740               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1741         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1742
1743         /* Turn off SM_DSP clock. */
1744         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1745               MII_TG3_AUXCTL_ACTL_TX_6DB;
1746         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1747 }
1748
1749 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1750 {
1751         u32 val;
1752
1753         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1754                 return;
1755
1756         tp->setlpicnt = 0;
1757
1758         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1759             current_link_up == 1 &&
1760             tp->link_config.active_duplex == DUPLEX_FULL &&
1761             (tp->link_config.active_speed == SPEED_100 ||
1762              tp->link_config.active_speed == SPEED_1000)) {
1763                 u32 eeectl;
1764
1765                 if (tp->link_config.active_speed == SPEED_1000)
1766                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1767                 else
1768                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1769
1770                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1771
1772                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1773                                   TG3_CL45_D7_EEERES_STAT, &val);
1774
1775                 switch (val) {
1776                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1777                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1778                         case ASIC_REV_5717:
1779                         case ASIC_REV_5719:
1780                         case ASIC_REV_57765:
1781                                 /* Enable SM_DSP clock and tx 6dB coding. */
1782                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1783                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1784                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1785                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1786
1787                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1788
1789                                 /* Turn off SM_DSP clock. */
1790                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1791                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1792                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1793                         }
1794                         /* Fallthrough */
1795                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1796                         tp->setlpicnt = 2;
1797                 }
1798         }
1799
1800         if (!tp->setlpicnt) {
1801                 val = tr32(TG3_CPMU_EEE_MODE);
1802                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1803         }
1804 }
1805
1806 static int tg3_wait_macro_done(struct tg3 *tp)
1807 {
1808         int limit = 100;
1809
1810         while (limit--) {
1811                 u32 tmp32;
1812
1813                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1814                         if ((tmp32 & 0x1000) == 0)
1815                                 break;
1816                 }
1817         }
1818         if (limit < 0)
1819                 return -EBUSY;
1820
1821         return 0;
1822 }
1823
1824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1825 {
1826         static const u32 test_pat[4][6] = {
1827         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1828         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1829         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1830         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1831         };
1832         int chan;
1833
1834         for (chan = 0; chan < 4; chan++) {
1835                 int i;
1836
1837                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1838                              (chan * 0x2000) | 0x0200);
1839                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1840
1841                 for (i = 0; i < 6; i++)
1842                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1843                                      test_pat[chan][i]);
1844
1845                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1846                 if (tg3_wait_macro_done(tp)) {
1847                         *resetp = 1;
1848                         return -EBUSY;
1849                 }
1850
1851                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1852                              (chan * 0x2000) | 0x0200);
1853                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1854                 if (tg3_wait_macro_done(tp)) {
1855                         *resetp = 1;
1856                         return -EBUSY;
1857                 }
1858
1859                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1860                 if (tg3_wait_macro_done(tp)) {
1861                         *resetp = 1;
1862                         return -EBUSY;
1863                 }
1864
1865                 for (i = 0; i < 6; i += 2) {
1866                         u32 low, high;
1867
1868                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1869                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1870                             tg3_wait_macro_done(tp)) {
1871                                 *resetp = 1;
1872                                 return -EBUSY;
1873                         }
1874                         low &= 0x7fff;
1875                         high &= 0x000f;
1876                         if (low != test_pat[chan][i] ||
1877                             high != test_pat[chan][i+1]) {
1878                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1879                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1880                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1881
1882                                 return -EBUSY;
1883                         }
1884                 }
1885         }
1886
1887         return 0;
1888 }
1889
1890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1891 {
1892         int chan;
1893
1894         for (chan = 0; chan < 4; chan++) {
1895                 int i;
1896
1897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1898                              (chan * 0x2000) | 0x0200);
1899                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1900                 for (i = 0; i < 6; i++)
1901                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1902                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1903                 if (tg3_wait_macro_done(tp))
1904                         return -EBUSY;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1911 {
1912         u32 reg32, phy9_orig;
1913         int retries, do_phy_reset, err;
1914
1915         retries = 10;
1916         do_phy_reset = 1;
1917         do {
1918                 if (do_phy_reset) {
1919                         err = tg3_bmcr_reset(tp);
1920                         if (err)
1921                                 return err;
1922                         do_phy_reset = 0;
1923                 }
1924
1925                 /* Disable transmitter and interrupt.  */
1926                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1927                         continue;
1928
1929                 reg32 |= 0x3000;
1930                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1931
1932                 /* Set full-duplex, 1000 mbps.  */
1933                 tg3_writephy(tp, MII_BMCR,
1934                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1935
1936                 /* Set to master mode.  */
1937                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1938                         continue;
1939
1940                 tg3_writephy(tp, MII_TG3_CTRL,
1941                              (MII_TG3_CTRL_AS_MASTER |
1942                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1943
1944                 /* Enable SM_DSP_CLOCK and 6dB.  */
1945                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1946
1947                 /* Block the PHY control access.  */
1948                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1949
1950                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1951                 if (!err)
1952                         break;
1953         } while (--retries);
1954
1955         err = tg3_phy_reset_chanpat(tp);
1956         if (err)
1957                 return err;
1958
1959         tg3_phydsp_write(tp, 0x8005, 0x0000);
1960
1961         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1962         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1963
1964         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1965             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1966                 /* Set Extended packet length bit for jumbo frames */
1967                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1968         } else {
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970         }
1971
1972         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1973
1974         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1975                 reg32 &= ~0x3000;
1976                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1977         } else if (!err)
1978                 err = -EBUSY;
1979
1980         return err;
1981 }
1982
1983 /* This will reset the tigon3 PHY if there is no valid
1984  * link unless the FORCE argument is non-zero.
1985  */
1986 static int tg3_phy_reset(struct tg3 *tp)
1987 {
1988         u32 val, cpmuctrl;
1989         int err;
1990
1991         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1992                 val = tr32(GRC_MISC_CFG);
1993                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1994                 udelay(40);
1995         }
1996         err  = tg3_readphy(tp, MII_BMSR, &val);
1997         err |= tg3_readphy(tp, MII_BMSR, &val);
1998         if (err != 0)
1999                 return -EBUSY;
2000
2001         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2002                 netif_carrier_off(tp->dev);
2003                 tg3_link_report(tp);
2004         }
2005
2006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2009                 err = tg3_phy_reset_5703_4_5(tp);
2010                 if (err)
2011                         return err;
2012                 goto out;
2013         }
2014
2015         cpmuctrl = 0;
2016         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2017             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2018                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2019                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2020                         tw32(TG3_CPMU_CTRL,
2021                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2022         }
2023
2024         err = tg3_bmcr_reset(tp);
2025         if (err)
2026                 return err;
2027
2028         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2029                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2030                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2031
2032                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2033         }
2034
2035         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2036             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2037                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2038                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2039                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2040                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2041                         udelay(40);
2042                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2043                 }
2044         }
2045
2046         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2047             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2048                 return 0;
2049
2050         tg3_phy_apply_otp(tp);
2051
2052         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2053                 tg3_phy_toggle_apd(tp, true);
2054         else
2055                 tg3_phy_toggle_apd(tp, false);
2056
2057 out:
2058         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2059                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2060                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2061                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2062                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2063         }
2064         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2065                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2066                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2067         }
2068         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2069                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2070                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2071                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2072                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2073                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2074         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2076                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2077                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2078                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2079                         tg3_writephy(tp, MII_TG3_TEST1,
2080                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2081                 } else
2082                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2083                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2084         }
2085         /* Set Extended packet length bit (bit 14) on all chips that */
2086         /* support jumbo frames */
2087         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2088                 /* Cannot do read-modify-write on 5401 */
2089                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2090         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2091                 /* Set bit 14 with read-modify-write to preserve other bits */
2092                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2093                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2095         }
2096
2097         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2098          * jumbo frames transmission.
2099          */
2100         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2101                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2102                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2103                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2104         }
2105
2106         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2107                 /* adjust output voltage */
2108                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2109         }
2110
2111         tg3_phy_toggle_automdix(tp, 1);
2112         tg3_phy_set_wirespeed(tp);
2113         return 0;
2114 }
2115
2116 static void tg3_frob_aux_power(struct tg3 *tp)
2117 {
2118         bool need_vaux = false;
2119
2120         /* The GPIOs do something completely different on 57765. */
2121         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2122             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2123             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2124                 return;
2125
2126         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2127              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2128              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2129              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2130             tp->pdev_peer != tp->pdev) {
2131                 struct net_device *dev_peer;
2132
2133                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2134
2135                 /* remove_one() may have been run on the peer. */
2136                 if (dev_peer) {
2137                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2138
2139                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2140                                 return;
2141
2142                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2143                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2144                                 need_vaux = true;
2145                 }
2146         }
2147
2148         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2149             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2150                 need_vaux = true;
2151
2152         if (need_vaux) {
2153                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2154                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2156                                     (GRC_LCLCTRL_GPIO_OE0 |
2157                                      GRC_LCLCTRL_GPIO_OE1 |
2158                                      GRC_LCLCTRL_GPIO_OE2 |
2159                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2161                                     100);
2162                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2163                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2164                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2165                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2166                                              GRC_LCLCTRL_GPIO_OE1 |
2167                                              GRC_LCLCTRL_GPIO_OE2 |
2168                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2169                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2170                                              tp->grc_local_ctrl;
2171                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2172
2173                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2174                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2175
2176                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2177                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2178                 } else {
2179                         u32 no_gpio2;
2180                         u32 grc_local_ctrl = 0;
2181
2182                         /* Workaround to prevent overdrawing Amps. */
2183                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2184                             ASIC_REV_5714) {
2185                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2186                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2187                                             grc_local_ctrl, 100);
2188                         }
2189
2190                         /* On 5753 and variants, GPIO2 cannot be used. */
2191                         no_gpio2 = tp->nic_sram_data_cfg &
2192                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2193
2194                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2195                                          GRC_LCLCTRL_GPIO_OE1 |
2196                                          GRC_LCLCTRL_GPIO_OE2 |
2197                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2198                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2199                         if (no_gpio2) {
2200                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2201                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2202                         }
2203                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2204                                                     grc_local_ctrl, 100);
2205
2206                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2207
2208                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2209                                                     grc_local_ctrl, 100);
2210
2211                         if (!no_gpio2) {
2212                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2213                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2214                                             grc_local_ctrl, 100);
2215                         }
2216                 }
2217         } else {
2218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2219                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2220                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2221                                     (GRC_LCLCTRL_GPIO_OE1 |
2222                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2223
2224                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2225                                     GRC_LCLCTRL_GPIO_OE1, 100);
2226
2227                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2228                                     (GRC_LCLCTRL_GPIO_OE1 |
2229                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2230                 }
2231         }
2232 }
2233
2234 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2235 {
2236         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2237                 return 1;
2238         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2239                 if (speed != SPEED_10)
2240                         return 1;
2241         } else if (speed == SPEED_10)
2242                 return 1;
2243
2244         return 0;
2245 }
2246
2247 static int tg3_setup_phy(struct tg3 *, int);
2248
2249 #define RESET_KIND_SHUTDOWN     0
2250 #define RESET_KIND_INIT         1
2251 #define RESET_KIND_SUSPEND      2
2252
2253 static void tg3_write_sig_post_reset(struct tg3 *, int);
2254 static int tg3_halt_cpu(struct tg3 *, u32);
2255
2256 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2257 {
2258         u32 val;
2259
2260         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2261                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2262                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2263                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2264
2265                         sg_dig_ctrl |=
2266                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2267                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2268                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2269                 }
2270                 return;
2271         }
2272
2273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2274                 tg3_bmcr_reset(tp);
2275                 val = tr32(GRC_MISC_CFG);
2276                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2277                 udelay(40);
2278                 return;
2279         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2280                 u32 phytest;
2281                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2282                         u32 phy;
2283
2284                         tg3_writephy(tp, MII_ADVERTISE, 0);
2285                         tg3_writephy(tp, MII_BMCR,
2286                                      BMCR_ANENABLE | BMCR_ANRESTART);
2287
2288                         tg3_writephy(tp, MII_TG3_FET_TEST,
2289                                      phytest | MII_TG3_FET_SHADOW_EN);
2290                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2291                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2292                                 tg3_writephy(tp,
2293                                              MII_TG3_FET_SHDW_AUXMODE4,
2294                                              phy);
2295                         }
2296                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2297                 }
2298                 return;
2299         } else if (do_low_power) {
2300                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2301                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2302
2303                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2304                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2305                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2306                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2307                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2308         }
2309
2310         /* The PHY should not be powered down on some chips because
2311          * of bugs.
2312          */
2313         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2314             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2315             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2316              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2317                 return;
2318
2319         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2320             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2321                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2322                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2323                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2324                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2325         }
2326
2327         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2328 }
2329
2330 /* tp->lock is held. */
2331 static int tg3_nvram_lock(struct tg3 *tp)
2332 {
2333         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2334                 int i;
2335
2336                 if (tp->nvram_lock_cnt == 0) {
2337                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2338                         for (i = 0; i < 8000; i++) {
2339                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2340                                         break;
2341                                 udelay(20);
2342                         }
2343                         if (i == 8000) {
2344                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2345                                 return -ENODEV;
2346                         }
2347                 }
2348                 tp->nvram_lock_cnt++;
2349         }
2350         return 0;
2351 }
2352
2353 /* tp->lock is held. */
2354 static void tg3_nvram_unlock(struct tg3 *tp)
2355 {
2356         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2357                 if (tp->nvram_lock_cnt > 0)
2358                         tp->nvram_lock_cnt--;
2359                 if (tp->nvram_lock_cnt == 0)
2360                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2361         }
2362 }
2363
2364 /* tp->lock is held. */
2365 static void tg3_enable_nvram_access(struct tg3 *tp)
2366 {
2367         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2368             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2369                 u32 nvaccess = tr32(NVRAM_ACCESS);
2370
2371                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2372         }
2373 }
2374
2375 /* tp->lock is held. */
2376 static void tg3_disable_nvram_access(struct tg3 *tp)
2377 {
2378         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2379             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2380                 u32 nvaccess = tr32(NVRAM_ACCESS);
2381
2382                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2383         }
2384 }
2385
2386 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2387                                         u32 offset, u32 *val)
2388 {
2389         u32 tmp;
2390         int i;
2391
2392         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2393                 return -EINVAL;
2394
2395         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2396                                         EEPROM_ADDR_DEVID_MASK |
2397                                         EEPROM_ADDR_READ);
2398         tw32(GRC_EEPROM_ADDR,
2399              tmp |
2400              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2401              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2402               EEPROM_ADDR_ADDR_MASK) |
2403              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2404
2405         for (i = 0; i < 1000; i++) {
2406                 tmp = tr32(GRC_EEPROM_ADDR);
2407
2408                 if (tmp & EEPROM_ADDR_COMPLETE)
2409                         break;
2410                 msleep(1);
2411         }
2412         if (!(tmp & EEPROM_ADDR_COMPLETE))
2413                 return -EBUSY;
2414
2415         tmp = tr32(GRC_EEPROM_DATA);
2416
2417         /*
2418          * The data will always be opposite the native endian
2419          * format.  Perform a blind byteswap to compensate.
2420          */
2421         *val = swab32(tmp);
2422
2423         return 0;
2424 }
2425
2426 #define NVRAM_CMD_TIMEOUT 10000
2427
2428 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2429 {
2430         int i;
2431
2432         tw32(NVRAM_CMD, nvram_cmd);
2433         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2434                 udelay(10);
2435                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2436                         udelay(10);
2437                         break;
2438                 }
2439         }
2440
2441         if (i == NVRAM_CMD_TIMEOUT)
2442                 return -EBUSY;
2443
2444         return 0;
2445 }
2446
2447 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2448 {
2449         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2450             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2451             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2452            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2453             (tp->nvram_jedecnum == JEDEC_ATMEL))
2454
2455                 addr = ((addr / tp->nvram_pagesize) <<
2456                         ATMEL_AT45DB0X1B_PAGE_POS) +
2457                        (addr % tp->nvram_pagesize);
2458
2459         return addr;
2460 }
2461
2462 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2463 {
2464         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2465             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2466             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2467            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2468             (tp->nvram_jedecnum == JEDEC_ATMEL))
2469
2470                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2471                         tp->nvram_pagesize) +
2472                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2473
2474         return addr;
2475 }
2476
2477 /* NOTE: Data read in from NVRAM is byteswapped according to
2478  * the byteswapping settings for all other register accesses.
2479  * tg3 devices are BE devices, so on a BE machine, the data
2480  * returned will be exactly as it is seen in NVRAM.  On a LE
2481  * machine, the 32-bit value will be byteswapped.
2482  */
2483 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2484 {
2485         int ret;
2486
2487         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2488                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2489
2490         offset = tg3_nvram_phys_addr(tp, offset);
2491
2492         if (offset > NVRAM_ADDR_MSK)
2493                 return -EINVAL;
2494
2495         ret = tg3_nvram_lock(tp);
2496         if (ret)
2497                 return ret;
2498
2499         tg3_enable_nvram_access(tp);
2500
2501         tw32(NVRAM_ADDR, offset);
2502         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2503                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2504
2505         if (ret == 0)
2506                 *val = tr32(NVRAM_RDDATA);
2507
2508         tg3_disable_nvram_access(tp);
2509
2510         tg3_nvram_unlock(tp);
2511
2512         return ret;
2513 }
2514
2515 /* Ensures NVRAM data is in bytestream format. */
2516 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2517 {
2518         u32 v;
2519         int res = tg3_nvram_read(tp, offset, &v);
2520         if (!res)
2521                 *val = cpu_to_be32(v);
2522         return res;
2523 }
2524
2525 /* tp->lock is held. */
2526 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2527 {
2528         u32 addr_high, addr_low;
2529         int i;
2530
2531         addr_high = ((tp->dev->dev_addr[0] << 8) |
2532                      tp->dev->dev_addr[1]);
2533         addr_low = ((tp->dev->dev_addr[2] << 24) |
2534                     (tp->dev->dev_addr[3] << 16) |
2535                     (tp->dev->dev_addr[4] <<  8) |
2536                     (tp->dev->dev_addr[5] <<  0));
2537         for (i = 0; i < 4; i++) {
2538                 if (i == 1 && skip_mac_1)
2539                         continue;
2540                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2541                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2542         }
2543
2544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2545             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2546                 for (i = 0; i < 12; i++) {
2547                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2548                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2549                 }
2550         }
2551
2552         addr_high = (tp->dev->dev_addr[0] +
2553                      tp->dev->dev_addr[1] +
2554                      tp->dev->dev_addr[2] +
2555                      tp->dev->dev_addr[3] +
2556                      tp->dev->dev_addr[4] +
2557                      tp->dev->dev_addr[5]) &
2558                 TX_BACKOFF_SEED_MASK;
2559         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2560 }
2561
2562 static void tg3_enable_register_access(struct tg3 *tp)
2563 {
2564         /*
2565          * Make sure register accesses (indirect or otherwise) will function
2566          * correctly.
2567          */
2568         pci_write_config_dword(tp->pdev,
2569                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2570 }
2571
2572 static int tg3_power_up(struct tg3 *tp)
2573 {
2574         tg3_enable_register_access(tp);
2575
2576         pci_set_power_state(tp->pdev, PCI_D0);
2577
2578         /* Switch out of Vaux if it is a NIC */
2579         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2580                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2581
2582         return 0;
2583 }
2584
2585 static int tg3_power_down_prepare(struct tg3 *tp)
2586 {
2587         u32 misc_host_ctrl;
2588         bool device_should_wake, do_low_power;
2589
2590         tg3_enable_register_access(tp);
2591
2592         /* Restore the CLKREQ setting. */
2593         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2594                 u16 lnkctl;
2595
2596                 pci_read_config_word(tp->pdev,
2597                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2598                                      &lnkctl);
2599                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2600                 pci_write_config_word(tp->pdev,
2601                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2602                                       lnkctl);
2603         }
2604
2605         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2606         tw32(TG3PCI_MISC_HOST_CTRL,
2607              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2608
2609         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2610                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2611
2612         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2613                 do_low_power = false;
2614                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2615                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2616                         struct phy_device *phydev;
2617                         u32 phyid, advertising;
2618
2619                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2620
2621                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2622
2623                         tp->link_config.orig_speed = phydev->speed;
2624                         tp->link_config.orig_duplex = phydev->duplex;
2625                         tp->link_config.orig_autoneg = phydev->autoneg;
2626                         tp->link_config.orig_advertising = phydev->advertising;
2627
2628                         advertising = ADVERTISED_TP |
2629                                       ADVERTISED_Pause |
2630                                       ADVERTISED_Autoneg |
2631                                       ADVERTISED_10baseT_Half;
2632
2633                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2634                             device_should_wake) {
2635                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2636                                         advertising |=
2637                                                 ADVERTISED_100baseT_Half |
2638                                                 ADVERTISED_100baseT_Full |
2639                                                 ADVERTISED_10baseT_Full;
2640                                 else
2641                                         advertising |= ADVERTISED_10baseT_Full;
2642                         }
2643
2644                         phydev->advertising = advertising;
2645
2646                         phy_start_aneg(phydev);
2647
2648                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2649                         if (phyid != PHY_ID_BCMAC131) {
2650                                 phyid &= PHY_BCM_OUI_MASK;
2651                                 if (phyid == PHY_BCM_OUI_1 ||
2652                                     phyid == PHY_BCM_OUI_2 ||
2653                                     phyid == PHY_BCM_OUI_3)
2654                                         do_low_power = true;
2655                         }
2656                 }
2657         } else {
2658                 do_low_power = true;
2659
2660                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2661                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2662                         tp->link_config.orig_speed = tp->link_config.speed;
2663                         tp->link_config.orig_duplex = tp->link_config.duplex;
2664                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2665                 }
2666
2667                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2668                         tp->link_config.speed = SPEED_10;
2669                         tp->link_config.duplex = DUPLEX_HALF;
2670                         tp->link_config.autoneg = AUTONEG_ENABLE;
2671                         tg3_setup_phy(tp, 0);
2672                 }
2673         }
2674
2675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2676                 u32 val;
2677
2678                 val = tr32(GRC_VCPU_EXT_CTRL);
2679                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2680         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2681                 int i;
2682                 u32 val;
2683
2684                 for (i = 0; i < 200; i++) {
2685                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2686                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2687                                 break;
2688                         msleep(1);
2689                 }
2690         }
2691         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2692                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2693                                                      WOL_DRV_STATE_SHUTDOWN |
2694                                                      WOL_DRV_WOL |
2695                                                      WOL_SET_MAGIC_PKT);
2696
2697         if (device_should_wake) {
2698                 u32 mac_mode;
2699
2700                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2701                         if (do_low_power) {
2702                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2703                                 udelay(40);
2704                         }
2705
2706                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2707                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2708                         else
2709                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2710
2711                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2712                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2713                             ASIC_REV_5700) {
2714                                 u32 speed = (tp->tg3_flags &
2715                                              TG3_FLAG_WOL_SPEED_100MB) ?
2716                                              SPEED_100 : SPEED_10;
2717                                 if (tg3_5700_link_polarity(tp, speed))
2718                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2719                                 else
2720                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2721                         }
2722                 } else {
2723                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2724                 }
2725
2726                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2727                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2728
2729                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2730                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2731                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2732                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2733                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2734                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2735
2736                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2737                         mac_mode |= MAC_MODE_APE_TX_EN |
2738                                     MAC_MODE_APE_RX_EN |
2739                                     MAC_MODE_TDE_ENABLE;
2740
2741                 tw32_f(MAC_MODE, mac_mode);
2742                 udelay(100);
2743
2744                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2745                 udelay(10);
2746         }
2747
2748         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2749             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2750              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2751                 u32 base_val;
2752
2753                 base_val = tp->pci_clock_ctrl;
2754                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2755                              CLOCK_CTRL_TXCLK_DISABLE);
2756
2757                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2758                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2759         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2760                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2761                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2762                 /* do nothing */
2763         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2764                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2765                 u32 newbits1, newbits2;
2766
2767                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2768                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2769                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2770                                     CLOCK_CTRL_TXCLK_DISABLE |
2771                                     CLOCK_CTRL_ALTCLK);
2772                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2773                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2774                         newbits1 = CLOCK_CTRL_625_CORE;
2775                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2776                 } else {
2777                         newbits1 = CLOCK_CTRL_ALTCLK;
2778                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2779                 }
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2782                             40);
2783
2784                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2785                             40);
2786
2787                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2788                         u32 newbits3;
2789
2790                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2791                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2792                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2793                                             CLOCK_CTRL_TXCLK_DISABLE |
2794                                             CLOCK_CTRL_44MHZ_CORE);
2795                         } else {
2796                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2797                         }
2798
2799                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2800                                     tp->pci_clock_ctrl | newbits3, 40);
2801                 }
2802         }
2803
2804         if (!(device_should_wake) &&
2805             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2806                 tg3_power_down_phy(tp, do_low_power);
2807
2808         tg3_frob_aux_power(tp);
2809
2810         /* Workaround for unstable PLL clock */
2811         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2812             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2813                 u32 val = tr32(0x7d00);
2814
2815                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2816                 tw32(0x7d00, val);
2817                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2818                         int err;
2819
2820                         err = tg3_nvram_lock(tp);
2821                         tg3_halt_cpu(tp, RX_CPU_BASE);
2822                         if (!err)
2823                                 tg3_nvram_unlock(tp);
2824                 }
2825         }
2826
2827         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2828
2829         return 0;
2830 }
2831
2832 static void tg3_power_down(struct tg3 *tp)
2833 {
2834         tg3_power_down_prepare(tp);
2835
2836         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2837         pci_set_power_state(tp->pdev, PCI_D3hot);
2838 }
2839
2840 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2841 {
2842         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2843         case MII_TG3_AUX_STAT_10HALF:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_HALF;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_10FULL:
2849                 *speed = SPEED_10;
2850                 *duplex = DUPLEX_FULL;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100HALF:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_HALF;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_100FULL:
2859                 *speed = SPEED_100;
2860                 *duplex = DUPLEX_FULL;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000HALF:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_HALF;
2866                 break;
2867
2868         case MII_TG3_AUX_STAT_1000FULL:
2869                 *speed = SPEED_1000;
2870                 *duplex = DUPLEX_FULL;
2871                 break;
2872
2873         default:
2874                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2875                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2876                                  SPEED_10;
2877                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2878                                   DUPLEX_HALF;
2879                         break;
2880                 }
2881                 *speed = SPEED_INVALID;
2882                 *duplex = DUPLEX_INVALID;
2883                 break;
2884         }
2885 }
2886
2887 static void tg3_phy_copper_begin(struct tg3 *tp)
2888 {
2889         u32 new_adv;
2890         int i;
2891
2892         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2893                 /* Entering low power mode.  Disable gigabit and
2894                  * 100baseT advertisements.
2895                  */
2896                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2897
2898                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2899                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2900                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2901                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2902
2903                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2904         } else if (tp->link_config.speed == SPEED_INVALID) {
2905                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2906                         tp->link_config.advertising &=
2907                                 ~(ADVERTISED_1000baseT_Half |
2908                                   ADVERTISED_1000baseT_Full);
2909
2910                 new_adv = ADVERTISE_CSMA;
2911                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2912                         new_adv |= ADVERTISE_10HALF;
2913                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2914                         new_adv |= ADVERTISE_10FULL;
2915                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2916                         new_adv |= ADVERTISE_100HALF;
2917                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2918                         new_adv |= ADVERTISE_100FULL;
2919
2920                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2921
2922                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2923
2924                 if (tp->link_config.advertising &
2925                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2926                         new_adv = 0;
2927                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2928                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2929                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2930                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2931                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2932                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2933                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2934                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2935                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2936                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2937                 } else {
2938                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2939                 }
2940         } else {
2941                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2942                 new_adv |= ADVERTISE_CSMA;
2943
2944                 /* Asking for a specific link mode. */
2945                 if (tp->link_config.speed == SPEED_1000) {
2946                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2947
2948                         if (tp->link_config.duplex == DUPLEX_FULL)
2949                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2950                         else
2951                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2952                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2953                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2954                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2955                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2956                 } else {
2957                         if (tp->link_config.speed == SPEED_100) {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_100FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_100HALF;
2962                         } else {
2963                                 if (tp->link_config.duplex == DUPLEX_FULL)
2964                                         new_adv |= ADVERTISE_10FULL;
2965                                 else
2966                                         new_adv |= ADVERTISE_10HALF;
2967                         }
2968                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2969
2970                         new_adv = 0;
2971                 }
2972
2973                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2974         }
2975
2976         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2977                 u32 val;
2978
2979                 tw32(TG3_CPMU_EEE_MODE,
2980                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2981
2982                 /* Enable SM_DSP clock and tx 6dB coding. */
2983                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2984                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2985                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2987
2988                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2989                 case ASIC_REV_5717:
2990                 case ASIC_REV_57765:
2991                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2992                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2993                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2994                         /* Fall through */
2995                 case ASIC_REV_5719:
2996                         val = MII_TG3_DSP_TAP26_ALNOKO |
2997                               MII_TG3_DSP_TAP26_RMRXSTO |
2998                               MII_TG3_DSP_TAP26_OPCSINPT;
2999                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3000                 }
3001
3002                 val = 0;
3003                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3004                         /* Advertise 100-BaseTX EEE ability */
3005                         if (tp->link_config.advertising &
3006                             ADVERTISED_100baseT_Full)
3007                                 val |= MDIO_AN_EEE_ADV_100TX;
3008                         /* Advertise 1000-BaseT EEE ability */
3009                         if (tp->link_config.advertising &
3010                             ADVERTISED_1000baseT_Full)
3011                                 val |= MDIO_AN_EEE_ADV_1000T;
3012                 }
3013                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3014
3015                 /* Turn off SM_DSP clock. */
3016                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3017                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3019         }
3020
3021         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3022             tp->link_config.speed != SPEED_INVALID) {
3023                 u32 bmcr, orig_bmcr;
3024
3025                 tp->link_config.active_speed = tp->link_config.speed;
3026                 tp->link_config.active_duplex = tp->link_config.duplex;
3027
3028                 bmcr = 0;
3029                 switch (tp->link_config.speed) {
3030                 default:
3031                 case SPEED_10:
3032                         break;
3033
3034                 case SPEED_100:
3035                         bmcr |= BMCR_SPEED100;
3036                         break;
3037
3038                 case SPEED_1000:
3039                         bmcr |= TG3_BMCR_SPEED1000;
3040                         break;
3041                 }
3042
3043                 if (tp->link_config.duplex == DUPLEX_FULL)
3044                         bmcr |= BMCR_FULLDPLX;
3045
3046                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3047                     (bmcr != orig_bmcr)) {
3048                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3049                         for (i = 0; i < 1500; i++) {
3050                                 u32 tmp;
3051
3052                                 udelay(10);
3053                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3054                                     tg3_readphy(tp, MII_BMSR, &tmp))
3055                                         continue;
3056                                 if (!(tmp & BMSR_LSTATUS)) {
3057                                         udelay(40);
3058                                         break;
3059                                 }
3060                         }
3061                         tg3_writephy(tp, MII_BMCR, bmcr);
3062                         udelay(40);
3063                 }
3064         } else {
3065                 tg3_writephy(tp, MII_BMCR,
3066                              BMCR_ANENABLE | BMCR_ANRESTART);
3067         }
3068 }
3069
3070 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3071 {
3072         int err;
3073
3074         /* Turn off tap power management. */
3075         /* Set Extended packet length bit */
3076         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3077
3078         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3079         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3080         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3081         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3082         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3083
3084         udelay(40);
3085
3086         return err;
3087 }
3088
3089 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3090 {
3091         u32 adv_reg, all_mask = 0;
3092
3093         if (mask & ADVERTISED_10baseT_Half)
3094                 all_mask |= ADVERTISE_10HALF;
3095         if (mask & ADVERTISED_10baseT_Full)
3096                 all_mask |= ADVERTISE_10FULL;
3097         if (mask & ADVERTISED_100baseT_Half)
3098                 all_mask |= ADVERTISE_100HALF;
3099         if (mask & ADVERTISED_100baseT_Full)
3100                 all_mask |= ADVERTISE_100FULL;
3101
3102         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3103                 return 0;
3104
3105         if ((adv_reg & all_mask) != all_mask)
3106                 return 0;
3107         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3108                 u32 tg3_ctrl;
3109
3110                 all_mask = 0;
3111                 if (mask & ADVERTISED_1000baseT_Half)
3112                         all_mask |= ADVERTISE_1000HALF;
3113                 if (mask & ADVERTISED_1000baseT_Full)
3114                         all_mask |= ADVERTISE_1000FULL;
3115
3116                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3117                         return 0;
3118
3119                 if ((tg3_ctrl & all_mask) != all_mask)
3120                         return 0;
3121         }
3122         return 1;
3123 }
3124
3125 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3126 {
3127         u32 curadv, reqadv;
3128
3129         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3130                 return 1;
3131
3132         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3133         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3134
3135         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3136                 if (curadv != reqadv)
3137                         return 0;
3138
3139                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3140                         tg3_readphy(tp, MII_LPA, rmtadv);
3141         } else {
3142                 /* Reprogram the advertisement register, even if it
3143                  * does not affect the current link.  If the link
3144                  * gets renegotiated in the future, we can save an
3145                  * additional renegotiation cycle by advertising
3146                  * it correctly in the first place.
3147                  */
3148                 if (curadv != reqadv) {
3149                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3150                                      ADVERTISE_PAUSE_ASYM);
3151                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3152                 }
3153         }
3154
3155         return 1;
3156 }
3157
3158 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3159 {
3160         int current_link_up;
3161         u32 bmsr, val;
3162         u32 lcl_adv, rmt_adv;
3163         u16 current_speed;
3164         u8 current_duplex;
3165         int i, err;
3166
3167         tw32(MAC_EVENT, 0);
3168
3169         tw32_f(MAC_STATUS,
3170              (MAC_STATUS_SYNC_CHANGED |
3171               MAC_STATUS_CFG_CHANGED |
3172               MAC_STATUS_MI_COMPLETION |
3173               MAC_STATUS_LNKSTATE_CHANGED));
3174         udelay(40);
3175
3176         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3177                 tw32_f(MAC_MI_MODE,
3178                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3179                 udelay(80);
3180         }
3181
3182         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3183
3184         /* Some third-party PHYs need to be reset on link going
3185          * down.
3186          */
3187         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3188              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3189              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3190             netif_carrier_ok(tp->dev)) {
3191                 tg3_readphy(tp, MII_BMSR, &bmsr);
3192                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3193                     !(bmsr & BMSR_LSTATUS))
3194                         force_reset = 1;
3195         }
3196         if (force_reset)
3197                 tg3_phy_reset(tp);
3198
3199         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3200                 tg3_readphy(tp, MII_BMSR, &bmsr);
3201                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3202                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3203                         bmsr = 0;
3204
3205                 if (!(bmsr & BMSR_LSTATUS)) {
3206                         err = tg3_init_5401phy_dsp(tp);
3207                         if (err)
3208                                 return err;
3209
3210                         tg3_readphy(tp, MII_BMSR, &bmsr);
3211                         for (i = 0; i < 1000; i++) {
3212                                 udelay(10);
3213                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3214                                     (bmsr & BMSR_LSTATUS)) {
3215                                         udelay(40);
3216                                         break;
3217                                 }
3218                         }
3219
3220                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3221                             TG3_PHY_REV_BCM5401_B0 &&
3222                             !(bmsr & BMSR_LSTATUS) &&
3223                             tp->link_config.active_speed == SPEED_1000) {
3224                                 err = tg3_phy_reset(tp);
3225                                 if (!err)
3226                                         err = tg3_init_5401phy_dsp(tp);
3227                                 if (err)
3228                                         return err;
3229                         }
3230                 }
3231         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3232                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3233                 /* 5701 {A0,B0} CRC bug workaround */
3234                 tg3_writephy(tp, 0x15, 0x0a75);
3235                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3236                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3237                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3238         }
3239
3240         /* Clear pending interrupts... */
3241         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3242         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3243
3244         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3245                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3246         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3247                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3248
3249         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3250             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3251                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3252                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3253                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3254                 else
3255                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3256         }
3257
3258         current_link_up = 0;
3259         current_speed = SPEED_INVALID;
3260         current_duplex = DUPLEX_INVALID;
3261
3262         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3263                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3264                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3265                 if (!(val & (1 << 10))) {
3266                         val |= (1 << 10);
3267                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3268                         goto relink;
3269                 }
3270         }
3271
3272         bmsr = 0;
3273         for (i = 0; i < 100; i++) {
3274                 tg3_readphy(tp, MII_BMSR, &bmsr);
3275                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3276                     (bmsr & BMSR_LSTATUS))
3277                         break;
3278                 udelay(40);
3279         }
3280
3281         if (bmsr & BMSR_LSTATUS) {
3282                 u32 aux_stat, bmcr;
3283
3284                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3285                 for (i = 0; i < 2000; i++) {
3286                         udelay(10);
3287                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3288                             aux_stat)
3289                                 break;
3290                 }
3291
3292                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3293                                              &current_speed,
3294                                              &current_duplex);
3295
3296                 bmcr = 0;
3297                 for (i = 0; i < 200; i++) {
3298                         tg3_readphy(tp, MII_BMCR, &bmcr);
3299                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3300                                 continue;
3301                         if (bmcr && bmcr != 0x7fff)
3302                                 break;
3303                         udelay(10);
3304                 }
3305
3306                 lcl_adv = 0;
3307                 rmt_adv = 0;
3308
3309                 tp->link_config.active_speed = current_speed;
3310                 tp->link_config.active_duplex = current_duplex;
3311
3312                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3313                         if ((bmcr & BMCR_ANENABLE) &&
3314                             tg3_copper_is_advertising_all(tp,
3315                                                 tp->link_config.advertising)) {
3316                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3317                                                                   &rmt_adv))
3318                                         current_link_up = 1;
3319                         }
3320                 } else {
3321                         if (!(bmcr & BMCR_ANENABLE) &&
3322                             tp->link_config.speed == current_speed &&
3323                             tp->link_config.duplex == current_duplex &&
3324                             tp->link_config.flowctrl ==
3325                             tp->link_config.active_flowctrl) {
3326                                 current_link_up = 1;
3327                         }
3328                 }
3329
3330                 if (current_link_up == 1 &&
3331                     tp->link_config.active_duplex == DUPLEX_FULL)
3332                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3333         }
3334
3335 relink:
3336         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3337                 tg3_phy_copper_begin(tp);
3338
3339                 tg3_readphy(tp, MII_BMSR, &bmsr);
3340                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3341                     (bmsr & BMSR_LSTATUS))
3342                         current_link_up = 1;
3343         }
3344
3345         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3346         if (current_link_up == 1) {
3347                 if (tp->link_config.active_speed == SPEED_100 ||
3348                     tp->link_config.active_speed == SPEED_10)
3349                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3350                 else
3351                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3352         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3353                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3354         else
3355                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3356
3357         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3358         if (tp->link_config.active_duplex == DUPLEX_HALF)
3359                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3360
3361         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3362                 if (current_link_up == 1 &&
3363                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3364                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3365                 else
3366                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3367         }
3368
3369         /* ??? Without this setting Netgear GA302T PHY does not
3370          * ??? send/receive packets...
3371          */
3372         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3373             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3374                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3375                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3376                 udelay(80);
3377         }
3378
3379         tw32_f(MAC_MODE, tp->mac_mode);
3380         udelay(40);
3381
3382         tg3_phy_eee_adjust(tp, current_link_up);
3383
3384         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3385                 /* Polled via timer. */
3386                 tw32_f(MAC_EVENT, 0);
3387         } else {
3388                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3389         }
3390         udelay(40);
3391
3392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3393             current_link_up == 1 &&
3394             tp->link_config.active_speed == SPEED_1000 &&
3395             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3396              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3397                 udelay(120);
3398                 tw32_f(MAC_STATUS,
3399                      (MAC_STATUS_SYNC_CHANGED |
3400                       MAC_STATUS_CFG_CHANGED));
3401                 udelay(40);
3402                 tg3_write_mem(tp,
3403                               NIC_SRAM_FIRMWARE_MBOX,
3404                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3405         }
3406
3407         /* Prevent send BD corruption. */
3408         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3409                 u16 oldlnkctl, newlnkctl;
3410
3411                 pci_read_config_word(tp->pdev,
3412                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3413                                      &oldlnkctl);
3414                 if (tp->link_config.active_speed == SPEED_100 ||
3415                     tp->link_config.active_speed == SPEED_10)
3416                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3417                 else
3418                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3419                 if (newlnkctl != oldlnkctl)
3420                         pci_write_config_word(tp->pdev,
3421                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3422                                               newlnkctl);
3423         }
3424
3425         if (current_link_up != netif_carrier_ok(tp->dev)) {
3426                 if (current_link_up)
3427                         netif_carrier_on(tp->dev);
3428                 else
3429                         netif_carrier_off(tp->dev);
3430                 tg3_link_report(tp);
3431         }
3432
3433         return 0;
3434 }
3435
3436 struct tg3_fiber_aneginfo {
3437         int state;
3438 #define ANEG_STATE_UNKNOWN              0
3439 #define ANEG_STATE_AN_ENABLE            1
3440 #define ANEG_STATE_RESTART_INIT         2
3441 #define ANEG_STATE_RESTART              3
3442 #define ANEG_STATE_DISABLE_LINK_OK      4
3443 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3444 #define ANEG_STATE_ABILITY_DETECT       6
3445 #define ANEG_STATE_ACK_DETECT_INIT      7
3446 #define ANEG_STATE_ACK_DETECT           8
3447 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3448 #define ANEG_STATE_COMPLETE_ACK         10
3449 #define ANEG_STATE_IDLE_DETECT_INIT     11
3450 #define ANEG_STATE_IDLE_DETECT          12
3451 #define ANEG_STATE_LINK_OK              13
3452 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3453 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3454
3455         u32 flags;
3456 #define MR_AN_ENABLE            0x00000001
3457 #define MR_RESTART_AN           0x00000002
3458 #define MR_AN_COMPLETE          0x00000004
3459 #define MR_PAGE_RX              0x00000008
3460 #define MR_NP_LOADED            0x00000010
3461 #define MR_TOGGLE_TX            0x00000020
3462 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3463 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3464 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3465 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3466 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3467 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3468 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3469 #define MR_TOGGLE_RX            0x00002000
3470 #define MR_NP_RX                0x00004000
3471
3472 #define MR_LINK_OK              0x80000000
3473
3474         unsigned long link_time, cur_time;
3475
3476         u32 ability_match_cfg;
3477         int ability_match_count;
3478
3479         char ability_match, idle_match, ack_match;
3480
3481         u32 txconfig, rxconfig;
3482 #define ANEG_CFG_NP             0x00000080
3483 #define ANEG_CFG_ACK            0x00000040
3484 #define ANEG_CFG_RF2            0x00000020
3485 #define ANEG_CFG_RF1            0x00000010
3486 #define ANEG_CFG_PS2            0x00000001
3487 #define ANEG_CFG_PS1            0x00008000
3488 #define ANEG_CFG_HD             0x00004000
3489 #define ANEG_CFG_FD             0x00002000
3490 #define ANEG_CFG_INVAL          0x00001f06
3491
3492 };
3493 #define ANEG_OK         0
3494 #define ANEG_DONE       1
3495 #define ANEG_TIMER_ENAB 2
3496 #define ANEG_FAILED     -1
3497
3498 #define ANEG_STATE_SETTLE_TIME  10000
3499
3500 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3501                                    struct tg3_fiber_aneginfo *ap)
3502 {
3503         u16 flowctrl;
3504         unsigned long delta;
3505         u32 rx_cfg_reg;
3506         int ret;
3507
3508         if (ap->state == ANEG_STATE_UNKNOWN) {
3509                 ap->rxconfig = 0;
3510                 ap->link_time = 0;
3511                 ap->cur_time = 0;
3512                 ap->ability_match_cfg = 0;
3513                 ap->ability_match_count = 0;
3514                 ap->ability_match = 0;
3515                 ap->idle_match = 0;
3516                 ap->ack_match = 0;
3517         }
3518         ap->cur_time++;
3519
3520         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3521                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3522
3523                 if (rx_cfg_reg != ap->ability_match_cfg) {
3524                         ap->ability_match_cfg = rx_cfg_reg;
3525                         ap->ability_match = 0;
3526                         ap->ability_match_count = 0;
3527                 } else {
3528                         if (++ap->ability_match_count > 1) {
3529                                 ap->ability_match = 1;
3530                                 ap->ability_match_cfg = rx_cfg_reg;
3531                         }
3532                 }
3533                 if (rx_cfg_reg & ANEG_CFG_ACK)
3534                         ap->ack_match = 1;
3535                 else
3536                         ap->ack_match = 0;
3537
3538                 ap->idle_match = 0;
3539         } else {
3540                 ap->idle_match = 1;
3541                 ap->ability_match_cfg = 0;
3542                 ap->ability_match_count = 0;
3543                 ap->ability_match = 0;
3544                 ap->ack_match = 0;
3545
3546                 rx_cfg_reg = 0;
3547         }
3548
3549         ap->rxconfig = rx_cfg_reg;
3550         ret = ANEG_OK;
3551
3552         switch (ap->state) {
3553         case ANEG_STATE_UNKNOWN:
3554                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556
3557                 /* fallthru */
3558         case ANEG_STATE_AN_ENABLE:
3559                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3560                 if (ap->flags & MR_AN_ENABLE) {
3561                         ap->link_time = 0;
3562                         ap->cur_time = 0;
3563                         ap->ability_match_cfg = 0;
3564                         ap->ability_match_count = 0;
3565                         ap->ability_match = 0;
3566                         ap->idle_match = 0;
3567                         ap->ack_match = 0;
3568
3569                         ap->state = ANEG_STATE_RESTART_INIT;
3570                 } else {
3571                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3572                 }
3573                 break;
3574
3575         case ANEG_STATE_RESTART_INIT:
3576                 ap->link_time = ap->cur_time;
3577                 ap->flags &= ~(MR_NP_LOADED);
3578                 ap->txconfig = 0;
3579                 tw32(MAC_TX_AUTO_NEG, 0);
3580                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3581                 tw32_f(MAC_MODE, tp->mac_mode);
3582                 udelay(40);
3583
3584                 ret = ANEG_TIMER_ENAB;
3585                 ap->state = ANEG_STATE_RESTART;
3586
3587                 /* fallthru */
3588         case ANEG_STATE_RESTART:
3589                 delta = ap->cur_time - ap->link_time;
3590                 if (delta > ANEG_STATE_SETTLE_TIME)
3591                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3592                 else
3593                         ret = ANEG_TIMER_ENAB;
3594                 break;
3595
3596         case ANEG_STATE_DISABLE_LINK_OK:
3597                 ret = ANEG_DONE;
3598                 break;
3599
3600         case ANEG_STATE_ABILITY_DETECT_INIT:
3601                 ap->flags &= ~(MR_TOGGLE_TX);
3602                 ap->txconfig = ANEG_CFG_FD;
3603                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3604                 if (flowctrl & ADVERTISE_1000XPAUSE)
3605                         ap->txconfig |= ANEG_CFG_PS1;
3606                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3607                         ap->txconfig |= ANEG_CFG_PS2;
3608                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3609                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3610                 tw32_f(MAC_MODE, tp->mac_mode);
3611                 udelay(40);
3612
3613                 ap->state = ANEG_STATE_ABILITY_DETECT;
3614                 break;
3615
3616         case ANEG_STATE_ABILITY_DETECT:
3617                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3618                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3619                 break;
3620
3621         case ANEG_STATE_ACK_DETECT_INIT:
3622                 ap->txconfig |= ANEG_CFG_ACK;
3623                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3624                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3625                 tw32_f(MAC_MODE, tp->mac_mode);
3626                 udelay(40);
3627
3628                 ap->state = ANEG_STATE_ACK_DETECT;
3629
3630                 /* fallthru */
3631         case ANEG_STATE_ACK_DETECT:
3632                 if (ap->ack_match != 0) {
3633                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3634                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3635                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3636                         } else {
3637                                 ap->state = ANEG_STATE_AN_ENABLE;
3638                         }
3639                 } else if (ap->ability_match != 0 &&
3640                            ap->rxconfig == 0) {
3641                         ap->state = ANEG_STATE_AN_ENABLE;
3642                 }
3643                 break;
3644
3645         case ANEG_STATE_COMPLETE_ACK_INIT:
3646                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3647                         ret = ANEG_FAILED;
3648                         break;
3649                 }
3650                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3651                                MR_LP_ADV_HALF_DUPLEX |
3652                                MR_LP_ADV_SYM_PAUSE |
3653                                MR_LP_ADV_ASYM_PAUSE |
3654                                MR_LP_ADV_REMOTE_FAULT1 |
3655                                MR_LP_ADV_REMOTE_FAULT2 |
3656                                MR_LP_ADV_NEXT_PAGE |
3657                                MR_TOGGLE_RX |
3658                                MR_NP_RX);
3659                 if (ap->rxconfig & ANEG_CFG_FD)
3660                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3661                 if (ap->rxconfig & ANEG_CFG_HD)
3662                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3663                 if (ap->rxconfig & ANEG_CFG_PS1)
3664                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3665                 if (ap->rxconfig & ANEG_CFG_PS2)
3666                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3667                 if (ap->rxconfig & ANEG_CFG_RF1)
3668                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3669                 if (ap->rxconfig & ANEG_CFG_RF2)
3670                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3671                 if (ap->rxconfig & ANEG_CFG_NP)
3672                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3673
3674                 ap->link_time = ap->cur_time;
3675
3676                 ap->flags ^= (MR_TOGGLE_TX);
3677                 if (ap->rxconfig & 0x0008)
3678                         ap->flags |= MR_TOGGLE_RX;
3679                 if (ap->rxconfig & ANEG_CFG_NP)
3680                         ap->flags |= MR_NP_RX;
3681                 ap->flags |= MR_PAGE_RX;
3682
3683                 ap->state = ANEG_STATE_COMPLETE_ACK;
3684                 ret = ANEG_TIMER_ENAB;
3685                 break;
3686
3687         case ANEG_STATE_COMPLETE_ACK:
3688                 if (ap->ability_match != 0 &&
3689                     ap->rxconfig == 0) {
3690                         ap->state = ANEG_STATE_AN_ENABLE;
3691                         break;
3692                 }
3693                 delta = ap->cur_time - ap->link_time;
3694                 if (delta > ANEG_STATE_SETTLE_TIME) {
3695                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3696                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3697                         } else {
3698                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3699                                     !(ap->flags & MR_NP_RX)) {
3700                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3701                                 } else {
3702                                         ret = ANEG_FAILED;
3703                                 }
3704                         }
3705                 }
3706                 break;
3707
3708         case ANEG_STATE_IDLE_DETECT_INIT:
3709                 ap->link_time = ap->cur_time;
3710                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3711                 tw32_f(MAC_MODE, tp->mac_mode);
3712                 udelay(40);
3713
3714                 ap->state = ANEG_STATE_IDLE_DETECT;
3715                 ret = ANEG_TIMER_ENAB;
3716                 break;
3717
3718         case ANEG_STATE_IDLE_DETECT:
3719                 if (ap->ability_match != 0 &&
3720                     ap->rxconfig == 0) {
3721                         ap->state = ANEG_STATE_AN_ENABLE;
3722                         break;
3723                 }
3724                 delta = ap->cur_time - ap->link_time;
3725                 if (delta > ANEG_STATE_SETTLE_TIME) {
3726                         /* XXX another gem from the Broadcom driver :( */
3727                         ap->state = ANEG_STATE_LINK_OK;
3728                 }
3729                 break;
3730
3731         case ANEG_STATE_LINK_OK:
3732                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3733                 ret = ANEG_DONE;
3734                 break;
3735
3736         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3737                 /* ??? unimplemented */
3738                 break;
3739
3740         case ANEG_STATE_NEXT_PAGE_WAIT:
3741                 /* ??? unimplemented */
3742                 break;
3743
3744         default:
3745                 ret = ANEG_FAILED;
3746                 break;
3747         }
3748
3749         return ret;
3750 }
3751
3752 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3753 {
3754         int res = 0;
3755         struct tg3_fiber_aneginfo aninfo;
3756         int status = ANEG_FAILED;
3757         unsigned int tick;
3758         u32 tmp;
3759
3760         tw32_f(MAC_TX_AUTO_NEG, 0);
3761
3762         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3763         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3764         udelay(40);
3765
3766         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3767         udelay(40);
3768
3769         memset(&aninfo, 0, sizeof(aninfo));
3770         aninfo.flags |= MR_AN_ENABLE;
3771         aninfo.state = ANEG_STATE_UNKNOWN;
3772         aninfo.cur_time = 0;
3773         tick = 0;
3774         while (++tick < 195000) {
3775                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3776                 if (status == ANEG_DONE || status == ANEG_FAILED)
3777                         break;
3778
3779                 udelay(1);
3780         }
3781
3782         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3783         tw32_f(MAC_MODE, tp->mac_mode);
3784         udelay(40);
3785
3786         *txflags = aninfo.txconfig;
3787         *rxflags = aninfo.flags;
3788
3789         if (status == ANEG_DONE &&
3790             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3791                              MR_LP_ADV_FULL_DUPLEX)))
3792                 res = 1;
3793
3794         return res;
3795 }
3796
3797 static void tg3_init_bcm8002(struct tg3 *tp)
3798 {
3799         u32 mac_status = tr32(MAC_STATUS);
3800         int i;
3801
3802         /* Reset when initting first time or we have a link. */
3803         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3804             !(mac_status & MAC_STATUS_PCS_SYNCED))
3805                 return;
3806
3807         /* Set PLL lock range. */
3808         tg3_writephy(tp, 0x16, 0x8007);
3809
3810         /* SW reset */
3811         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3812
3813         /* Wait for reset to complete. */
3814         /* XXX schedule_timeout() ... */
3815         for (i = 0; i < 500; i++)
3816                 udelay(10);
3817
3818         /* Config mode; select PMA/Ch 1 regs. */
3819         tg3_writephy(tp, 0x10, 0x8411);
3820
3821         /* Enable auto-lock and comdet, select txclk for tx. */
3822         tg3_writephy(tp, 0x11, 0x0a10);
3823
3824         tg3_writephy(tp, 0x18, 0x00a0);
3825         tg3_writephy(tp, 0x16, 0x41ff);
3826
3827         /* Assert and deassert POR. */
3828         tg3_writephy(tp, 0x13, 0x0400);
3829         udelay(40);
3830         tg3_writephy(tp, 0x13, 0x0000);
3831
3832         tg3_writephy(tp, 0x11, 0x0a50);
3833         udelay(40);
3834         tg3_writephy(tp, 0x11, 0x0a10);
3835
3836         /* Wait for signal to stabilize */
3837         /* XXX schedule_timeout() ... */
3838         for (i = 0; i < 15000; i++)
3839                 udelay(10);
3840
3841         /* Deselect the channel register so we can read the PHYID
3842          * later.
3843          */
3844         tg3_writephy(tp, 0x10, 0x8011);
3845 }
3846
3847 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3848 {
3849         u16 flowctrl;
3850         u32 sg_dig_ctrl, sg_dig_status;
3851         u32 serdes_cfg, expected_sg_dig_ctrl;
3852         int workaround, port_a;
3853         int current_link_up;
3854
3855         serdes_cfg = 0;
3856         expected_sg_dig_ctrl = 0;
3857         workaround = 0;
3858         port_a = 1;
3859         current_link_up = 0;
3860
3861         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3862             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3863                 workaround = 1;
3864                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3865                         port_a = 0;
3866
3867                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3868                 /* preserve bits 20-23 for voltage regulator */
3869                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3870         }
3871
3872         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3873
3874         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3875                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3876                         if (workaround) {
3877                                 u32 val = serdes_cfg;
3878
3879                                 if (port_a)
3880                                         val |= 0xc010000;
3881                                 else
3882                                         val |= 0x4010000;
3883                                 tw32_f(MAC_SERDES_CFG, val);
3884                         }
3885
3886                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3887                 }
3888                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3889                         tg3_setup_flow_control(tp, 0, 0);
3890                         current_link_up = 1;
3891                 }
3892                 goto out;
3893         }
3894
3895         /* Want auto-negotiation.  */
3896         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3897
3898         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3899         if (flowctrl & ADVERTISE_1000XPAUSE)
3900                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3901         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3902                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3903
3904         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3905                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3906                     tp->serdes_counter &&
3907                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3908                                     MAC_STATUS_RCVD_CFG)) ==
3909                      MAC_STATUS_PCS_SYNCED)) {
3910                         tp->serdes_counter--;
3911                         current_link_up = 1;
3912                         goto out;
3913                 }
3914 restart_autoneg:
3915                 if (workaround)
3916                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3917                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3918                 udelay(5);
3919                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3920
3921                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3922                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3923         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3924                                  MAC_STATUS_SIGNAL_DET)) {
3925                 sg_dig_status = tr32(SG_DIG_STATUS);
3926                 mac_status = tr32(MAC_STATUS);
3927
3928                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3929                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3930                         u32 local_adv = 0, remote_adv = 0;
3931
3932                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3933                                 local_adv |= ADVERTISE_1000XPAUSE;
3934                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3935                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3936
3937                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3938                                 remote_adv |= LPA_1000XPAUSE;
3939                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3940                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3941
3942                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3943                         current_link_up = 1;
3944                         tp->serdes_counter = 0;
3945                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3946                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3947                         if (tp->serdes_counter)
3948                                 tp->serdes_counter--;
3949                         else {
3950                                 if (workaround) {
3951                                         u32 val = serdes_cfg;
3952
3953                                         if (port_a)
3954                                                 val |= 0xc010000;
3955                                         else
3956                                                 val |= 0x4010000;
3957
3958                                         tw32_f(MAC_SERDES_CFG, val);
3959                                 }
3960
3961                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3962                                 udelay(40);
3963
3964                                 /* Link parallel detection - link is up */
3965                                 /* only if we have PCS_SYNC and not */
3966                                 /* receiving config code words */
3967                                 mac_status = tr32(MAC_STATUS);
3968                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3969                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3970                                         tg3_setup_flow_control(tp, 0, 0);
3971                                         current_link_up = 1;
3972                                         tp->phy_flags |=
3973                                                 TG3_PHYFLG_PARALLEL_DETECT;
3974                                         tp->serdes_counter =
3975                                                 SERDES_PARALLEL_DET_TIMEOUT;
3976                                 } else
3977                                         goto restart_autoneg;
3978                         }
3979                 }
3980         } else {
3981                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3982                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3983         }
3984
3985 out:
3986         return current_link_up;
3987 }
3988
3989 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3990 {
3991         int current_link_up = 0;
3992
3993         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3994                 goto out;
3995
3996         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3997                 u32 txflags, rxflags;
3998                 int i;
3999
4000                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4001                         u32 local_adv = 0, remote_adv = 0;
4002
4003                         if (txflags & ANEG_CFG_PS1)
4004                                 local_adv |= ADVERTISE_1000XPAUSE;
4005                         if (txflags & ANEG_CFG_PS2)
4006                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4007
4008                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4009                                 remote_adv |= LPA_1000XPAUSE;
4010                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4011                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4012
4013                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4014
4015                         current_link_up = 1;
4016                 }
4017                 for (i = 0; i < 30; i++) {
4018                         udelay(20);
4019                         tw32_f(MAC_STATUS,
4020                                (MAC_STATUS_SYNC_CHANGED |
4021                                 MAC_STATUS_CFG_CHANGED));
4022                         udelay(40);
4023                         if ((tr32(MAC_STATUS) &
4024                              (MAC_STATUS_SYNC_CHANGED |
4025                               MAC_STATUS_CFG_CHANGED)) == 0)
4026                                 break;
4027                 }
4028
4029                 mac_status = tr32(MAC_STATUS);
4030                 if (current_link_up == 0 &&
4031                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4032                     !(mac_status & MAC_STATUS_RCVD_CFG))
4033                         current_link_up = 1;
4034         } else {
4035                 tg3_setup_flow_control(tp, 0, 0);
4036
4037                 /* Forcing 1000FD link up. */
4038                 current_link_up = 1;
4039
4040                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4041                 udelay(40);
4042
4043                 tw32_f(MAC_MODE, tp->mac_mode);
4044                 udelay(40);
4045         }
4046
4047 out:
4048         return current_link_up;
4049 }
4050
4051 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4052 {
4053         u32 orig_pause_cfg;
4054         u16 orig_active_speed;
4055         u8 orig_active_duplex;
4056         u32 mac_status;
4057         int current_link_up;
4058         int i;
4059
4060         orig_pause_cfg = tp->link_config.active_flowctrl;
4061         orig_active_speed = tp->link_config.active_speed;
4062         orig_active_duplex = tp->link_config.active_duplex;
4063
4064         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4065             netif_carrier_ok(tp->dev) &&
4066             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4067                 mac_status = tr32(MAC_STATUS);
4068                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4069                                MAC_STATUS_SIGNAL_DET |
4070                                MAC_STATUS_CFG_CHANGED |
4071                                MAC_STATUS_RCVD_CFG);
4072                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4073                                    MAC_STATUS_SIGNAL_DET)) {
4074                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4075                                             MAC_STATUS_CFG_CHANGED));
4076                         return 0;
4077                 }
4078         }
4079
4080         tw32_f(MAC_TX_AUTO_NEG, 0);
4081
4082         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4083         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4084         tw32_f(MAC_MODE, tp->mac_mode);
4085         udelay(40);
4086
4087         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4088                 tg3_init_bcm8002(tp);
4089
4090         /* Enable link change event even when serdes polling.  */
4091         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4092         udelay(40);
4093
4094         current_link_up = 0;
4095         mac_status = tr32(MAC_STATUS);
4096
4097         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4098                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4099         else
4100                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4101
4102         tp->napi[0].hw_status->status =
4103                 (SD_STATUS_UPDATED |
4104                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4105
4106         for (i = 0; i < 100; i++) {
4107                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4108                                     MAC_STATUS_CFG_CHANGED));
4109                 udelay(5);
4110                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4111                                          MAC_STATUS_CFG_CHANGED |
4112                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4113                         break;
4114         }
4115
4116         mac_status = tr32(MAC_STATUS);
4117         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4118                 current_link_up = 0;
4119                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4120                     tp->serdes_counter == 0) {
4121                         tw32_f(MAC_MODE, (tp->mac_mode |
4122                                           MAC_MODE_SEND_CONFIGS));
4123                         udelay(1);
4124                         tw32_f(MAC_MODE, tp->mac_mode);
4125                 }
4126         }
4127
4128         if (current_link_up == 1) {
4129                 tp->link_config.active_speed = SPEED_1000;
4130                 tp->link_config.active_duplex = DUPLEX_FULL;
4131                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4132                                     LED_CTRL_LNKLED_OVERRIDE |
4133                                     LED_CTRL_1000MBPS_ON));
4134         } else {
4135                 tp->link_config.active_speed = SPEED_INVALID;
4136                 tp->link_config.active_duplex = DUPLEX_INVALID;
4137                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4138                                     LED_CTRL_LNKLED_OVERRIDE |
4139                                     LED_CTRL_TRAFFIC_OVERRIDE));
4140         }
4141
4142         if (current_link_up != netif_carrier_ok(tp->dev)) {
4143                 if (current_link_up)
4144                         netif_carrier_on(tp->dev);
4145                 else
4146                         netif_carrier_off(tp->dev);
4147                 tg3_link_report(tp);
4148         } else {
4149                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4150                 if (orig_pause_cfg != now_pause_cfg ||
4151                     orig_active_speed != tp->link_config.active_speed ||
4152                     orig_active_duplex != tp->link_config.active_duplex)
4153                         tg3_link_report(tp);
4154         }
4155
4156         return 0;
4157 }
4158
4159 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4160 {
4161         int current_link_up, err = 0;
4162         u32 bmsr, bmcr;
4163         u16 current_speed;
4164         u8 current_duplex;
4165         u32 local_adv, remote_adv;
4166
4167         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4168         tw32_f(MAC_MODE, tp->mac_mode);
4169         udelay(40);
4170
4171         tw32(MAC_EVENT, 0);
4172
4173         tw32_f(MAC_STATUS,
4174              (MAC_STATUS_SYNC_CHANGED |
4175               MAC_STATUS_CFG_CHANGED |
4176               MAC_STATUS_MI_COMPLETION |
4177               MAC_STATUS_LNKSTATE_CHANGED));
4178         udelay(40);
4179
4180         if (force_reset)
4181                 tg3_phy_reset(tp);
4182
4183         current_link_up = 0;
4184         current_speed = SPEED_INVALID;
4185         current_duplex = DUPLEX_INVALID;
4186
4187         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4188         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4190                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4191                         bmsr |= BMSR_LSTATUS;
4192                 else
4193                         bmsr &= ~BMSR_LSTATUS;
4194         }
4195
4196         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4197
4198         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4199             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4200                 /* do nothing, just check for link up at the end */
4201         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4202                 u32 adv, new_adv;
4203
4204                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4205                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4206                                   ADVERTISE_1000XPAUSE |
4207                                   ADVERTISE_1000XPSE_ASYM |
4208                                   ADVERTISE_SLCT);
4209
4210                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4211
4212                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4213                         new_adv |= ADVERTISE_1000XHALF;
4214                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4215                         new_adv |= ADVERTISE_1000XFULL;
4216
4217                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4218                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4219                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4220                         tg3_writephy(tp, MII_BMCR, bmcr);
4221
4222                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4223                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4224                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4225
4226                         return err;
4227                 }
4228         } else {
4229                 u32 new_bmcr;
4230
4231                 bmcr &= ~BMCR_SPEED1000;
4232                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4233
4234                 if (tp->link_config.duplex == DUPLEX_FULL)
4235                         new_bmcr |= BMCR_FULLDPLX;
4236
4237                 if (new_bmcr != bmcr) {
4238                         /* BMCR_SPEED1000 is a reserved bit that needs
4239                          * to be set on write.
4240                          */
4241                         new_bmcr |= BMCR_SPEED1000;
4242
4243                         /* Force a linkdown */
4244                         if (netif_carrier_ok(tp->dev)) {
4245                                 u32 adv;
4246
4247                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4248                                 adv &= ~(ADVERTISE_1000XFULL |
4249                                          ADVERTISE_1000XHALF |
4250                                          ADVERTISE_SLCT);
4251                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4252                                 tg3_writephy(tp, MII_BMCR, bmcr |
4253                                                            BMCR_ANRESTART |
4254                                                            BMCR_ANENABLE);
4255                                 udelay(10);
4256                                 netif_carrier_off(tp->dev);
4257                         }
4258                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4259                         bmcr = new_bmcr;
4260                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4261                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4262                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4263                             ASIC_REV_5714) {
4264                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4265                                         bmsr |= BMSR_LSTATUS;
4266                                 else
4267                                         bmsr &= ~BMSR_LSTATUS;
4268                         }
4269                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4270                 }
4271         }
4272
4273         if (bmsr & BMSR_LSTATUS) {
4274                 current_speed = SPEED_1000;
4275                 current_link_up = 1;
4276                 if (bmcr & BMCR_FULLDPLX)
4277                         current_duplex = DUPLEX_FULL;
4278                 else
4279                         current_duplex = DUPLEX_HALF;
4280
4281                 local_adv = 0;
4282                 remote_adv = 0;
4283
4284                 if (bmcr & BMCR_ANENABLE) {
4285                         u32 common;
4286
4287                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4288                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4289                         common = local_adv & remote_adv;
4290                         if (common & (ADVERTISE_1000XHALF |
4291                                       ADVERTISE_1000XFULL)) {
4292                                 if (common & ADVERTISE_1000XFULL)
4293                                         current_duplex = DUPLEX_FULL;
4294                                 else
4295                                         current_duplex = DUPLEX_HALF;
4296                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4297                                 /* Link is up via parallel detect */
4298                         } else {
4299                                 current_link_up = 0;
4300                         }
4301                 }
4302         }
4303
4304         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4305                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4306
4307         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4308         if (tp->link_config.active_duplex == DUPLEX_HALF)
4309                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4310
4311         tw32_f(MAC_MODE, tp->mac_mode);
4312         udelay(40);
4313
4314         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4315
4316         tp->link_config.active_speed = current_speed;
4317         tp->link_config.active_duplex = current_duplex;
4318
4319         if (current_link_up != netif_carrier_ok(tp->dev)) {
4320                 if (current_link_up)
4321                         netif_carrier_on(tp->dev);
4322                 else {
4323                         netif_carrier_off(tp->dev);
4324                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4325                 }
4326                 tg3_link_report(tp);
4327         }
4328         return err;
4329 }
4330
4331 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4332 {
4333         if (tp->serdes_counter) {
4334                 /* Give autoneg time to complete. */
4335                 tp->serdes_counter--;
4336                 return;
4337         }
4338
4339         if (!netif_carrier_ok(tp->dev) &&
4340             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4341                 u32 bmcr;
4342
4343                 tg3_readphy(tp, MII_BMCR, &bmcr);
4344                 if (bmcr & BMCR_ANENABLE) {
4345                         u32 phy1, phy2;
4346
4347                         /* Select shadow register 0x1f */
4348                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4349                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4350
4351                         /* Select expansion interrupt status register */
4352                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4353                                          MII_TG3_DSP_EXP1_INT_STAT);
4354                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4355                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4356
4357                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4358                                 /* We have signal detect and not receiving
4359                                  * config code words, link is up by parallel
4360                                  * detection.
4361                                  */
4362
4363                                 bmcr &= ~BMCR_ANENABLE;
4364                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4365                                 tg3_writephy(tp, MII_BMCR, bmcr);
4366                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4367                         }
4368                 }
4369         } else if (netif_carrier_ok(tp->dev) &&
4370                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4371                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4372                 u32 phy2;
4373
4374                 /* Select expansion interrupt status register */
4375                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4376                                  MII_TG3_DSP_EXP1_INT_STAT);
4377                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4378                 if (phy2 & 0x20) {
4379                         u32 bmcr;
4380
4381                         /* Config code words received, turn on autoneg. */
4382                         tg3_readphy(tp, MII_BMCR, &bmcr);
4383                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4384
4385                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4386
4387                 }
4388         }
4389 }
4390
4391 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4392 {
4393         u32 val;
4394         int err;
4395
4396         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4397                 err = tg3_setup_fiber_phy(tp, force_reset);
4398         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4399                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4400         else
4401                 err = tg3_setup_copper_phy(tp, force_reset);
4402
4403         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4404                 u32 scale;
4405
4406                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4407                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4408                         scale = 65;
4409                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4410                         scale = 6;
4411                 else
4412                         scale = 12;
4413
4414                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4415                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4416                 tw32(GRC_MISC_CFG, val);
4417         }
4418
4419         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4420               (6 << TX_LENGTHS_IPG_SHIFT);
4421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4422                 val |= tr32(MAC_TX_LENGTHS) &
4423                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4424                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4425
4426         if (tp->link_config.active_speed == SPEED_1000 &&
4427             tp->link_config.active_duplex == DUPLEX_HALF)
4428                 tw32(MAC_TX_LENGTHS, val |
4429                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4430         else
4431                 tw32(MAC_TX_LENGTHS, val |
4432                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4433
4434         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4435                 if (netif_carrier_ok(tp->dev)) {
4436                         tw32(HOSTCC_STAT_COAL_TICKS,
4437                              tp->coal.stats_block_coalesce_usecs);
4438                 } else {
4439                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4440                 }
4441         }
4442
4443         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4444                 val = tr32(PCIE_PWR_MGMT_THRESH);
4445                 if (!netif_carrier_ok(tp->dev))
4446                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4447                               tp->pwrmgmt_thresh;
4448                 else
4449                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4450                 tw32(PCIE_PWR_MGMT_THRESH, val);
4451         }
4452
4453         return err;
4454 }
4455
4456 static inline int tg3_irq_sync(struct tg3 *tp)
4457 {
4458         return tp->irq_sync;
4459 }
4460
4461 /* This is called whenever we suspect that the system chipset is re-
4462  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4463  * is bogus tx completions. We try to recover by setting the
4464  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4465  * in the workqueue.
4466  */
4467 static void tg3_tx_recover(struct tg3 *tp)
4468 {
4469         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4470                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4471
4472         netdev_warn(tp->dev,
4473                     "The system may be re-ordering memory-mapped I/O "
4474                     "cycles to the network device, attempting to recover. "
4475                     "Please report the problem to the driver maintainer "
4476                     "and include system chipset information.\n");
4477
4478         spin_lock(&tp->lock);
4479         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4480         spin_unlock(&tp->lock);
4481 }
4482
4483 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4484 {
4485         /* Tell compiler to fetch tx indices from memory. */
4486         barrier();
4487         return tnapi->tx_pending -
4488                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4489 }
4490
4491 /* Tigon3 never reports partial packet sends.  So we do not
4492  * need special logic to handle SKBs that have not had all
4493  * of their frags sent yet, like SunGEM does.
4494  */
4495 static void tg3_tx(struct tg3_napi *tnapi)
4496 {
4497         struct tg3 *tp = tnapi->tp;
4498         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4499         u32 sw_idx = tnapi->tx_cons;
4500         struct netdev_queue *txq;
4501         int index = tnapi - tp->napi;
4502
4503         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4504                 index--;
4505
4506         txq = netdev_get_tx_queue(tp->dev, index);
4507
4508         while (sw_idx != hw_idx) {
4509                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4510                 struct sk_buff *skb = ri->skb;
4511                 int i, tx_bug = 0;
4512
4513                 if (unlikely(skb == NULL)) {
4514                         tg3_tx_recover(tp);
4515                         return;
4516                 }
4517
4518                 pci_unmap_single(tp->pdev,
4519                                  dma_unmap_addr(ri, mapping),
4520                                  skb_headlen(skb),
4521                                  PCI_DMA_TODEVICE);
4522
4523                 ri->skb = NULL;
4524
4525                 sw_idx = NEXT_TX(sw_idx);
4526
4527                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4528                         ri = &tnapi->tx_buffers[sw_idx];
4529                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4530                                 tx_bug = 1;
4531
4532                         pci_unmap_page(tp->pdev,
4533                                        dma_unmap_addr(ri, mapping),
4534                                        skb_shinfo(skb)->frags[i].size,
4535                                        PCI_DMA_TODEVICE);
4536                         sw_idx = NEXT_TX(sw_idx);
4537                 }
4538
4539                 dev_kfree_skb(skb);
4540
4541                 if (unlikely(tx_bug)) {
4542                         tg3_tx_recover(tp);
4543                         return;
4544                 }
4545         }
4546
4547         tnapi->tx_cons = sw_idx;
4548
4549         /* Need to make the tx_cons update visible to tg3_start_xmit()
4550          * before checking for netif_queue_stopped().  Without the
4551          * memory barrier, there is a small possibility that tg3_start_xmit()
4552          * will miss it and cause the queue to be stopped forever.
4553          */
4554         smp_mb();
4555
4556         if (unlikely(netif_tx_queue_stopped(txq) &&
4557                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4558                 __netif_tx_lock(txq, smp_processor_id());
4559                 if (netif_tx_queue_stopped(txq) &&
4560                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4561                         netif_tx_wake_queue(txq);
4562                 __netif_tx_unlock(txq);
4563         }
4564 }
4565
4566 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4567 {
4568         if (!ri->skb)
4569                 return;
4570
4571         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4572                          map_sz, PCI_DMA_FROMDEVICE);
4573         dev_kfree_skb_any(ri->skb);
4574         ri->skb = NULL;
4575 }
4576
4577 /* Returns size of skb allocated or < 0 on error.
4578  *
4579  * We only need to fill in the address because the other members
4580  * of the RX descriptor are invariant, see tg3_init_rings.
4581  *
4582  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4583  * posting buffers we only dirty the first cache line of the RX
4584  * descriptor (containing the address).  Whereas for the RX status
4585  * buffers the cpu only reads the last cacheline of the RX descriptor
4586  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4587  */
4588 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4589                             u32 opaque_key, u32 dest_idx_unmasked)
4590 {
4591         struct tg3_rx_buffer_desc *desc;
4592         struct ring_info *map;
4593         struct sk_buff *skb;
4594         dma_addr_t mapping;
4595         int skb_size, dest_idx;
4596
4597         switch (opaque_key) {
4598         case RXD_OPAQUE_RING_STD:
4599                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4600                 desc = &tpr->rx_std[dest_idx];
4601                 map = &tpr->rx_std_buffers[dest_idx];
4602                 skb_size = tp->rx_pkt_map_sz;
4603                 break;
4604
4605         case RXD_OPAQUE_RING_JUMBO:
4606                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4607                 desc = &tpr->rx_jmb[dest_idx].std;
4608                 map = &tpr->rx_jmb_buffers[dest_idx];
4609                 skb_size = TG3_RX_JMB_MAP_SZ;
4610                 break;
4611
4612         default:
4613                 return -EINVAL;
4614         }
4615
4616         /* Do not overwrite any of the map or rp information
4617          * until we are sure we can commit to a new buffer.
4618          *
4619          * Callers depend upon this behavior and assume that
4620          * we leave everything unchanged if we fail.
4621          */
4622         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4623         if (skb == NULL)
4624                 return -ENOMEM;
4625
4626         skb_reserve(skb, tp->rx_offset);
4627
4628         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4629                                  PCI_DMA_FROMDEVICE);
4630         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4631                 dev_kfree_skb(skb);
4632                 return -EIO;
4633         }
4634
4635         map->skb = skb;
4636         dma_unmap_addr_set(map, mapping, mapping);
4637
4638         desc->addr_hi = ((u64)mapping >> 32);
4639         desc->addr_lo = ((u64)mapping & 0xffffffff);
4640
4641         return skb_size;
4642 }
4643
4644 /* We only need to move over in the address because the other
4645  * members of the RX descriptor are invariant.  See notes above
4646  * tg3_alloc_rx_skb for full details.
4647  */
4648 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4649                            struct tg3_rx_prodring_set *dpr,
4650                            u32 opaque_key, int src_idx,
4651                            u32 dest_idx_unmasked)
4652 {
4653         struct tg3 *tp = tnapi->tp;
4654         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4655         struct ring_info *src_map, *dest_map;
4656         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4657         int dest_idx;
4658
4659         switch (opaque_key) {
4660         case RXD_OPAQUE_RING_STD:
4661                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4662                 dest_desc = &dpr->rx_std[dest_idx];
4663                 dest_map = &dpr->rx_std_buffers[dest_idx];
4664                 src_desc = &spr->rx_std[src_idx];
4665                 src_map = &spr->rx_std_buffers[src_idx];
4666                 break;
4667
4668         case RXD_OPAQUE_RING_JUMBO:
4669                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4670                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4671                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4672                 src_desc = &spr->rx_jmb[src_idx].std;
4673                 src_map = &spr->rx_jmb_buffers[src_idx];
4674                 break;
4675
4676         default:
4677                 return;
4678         }
4679
4680         dest_map->skb = src_map->skb;
4681         dma_unmap_addr_set(dest_map, mapping,
4682                            dma_unmap_addr(src_map, mapping));
4683         dest_desc->addr_hi = src_desc->addr_hi;
4684         dest_desc->addr_lo = src_desc->addr_lo;
4685
4686         /* Ensure that the update to the skb happens after the physical
4687          * addresses have been transferred to the new BD location.
4688          */
4689         smp_wmb();
4690
4691         src_map->skb = NULL;
4692 }
4693
4694 /* The RX ring scheme is composed of multiple rings which post fresh
4695  * buffers to the chip, and one special ring the chip uses to report
4696  * status back to the host.
4697  *
4698  * The special ring reports the status of received packets to the
4699  * host.  The chip does not write into the original descriptor the
4700  * RX buffer was obtained from.  The chip simply takes the original
4701  * descriptor as provided by the host, updates the status and length
4702  * field, then writes this into the next status ring entry.
4703  *
4704  * Each ring the host uses to post buffers to the chip is described
4705  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4706  * it is first placed into the on-chip ram.  When the packet's length
4707  * is known, it walks down the TG3_BDINFO entries to select the ring.
4708  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4709  * which is within the range of the new packet's length is chosen.
4710  *
4711  * The "separate ring for rx status" scheme may sound queer, but it makes
4712  * sense from a cache coherency perspective.  If only the host writes
4713  * to the buffer post rings, and only the chip writes to the rx status
4714  * rings, then cache lines never move beyond shared-modified state.
4715  * If both the host and chip were to write into the same ring, cache line
4716  * eviction could occur since both entities want it in an exclusive state.
4717  */
4718 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4719 {
4720         struct tg3 *tp = tnapi->tp;
4721         u32 work_mask, rx_std_posted = 0;
4722         u32 std_prod_idx, jmb_prod_idx;
4723         u32 sw_idx = tnapi->rx_rcb_ptr;
4724         u16 hw_idx;
4725         int received;
4726         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4727
4728         hw_idx = *(tnapi->rx_rcb_prod_idx);
4729         /*
4730          * We need to order the read of hw_idx and the read of
4731          * the opaque cookie.
4732          */
4733         rmb();
4734         work_mask = 0;
4735         received = 0;
4736         std_prod_idx = tpr->rx_std_prod_idx;
4737         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4738         while (sw_idx != hw_idx && budget > 0) {
4739                 struct ring_info *ri;
4740                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4741                 unsigned int len;
4742                 struct sk_buff *skb;
4743                 dma_addr_t dma_addr;
4744                 u32 opaque_key, desc_idx, *post_ptr;
4745
4746                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4747                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4748                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4749                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4750                         dma_addr = dma_unmap_addr(ri, mapping);
4751                         skb = ri->skb;
4752                         post_ptr = &std_prod_idx;
4753                         rx_std_posted++;
4754                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4755                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4756                         dma_addr = dma_unmap_addr(ri, mapping);
4757                         skb = ri->skb;
4758                         post_ptr = &jmb_prod_idx;
4759                 } else
4760                         goto next_pkt_nopost;
4761
4762                 work_mask |= opaque_key;
4763
4764                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4765                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4766                 drop_it:
4767                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4768                                        desc_idx, *post_ptr);
4769                 drop_it_no_recycle:
4770                         /* Other statistics kept track of by card. */
4771                         tp->rx_dropped++;
4772                         goto next_pkt;
4773                 }
4774
4775                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4776                       ETH_FCS_LEN;
4777
4778                 if (len > TG3_RX_COPY_THRESH(tp)) {
4779                         int skb_size;
4780
4781                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4782                                                     *post_ptr);
4783                         if (skb_size < 0)
4784                                 goto drop_it;
4785
4786                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4787                                          PCI_DMA_FROMDEVICE);
4788
4789                         /* Ensure that the update to the skb happens
4790                          * after the usage of the old DMA mapping.
4791                          */
4792                         smp_wmb();
4793
4794                         ri->skb = NULL;
4795
4796                         skb_put(skb, len);
4797                 } else {
4798                         struct sk_buff *copy_skb;
4799
4800                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4801                                        desc_idx, *post_ptr);
4802
4803                         copy_skb = netdev_alloc_skb(tp->dev, len +
4804                                                     TG3_RAW_IP_ALIGN);
4805                         if (copy_skb == NULL)
4806                                 goto drop_it_no_recycle;
4807
4808                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4809                         skb_put(copy_skb, len);
4810                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4811                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4812                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4813
4814                         /* We'll reuse the original ring buffer. */
4815                         skb = copy_skb;
4816                 }
4817
4818                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4819                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4820                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4821                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4822                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4823                 else
4824                         skb_checksum_none_assert(skb);
4825
4826                 skb->protocol = eth_type_trans(skb, tp->dev);
4827
4828                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4829                     skb->protocol != htons(ETH_P_8021Q)) {
4830                         dev_kfree_skb(skb);
4831                         goto drop_it_no_recycle;
4832                 }
4833
4834                 if (desc->type_flags & RXD_FLAG_VLAN &&
4835                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4836                         __vlan_hwaccel_put_tag(skb,
4837                                                desc->err_vlan & RXD_VLAN_MASK);
4838
4839                 napi_gro_receive(&tnapi->napi, skb);
4840
4841                 received++;
4842                 budget--;
4843
4844 next_pkt:
4845                 (*post_ptr)++;
4846
4847                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4848                         tpr->rx_std_prod_idx = std_prod_idx &
4849                                                tp->rx_std_ring_mask;
4850                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4851                                      tpr->rx_std_prod_idx);
4852                         work_mask &= ~RXD_OPAQUE_RING_STD;
4853                         rx_std_posted = 0;
4854                 }
4855 next_pkt_nopost:
4856                 sw_idx++;
4857                 sw_idx &= tp->rx_ret_ring_mask;
4858
4859                 /* Refresh hw_idx to see if there is new work */
4860                 if (sw_idx == hw_idx) {
4861                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4862                         rmb();
4863                 }
4864         }
4865
4866         /* ACK the status ring. */
4867         tnapi->rx_rcb_ptr = sw_idx;
4868         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4869
4870         /* Refill RX ring(s). */
4871         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4872                 if (work_mask & RXD_OPAQUE_RING_STD) {
4873                         tpr->rx_std_prod_idx = std_prod_idx &
4874                                                tp->rx_std_ring_mask;
4875                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4876                                      tpr->rx_std_prod_idx);
4877                 }
4878                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4879                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4880                                                tp->rx_jmb_ring_mask;
4881                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4882                                      tpr->rx_jmb_prod_idx);
4883                 }
4884                 mmiowb();
4885         } else if (work_mask) {
4886                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4887                  * updated before the producer indices can be updated.
4888                  */
4889                 smp_wmb();
4890
4891                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4892                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4893
4894                 if (tnapi != &tp->napi[1])
4895                         napi_schedule(&tp->napi[1].napi);
4896         }
4897
4898         return received;
4899 }
4900
4901 static void tg3_poll_link(struct tg3 *tp)
4902 {
4903         /* handle link change and other phy events */
4904         if (!(tp->tg3_flags &
4905               (TG3_FLAG_USE_LINKCHG_REG |
4906                TG3_FLAG_POLL_SERDES))) {
4907                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4908
4909                 if (sblk->status & SD_STATUS_LINK_CHG) {
4910                         sblk->status = SD_STATUS_UPDATED |
4911                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4912                         spin_lock(&tp->lock);
4913                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4914                                 tw32_f(MAC_STATUS,
4915                                      (MAC_STATUS_SYNC_CHANGED |
4916                                       MAC_STATUS_CFG_CHANGED |
4917                                       MAC_STATUS_MI_COMPLETION |
4918                                       MAC_STATUS_LNKSTATE_CHANGED));
4919                                 udelay(40);
4920                         } else
4921                                 tg3_setup_phy(tp, 0);
4922                         spin_unlock(&tp->lock);
4923                 }
4924         }
4925 }
4926
4927 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4928                                 struct tg3_rx_prodring_set *dpr,
4929                                 struct tg3_rx_prodring_set *spr)
4930 {
4931         u32 si, di, cpycnt, src_prod_idx;
4932         int i, err = 0;
4933
4934         while (1) {
4935                 src_prod_idx = spr->rx_std_prod_idx;
4936
4937                 /* Make sure updates to the rx_std_buffers[] entries and the
4938                  * standard producer index are seen in the correct order.
4939                  */
4940                 smp_rmb();
4941
4942                 if (spr->rx_std_cons_idx == src_prod_idx)
4943                         break;
4944
4945                 if (spr->rx_std_cons_idx < src_prod_idx)
4946                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4947                 else
4948                         cpycnt = tp->rx_std_ring_mask + 1 -
4949                                  spr->rx_std_cons_idx;
4950
4951                 cpycnt = min(cpycnt,
4952                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4953
4954                 si = spr->rx_std_cons_idx;
4955                 di = dpr->rx_std_prod_idx;
4956
4957                 for (i = di; i < di + cpycnt; i++) {
4958                         if (dpr->rx_std_buffers[i].skb) {
4959                                 cpycnt = i - di;
4960                                 err = -ENOSPC;
4961                                 break;
4962                         }
4963                 }
4964
4965                 if (!cpycnt)
4966                         break;
4967
4968                 /* Ensure that updates to the rx_std_buffers ring and the
4969                  * shadowed hardware producer ring from tg3_recycle_skb() are
4970                  * ordered correctly WRT the skb check above.
4971                  */
4972                 smp_rmb();
4973
4974                 memcpy(&dpr->rx_std_buffers[di],
4975                        &spr->rx_std_buffers[si],
4976                        cpycnt * sizeof(struct ring_info));
4977
4978                 for (i = 0; i < cpycnt; i++, di++, si++) {
4979                         struct tg3_rx_buffer_desc *sbd, *dbd;
4980                         sbd = &spr->rx_std[si];
4981                         dbd = &dpr->rx_std[di];
4982                         dbd->addr_hi = sbd->addr_hi;
4983                         dbd->addr_lo = sbd->addr_lo;
4984                 }
4985
4986                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4987                                        tp->rx_std_ring_mask;
4988                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4989                                        tp->rx_std_ring_mask;
4990         }
4991
4992         while (1) {
4993                 src_prod_idx = spr->rx_jmb_prod_idx;
4994
4995                 /* Make sure updates to the rx_jmb_buffers[] entries and
4996                  * the jumbo producer index are seen in the correct order.
4997                  */
4998                 smp_rmb();
4999
5000                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5001                         break;
5002
5003                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5004                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5005                 else
5006                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5007                                  spr->rx_jmb_cons_idx;
5008
5009                 cpycnt = min(cpycnt,
5010                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5011
5012                 si = spr->rx_jmb_cons_idx;
5013                 di = dpr->rx_jmb_prod_idx;
5014
5015                 for (i = di; i < di + cpycnt; i++) {
5016                         if (dpr->rx_jmb_buffers[i].skb) {
5017                                 cpycnt = i - di;
5018                                 err = -ENOSPC;
5019                                 break;
5020                         }
5021                 }
5022
5023                 if (!cpycnt)
5024                         break;
5025
5026                 /* Ensure that updates to the rx_jmb_buffers ring and the
5027                  * shadowed hardware producer ring from tg3_recycle_skb() are
5028                  * ordered correctly WRT the skb check above.
5029                  */
5030                 smp_rmb();
5031
5032                 memcpy(&dpr->rx_jmb_buffers[di],
5033                        &spr->rx_jmb_buffers[si],
5034                        cpycnt * sizeof(struct ring_info));
5035
5036                 for (i = 0; i < cpycnt; i++, di++, si++) {
5037                         struct tg3_rx_buffer_desc *sbd, *dbd;
5038                         sbd = &spr->rx_jmb[si].std;
5039                         dbd = &dpr->rx_jmb[di].std;
5040                         dbd->addr_hi = sbd->addr_hi;
5041                         dbd->addr_lo = sbd->addr_lo;
5042                 }
5043
5044                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5045                                        tp->rx_jmb_ring_mask;
5046                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5047                                        tp->rx_jmb_ring_mask;
5048         }
5049
5050         return err;
5051 }
5052
5053 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5054 {
5055         struct tg3 *tp = tnapi->tp;
5056
5057         /* run TX completion thread */
5058         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5059                 tg3_tx(tnapi);
5060                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5061                         return work_done;
5062         }
5063
5064         /* run RX thread, within the bounds set by NAPI.
5065          * All RX "locking" is done by ensuring outside
5066          * code synchronizes with tg3->napi.poll()
5067          */
5068         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5069                 work_done += tg3_rx(tnapi, budget - work_done);
5070
5071         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5072                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5073                 int i, err = 0;
5074                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5075                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5076
5077                 for (i = 1; i < tp->irq_cnt; i++)
5078                         err |= tg3_rx_prodring_xfer(tp, dpr,
5079                                                     &tp->napi[i].prodring);
5080
5081                 wmb();
5082
5083                 if (std_prod_idx != dpr->rx_std_prod_idx)
5084                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5085                                      dpr->rx_std_prod_idx);
5086
5087                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5088                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5089                                      dpr->rx_jmb_prod_idx);
5090
5091                 mmiowb();
5092
5093                 if (err)
5094                         tw32_f(HOSTCC_MODE, tp->coal_now);
5095         }
5096
5097         return work_done;
5098 }
5099
5100 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5101 {
5102         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5103         struct tg3 *tp = tnapi->tp;
5104         int work_done = 0;
5105         struct tg3_hw_status *sblk = tnapi->hw_status;
5106
5107         while (1) {
5108                 work_done = tg3_poll_work(tnapi, work_done, budget);
5109
5110                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5111                         goto tx_recovery;
5112
5113                 if (unlikely(work_done >= budget))
5114                         break;
5115
5116                 /* tp->last_tag is used in tg3_int_reenable() below
5117                  * to tell the hw how much work has been processed,
5118                  * so we must read it before checking for more work.
5119                  */
5120                 tnapi->last_tag = sblk->status_tag;
5121                 tnapi->last_irq_tag = tnapi->last_tag;
5122                 rmb();
5123
5124                 /* check for RX/TX work to do */
5125                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5126                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5127                         napi_complete(napi);
5128                         /* Reenable interrupts. */
5129                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5130                         mmiowb();
5131                         break;
5132                 }
5133         }
5134
5135         return work_done;
5136
5137 tx_recovery:
5138         /* work_done is guaranteed to be less than budget. */
5139         napi_complete(napi);
5140         schedule_work(&tp->reset_task);
5141         return work_done;
5142 }
5143
5144 static int tg3_poll(struct napi_struct *napi, int budget)
5145 {
5146         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5147         struct tg3 *tp = tnapi->tp;
5148         int work_done = 0;
5149         struct tg3_hw_status *sblk = tnapi->hw_status;
5150
5151         while (1) {
5152                 tg3_poll_link(tp);
5153
5154                 work_done = tg3_poll_work(tnapi, work_done, budget);
5155
5156                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5157                         goto tx_recovery;
5158
5159                 if (unlikely(work_done >= budget))
5160                         break;
5161
5162                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5163                         /* tp->last_tag is used in tg3_int_reenable() below
5164                          * to tell the hw how much work has been processed,
5165                          * so we must read it before checking for more work.
5166                          */
5167                         tnapi->last_tag = sblk->status_tag;
5168                         tnapi->last_irq_tag = tnapi->last_tag;
5169                         rmb();
5170                 } else
5171                         sblk->status &= ~SD_STATUS_UPDATED;
5172
5173                 if (likely(!tg3_has_work(tnapi))) {
5174                         napi_complete(napi);
5175                         tg3_int_reenable(tnapi);
5176                         break;
5177                 }
5178         }
5179
5180         return work_done;
5181
5182 tx_recovery:
5183         /* work_done is guaranteed to be less than budget. */
5184         napi_complete(napi);
5185         schedule_work(&tp->reset_task);
5186         return work_done;
5187 }
5188
5189 static void tg3_napi_disable(struct tg3 *tp)
5190 {
5191         int i;
5192
5193         for (i = tp->irq_cnt - 1; i >= 0; i--)
5194                 napi_disable(&tp->napi[i].napi);
5195 }
5196
5197 static void tg3_napi_enable(struct tg3 *tp)
5198 {
5199         int i;
5200
5201         for (i = 0; i < tp->irq_cnt; i++)
5202                 napi_enable(&tp->napi[i].napi);
5203 }
5204
5205 static void tg3_napi_init(struct tg3 *tp)
5206 {
5207         int i;
5208
5209         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5210         for (i = 1; i < tp->irq_cnt; i++)
5211                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5212 }
5213
5214 static void tg3_napi_fini(struct tg3 *tp)
5215 {
5216         int i;
5217
5218         for (i = 0; i < tp->irq_cnt; i++)
5219                 netif_napi_del(&tp->napi[i].napi);
5220 }
5221
5222 static inline void tg3_netif_stop(struct tg3 *tp)
5223 {
5224         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5225         tg3_napi_disable(tp);
5226         netif_tx_disable(tp->dev);
5227 }
5228
5229 static inline void tg3_netif_start(struct tg3 *tp)
5230 {
5231         /* NOTE: unconditional netif_tx_wake_all_queues is only
5232          * appropriate so long as all callers are assured to
5233          * have free tx slots (such as after tg3_init_hw)
5234          */
5235         netif_tx_wake_all_queues(tp->dev);
5236
5237         tg3_napi_enable(tp);
5238         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5239         tg3_enable_ints(tp);
5240 }
5241
5242 static void tg3_irq_quiesce(struct tg3 *tp)
5243 {
5244         int i;
5245
5246         BUG_ON(tp->irq_sync);
5247
5248         tp->irq_sync = 1;
5249         smp_mb();
5250
5251         for (i = 0; i < tp->irq_cnt; i++)
5252                 synchronize_irq(tp->napi[i].irq_vec);
5253 }
5254
5255 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5256  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5257  * with as well.  Most of the time, this is not necessary except when
5258  * shutting down the device.
5259  */
5260 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5261 {
5262         spin_lock_bh(&tp->lock);
5263         if (irq_sync)
5264                 tg3_irq_quiesce(tp);
5265 }
5266
5267 static inline void tg3_full_unlock(struct tg3 *tp)
5268 {
5269         spin_unlock_bh(&tp->lock);
5270 }
5271
5272 /* One-shot MSI handler - Chip automatically disables interrupt
5273  * after sending MSI so driver doesn't have to do it.
5274  */
5275 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5276 {
5277         struct tg3_napi *tnapi = dev_id;
5278         struct tg3 *tp = tnapi->tp;
5279
5280         prefetch(tnapi->hw_status);
5281         if (tnapi->rx_rcb)
5282                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5283
5284         if (likely(!tg3_irq_sync(tp)))
5285                 napi_schedule(&tnapi->napi);
5286
5287         return IRQ_HANDLED;
5288 }
5289
5290 /* MSI ISR - No need to check for interrupt sharing and no need to
5291  * flush status block and interrupt mailbox. PCI ordering rules
5292  * guarantee that MSI will arrive after the status block.
5293  */
5294 static irqreturn_t tg3_msi(int irq, void *dev_id)
5295 {
5296         struct tg3_napi *tnapi = dev_id;
5297         struct tg3 *tp = tnapi->tp;
5298
5299         prefetch(tnapi->hw_status);
5300         if (tnapi->rx_rcb)
5301                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5302         /*
5303          * Writing any value to intr-mbox-0 clears PCI INTA# and
5304          * chip-internal interrupt pending events.
5305          * Writing non-zero to intr-mbox-0 additional tells the
5306          * NIC to stop sending us irqs, engaging "in-intr-handler"
5307          * event coalescing.
5308          */
5309         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5310         if (likely(!tg3_irq_sync(tp)))
5311                 napi_schedule(&tnapi->napi);
5312
5313         return IRQ_RETVAL(1);
5314 }
5315
5316 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5317 {
5318         struct tg3_napi *tnapi = dev_id;
5319         struct tg3 *tp = tnapi->tp;
5320         struct tg3_hw_status *sblk = tnapi->hw_status;
5321         unsigned int handled = 1;
5322
5323         /* In INTx mode, it is possible for the interrupt to arrive at
5324          * the CPU before the status block posted prior to the interrupt.
5325          * Reading the PCI State register will confirm whether the
5326          * interrupt is ours and will flush the status block.
5327          */
5328         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5329                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5330                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5331                         handled = 0;
5332                         goto out;
5333                 }
5334         }
5335
5336         /*
5337          * Writing any value to intr-mbox-0 clears PCI INTA# and
5338          * chip-internal interrupt pending events.
5339          * Writing non-zero to intr-mbox-0 additional tells the
5340          * NIC to stop sending us irqs, engaging "in-intr-handler"
5341          * event coalescing.
5342          *
5343          * Flush the mailbox to de-assert the IRQ immediately to prevent
5344          * spurious interrupts.  The flush impacts performance but
5345          * excessive spurious interrupts can be worse in some cases.
5346          */
5347         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5348         if (tg3_irq_sync(tp))
5349                 goto out;
5350         sblk->status &= ~SD_STATUS_UPDATED;
5351         if (likely(tg3_has_work(tnapi))) {
5352                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5353                 napi_schedule(&tnapi->napi);
5354         } else {
5355                 /* No work, shared interrupt perhaps?  re-enable
5356                  * interrupts, and flush that PCI write
5357                  */
5358                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5359                                0x00000000);
5360         }
5361 out:
5362         return IRQ_RETVAL(handled);
5363 }
5364
5365 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5366 {
5367         struct tg3_napi *tnapi = dev_id;
5368         struct tg3 *tp = tnapi->tp;
5369         struct tg3_hw_status *sblk = tnapi->hw_status;
5370         unsigned int handled = 1;
5371
5372         /* In INTx mode, it is possible for the interrupt to arrive at
5373          * the CPU before the status block posted prior to the interrupt.
5374          * Reading the PCI State register will confirm whether the
5375          * interrupt is ours and will flush the status block.
5376          */
5377         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5378                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5379                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5380                         handled = 0;
5381                         goto out;
5382                 }
5383         }
5384
5385         /*
5386          * writing any value to intr-mbox-0 clears PCI INTA# and
5387          * chip-internal interrupt pending events.
5388          * writing non-zero to intr-mbox-0 additional tells the
5389          * NIC to stop sending us irqs, engaging "in-intr-handler"
5390          * event coalescing.
5391          *
5392          * Flush the mailbox to de-assert the IRQ immediately to prevent
5393          * spurious interrupts.  The flush impacts performance but
5394          * excessive spurious interrupts can be worse in some cases.
5395          */
5396         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5397
5398         /*
5399          * In a shared interrupt configuration, sometimes other devices'
5400          * interrupts will scream.  We record the current status tag here
5401          * so that the above check can report that the screaming interrupts
5402          * are unhandled.  Eventually they will be silenced.
5403          */
5404         tnapi->last_irq_tag = sblk->status_tag;
5405
5406         if (tg3_irq_sync(tp))
5407                 goto out;
5408
5409         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5410
5411         napi_schedule(&tnapi->napi);
5412
5413 out:
5414         return IRQ_RETVAL(handled);
5415 }
5416
5417 /* ISR for interrupt test */
5418 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5419 {
5420         struct tg3_napi *tnapi = dev_id;
5421         struct tg3 *tp = tnapi->tp;
5422         struct tg3_hw_status *sblk = tnapi->hw_status;
5423
5424         if ((sblk->status & SD_STATUS_UPDATED) ||
5425             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5426                 tg3_disable_ints(tp);
5427                 return IRQ_RETVAL(1);
5428         }
5429         return IRQ_RETVAL(0);
5430 }
5431
5432 static int tg3_init_hw(struct tg3 *, int);
5433 static int tg3_halt(struct tg3 *, int, int);
5434
5435 /* Restart hardware after configuration changes, self-test, etc.
5436  * Invoked with tp->lock held.
5437  */
5438 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5439         __releases(tp->lock)
5440         __acquires(tp->lock)
5441 {
5442         int err;
5443
5444         err = tg3_init_hw(tp, reset_phy);
5445         if (err) {
5446                 netdev_err(tp->dev,
5447                            "Failed to re-initialize device, aborting\n");
5448                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5449                 tg3_full_unlock(tp);
5450                 del_timer_sync(&tp->timer);
5451                 tp->irq_sync = 0;
5452                 tg3_napi_enable(tp);
5453                 dev_close(tp->dev);
5454                 tg3_full_lock(tp, 0);
5455         }
5456         return err;
5457 }
5458
5459 #ifdef CONFIG_NET_POLL_CONTROLLER
5460 static void tg3_poll_controller(struct net_device *dev)
5461 {
5462         int i;
5463         struct tg3 *tp = netdev_priv(dev);
5464
5465         for (i = 0; i < tp->irq_cnt; i++)
5466                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5467 }
5468 #endif
5469
5470 static void tg3_reset_task(struct work_struct *work)
5471 {
5472         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5473         int err;
5474         unsigned int restart_timer;
5475
5476         tg3_full_lock(tp, 0);
5477
5478         if (!netif_running(tp->dev)) {
5479                 tg3_full_unlock(tp);
5480                 return;
5481         }
5482
5483         tg3_full_unlock(tp);
5484
5485         tg3_phy_stop(tp);
5486
5487         tg3_netif_stop(tp);
5488
5489         tg3_full_lock(tp, 1);
5490
5491         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5492         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5493
5494         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5495                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5496                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5497                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5498                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5499         }
5500
5501         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5502         err = tg3_init_hw(tp, 1);
5503         if (err)
5504                 goto out;
5505
5506         tg3_netif_start(tp);
5507
5508         if (restart_timer)
5509                 mod_timer(&tp->timer, jiffies + 1);
5510
5511 out:
5512         tg3_full_unlock(tp);
5513
5514         if (!err)
5515                 tg3_phy_start(tp);
5516 }
5517
5518 static void tg3_dump_short_state(struct tg3 *tp)
5519 {
5520         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5521                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5522         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5523                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5524 }
5525
5526 static void tg3_tx_timeout(struct net_device *dev)
5527 {
5528         struct tg3 *tp = netdev_priv(dev);
5529
5530         if (netif_msg_tx_err(tp)) {
5531                 netdev_err(dev, "transmit timed out, resetting\n");
5532                 tg3_dump_short_state(tp);
5533         }
5534
5535         schedule_work(&tp->reset_task);
5536 }
5537
5538 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5539 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5540 {
5541         u32 base = (u32) mapping & 0xffffffff;
5542
5543         return (base > 0xffffdcc0) && (base + len + 8 < base);
5544 }
5545
5546 /* Test for DMA addresses > 40-bit */
5547 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5548                                           int len)
5549 {
5550 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5551         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5552                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5553         return 0;
5554 #else
5555         return 0;
5556 #endif
5557 }
5558
5559 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5560
5561 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5562 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5563                                        struct sk_buff *skb, u32 last_plus_one,
5564                                        u32 *start, u32 base_flags, u32 mss)
5565 {
5566         struct tg3 *tp = tnapi->tp;
5567         struct sk_buff *new_skb;
5568         dma_addr_t new_addr = 0;
5569         u32 entry = *start;
5570         int i, ret = 0;
5571
5572         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5573                 new_skb = skb_copy(skb, GFP_ATOMIC);
5574         else {
5575                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5576
5577                 new_skb = skb_copy_expand(skb,
5578                                           skb_headroom(skb) + more_headroom,
5579                                           skb_tailroom(skb), GFP_ATOMIC);
5580         }
5581
5582         if (!new_skb) {
5583                 ret = -1;
5584         } else {
5585                 /* New SKB is guaranteed to be linear. */
5586                 entry = *start;
5587                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5588                                           PCI_DMA_TODEVICE);
5589                 /* Make sure the mapping succeeded */
5590                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5591                         ret = -1;
5592                         dev_kfree_skb(new_skb);
5593                         new_skb = NULL;
5594
5595                 /* Make sure new skb does not cross any 4G boundaries.
5596                  * Drop the packet if it does.
5597                  */
5598                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5599                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5600                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5601                                          PCI_DMA_TODEVICE);
5602                         ret = -1;
5603                         dev_kfree_skb(new_skb);
5604                         new_skb = NULL;
5605                 } else {
5606                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5607                                     base_flags, 1 | (mss << 1));
5608                         *start = NEXT_TX(entry);
5609                 }
5610         }
5611
5612         /* Now clean up the sw ring entries. */
5613         i = 0;
5614         while (entry != last_plus_one) {
5615                 int len;
5616
5617                 if (i == 0)
5618                         len = skb_headlen(skb);
5619                 else
5620                         len = skb_shinfo(skb)->frags[i-1].size;
5621
5622                 pci_unmap_single(tp->pdev,
5623                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5624                                                 mapping),
5625                                  len, PCI_DMA_TODEVICE);
5626                 if (i == 0) {
5627                         tnapi->tx_buffers[entry].skb = new_skb;
5628                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5629                                            new_addr);
5630                 } else {
5631                         tnapi->tx_buffers[entry].skb = NULL;
5632                 }
5633                 entry = NEXT_TX(entry);
5634                 i++;
5635         }
5636
5637         dev_kfree_skb(skb);
5638
5639         return ret;
5640 }
5641
5642 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5643                         dma_addr_t mapping, int len, u32 flags,
5644                         u32 mss_and_is_end)
5645 {
5646         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5647         int is_end = (mss_and_is_end & 0x1);
5648         u32 mss = (mss_and_is_end >> 1);
5649         u32 vlan_tag = 0;
5650
5651         if (is_end)
5652                 flags |= TXD_FLAG_END;
5653         if (flags & TXD_FLAG_VLAN) {
5654                 vlan_tag = flags >> 16;
5655                 flags &= 0xffff;
5656         }
5657         vlan_tag |= (mss << TXD_MSS_SHIFT);
5658
5659         txd->addr_hi = ((u64) mapping >> 32);
5660         txd->addr_lo = ((u64) mapping & 0xffffffff);
5661         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5662         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5663 }
5664
5665 /* hard_start_xmit for devices that don't have any bugs and
5666  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5667  */
5668 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5669                                   struct net_device *dev)
5670 {
5671         struct tg3 *tp = netdev_priv(dev);
5672         u32 len, entry, base_flags, mss;
5673         dma_addr_t mapping;
5674         struct tg3_napi *tnapi;
5675         struct netdev_queue *txq;
5676         unsigned int i, last;
5677
5678         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5679         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5680         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5681                 tnapi++;
5682
5683         /* We are running in BH disabled context with netif_tx_lock
5684          * and TX reclaim runs via tp->napi.poll inside of a software
5685          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5686          * no IRQ context deadlocks to worry about either.  Rejoice!
5687          */
5688         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5689                 if (!netif_tx_queue_stopped(txq)) {
5690                         netif_tx_stop_queue(txq);
5691
5692                         /* This is a hard error, log it. */
5693                         netdev_err(dev,
5694                                    "BUG! Tx Ring full when queue awake!\n");
5695                 }
5696                 return NETDEV_TX_BUSY;
5697         }
5698
5699         entry = tnapi->tx_prod;
5700         base_flags = 0;
5701         mss = skb_shinfo(skb)->gso_size;
5702         if (mss) {
5703                 int tcp_opt_len, ip_tcp_len;
5704                 u32 hdrlen;
5705
5706                 if (skb_header_cloned(skb) &&
5707                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5708                         dev_kfree_skb(skb);
5709                         goto out_unlock;
5710                 }
5711
5712                 if (skb_is_gso_v6(skb)) {
5713                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5714                 } else {
5715                         struct iphdr *iph = ip_hdr(skb);
5716
5717                         tcp_opt_len = tcp_optlen(skb);
5718                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5719
5720                         iph->check = 0;
5721                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5722                         hdrlen = ip_tcp_len + tcp_opt_len;
5723                 }
5724
5725                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5726                         mss |= (hdrlen & 0xc) << 12;
5727                         if (hdrlen & 0x10)
5728                                 base_flags |= 0x00000010;
5729                         base_flags |= (hdrlen & 0x3e0) << 5;
5730                 } else
5731                         mss |= hdrlen << 9;
5732
5733                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5734                                TXD_FLAG_CPU_POST_DMA);
5735
5736                 tcp_hdr(skb)->check = 0;
5737
5738         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5739                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5740         }
5741
5742         if (vlan_tx_tag_present(skb))
5743                 base_flags |= (TXD_FLAG_VLAN |
5744                                (vlan_tx_tag_get(skb) << 16));
5745
5746         len = skb_headlen(skb);
5747
5748         /* Queue skb data, a.k.a. the main skb fragment. */
5749         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5750         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5751                 dev_kfree_skb(skb);
5752                 goto out_unlock;
5753         }
5754
5755         tnapi->tx_buffers[entry].skb = skb;
5756         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5757
5758         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5759             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5760                 base_flags |= TXD_FLAG_JMB_PKT;
5761
5762         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5763                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5764
5765         entry = NEXT_TX(entry);
5766
5767         /* Now loop through additional data fragments, and queue them. */
5768         if (skb_shinfo(skb)->nr_frags > 0) {
5769                 last = skb_shinfo(skb)->nr_frags - 1;
5770                 for (i = 0; i <= last; i++) {
5771                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5772
5773                         len = frag->size;
5774                         mapping = pci_map_page(tp->pdev,
5775                                                frag->page,
5776                                                frag->page_offset,
5777                                                len, PCI_DMA_TODEVICE);
5778                         if (pci_dma_mapping_error(tp->pdev, mapping))
5779                                 goto dma_error;
5780
5781                         tnapi->tx_buffers[entry].skb = NULL;
5782                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5783                                            mapping);
5784
5785                         tg3_set_txd(tnapi, entry, mapping, len,
5786                                     base_flags, (i == last) | (mss << 1));
5787
5788                         entry = NEXT_TX(entry);
5789                 }
5790         }
5791
5792         /* Packets are ready, update Tx producer idx local and on card. */
5793         tw32_tx_mbox(tnapi->prodmbox, entry);
5794
5795         tnapi->tx_prod = entry;
5796         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5797                 netif_tx_stop_queue(txq);
5798
5799                 /* netif_tx_stop_queue() must be done before checking
5800                  * checking tx index in tg3_tx_avail() below, because in
5801                  * tg3_tx(), we update tx index before checking for
5802                  * netif_tx_queue_stopped().
5803                  */
5804                 smp_mb();
5805                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5806                         netif_tx_wake_queue(txq);
5807         }
5808
5809 out_unlock:
5810         mmiowb();
5811
5812         return NETDEV_TX_OK;
5813
5814 dma_error:
5815         last = i;
5816         entry = tnapi->tx_prod;
5817         tnapi->tx_buffers[entry].skb = NULL;
5818         pci_unmap_single(tp->pdev,
5819                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5820                          skb_headlen(skb),
5821                          PCI_DMA_TODEVICE);
5822         for (i = 0; i <= last; i++) {
5823                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5824                 entry = NEXT_TX(entry);
5825
5826                 pci_unmap_page(tp->pdev,
5827                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5828                                               mapping),
5829                                frag->size, PCI_DMA_TODEVICE);
5830         }
5831
5832         dev_kfree_skb(skb);
5833         return NETDEV_TX_OK;
5834 }
5835
5836 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5837                                           struct net_device *);
5838
5839 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5840  * TSO header is greater than 80 bytes.
5841  */
5842 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5843 {
5844         struct sk_buff *segs, *nskb;
5845         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5846
5847         /* Estimate the number of fragments in the worst case */
5848         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5849                 netif_stop_queue(tp->dev);
5850
5851                 /* netif_tx_stop_queue() must be done before checking
5852                  * checking tx index in tg3_tx_avail() below, because in
5853                  * tg3_tx(), we update tx index before checking for
5854                  * netif_tx_queue_stopped().
5855                  */
5856                 smp_mb();
5857                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5858                         return NETDEV_TX_BUSY;
5859
5860                 netif_wake_queue(tp->dev);
5861         }
5862
5863         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5864         if (IS_ERR(segs))
5865                 goto tg3_tso_bug_end;
5866
5867         do {
5868                 nskb = segs;
5869                 segs = segs->next;
5870                 nskb->next = NULL;
5871                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5872         } while (segs);
5873
5874 tg3_tso_bug_end:
5875         dev_kfree_skb(skb);
5876
5877         return NETDEV_TX_OK;
5878 }
5879
5880 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5881  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5882  */
5883 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5884                                           struct net_device *dev)
5885 {
5886         struct tg3 *tp = netdev_priv(dev);
5887         u32 len, entry, base_flags, mss;
5888         int would_hit_hwbug;
5889         dma_addr_t mapping;
5890         struct tg3_napi *tnapi;
5891         struct netdev_queue *txq;
5892         unsigned int i, last;
5893
5894         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5895         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5896         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5897                 tnapi++;
5898
5899         /* We are running in BH disabled context with netif_tx_lock
5900          * and TX reclaim runs via tp->napi.poll inside of a software
5901          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5902          * no IRQ context deadlocks to worry about either.  Rejoice!
5903          */
5904         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5905                 if (!netif_tx_queue_stopped(txq)) {
5906                         netif_tx_stop_queue(txq);
5907
5908                         /* This is a hard error, log it. */
5909                         netdev_err(dev,
5910                                    "BUG! Tx Ring full when queue awake!\n");
5911                 }
5912                 return NETDEV_TX_BUSY;
5913         }
5914
5915         entry = tnapi->tx_prod;
5916         base_flags = 0;
5917         if (skb->ip_summed == CHECKSUM_PARTIAL)
5918                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5919
5920         mss = skb_shinfo(skb)->gso_size;
5921         if (mss) {
5922                 struct iphdr *iph;
5923                 u32 tcp_opt_len, hdr_len;
5924
5925                 if (skb_header_cloned(skb) &&
5926                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5927                         dev_kfree_skb(skb);
5928                         goto out_unlock;
5929                 }
5930
5931                 iph = ip_hdr(skb);
5932                 tcp_opt_len = tcp_optlen(skb);
5933
5934                 if (skb_is_gso_v6(skb)) {
5935                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5936                 } else {
5937                         u32 ip_tcp_len;
5938
5939                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5940                         hdr_len = ip_tcp_len + tcp_opt_len;
5941
5942                         iph->check = 0;
5943                         iph->tot_len = htons(mss + hdr_len);
5944                 }
5945
5946                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5947                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5948                         return tg3_tso_bug(tp, skb);
5949
5950                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5951                                TXD_FLAG_CPU_POST_DMA);
5952
5953                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5954                         tcp_hdr(skb)->check = 0;
5955                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5956                 } else
5957                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5958                                                                  iph->daddr, 0,
5959                                                                  IPPROTO_TCP,
5960                                                                  0);
5961
5962                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5963                         mss |= (hdr_len & 0xc) << 12;
5964                         if (hdr_len & 0x10)
5965                                 base_flags |= 0x00000010;
5966                         base_flags |= (hdr_len & 0x3e0) << 5;
5967                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5968                         mss |= hdr_len << 9;
5969                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5970                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5971                         if (tcp_opt_len || iph->ihl > 5) {
5972                                 int tsflags;
5973
5974                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5975                                 mss |= (tsflags << 11);
5976                         }
5977                 } else {
5978                         if (tcp_opt_len || iph->ihl > 5) {
5979                                 int tsflags;
5980
5981                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5982                                 base_flags |= tsflags << 12;
5983                         }
5984                 }
5985         }
5986
5987         if (vlan_tx_tag_present(skb))
5988                 base_flags |= (TXD_FLAG_VLAN |
5989                                (vlan_tx_tag_get(skb) << 16));
5990
5991         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5992             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5993                 base_flags |= TXD_FLAG_JMB_PKT;
5994
5995         len = skb_headlen(skb);
5996
5997         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5998         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5999                 dev_kfree_skb(skb);
6000                 goto out_unlock;
6001         }
6002
6003         tnapi->tx_buffers[entry].skb = skb;
6004         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6005
6006         would_hit_hwbug = 0;
6007
6008         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6009                 would_hit_hwbug = 1;
6010
6011         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6012             tg3_4g_overflow_test(mapping, len))
6013                 would_hit_hwbug = 1;
6014
6015         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6016             tg3_40bit_overflow_test(tp, mapping, len))
6017                 would_hit_hwbug = 1;
6018
6019         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6020                 would_hit_hwbug = 1;
6021
6022         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6023                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6024
6025         entry = NEXT_TX(entry);
6026
6027         /* Now loop through additional data fragments, and queue them. */
6028         if (skb_shinfo(skb)->nr_frags > 0) {
6029                 last = skb_shinfo(skb)->nr_frags - 1;
6030                 for (i = 0; i <= last; i++) {
6031                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6032
6033                         len = frag->size;
6034                         mapping = pci_map_page(tp->pdev,
6035                                                frag->page,
6036                                                frag->page_offset,
6037                                                len, PCI_DMA_TODEVICE);
6038
6039                         tnapi->tx_buffers[entry].skb = NULL;
6040                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6041                                            mapping);
6042                         if (pci_dma_mapping_error(tp->pdev, mapping))
6043                                 goto dma_error;
6044
6045                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6046                             len <= 8)
6047                                 would_hit_hwbug = 1;
6048
6049                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6050                             tg3_4g_overflow_test(mapping, len))
6051                                 would_hit_hwbug = 1;
6052
6053                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6054                             tg3_40bit_overflow_test(tp, mapping, len))
6055                                 would_hit_hwbug = 1;
6056
6057                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6058                                 tg3_set_txd(tnapi, entry, mapping, len,
6059                                             base_flags, (i == last)|(mss << 1));
6060                         else
6061                                 tg3_set_txd(tnapi, entry, mapping, len,
6062                                             base_flags, (i == last));
6063
6064                         entry = NEXT_TX(entry);
6065                 }
6066         }
6067
6068         if (would_hit_hwbug) {
6069                 u32 last_plus_one = entry;
6070                 u32 start;
6071
6072                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6073                 start &= (TG3_TX_RING_SIZE - 1);
6074
6075                 /* If the workaround fails due to memory/mapping
6076                  * failure, silently drop this packet.
6077                  */
6078                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6079                                                 &start, base_flags, mss))
6080                         goto out_unlock;
6081
6082                 entry = start;
6083         }
6084
6085         /* Packets are ready, update Tx producer idx local and on card. */
6086         tw32_tx_mbox(tnapi->prodmbox, entry);
6087
6088         tnapi->tx_prod = entry;
6089         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6090                 netif_tx_stop_queue(txq);
6091
6092                 /* netif_tx_stop_queue() must be done before checking
6093                  * checking tx index in tg3_tx_avail() below, because in
6094                  * tg3_tx(), we update tx index before checking for
6095                  * netif_tx_queue_stopped().
6096                  */
6097                 smp_mb();
6098                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6099                         netif_tx_wake_queue(txq);
6100         }
6101
6102 out_unlock:
6103         mmiowb();
6104
6105         return NETDEV_TX_OK;
6106
6107 dma_error:
6108         last = i;
6109         entry = tnapi->tx_prod;
6110         tnapi->tx_buffers[entry].skb = NULL;
6111         pci_unmap_single(tp->pdev,
6112                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6113                          skb_headlen(skb),
6114                          PCI_DMA_TODEVICE);
6115         for (i = 0; i <= last; i++) {
6116                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6117                 entry = NEXT_TX(entry);
6118
6119                 pci_unmap_page(tp->pdev,
6120                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6121                                               mapping),
6122                                frag->size, PCI_DMA_TODEVICE);
6123         }
6124
6125         dev_kfree_skb(skb);
6126         return NETDEV_TX_OK;
6127 }
6128
6129 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6130                                int new_mtu)
6131 {
6132         dev->mtu = new_mtu;
6133
6134         if (new_mtu > ETH_DATA_LEN) {
6135                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6136                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6137                         ethtool_op_set_tso(dev, 0);
6138                 } else {
6139                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6140                 }
6141         } else {
6142                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6143                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6144                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6145         }
6146 }
6147
6148 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6149 {
6150         struct tg3 *tp = netdev_priv(dev);
6151         int err;
6152
6153         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6154                 return -EINVAL;
6155
6156         if (!netif_running(dev)) {
6157                 /* We'll just catch it later when the
6158                  * device is up'd.
6159                  */
6160                 tg3_set_mtu(dev, tp, new_mtu);
6161                 return 0;
6162         }
6163
6164         tg3_phy_stop(tp);
6165
6166         tg3_netif_stop(tp);
6167
6168         tg3_full_lock(tp, 1);
6169
6170         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6171
6172         tg3_set_mtu(dev, tp, new_mtu);
6173
6174         err = tg3_restart_hw(tp, 0);
6175
6176         if (!err)
6177                 tg3_netif_start(tp);
6178
6179         tg3_full_unlock(tp);
6180
6181         if (!err)
6182                 tg3_phy_start(tp);
6183
6184         return err;
6185 }
6186
6187 static void tg3_rx_prodring_free(struct tg3 *tp,
6188                                  struct tg3_rx_prodring_set *tpr)
6189 {
6190         int i;
6191
6192         if (tpr != &tp->napi[0].prodring) {
6193                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6194                      i = (i + 1) & tp->rx_std_ring_mask)
6195                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6196                                         tp->rx_pkt_map_sz);
6197
6198                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6199                         for (i = tpr->rx_jmb_cons_idx;
6200                              i != tpr->rx_jmb_prod_idx;
6201                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6202                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6203                                                 TG3_RX_JMB_MAP_SZ);
6204                         }
6205                 }
6206
6207                 return;
6208         }
6209
6210         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6211                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6212                                 tp->rx_pkt_map_sz);
6213
6214         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6215             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6216                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6217                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6218                                         TG3_RX_JMB_MAP_SZ);
6219         }
6220 }
6221
6222 /* Initialize rx rings for packet processing.
6223  *
6224  * The chip has been shut down and the driver detached from
6225  * the networking, so no interrupts or new tx packets will
6226  * end up in the driver.  tp->{tx,}lock are held and thus
6227  * we may not sleep.
6228  */
6229 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6230                                  struct tg3_rx_prodring_set *tpr)
6231 {
6232         u32 i, rx_pkt_dma_sz;
6233
6234         tpr->rx_std_cons_idx = 0;
6235         tpr->rx_std_prod_idx = 0;
6236         tpr->rx_jmb_cons_idx = 0;
6237         tpr->rx_jmb_prod_idx = 0;
6238
6239         if (tpr != &tp->napi[0].prodring) {
6240                 memset(&tpr->rx_std_buffers[0], 0,
6241                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6242                 if (tpr->rx_jmb_buffers)
6243                         memset(&tpr->rx_jmb_buffers[0], 0,
6244                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6245                 goto done;
6246         }
6247
6248         /* Zero out all descriptors. */
6249         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6250
6251         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6252         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6253             tp->dev->mtu > ETH_DATA_LEN)
6254                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6255         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6256
6257         /* Initialize invariants of the rings, we only set this
6258          * stuff once.  This works because the card does not
6259          * write into the rx buffer posting rings.
6260          */
6261         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6262                 struct tg3_rx_buffer_desc *rxd;
6263
6264                 rxd = &tpr->rx_std[i];
6265                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6266                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6267                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6268                                (i << RXD_OPAQUE_INDEX_SHIFT));
6269         }
6270
6271         /* Now allocate fresh SKBs for each rx ring. */
6272         for (i = 0; i < tp->rx_pending; i++) {
6273                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6274                         netdev_warn(tp->dev,
6275                                     "Using a smaller RX standard ring. Only "
6276                                     "%d out of %d buffers were allocated "
6277                                     "successfully\n", i, tp->rx_pending);
6278                         if (i == 0)
6279                                 goto initfail;
6280                         tp->rx_pending = i;
6281                         break;
6282                 }
6283         }
6284
6285         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6286             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6287                 goto done;
6288
6289         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6290
6291         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6292                 goto done;
6293
6294         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6295                 struct tg3_rx_buffer_desc *rxd;
6296
6297                 rxd = &tpr->rx_jmb[i].std;
6298                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6299                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6300                                   RXD_FLAG_JUMBO;
6301                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6302                        (i << RXD_OPAQUE_INDEX_SHIFT));
6303         }
6304
6305         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6306                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6307                         netdev_warn(tp->dev,
6308                                     "Using a smaller RX jumbo ring. Only %d "
6309                                     "out of %d buffers were allocated "
6310                                     "successfully\n", i, tp->rx_jumbo_pending);
6311                         if (i == 0)
6312                                 goto initfail;
6313                         tp->rx_jumbo_pending = i;
6314                         break;
6315                 }
6316         }
6317
6318 done:
6319         return 0;
6320
6321 initfail:
6322         tg3_rx_prodring_free(tp, tpr);
6323         return -ENOMEM;
6324 }
6325
6326 static void tg3_rx_prodring_fini(struct tg3 *tp,
6327                                  struct tg3_rx_prodring_set *tpr)
6328 {
6329         kfree(tpr->rx_std_buffers);
6330         tpr->rx_std_buffers = NULL;
6331         kfree(tpr->rx_jmb_buffers);
6332         tpr->rx_jmb_buffers = NULL;
6333         if (tpr->rx_std) {
6334                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6335                                   tpr->rx_std, tpr->rx_std_mapping);
6336                 tpr->rx_std = NULL;
6337         }
6338         if (tpr->rx_jmb) {
6339                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6340                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6341                 tpr->rx_jmb = NULL;
6342         }
6343 }
6344
6345 static int tg3_rx_prodring_init(struct tg3 *tp,
6346                                 struct tg3_rx_prodring_set *tpr)
6347 {
6348         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6349                                       GFP_KERNEL);
6350         if (!tpr->rx_std_buffers)
6351                 return -ENOMEM;
6352
6353         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6354                                          TG3_RX_STD_RING_BYTES(tp),
6355                                          &tpr->rx_std_mapping,
6356                                          GFP_KERNEL);
6357         if (!tpr->rx_std)
6358                 goto err_out;
6359
6360         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6361             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6362                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6363                                               GFP_KERNEL);
6364                 if (!tpr->rx_jmb_buffers)
6365                         goto err_out;
6366
6367                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6368                                                  TG3_RX_JMB_RING_BYTES(tp),
6369                                                  &tpr->rx_jmb_mapping,
6370                                                  GFP_KERNEL);
6371                 if (!tpr->rx_jmb)
6372                         goto err_out;
6373         }
6374
6375         return 0;
6376
6377 err_out:
6378         tg3_rx_prodring_fini(tp, tpr);
6379         return -ENOMEM;
6380 }
6381
6382 /* Free up pending packets in all rx/tx rings.
6383  *
6384  * The chip has been shut down and the driver detached from
6385  * the networking, so no interrupts or new tx packets will
6386  * end up in the driver.  tp->{tx,}lock is not held and we are not
6387  * in an interrupt context and thus may sleep.
6388  */
6389 static void tg3_free_rings(struct tg3 *tp)
6390 {
6391         int i, j;
6392
6393         for (j = 0; j < tp->irq_cnt; j++) {
6394                 struct tg3_napi *tnapi = &tp->napi[j];
6395
6396                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6397
6398                 if (!tnapi->tx_buffers)
6399                         continue;
6400
6401                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6402                         struct ring_info *txp;
6403                         struct sk_buff *skb;
6404                         unsigned int k;
6405
6406                         txp = &tnapi->tx_buffers[i];
6407                         skb = txp->skb;
6408
6409                         if (skb == NULL) {
6410                                 i++;
6411                                 continue;
6412                         }
6413
6414                         pci_unmap_single(tp->pdev,
6415                                          dma_unmap_addr(txp, mapping),
6416                                          skb_headlen(skb),
6417                                          PCI_DMA_TODEVICE);
6418                         txp->skb = NULL;
6419
6420                         i++;
6421
6422                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6423                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6424                                 pci_unmap_page(tp->pdev,
6425                                                dma_unmap_addr(txp, mapping),
6426                                                skb_shinfo(skb)->frags[k].size,
6427                                                PCI_DMA_TODEVICE);
6428                                 i++;
6429                         }
6430
6431                         dev_kfree_skb_any(skb);
6432                 }
6433         }
6434 }
6435
6436 /* Initialize tx/rx rings for packet processing.
6437  *
6438  * The chip has been shut down and the driver detached from
6439  * the networking, so no interrupts or new tx packets will
6440  * end up in the driver.  tp->{tx,}lock are held and thus
6441  * we may not sleep.
6442  */
6443 static int tg3_init_rings(struct tg3 *tp)
6444 {
6445         int i;
6446
6447         /* Free up all the SKBs. */
6448         tg3_free_rings(tp);
6449
6450         for (i = 0; i < tp->irq_cnt; i++) {
6451                 struct tg3_napi *tnapi = &tp->napi[i];
6452
6453                 tnapi->last_tag = 0;
6454                 tnapi->last_irq_tag = 0;
6455                 tnapi->hw_status->status = 0;
6456                 tnapi->hw_status->status_tag = 0;
6457                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6458
6459                 tnapi->tx_prod = 0;
6460                 tnapi->tx_cons = 0;
6461                 if (tnapi->tx_ring)
6462                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6463
6464                 tnapi->rx_rcb_ptr = 0;
6465                 if (tnapi->rx_rcb)
6466                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6467
6468                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6469                         tg3_free_rings(tp);
6470                         return -ENOMEM;
6471                 }
6472         }
6473
6474         return 0;
6475 }
6476
6477 /*
6478  * Must not be invoked with interrupt sources disabled and
6479  * the hardware shutdown down.
6480  */
6481 static void tg3_free_consistent(struct tg3 *tp)
6482 {
6483         int i;
6484
6485         for (i = 0; i < tp->irq_cnt; i++) {
6486                 struct tg3_napi *tnapi = &tp->napi[i];
6487
6488                 if (tnapi->tx_ring) {
6489                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6490                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6491                         tnapi->tx_ring = NULL;
6492                 }
6493
6494                 kfree(tnapi->tx_buffers);
6495                 tnapi->tx_buffers = NULL;
6496
6497                 if (tnapi->rx_rcb) {
6498                         dma_free_coherent(&tp->pdev->dev,
6499                                           TG3_RX_RCB_RING_BYTES(tp),
6500                                           tnapi->rx_rcb,
6501                                           tnapi->rx_rcb_mapping);
6502                         tnapi->rx_rcb = NULL;
6503                 }
6504
6505                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6506
6507                 if (tnapi->hw_status) {
6508                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6509                                           tnapi->hw_status,
6510                                           tnapi->status_mapping);
6511                         tnapi->hw_status = NULL;
6512                 }
6513         }
6514
6515         if (tp->hw_stats) {
6516                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6517                                   tp->hw_stats, tp->stats_mapping);
6518                 tp->hw_stats = NULL;
6519         }
6520 }
6521
6522 /*
6523  * Must not be invoked with interrupt sources disabled and
6524  * the hardware shutdown down.  Can sleep.
6525  */
6526 static int tg3_alloc_consistent(struct tg3 *tp)
6527 {
6528         int i;
6529
6530         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6531                                           sizeof(struct tg3_hw_stats),
6532                                           &tp->stats_mapping,
6533                                           GFP_KERNEL);
6534         if (!tp->hw_stats)
6535                 goto err_out;
6536
6537         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6538
6539         for (i = 0; i < tp->irq_cnt; i++) {
6540                 struct tg3_napi *tnapi = &tp->napi[i];
6541                 struct tg3_hw_status *sblk;
6542
6543                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6544                                                       TG3_HW_STATUS_SIZE,
6545                                                       &tnapi->status_mapping,
6546                                                       GFP_KERNEL);
6547                 if (!tnapi->hw_status)
6548                         goto err_out;
6549
6550                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6551                 sblk = tnapi->hw_status;
6552
6553                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6554                         goto err_out;
6555
6556                 /* If multivector TSS is enabled, vector 0 does not handle
6557                  * tx interrupts.  Don't allocate any resources for it.
6558                  */
6559                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6560                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6561                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6562                                                     TG3_TX_RING_SIZE,
6563                                                     GFP_KERNEL);
6564                         if (!tnapi->tx_buffers)
6565                                 goto err_out;
6566
6567                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6568                                                             TG3_TX_RING_BYTES,
6569                                                         &tnapi->tx_desc_mapping,
6570                                                             GFP_KERNEL);
6571                         if (!tnapi->tx_ring)
6572                                 goto err_out;
6573                 }
6574
6575                 /*
6576                  * When RSS is enabled, the status block format changes
6577                  * slightly.  The "rx_jumbo_consumer", "reserved",
6578                  * and "rx_mini_consumer" members get mapped to the
6579                  * other three rx return ring producer indexes.
6580                  */
6581                 switch (i) {
6582                 default:
6583                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6584                         break;
6585                 case 2:
6586                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6587                         break;
6588                 case 3:
6589                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6590                         break;
6591                 case 4:
6592                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6593                         break;
6594                 }
6595
6596                 /*
6597                  * If multivector RSS is enabled, vector 0 does not handle
6598                  * rx or tx interrupts.  Don't allocate any resources for it.
6599                  */
6600                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6601                         continue;
6602
6603                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6604                                                    TG3_RX_RCB_RING_BYTES(tp),
6605                                                    &tnapi->rx_rcb_mapping,
6606                                                    GFP_KERNEL);
6607                 if (!tnapi->rx_rcb)
6608                         goto err_out;
6609
6610                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6611         }
6612
6613         return 0;
6614
6615 err_out:
6616         tg3_free_consistent(tp);
6617         return -ENOMEM;
6618 }
6619
6620 #define MAX_WAIT_CNT 1000
6621
6622 /* To stop a block, clear the enable bit and poll till it
6623  * clears.  tp->lock is held.
6624  */
6625 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6626 {
6627         unsigned int i;
6628         u32 val;
6629
6630         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6631                 switch (ofs) {
6632                 case RCVLSC_MODE:
6633                 case DMAC_MODE:
6634                 case MBFREE_MODE:
6635                 case BUFMGR_MODE:
6636                 case MEMARB_MODE:
6637                         /* We can't enable/disable these bits of the
6638                          * 5705/5750, just say success.
6639                          */
6640                         return 0;
6641
6642                 default:
6643                         break;
6644                 }
6645         }
6646
6647         val = tr32(ofs);
6648         val &= ~enable_bit;
6649         tw32_f(ofs, val);
6650
6651         for (i = 0; i < MAX_WAIT_CNT; i++) {
6652                 udelay(100);
6653                 val = tr32(ofs);
6654                 if ((val & enable_bit) == 0)
6655                         break;
6656         }
6657
6658         if (i == MAX_WAIT_CNT && !silent) {
6659                 dev_err(&tp->pdev->dev,
6660                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6661                         ofs, enable_bit);
6662                 return -ENODEV;
6663         }
6664
6665         return 0;
6666 }
6667
6668 /* tp->lock is held. */
6669 static int tg3_abort_hw(struct tg3 *tp, int silent)
6670 {
6671         int i, err;
6672
6673         tg3_disable_ints(tp);
6674
6675         tp->rx_mode &= ~RX_MODE_ENABLE;
6676         tw32_f(MAC_RX_MODE, tp->rx_mode);
6677         udelay(10);
6678
6679         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6680         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6681         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6682         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6683         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6684         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6685
6686         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6687         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6688         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6689         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6690         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6691         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6692         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6693
6694         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6695         tw32_f(MAC_MODE, tp->mac_mode);
6696         udelay(40);
6697
6698         tp->tx_mode &= ~TX_MODE_ENABLE;
6699         tw32_f(MAC_TX_MODE, tp->tx_mode);
6700
6701         for (i = 0; i < MAX_WAIT_CNT; i++) {
6702                 udelay(100);
6703                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6704                         break;
6705         }
6706         if (i >= MAX_WAIT_CNT) {
6707                 dev_err(&tp->pdev->dev,
6708                         "%s timed out, TX_MODE_ENABLE will not clear "
6709                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6710                 err |= -ENODEV;
6711         }
6712
6713         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6714         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6715         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6716
6717         tw32(FTQ_RESET, 0xffffffff);
6718         tw32(FTQ_RESET, 0x00000000);
6719
6720         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6721         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6722
6723         for (i = 0; i < tp->irq_cnt; i++) {
6724                 struct tg3_napi *tnapi = &tp->napi[i];
6725                 if (tnapi->hw_status)
6726                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6727         }
6728         if (tp->hw_stats)
6729                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6730
6731         return err;
6732 }
6733
6734 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6735 {
6736         int i;
6737         u32 apedata;
6738
6739         /* NCSI does not support APE events */
6740         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6741                 return;
6742
6743         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6744         if (apedata != APE_SEG_SIG_MAGIC)
6745                 return;
6746
6747         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6748         if (!(apedata & APE_FW_STATUS_READY))
6749                 return;
6750
6751         /* Wait for up to 1 millisecond for APE to service previous event. */
6752         for (i = 0; i < 10; i++) {
6753                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6754                         return;
6755
6756                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6757
6758                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6759                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6760                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6761
6762                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6763
6764                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6765                         break;
6766
6767                 udelay(100);
6768         }
6769
6770         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6771                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6772 }
6773
6774 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6775 {
6776         u32 event;
6777         u32 apedata;
6778
6779         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6780                 return;
6781
6782         switch (kind) {
6783         case RESET_KIND_INIT:
6784                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6785                                 APE_HOST_SEG_SIG_MAGIC);
6786                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6787                                 APE_HOST_SEG_LEN_MAGIC);
6788                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6789                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6790                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6791                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6792                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6793                                 APE_HOST_BEHAV_NO_PHYLOCK);
6794                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6795                                     TG3_APE_HOST_DRVR_STATE_START);
6796
6797                 event = APE_EVENT_STATUS_STATE_START;
6798                 break;
6799         case RESET_KIND_SHUTDOWN:
6800                 /* With the interface we are currently using,
6801                  * APE does not track driver state.  Wiping
6802                  * out the HOST SEGMENT SIGNATURE forces
6803                  * the APE to assume OS absent status.
6804                  */
6805                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6806
6807                 if (device_may_wakeup(&tp->pdev->dev) &&
6808                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6809                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6810                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6811                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6812                 } else
6813                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6814
6815                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6816
6817                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6818                 break;
6819         case RESET_KIND_SUSPEND:
6820                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6821                 break;
6822         default:
6823                 return;
6824         }
6825
6826         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6827
6828         tg3_ape_send_event(tp, event);
6829 }
6830
6831 /* tp->lock is held. */
6832 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6833 {
6834         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6835                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6836
6837         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6838                 switch (kind) {
6839                 case RESET_KIND_INIT:
6840                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6841                                       DRV_STATE_START);
6842                         break;
6843
6844                 case RESET_KIND_SHUTDOWN:
6845                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6846                                       DRV_STATE_UNLOAD);
6847                         break;
6848
6849                 case RESET_KIND_SUSPEND:
6850                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6851                                       DRV_STATE_SUSPEND);
6852                         break;
6853
6854                 default:
6855                         break;
6856                 }
6857         }
6858
6859         if (kind == RESET_KIND_INIT ||
6860             kind == RESET_KIND_SUSPEND)
6861                 tg3_ape_driver_state_change(tp, kind);
6862 }
6863
6864 /* tp->lock is held. */
6865 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6866 {
6867         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6868                 switch (kind) {
6869                 case RESET_KIND_INIT:
6870                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6871                                       DRV_STATE_START_DONE);
6872                         break;
6873
6874                 case RESET_KIND_SHUTDOWN:
6875                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6876                                       DRV_STATE_UNLOAD_DONE);
6877                         break;
6878
6879                 default:
6880                         break;
6881                 }
6882         }
6883
6884         if (kind == RESET_KIND_SHUTDOWN)
6885                 tg3_ape_driver_state_change(tp, kind);
6886 }
6887
6888 /* tp->lock is held. */
6889 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6890 {
6891         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6892                 switch (kind) {
6893                 case RESET_KIND_INIT:
6894                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6895                                       DRV_STATE_START);
6896                         break;
6897
6898                 case RESET_KIND_SHUTDOWN:
6899                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6900                                       DRV_STATE_UNLOAD);
6901                         break;
6902
6903                 case RESET_KIND_SUSPEND:
6904                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6905                                       DRV_STATE_SUSPEND);
6906                         break;
6907
6908                 default:
6909                         break;
6910                 }
6911         }
6912 }
6913
6914 static int tg3_poll_fw(struct tg3 *tp)
6915 {
6916         int i;
6917         u32 val;
6918
6919         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6920                 /* Wait up to 20ms for init done. */
6921                 for (i = 0; i < 200; i++) {
6922                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6923                                 return 0;
6924                         udelay(100);
6925                 }
6926                 return -ENODEV;
6927         }
6928
6929         /* Wait for firmware initialization to complete. */
6930         for (i = 0; i < 100000; i++) {
6931                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6932                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6933                         break;
6934                 udelay(10);
6935         }
6936
6937         /* Chip might not be fitted with firmware.  Some Sun onboard
6938          * parts are configured like that.  So don't signal the timeout
6939          * of the above loop as an error, but do report the lack of
6940          * running firmware once.
6941          */
6942         if (i >= 100000 &&
6943             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6944                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6945
6946                 netdev_info(tp->dev, "No firmware running\n");
6947         }
6948
6949         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6950                 /* The 57765 A0 needs a little more
6951                  * time to do some important work.
6952                  */
6953                 mdelay(10);
6954         }
6955
6956         return 0;
6957 }
6958
6959 /* Save PCI command register before chip reset */
6960 static void tg3_save_pci_state(struct tg3 *tp)
6961 {
6962         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6963 }
6964
6965 /* Restore PCI state after chip reset */
6966 static void tg3_restore_pci_state(struct tg3 *tp)
6967 {
6968         u32 val;
6969
6970         /* Re-enable indirect register accesses. */
6971         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6972                                tp->misc_host_ctrl);
6973
6974         /* Set MAX PCI retry to zero. */
6975         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6976         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6977             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6978                 val |= PCISTATE_RETRY_SAME_DMA;
6979         /* Allow reads and writes to the APE register and memory space. */
6980         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6981                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6982                        PCISTATE_ALLOW_APE_SHMEM_WR |
6983                        PCISTATE_ALLOW_APE_PSPACE_WR;
6984         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6985
6986         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6987
6988         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6989                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6990                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6991                 else {
6992                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6993                                               tp->pci_cacheline_sz);
6994                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6995                                               tp->pci_lat_timer);
6996                 }
6997         }
6998
6999         /* Make sure PCI-X relaxed ordering bit is clear. */
7000         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7001                 u16 pcix_cmd;
7002
7003                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7004                                      &pcix_cmd);
7005                 pcix_cmd &= ~PCI_X_CMD_ERO;
7006                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7007                                       pcix_cmd);
7008         }
7009
7010         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7011
7012                 /* Chip reset on 5780 will reset MSI enable bit,
7013                  * so need to restore it.
7014                  */
7015                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7016                         u16 ctrl;
7017
7018                         pci_read_config_word(tp->pdev,
7019                                              tp->msi_cap + PCI_MSI_FLAGS,
7020                                              &ctrl);
7021                         pci_write_config_word(tp->pdev,
7022                                               tp->msi_cap + PCI_MSI_FLAGS,
7023                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7024                         val = tr32(MSGINT_MODE);
7025                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7026                 }
7027         }
7028 }
7029
7030 static void tg3_stop_fw(struct tg3 *);
7031
7032 /* tp->lock is held. */
7033 static int tg3_chip_reset(struct tg3 *tp)
7034 {
7035         u32 val;
7036         void (*write_op)(struct tg3 *, u32, u32);
7037         int i, err;
7038
7039         tg3_nvram_lock(tp);
7040
7041         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7042
7043         /* No matching tg3_nvram_unlock() after this because
7044          * chip reset below will undo the nvram lock.
7045          */
7046         tp->nvram_lock_cnt = 0;
7047
7048         /* GRC_MISC_CFG core clock reset will clear the memory
7049          * enable bit in PCI register 4 and the MSI enable bit
7050          * on some chips, so we save relevant registers here.
7051          */
7052         tg3_save_pci_state(tp);
7053
7054         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7055             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7056                 tw32(GRC_FASTBOOT_PC, 0);
7057
7058         /*
7059          * We must avoid the readl() that normally takes place.
7060          * It locks machines, causes machine checks, and other
7061          * fun things.  So, temporarily disable the 5701
7062          * hardware workaround, while we do the reset.
7063          */
7064         write_op = tp->write32;
7065         if (write_op == tg3_write_flush_reg32)
7066                 tp->write32 = tg3_write32;
7067
7068         /* Prevent the irq handler from reading or writing PCI registers
7069          * during chip reset when the memory enable bit in the PCI command
7070          * register may be cleared.  The chip does not generate interrupt
7071          * at this time, but the irq handler may still be called due to irq
7072          * sharing or irqpoll.
7073          */
7074         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7075         for (i = 0; i < tp->irq_cnt; i++) {
7076                 struct tg3_napi *tnapi = &tp->napi[i];
7077                 if (tnapi->hw_status) {
7078                         tnapi->hw_status->status = 0;
7079                         tnapi->hw_status->status_tag = 0;
7080                 }
7081                 tnapi->last_tag = 0;
7082                 tnapi->last_irq_tag = 0;
7083         }
7084         smp_mb();
7085
7086         for (i = 0; i < tp->irq_cnt; i++)
7087                 synchronize_irq(tp->napi[i].irq_vec);
7088
7089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7090                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7091                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7092         }
7093
7094         /* do the reset */
7095         val = GRC_MISC_CFG_CORECLK_RESET;
7096
7097         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7098                 /* Force PCIe 1.0a mode */
7099                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7100                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
7101                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7102                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7103                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7104
7105                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7106                         tw32(GRC_MISC_CFG, (1 << 29));
7107                         val |= (1 << 29);
7108                 }
7109         }
7110
7111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7112                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7113                 tw32(GRC_VCPU_EXT_CTRL,
7114                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7115         }
7116
7117         /* Manage gphy power for all CPMU absent PCIe devices. */
7118         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7119             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7120                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7121
7122         tw32(GRC_MISC_CFG, val);
7123
7124         /* restore 5701 hardware bug workaround write method */
7125         tp->write32 = write_op;
7126
7127         /* Unfortunately, we have to delay before the PCI read back.
7128          * Some 575X chips even will not respond to a PCI cfg access
7129          * when the reset command is given to the chip.
7130          *
7131          * How do these hardware designers expect things to work
7132          * properly if the PCI write is posted for a long period
7133          * of time?  It is always necessary to have some method by
7134          * which a register read back can occur to push the write
7135          * out which does the reset.
7136          *
7137          * For most tg3 variants the trick below was working.
7138          * Ho hum...
7139          */
7140         udelay(120);
7141
7142         /* Flush PCI posted writes.  The normal MMIO registers
7143          * are inaccessible at this time so this is the only
7144          * way to make this reliably (actually, this is no longer
7145          * the case, see above).  I tried to use indirect
7146          * register read/write but this upset some 5701 variants.
7147          */
7148         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7149
7150         udelay(120);
7151
7152         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7153                 u16 val16;
7154
7155                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7156                         int i;
7157                         u32 cfg_val;
7158
7159                         /* Wait for link training to complete.  */
7160                         for (i = 0; i < 5000; i++)
7161                                 udelay(100);
7162
7163                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7164                         pci_write_config_dword(tp->pdev, 0xc4,
7165                                                cfg_val | (1 << 15));
7166                 }
7167
7168                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7169                 pci_read_config_word(tp->pdev,
7170                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7171                                      &val16);
7172                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7173                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7174                 /*
7175                  * Older PCIe devices only support the 128 byte
7176                  * MPS setting.  Enforce the restriction.
7177                  */
7178                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7179                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7180                 pci_write_config_word(tp->pdev,
7181                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7182                                       val16);
7183
7184                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7185
7186                 /* Clear error status */
7187                 pci_write_config_word(tp->pdev,
7188                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7189                                       PCI_EXP_DEVSTA_CED |
7190                                       PCI_EXP_DEVSTA_NFED |
7191                                       PCI_EXP_DEVSTA_FED |
7192                                       PCI_EXP_DEVSTA_URD);
7193         }
7194
7195         tg3_restore_pci_state(tp);
7196
7197         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7198
7199         val = 0;
7200         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7201                 val = tr32(MEMARB_MODE);
7202         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7203
7204         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7205                 tg3_stop_fw(tp);
7206                 tw32(0x5000, 0x400);
7207         }
7208
7209         tw32(GRC_MODE, tp->grc_mode);
7210
7211         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7212                 val = tr32(0xc4);
7213
7214                 tw32(0xc4, val | (1 << 15));
7215         }
7216
7217         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7218             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7219                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7220                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7221                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7222                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7223         }
7224
7225         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7226                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7227                                MAC_MODE_APE_RX_EN |
7228                                MAC_MODE_TDE_ENABLE;
7229
7230         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7231                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7232                 val = tp->mac_mode;
7233         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7234                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7235                 val = tp->mac_mode;
7236         } else
7237                 val = 0;
7238
7239         tw32_f(MAC_MODE, val);
7240         udelay(40);
7241
7242         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7243
7244         err = tg3_poll_fw(tp);
7245         if (err)
7246                 return err;
7247
7248         tg3_mdio_start(tp);
7249
7250         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7251             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7252             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7253             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
7254                 val = tr32(0x7c00);
7255
7256                 tw32(0x7c00, val | (1 << 25));
7257         }
7258
7259         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7260                 val = tr32(TG3_CPMU_CLCK_ORIDE);
7261                 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7262         }
7263
7264         /* Reprobe ASF enable state.  */
7265         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7266         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7267         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7268         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7269                 u32 nic_cfg;
7270
7271                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7272                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7273                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7274                         tp->last_event_jiffies = jiffies;
7275                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7276                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7277                 }
7278         }
7279
7280         return 0;
7281 }
7282
7283 /* tp->lock is held. */
7284 static void tg3_stop_fw(struct tg3 *tp)
7285 {
7286         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7287            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7288                 /* Wait for RX cpu to ACK the previous event. */
7289                 tg3_wait_for_event_ack(tp);
7290
7291                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7292
7293                 tg3_generate_fw_event(tp);
7294
7295                 /* Wait for RX cpu to ACK this event. */
7296                 tg3_wait_for_event_ack(tp);
7297         }
7298 }
7299
7300 /* tp->lock is held. */
7301 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7302 {
7303         int err;
7304
7305         tg3_stop_fw(tp);
7306
7307         tg3_write_sig_pre_reset(tp, kind);
7308
7309         tg3_abort_hw(tp, silent);
7310         err = tg3_chip_reset(tp);
7311
7312         __tg3_set_mac_addr(tp, 0);
7313
7314         tg3_write_sig_legacy(tp, kind);
7315         tg3_write_sig_post_reset(tp, kind);
7316
7317         if (err)
7318                 return err;
7319
7320         return 0;
7321 }
7322
7323 #define RX_CPU_SCRATCH_BASE     0x30000
7324 #define RX_CPU_SCRATCH_SIZE     0x04000
7325 #define TX_CPU_SCRATCH_BASE     0x34000
7326 #define TX_CPU_SCRATCH_SIZE     0x04000
7327
7328 /* tp->lock is held. */
7329 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7330 {
7331         int i;
7332
7333         BUG_ON(offset == TX_CPU_BASE &&
7334             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7335
7336         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7337                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7338
7339                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7340                 return 0;
7341         }
7342         if (offset == RX_CPU_BASE) {
7343                 for (i = 0; i < 10000; i++) {
7344                         tw32(offset + CPU_STATE, 0xffffffff);
7345                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7346                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7347                                 break;
7348                 }
7349
7350                 tw32(offset + CPU_STATE, 0xffffffff);
7351                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7352                 udelay(10);
7353         } else {
7354                 for (i = 0; i < 10000; i++) {
7355                         tw32(offset + CPU_STATE, 0xffffffff);
7356                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7357                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7358                                 break;
7359                 }
7360         }
7361
7362         if (i >= 10000) {
7363                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7364                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7365                 return -ENODEV;
7366         }
7367
7368         /* Clear firmware's nvram arbitration. */
7369         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7370                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7371         return 0;
7372 }
7373
7374 struct fw_info {
7375         unsigned int fw_base;
7376         unsigned int fw_len;
7377         const __be32 *fw_data;
7378 };
7379
7380 /* tp->lock is held. */
7381 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7382                                  int cpu_scratch_size, struct fw_info *info)
7383 {
7384         int err, lock_err, i;
7385         void (*write_op)(struct tg3 *, u32, u32);
7386
7387         if (cpu_base == TX_CPU_BASE &&
7388             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7389                 netdev_err(tp->dev,
7390                            "%s: Trying to load TX cpu firmware which is 5705\n",
7391                            __func__);
7392                 return -EINVAL;
7393         }
7394
7395         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7396                 write_op = tg3_write_mem;
7397         else
7398                 write_op = tg3_write_indirect_reg32;
7399
7400         /* It is possible that bootcode is still loading at this point.
7401          * Get the nvram lock first before halting the cpu.
7402          */
7403         lock_err = tg3_nvram_lock(tp);
7404         err = tg3_halt_cpu(tp, cpu_base);
7405         if (!lock_err)
7406                 tg3_nvram_unlock(tp);
7407         if (err)
7408                 goto out;
7409
7410         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7411                 write_op(tp, cpu_scratch_base + i, 0);
7412         tw32(cpu_base + CPU_STATE, 0xffffffff);
7413         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7414         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7415                 write_op(tp, (cpu_scratch_base +
7416                               (info->fw_base & 0xffff) +
7417                               (i * sizeof(u32))),
7418                               be32_to_cpu(info->fw_data[i]));
7419
7420         err = 0;
7421
7422 out:
7423         return err;
7424 }
7425
7426 /* tp->lock is held. */
7427 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7428 {
7429         struct fw_info info;
7430         const __be32 *fw_data;
7431         int err, i;
7432
7433         fw_data = (void *)tp->fw->data;
7434
7435         /* Firmware blob starts with version numbers, followed by
7436            start address and length. We are setting complete length.
7437            length = end_address_of_bss - start_address_of_text.
7438            Remainder is the blob to be loaded contiguously
7439            from start address. */
7440
7441         info.fw_base = be32_to_cpu(fw_data[1]);
7442         info.fw_len = tp->fw->size - 12;
7443         info.fw_data = &fw_data[3];
7444
7445         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7446                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7447                                     &info);
7448         if (err)
7449                 return err;
7450
7451         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7452                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7453                                     &info);
7454         if (err)
7455                 return err;
7456
7457         /* Now startup only the RX cpu. */
7458         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7459         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7460
7461         for (i = 0; i < 5; i++) {
7462                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7463                         break;
7464                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7465                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7466                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7467                 udelay(1000);
7468         }
7469         if (i >= 5) {
7470                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7471                            "should be %08x\n", __func__,
7472                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7473                 return -ENODEV;
7474         }
7475         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7476         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7477
7478         return 0;
7479 }
7480
7481 /* 5705 needs a special version of the TSO firmware.  */
7482
7483 /* tp->lock is held. */
7484 static int tg3_load_tso_firmware(struct tg3 *tp)
7485 {
7486         struct fw_info info;
7487         const __be32 *fw_data;
7488         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7489         int err, i;
7490
7491         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7492                 return 0;
7493
7494         fw_data = (void *)tp->fw->data;
7495
7496         /* Firmware blob starts with version numbers, followed by
7497            start address and length. We are setting complete length.
7498            length = end_address_of_bss - start_address_of_text.
7499            Remainder is the blob to be loaded contiguously
7500            from start address. */
7501
7502         info.fw_base = be32_to_cpu(fw_data[1]);
7503         cpu_scratch_size = tp->fw_len;
7504         info.fw_len = tp->fw->size - 12;
7505         info.fw_data = &fw_data[3];
7506
7507         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7508                 cpu_base = RX_CPU_BASE;
7509                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7510         } else {
7511                 cpu_base = TX_CPU_BASE;
7512                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7513                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7514         }
7515
7516         err = tg3_load_firmware_cpu(tp, cpu_base,
7517                                     cpu_scratch_base, cpu_scratch_size,
7518                                     &info);
7519         if (err)
7520                 return err;
7521
7522         /* Now startup the cpu. */
7523         tw32(cpu_base + CPU_STATE, 0xffffffff);
7524         tw32_f(cpu_base + CPU_PC, info.fw_base);
7525
7526         for (i = 0; i < 5; i++) {
7527                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7528                         break;
7529                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7530                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7531                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7532                 udelay(1000);
7533         }
7534         if (i >= 5) {
7535                 netdev_err(tp->dev,
7536                            "%s fails to set CPU PC, is %08x should be %08x\n",
7537                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7538                 return -ENODEV;
7539         }
7540         tw32(cpu_base + CPU_STATE, 0xffffffff);
7541         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7542         return 0;
7543 }
7544
7545
7546 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7547 {
7548         struct tg3 *tp = netdev_priv(dev);
7549         struct sockaddr *addr = p;
7550         int err = 0, skip_mac_1 = 0;
7551
7552         if (!is_valid_ether_addr(addr->sa_data))
7553                 return -EINVAL;
7554
7555         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7556
7557         if (!netif_running(dev))
7558                 return 0;
7559
7560         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7561                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7562
7563                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7564                 addr0_low = tr32(MAC_ADDR_0_LOW);
7565                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7566                 addr1_low = tr32(MAC_ADDR_1_LOW);
7567
7568                 /* Skip MAC addr 1 if ASF is using it. */
7569                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7570                     !(addr1_high == 0 && addr1_low == 0))
7571                         skip_mac_1 = 1;
7572         }
7573         spin_lock_bh(&tp->lock);
7574         __tg3_set_mac_addr(tp, skip_mac_1);
7575         spin_unlock_bh(&tp->lock);
7576
7577         return err;
7578 }
7579
7580 /* tp->lock is held. */
7581 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7582                            dma_addr_t mapping, u32 maxlen_flags,
7583                            u32 nic_addr)
7584 {
7585         tg3_write_mem(tp,
7586                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7587                       ((u64) mapping >> 32));
7588         tg3_write_mem(tp,
7589                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7590                       ((u64) mapping & 0xffffffff));
7591         tg3_write_mem(tp,
7592                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7593                        maxlen_flags);
7594
7595         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7596                 tg3_write_mem(tp,
7597                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7598                               nic_addr);
7599 }
7600
7601 static void __tg3_set_rx_mode(struct net_device *);
7602 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7603 {
7604         int i;
7605
7606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7607                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7608                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7609                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7610         } else {
7611                 tw32(HOSTCC_TXCOL_TICKS, 0);
7612                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7613                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7614         }
7615
7616         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7617                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7618                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7619                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7620         } else {
7621                 tw32(HOSTCC_RXCOL_TICKS, 0);
7622                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7623                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7624         }
7625
7626         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7627                 u32 val = ec->stats_block_coalesce_usecs;
7628
7629                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7630                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7631
7632                 if (!netif_carrier_ok(tp->dev))
7633                         val = 0;
7634
7635                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7636         }
7637
7638         for (i = 0; i < tp->irq_cnt - 1; i++) {
7639                 u32 reg;
7640
7641                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7642                 tw32(reg, ec->rx_coalesce_usecs);
7643                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7644                 tw32(reg, ec->rx_max_coalesced_frames);
7645                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7646                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7647
7648                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7649                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7650                         tw32(reg, ec->tx_coalesce_usecs);
7651                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7652                         tw32(reg, ec->tx_max_coalesced_frames);
7653                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7654                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7655                 }
7656         }
7657
7658         for (; i < tp->irq_max - 1; i++) {
7659                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7660                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7661                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7662
7663                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7664                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7665                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7666                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7667                 }
7668         }
7669 }
7670
7671 /* tp->lock is held. */
7672 static void tg3_rings_reset(struct tg3 *tp)
7673 {
7674         int i;
7675         u32 stblk, txrcb, rxrcb, limit;
7676         struct tg3_napi *tnapi = &tp->napi[0];
7677
7678         /* Disable all transmit rings but the first. */
7679         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7680                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7681         else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7682                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7683         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7684                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7685         else
7686                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7687
7688         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7689              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7690                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7691                               BDINFO_FLAGS_DISABLED);
7692
7693
7694         /* Disable all receive return rings but the first. */
7695         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7696                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7697         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7698                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7699         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7700                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7701                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7702         else
7703                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7704
7705         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7706              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7707                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7708                               BDINFO_FLAGS_DISABLED);
7709
7710         /* Disable interrupts */
7711         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7712
7713         /* Zero mailbox registers. */
7714         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7715                 for (i = 1; i < tp->irq_max; i++) {
7716                         tp->napi[i].tx_prod = 0;
7717                         tp->napi[i].tx_cons = 0;
7718                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7719                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7720                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7721                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7722                 }
7723                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7724                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7725         } else {
7726                 tp->napi[0].tx_prod = 0;
7727                 tp->napi[0].tx_cons = 0;
7728                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7729                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7730         }
7731
7732         /* Make sure the NIC-based send BD rings are disabled. */
7733         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7734                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7735                 for (i = 0; i < 16; i++)
7736                         tw32_tx_mbox(mbox + i * 8, 0);
7737         }
7738
7739         txrcb = NIC_SRAM_SEND_RCB;
7740         rxrcb = NIC_SRAM_RCV_RET_RCB;
7741
7742         /* Clear status block in ram. */
7743         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7744
7745         /* Set status block DMA address */
7746         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7747              ((u64) tnapi->status_mapping >> 32));
7748         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7749              ((u64) tnapi->status_mapping & 0xffffffff));
7750
7751         if (tnapi->tx_ring) {
7752                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7753                                (TG3_TX_RING_SIZE <<
7754                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7755                                NIC_SRAM_TX_BUFFER_DESC);
7756                 txrcb += TG3_BDINFO_SIZE;
7757         }
7758
7759         if (tnapi->rx_rcb) {
7760                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7761                                (tp->rx_ret_ring_mask + 1) <<
7762                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7763                 rxrcb += TG3_BDINFO_SIZE;
7764         }
7765
7766         stblk = HOSTCC_STATBLCK_RING1;
7767
7768         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7769                 u64 mapping = (u64)tnapi->status_mapping;
7770                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7771                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7772
7773                 /* Clear status block in ram. */
7774                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7775
7776                 if (tnapi->tx_ring) {
7777                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7778                                        (TG3_TX_RING_SIZE <<
7779                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7780                                        NIC_SRAM_TX_BUFFER_DESC);
7781                         txrcb += TG3_BDINFO_SIZE;
7782                 }
7783
7784                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7785                                ((tp->rx_ret_ring_mask + 1) <<
7786                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7787
7788                 stblk += 8;
7789                 rxrcb += TG3_BDINFO_SIZE;
7790         }
7791 }
7792
7793 /* tp->lock is held. */
7794 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7795 {
7796         u32 val, rdmac_mode;
7797         int i, err, limit;
7798         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7799
7800         tg3_disable_ints(tp);
7801
7802         tg3_stop_fw(tp);
7803
7804         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7805
7806         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7807                 tg3_abort_hw(tp, 1);
7808
7809         /* Enable MAC control of LPI */
7810         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7811                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7812                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7813                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7814
7815                 tw32_f(TG3_CPMU_EEE_CTRL,
7816                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7817
7818                 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7819                       TG3_CPMU_EEEMD_LPI_IN_TX |
7820                       TG3_CPMU_EEEMD_LPI_IN_RX |
7821                       TG3_CPMU_EEEMD_EEE_ENABLE;
7822
7823                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7824                         val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7825
7826                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7827                         val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7828
7829                 tw32_f(TG3_CPMU_EEE_MODE, val);
7830
7831                 tw32_f(TG3_CPMU_EEE_DBTMR1,
7832                        TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7833                        TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7834
7835                 tw32_f(TG3_CPMU_EEE_DBTMR2,
7836                        TG3_CPMU_DBTMR2_APE_TX_2047US |
7837                        TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7838         }
7839
7840         if (reset_phy)
7841                 tg3_phy_reset(tp);
7842
7843         err = tg3_chip_reset(tp);
7844         if (err)
7845                 return err;
7846
7847         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7848
7849         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7850                 val = tr32(TG3_CPMU_CTRL);
7851                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7852                 tw32(TG3_CPMU_CTRL, val);
7853
7854                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7855                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7856                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7857                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7858
7859                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7860                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7861                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7862                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7863
7864                 val = tr32(TG3_CPMU_HST_ACC);
7865                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7866                 val |= CPMU_HST_ACC_MACCLK_6_25;
7867                 tw32(TG3_CPMU_HST_ACC, val);
7868         }
7869
7870         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7871                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7872                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7873                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7874                 tw32(PCIE_PWR_MGMT_THRESH, val);
7875
7876                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7877                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7878
7879                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7880
7881                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7882                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7883         }
7884
7885         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7886                 u32 grc_mode = tr32(GRC_MODE);
7887
7888                 /* Access the lower 1K of PL PCIE block registers. */
7889                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7890                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7891
7892                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7893                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7894                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7895
7896                 tw32(GRC_MODE, grc_mode);
7897         }
7898
7899         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7900                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7901                         u32 grc_mode = tr32(GRC_MODE);
7902
7903                         /* Access the lower 1K of PL PCIE block registers. */
7904                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7905                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7906
7907                         val = tr32(TG3_PCIE_TLDLPL_PORT +
7908                                    TG3_PCIE_PL_LO_PHYCTL5);
7909                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7910                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7911
7912                         tw32(GRC_MODE, grc_mode);
7913                 }
7914
7915                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7916                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7917                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7918                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7919         }
7920
7921         /* This works around an issue with Athlon chipsets on
7922          * B3 tigon3 silicon.  This bit has no effect on any
7923          * other revision.  But do not set this on PCI Express
7924          * chips and don't even touch the clocks if the CPMU is present.
7925          */
7926         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7927                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7928                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7929                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7930         }
7931
7932         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7933             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7934                 val = tr32(TG3PCI_PCISTATE);
7935                 val |= PCISTATE_RETRY_SAME_DMA;
7936                 tw32(TG3PCI_PCISTATE, val);
7937         }
7938
7939         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7940                 /* Allow reads and writes to the
7941                  * APE register and memory space.
7942                  */
7943                 val = tr32(TG3PCI_PCISTATE);
7944                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7945                        PCISTATE_ALLOW_APE_SHMEM_WR |
7946                        PCISTATE_ALLOW_APE_PSPACE_WR;
7947                 tw32(TG3PCI_PCISTATE, val);
7948         }
7949
7950         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7951                 /* Enable some hw fixes.  */
7952                 val = tr32(TG3PCI_MSI_DATA);
7953                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7954                 tw32(TG3PCI_MSI_DATA, val);
7955         }
7956
7957         /* Descriptor ring init may make accesses to the
7958          * NIC SRAM area to setup the TX descriptors, so we
7959          * can only do this after the hardware has been
7960          * successfully reset.
7961          */
7962         err = tg3_init_rings(tp);
7963         if (err)
7964                 return err;
7965
7966         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
7967                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7968                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7969                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7970                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7971                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7972         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7973                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7974                 /* This value is determined during the probe time DMA
7975                  * engine test, tg3_test_dma.
7976                  */
7977                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7978         }
7979
7980         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7981                           GRC_MODE_4X_NIC_SEND_RINGS |
7982                           GRC_MODE_NO_TX_PHDR_CSUM |
7983                           GRC_MODE_NO_RX_PHDR_CSUM);
7984         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7985
7986         /* Pseudo-header checksum is done by hardware logic and not
7987          * the offload processers, so make the chip do the pseudo-
7988          * header checksums on receive.  For transmit it is more
7989          * convenient to do the pseudo-header checksum in software
7990          * as Linux does that on transmit for us in all cases.
7991          */
7992         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7993
7994         tw32(GRC_MODE,
7995              tp->grc_mode |
7996              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7997
7998         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7999         val = tr32(GRC_MISC_CFG);
8000         val &= ~0xff;
8001         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8002         tw32(GRC_MISC_CFG, val);
8003
8004         /* Initialize MBUF/DESC pool. */
8005         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8006                 /* Do nothing.  */
8007         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8008                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8009                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8010                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8011                 else
8012                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8013                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8014                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8015         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8016                 int fw_len;
8017
8018                 fw_len = tp->fw_len;
8019                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8020                 tw32(BUFMGR_MB_POOL_ADDR,
8021                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8022                 tw32(BUFMGR_MB_POOL_SIZE,
8023                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8024         }
8025
8026         if (tp->dev->mtu <= ETH_DATA_LEN) {
8027                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8028                      tp->bufmgr_config.mbuf_read_dma_low_water);
8029                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8030                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8031                 tw32(BUFMGR_MB_HIGH_WATER,
8032                      tp->bufmgr_config.mbuf_high_water);
8033         } else {
8034                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8035                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8036                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8037                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8038                 tw32(BUFMGR_MB_HIGH_WATER,
8039                      tp->bufmgr_config.mbuf_high_water_jumbo);
8040         }
8041         tw32(BUFMGR_DMA_LOW_WATER,
8042              tp->bufmgr_config.dma_low_water);
8043         tw32(BUFMGR_DMA_HIGH_WATER,
8044              tp->bufmgr_config.dma_high_water);
8045
8046         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8048                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8049         tw32(BUFMGR_MODE, val);
8050         for (i = 0; i < 2000; i++) {
8051                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8052                         break;
8053                 udelay(10);
8054         }
8055         if (i >= 2000) {
8056                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8057                 return -ENODEV;
8058         }
8059
8060         /* Setup replenish threshold. */
8061         val = tp->rx_pending / 8;
8062         if (val == 0)
8063                 val = 1;
8064         else if (val > tp->rx_std_max_post)
8065                 val = tp->rx_std_max_post;
8066         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8067                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8068                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8069
8070                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8071                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8072         }
8073
8074         tw32(RCVBDI_STD_THRESH, val);
8075
8076         /* Initialize TG3_BDINFO's at:
8077          *  RCVDBDI_STD_BD:     standard eth size rx ring
8078          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8079          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8080          *
8081          * like so:
8082          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8083          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8084          *                              ring attribute flags
8085          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8086          *
8087          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8088          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8089          *
8090          * The size of each ring is fixed in the firmware, but the location is
8091          * configurable.
8092          */
8093         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8094              ((u64) tpr->rx_std_mapping >> 32));
8095         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8096              ((u64) tpr->rx_std_mapping & 0xffffffff));
8097         if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
8098                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8099                      NIC_SRAM_RX_BUFFER_DESC);
8100
8101         /* Disable the mini ring */
8102         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8103                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8104                      BDINFO_FLAGS_DISABLED);
8105
8106         /* Program the jumbo buffer descriptor ring control
8107          * blocks on those devices that have them.
8108          */
8109         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8110             ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8111             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8112                 /* Setup replenish threshold. */
8113                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8114
8115                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8116                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8117                              ((u64) tpr->rx_jmb_mapping >> 32));
8118                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8119                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8120                         val = TG3_RX_JMB_RING_SIZE(tp) <<
8121                               BDINFO_FLAGS_MAXLEN_SHIFT;
8122                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8123                              val | BDINFO_FLAGS_USE_EXT_RECV);
8124                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8125                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8126                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8127                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8128                 } else {
8129                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8130                              BDINFO_FLAGS_DISABLED);
8131                 }
8132
8133                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8134                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8135                                 val = TG3_RX_STD_MAX_SIZE_5700;
8136                         else
8137                                 val = TG3_RX_STD_MAX_SIZE_5717;
8138                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8139                         val |= (TG3_RX_STD_DMA_SZ << 2);
8140                 } else
8141                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8142         } else
8143                 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8144
8145         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8146
8147         tpr->rx_std_prod_idx = tp->rx_pending;
8148         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8149
8150         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8151                           tp->rx_jumbo_pending : 0;
8152         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8153
8154         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8155                 tw32(STD_REPLENISH_LWM, 32);
8156                 tw32(JMB_REPLENISH_LWM, 16);
8157         }
8158
8159         tg3_rings_reset(tp);
8160
8161         /* Initialize MAC address and backoff seed. */
8162         __tg3_set_mac_addr(tp, 0);
8163
8164         /* MTU + ethernet header + FCS + optional VLAN tag */
8165         tw32(MAC_RX_MTU_SIZE,
8166              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8167
8168         /* The slot time is changed by tg3_setup_phy if we
8169          * run at gigabit with half duplex.
8170          */
8171         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8172               (6 << TX_LENGTHS_IPG_SHIFT) |
8173               (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8174
8175         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8176                 val |= tr32(MAC_TX_LENGTHS) &
8177                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
8178                         TX_LENGTHS_CNT_DWN_VAL_MSK);
8179
8180         tw32(MAC_TX_LENGTHS, val);
8181
8182         /* Receive rules. */
8183         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8184         tw32(RCVLPC_CONFIG, 0x0181);
8185
8186         /* Calculate RDMAC_MODE setting early, we need it to determine
8187          * the RCVLPC_STATE_ENABLE mask.
8188          */
8189         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8190                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8191                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8192                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8193                       RDMAC_MODE_LNGREAD_ENAB);
8194
8195         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8196                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8197
8198         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8199             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8200             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8201                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8202                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8203                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8204
8205         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8206             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8207                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8208                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8209                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8210                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8211                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8212                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8213                 }
8214         }
8215
8216         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8217                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8218
8219         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8220                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8221
8222         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8223             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8224             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8225                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8226
8227         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8228                 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8229
8230         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8231             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8232             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8233             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8234             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
8235                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8236                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8237                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8238                         val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8239                                  TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8240                                  TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8241                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8242                                TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8243                                TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8244                 }
8245                 tw32(TG3_RDMA_RSRVCTRL_REG,
8246                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8247         }
8248
8249         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8250             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8251                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8252                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8253                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8254                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8255         }
8256
8257         /* Receive/send statistics. */
8258         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8259                 val = tr32(RCVLPC_STATS_ENABLE);
8260                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8261                 tw32(RCVLPC_STATS_ENABLE, val);
8262         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8263                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8264                 val = tr32(RCVLPC_STATS_ENABLE);
8265                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8266                 tw32(RCVLPC_STATS_ENABLE, val);
8267         } else {
8268                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8269         }
8270         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8271         tw32(SNDDATAI_STATSENAB, 0xffffff);
8272         tw32(SNDDATAI_STATSCTRL,
8273              (SNDDATAI_SCTRL_ENABLE |
8274               SNDDATAI_SCTRL_FASTUPD));
8275
8276         /* Setup host coalescing engine. */
8277         tw32(HOSTCC_MODE, 0);
8278         for (i = 0; i < 2000; i++) {
8279                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8280                         break;
8281                 udelay(10);
8282         }
8283
8284         __tg3_set_coalesce(tp, &tp->coal);
8285
8286         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8287                 /* Status/statistics block address.  See tg3_timer,
8288                  * the tg3_periodic_fetch_stats call there, and
8289                  * tg3_get_stats to see how this works for 5705/5750 chips.
8290                  */
8291                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8292                      ((u64) tp->stats_mapping >> 32));
8293                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8294                      ((u64) tp->stats_mapping & 0xffffffff));
8295                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8296
8297                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8298
8299                 /* Clear statistics and status block memory areas */
8300                 for (i = NIC_SRAM_STATS_BLK;
8301                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8302                      i += sizeof(u32)) {
8303                         tg3_write_mem(tp, i, 0);
8304                         udelay(40);
8305                 }
8306         }
8307
8308         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8309
8310         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8311         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8312         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8313                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8314
8315         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8316                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8317                 /* reset to prevent losing 1st rx packet intermittently */
8318                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8319                 udelay(10);
8320         }
8321
8322         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8323                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8324         else
8325                 tp->mac_mode = 0;
8326         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8327                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8328         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8329             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8330             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8331                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8332         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8333         udelay(40);
8334
8335         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8336          * If TG3_FLG2_IS_NIC is zero, we should read the
8337          * register to preserve the GPIO settings for LOMs. The GPIOs,
8338          * whether used as inputs or outputs, are set by boot code after
8339          * reset.
8340          */
8341         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8342                 u32 gpio_mask;
8343
8344                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8345                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8346                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8347
8348                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8349                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8350                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8351
8352                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8353                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8354
8355                 tp->grc_local_ctrl &= ~gpio_mask;
8356                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8357
8358                 /* GPIO1 must be driven high for eeprom write protect */
8359                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8360                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8361                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8362         }
8363         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8364         udelay(100);
8365
8366         if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8367                 tp->irq_cnt > 1) {
8368                 val = tr32(MSGINT_MODE);
8369                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8370                 tw32(MSGINT_MODE, val);
8371         }
8372
8373         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8374                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8375                 udelay(40);
8376         }
8377
8378         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8379                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8380                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8381                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8382                WDMAC_MODE_LNGREAD_ENAB);
8383
8384         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8385             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8386                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8387                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8388                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8389                         /* nothing */
8390                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8391                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8392                         val |= WDMAC_MODE_RX_ACCEL;
8393                 }
8394         }
8395
8396         /* Enable host coalescing bug fix */
8397         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8398                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8399
8400         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8401                 val |= WDMAC_MODE_BURST_ALL_DATA;
8402
8403         tw32_f(WDMAC_MODE, val);
8404         udelay(40);
8405
8406         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8407                 u16 pcix_cmd;
8408
8409                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8410                                      &pcix_cmd);
8411                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8412                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8413                         pcix_cmd |= PCI_X_CMD_READ_2K;
8414                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8415                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8416                         pcix_cmd |= PCI_X_CMD_READ_2K;
8417                 }
8418                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8419                                       pcix_cmd);
8420         }
8421
8422         tw32_f(RDMAC_MODE, rdmac_mode);
8423         udelay(40);
8424
8425         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8426         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8427                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8428
8429         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8430                 tw32(SNDDATAC_MODE,
8431                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8432         else
8433                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8434
8435         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8436         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8437         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8438         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
8439                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8440         tw32(RCVDBDI_MODE, val);
8441         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8442         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8443                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8444         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8445         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8446                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8447         tw32(SNDBDI_MODE, val);
8448         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8449
8450         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8451                 err = tg3_load_5701_a0_firmware_fix(tp);
8452                 if (err)
8453                         return err;
8454         }
8455
8456         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8457                 err = tg3_load_tso_firmware(tp);
8458                 if (err)
8459                         return err;
8460         }
8461
8462         tp->tx_mode = TX_MODE_ENABLE;
8463
8464         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8465             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8466                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8467
8468         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8469                 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8470                 tp->tx_mode &= ~val;
8471                 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8472         }
8473
8474         tw32_f(MAC_TX_MODE, tp->tx_mode);
8475         udelay(100);
8476
8477         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8478                 u32 reg = MAC_RSS_INDIR_TBL_0;
8479                 u8 *ent = (u8 *)&val;
8480
8481                 /* Setup the indirection table */
8482                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8483                         int idx = i % sizeof(val);
8484
8485                         ent[idx] = i % (tp->irq_cnt - 1);
8486                         if (idx == sizeof(val) - 1) {
8487                                 tw32(reg, val);
8488                                 reg += 4;
8489                         }
8490                 }
8491
8492                 /* Setup the "secret" hash key. */
8493                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8494                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8495                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8496                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8497                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8498                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8499                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8500                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8501                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8502                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8503         }
8504
8505         tp->rx_mode = RX_MODE_ENABLE;
8506         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8507                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8508
8509         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8510                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8511                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8512                                RX_MODE_RSS_IPV6_HASH_EN |
8513                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8514                                RX_MODE_RSS_IPV4_HASH_EN |
8515                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8516
8517         tw32_f(MAC_RX_MODE, tp->rx_mode);
8518         udelay(10);
8519
8520         tw32(MAC_LED_CTRL, tp->led_ctrl);
8521
8522         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8523         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8524                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8525                 udelay(10);
8526         }
8527         tw32_f(MAC_RX_MODE, tp->rx_mode);
8528         udelay(10);
8529
8530         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8531                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8532                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8533                         /* Set drive transmission level to 1.2V  */
8534                         /* only if the signal pre-emphasis bit is not set  */
8535                         val = tr32(MAC_SERDES_CFG);
8536                         val &= 0xfffff000;
8537                         val |= 0x880;
8538                         tw32(MAC_SERDES_CFG, val);
8539                 }
8540                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8541                         tw32(MAC_SERDES_CFG, 0x616000);
8542         }
8543
8544         /* Prevent chip from dropping frames when flow control
8545          * is enabled.
8546          */
8547         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8548                 val = 1;
8549         else
8550                 val = 2;
8551         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8552
8553         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8554             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8555                 /* Use hardware link auto-negotiation */
8556                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8557         }
8558
8559         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8560             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8561                 u32 tmp;
8562
8563                 tmp = tr32(SERDES_RX_CTRL);
8564                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8565                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8566                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8567                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8568         }
8569
8570         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8571                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8572                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8573                         tp->link_config.speed = tp->link_config.orig_speed;
8574                         tp->link_config.duplex = tp->link_config.orig_duplex;
8575                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8576                 }
8577
8578                 err = tg3_setup_phy(tp, 0);
8579                 if (err)
8580                         return err;
8581
8582                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8583                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8584                         u32 tmp;
8585
8586                         /* Clear CRC stats. */
8587                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8588                                 tg3_writephy(tp, MII_TG3_TEST1,
8589                                              tmp | MII_TG3_TEST1_CRC_EN);
8590                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8591                         }
8592                 }
8593         }
8594
8595         __tg3_set_rx_mode(tp->dev);
8596
8597         /* Initialize receive rules. */
8598         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8599         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8600         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8601         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8602
8603         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8604             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8605                 limit = 8;
8606         else
8607                 limit = 16;
8608         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8609                 limit -= 4;
8610         switch (limit) {
8611         case 16:
8612                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8613         case 15:
8614                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8615         case 14:
8616                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8617         case 13:
8618                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8619         case 12:
8620                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8621         case 11:
8622                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8623         case 10:
8624                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8625         case 9:
8626                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8627         case 8:
8628                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8629         case 7:
8630                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8631         case 6:
8632                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8633         case 5:
8634                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8635         case 4:
8636                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8637         case 3:
8638                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8639         case 2:
8640         case 1:
8641
8642         default:
8643                 break;
8644         }
8645
8646         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8647                 /* Write our heartbeat update interval to APE. */
8648                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8649                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8650
8651         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8652
8653         return 0;
8654 }
8655
8656 /* Called at device open time to get the chip ready for
8657  * packet processing.  Invoked with tp->lock held.
8658  */
8659 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8660 {
8661         tg3_switch_clocks(tp);
8662
8663         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8664
8665         return tg3_reset_hw(tp, reset_phy);
8666 }
8667
8668 #define TG3_STAT_ADD32(PSTAT, REG) \
8669 do {    u32 __val = tr32(REG); \
8670         (PSTAT)->low += __val; \
8671         if ((PSTAT)->low < __val) \
8672                 (PSTAT)->high += 1; \
8673 } while (0)
8674
8675 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8676 {
8677         struct tg3_hw_stats *sp = tp->hw_stats;
8678
8679         if (!netif_carrier_ok(tp->dev))
8680                 return;
8681
8682         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8683         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8684         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8685         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8686         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8687         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8688         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8689         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8690         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8691         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8692         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8693         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8694         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8695
8696         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8697         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8698         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8699         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8700         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8701         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8702         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8703         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8704         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8705         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8706         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8707         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8708         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8709         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8710
8711         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8712         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8713         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8714 }
8715
8716 static void tg3_timer(unsigned long __opaque)
8717 {
8718         struct tg3 *tp = (struct tg3 *) __opaque;
8719
8720         if (tp->irq_sync)
8721                 goto restart_timer;
8722
8723         spin_lock(&tp->lock);
8724
8725         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8726                 /* All of this garbage is because when using non-tagged
8727                  * IRQ status the mailbox/status_block protocol the chip
8728                  * uses with the cpu is race prone.
8729                  */
8730                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8731                         tw32(GRC_LOCAL_CTRL,
8732                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8733                 } else {
8734                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8735                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8736                 }
8737
8738                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8739                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8740                         spin_unlock(&tp->lock);
8741                         schedule_work(&tp->reset_task);
8742                         return;
8743                 }
8744         }
8745
8746         /* This part only runs once per second. */
8747         if (!--tp->timer_counter) {
8748                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8749                         tg3_periodic_fetch_stats(tp);
8750
8751                 if (tp->setlpicnt && !--tp->setlpicnt) {
8752                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8753                         tw32(TG3_CPMU_EEE_MODE,
8754                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8755                 }
8756
8757                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8758                         u32 mac_stat;
8759                         int phy_event;
8760
8761                         mac_stat = tr32(MAC_STATUS);
8762
8763                         phy_event = 0;
8764                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8765                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8766                                         phy_event = 1;
8767                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8768                                 phy_event = 1;
8769
8770                         if (phy_event)
8771                                 tg3_setup_phy(tp, 0);
8772                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8773                         u32 mac_stat = tr32(MAC_STATUS);
8774                         int need_setup = 0;
8775
8776                         if (netif_carrier_ok(tp->dev) &&
8777                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8778                                 need_setup = 1;
8779                         }
8780                         if (!netif_carrier_ok(tp->dev) &&
8781                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8782                                          MAC_STATUS_SIGNAL_DET))) {
8783                                 need_setup = 1;
8784                         }
8785                         if (need_setup) {
8786                                 if (!tp->serdes_counter) {
8787                                         tw32_f(MAC_MODE,
8788                                              (tp->mac_mode &
8789                                               ~MAC_MODE_PORT_MODE_MASK));
8790                                         udelay(40);
8791                                         tw32_f(MAC_MODE, tp->mac_mode);
8792                                         udelay(40);
8793                                 }
8794                                 tg3_setup_phy(tp, 0);
8795                         }
8796                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8797                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8798                         tg3_serdes_parallel_detect(tp);
8799                 }
8800
8801                 tp->timer_counter = tp->timer_multiplier;
8802         }
8803
8804         /* Heartbeat is only sent once every 2 seconds.
8805          *
8806          * The heartbeat is to tell the ASF firmware that the host
8807          * driver is still alive.  In the event that the OS crashes,
8808          * ASF needs to reset the hardware to free up the FIFO space
8809          * that may be filled with rx packets destined for the host.
8810          * If the FIFO is full, ASF will no longer function properly.
8811          *
8812          * Unintended resets have been reported on real time kernels
8813          * where the timer doesn't run on time.  Netpoll will also have
8814          * same problem.
8815          *
8816          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8817          * to check the ring condition when the heartbeat is expiring
8818          * before doing the reset.  This will prevent most unintended
8819          * resets.
8820          */
8821         if (!--tp->asf_counter) {
8822                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8823                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8824                         tg3_wait_for_event_ack(tp);
8825
8826                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8827                                       FWCMD_NICDRV_ALIVE3);
8828                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8829                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8830                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8831
8832                         tg3_generate_fw_event(tp);
8833                 }
8834                 tp->asf_counter = tp->asf_multiplier;
8835         }
8836
8837         spin_unlock(&tp->lock);
8838
8839 restart_timer:
8840         tp->timer.expires = jiffies + tp->timer_offset;
8841         add_timer(&tp->timer);
8842 }
8843
8844 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8845 {
8846         irq_handler_t fn;
8847         unsigned long flags;
8848         char *name;
8849         struct tg3_napi *tnapi = &tp->napi[irq_num];
8850
8851         if (tp->irq_cnt == 1)
8852                 name = tp->dev->name;
8853         else {
8854                 name = &tnapi->irq_lbl[0];
8855                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8856                 name[IFNAMSIZ-1] = 0;
8857         }
8858
8859         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8860                 fn = tg3_msi;
8861                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8862                         fn = tg3_msi_1shot;
8863                 flags = 0;
8864         } else {
8865                 fn = tg3_interrupt;
8866                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8867                         fn = tg3_interrupt_tagged;
8868                 flags = IRQF_SHARED;
8869         }
8870
8871         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8872 }
8873
8874 static int tg3_test_interrupt(struct tg3 *tp)
8875 {
8876         struct tg3_napi *tnapi = &tp->napi[0];
8877         struct net_device *dev = tp->dev;
8878         int err, i, intr_ok = 0;
8879         u32 val;
8880
8881         if (!netif_running(dev))
8882                 return -ENODEV;
8883
8884         tg3_disable_ints(tp);
8885
8886         free_irq(tnapi->irq_vec, tnapi);
8887
8888         /*
8889          * Turn off MSI one shot mode.  Otherwise this test has no
8890          * observable way to know whether the interrupt was delivered.
8891          */
8892         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
8893             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8894                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8895                 tw32(MSGINT_MODE, val);
8896         }
8897
8898         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8899                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8900         if (err)
8901                 return err;
8902
8903         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8904         tg3_enable_ints(tp);
8905
8906         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8907                tnapi->coal_now);
8908
8909         for (i = 0; i < 5; i++) {
8910                 u32 int_mbox, misc_host_ctrl;
8911
8912                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8913                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8914
8915                 if ((int_mbox != 0) ||
8916                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8917                         intr_ok = 1;
8918                         break;
8919                 }
8920
8921                 msleep(10);
8922         }
8923
8924         tg3_disable_ints(tp);
8925
8926         free_irq(tnapi->irq_vec, tnapi);
8927
8928         err = tg3_request_irq(tp, 0);
8929
8930         if (err)
8931                 return err;
8932
8933         if (intr_ok) {
8934                 /* Reenable MSI one shot mode. */
8935                 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
8936                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8937                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8938                         tw32(MSGINT_MODE, val);
8939                 }
8940                 return 0;
8941         }
8942
8943         return -EIO;
8944 }
8945
8946 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8947  * successfully restored
8948  */
8949 static int tg3_test_msi(struct tg3 *tp)
8950 {
8951         int err;
8952         u16 pci_cmd;
8953
8954         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8955                 return 0;
8956
8957         /* Turn off SERR reporting in case MSI terminates with Master
8958          * Abort.
8959          */
8960         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8961         pci_write_config_word(tp->pdev, PCI_COMMAND,
8962                               pci_cmd & ~PCI_COMMAND_SERR);
8963
8964         err = tg3_test_interrupt(tp);
8965
8966         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8967
8968         if (!err)
8969                 return 0;
8970
8971         /* other failures */
8972         if (err != -EIO)
8973                 return err;
8974
8975         /* MSI test failed, go back to INTx mode */
8976         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8977                     "to INTx mode. Please report this failure to the PCI "
8978                     "maintainer and include system chipset information\n");
8979
8980         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8981
8982         pci_disable_msi(tp->pdev);
8983
8984         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8985         tp->napi[0].irq_vec = tp->pdev->irq;
8986
8987         err = tg3_request_irq(tp, 0);
8988         if (err)
8989                 return err;
8990
8991         /* Need to reset the chip because the MSI cycle may have terminated
8992          * with Master Abort.
8993          */
8994         tg3_full_lock(tp, 1);
8995
8996         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8997         err = tg3_init_hw(tp, 1);
8998
8999         tg3_full_unlock(tp);
9000
9001         if (err)
9002                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9003
9004         return err;
9005 }
9006
9007 static int tg3_request_firmware(struct tg3 *tp)
9008 {
9009         const __be32 *fw_data;
9010
9011         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9012                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9013                            tp->fw_needed);
9014                 return -ENOENT;
9015         }
9016
9017         fw_data = (void *)tp->fw->data;
9018
9019         /* Firmware blob starts with version numbers, followed by
9020          * start address and _full_ length including BSS sections
9021          * (which must be longer than the actual data, of course
9022          */
9023
9024         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
9025         if (tp->fw_len < (tp->fw->size - 12)) {
9026                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9027                            tp->fw_len, tp->fw_needed);
9028                 release_firmware(tp->fw);
9029                 tp->fw = NULL;
9030                 return -EINVAL;
9031         }
9032
9033         /* We no longer need firmware; we have it. */
9034         tp->fw_needed = NULL;
9035         return 0;
9036 }
9037
9038 static bool tg3_enable_msix(struct tg3 *tp)
9039 {
9040         int i, rc, cpus = num_online_cpus();
9041         struct msix_entry msix_ent[tp->irq_max];
9042
9043         if (cpus == 1)
9044                 /* Just fallback to the simpler MSI mode. */
9045                 return false;
9046
9047         /*
9048          * We want as many rx rings enabled as there are cpus.
9049          * The first MSIX vector only deals with link interrupts, etc,
9050          * so we add one to the number of vectors we are requesting.
9051          */
9052         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9053
9054         for (i = 0; i < tp->irq_max; i++) {
9055                 msix_ent[i].entry  = i;
9056                 msix_ent[i].vector = 0;
9057         }
9058
9059         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9060         if (rc < 0) {
9061                 return false;
9062         } else if (rc != 0) {
9063                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9064                         return false;
9065                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9066                               tp->irq_cnt, rc);
9067                 tp->irq_cnt = rc;
9068         }
9069
9070         for (i = 0; i < tp->irq_max; i++)
9071                 tp->napi[i].irq_vec = msix_ent[i].vector;
9072
9073         netif_set_real_num_tx_queues(tp->dev, 1);
9074         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9075         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9076                 pci_disable_msix(tp->pdev);
9077                 return false;
9078         }
9079
9080         if (tp->irq_cnt > 1) {
9081                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9082
9083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9084                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9085                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9086                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9087                 }
9088         }
9089
9090         return true;
9091 }
9092
9093 static void tg3_ints_init(struct tg3 *tp)
9094 {
9095         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9096             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9097                 /* All MSI supporting chips should support tagged
9098                  * status.  Assert that this is the case.
9099                  */
9100                 netdev_warn(tp->dev,
9101                             "MSI without TAGGED_STATUS? Not using MSI\n");
9102                 goto defcfg;
9103         }
9104
9105         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9106                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9107         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9108                  pci_enable_msi(tp->pdev) == 0)
9109                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9110
9111         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9112                 u32 msi_mode = tr32(MSGINT_MODE);
9113                 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9114                     tp->irq_cnt > 1)
9115                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9116                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9117         }
9118 defcfg:
9119         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9120                 tp->irq_cnt = 1;
9121                 tp->napi[0].irq_vec = tp->pdev->irq;
9122                 netif_set_real_num_tx_queues(tp->dev, 1);
9123                 netif_set_real_num_rx_queues(tp->dev, 1);
9124         }
9125 }
9126
9127 static void tg3_ints_fini(struct tg3 *tp)
9128 {
9129         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9130                 pci_disable_msix(tp->pdev);
9131         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9132                 pci_disable_msi(tp->pdev);
9133         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9134         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9135 }
9136
9137 static int tg3_open(struct net_device *dev)
9138 {
9139         struct tg3 *tp = netdev_priv(dev);
9140         int i, err;
9141
9142         if (tp->fw_needed) {
9143                 err = tg3_request_firmware(tp);
9144                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9145                         if (err)
9146                                 return err;
9147                 } else if (err) {
9148                         netdev_warn(tp->dev, "TSO capability disabled\n");
9149                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9150                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9151                         netdev_notice(tp->dev, "TSO capability restored\n");
9152                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9153                 }
9154         }
9155
9156         netif_carrier_off(tp->dev);
9157
9158         err = tg3_power_up(tp);
9159         if (err)
9160                 return err;
9161
9162         tg3_full_lock(tp, 0);
9163
9164         tg3_disable_ints(tp);
9165         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9166
9167         tg3_full_unlock(tp);
9168
9169         /*
9170          * Setup interrupts first so we know how
9171          * many NAPI resources to allocate
9172          */
9173         tg3_ints_init(tp);
9174
9175         /* The placement of this call is tied
9176          * to the setup and use of Host TX descriptors.
9177          */
9178         err = tg3_alloc_consistent(tp);
9179         if (err)
9180                 goto err_out1;
9181
9182         tg3_napi_init(tp);
9183
9184         tg3_napi_enable(tp);
9185
9186         for (i = 0; i < tp->irq_cnt; i++) {
9187                 struct tg3_napi *tnapi = &tp->napi[i];
9188                 err = tg3_request_irq(tp, i);
9189                 if (err) {
9190                         for (i--; i >= 0; i--)
9191                                 free_irq(tnapi->irq_vec, tnapi);
9192                         break;
9193                 }
9194         }
9195
9196         if (err)
9197                 goto err_out2;
9198
9199         tg3_full_lock(tp, 0);
9200
9201         err = tg3_init_hw(tp, 1);
9202         if (err) {
9203                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9204                 tg3_free_rings(tp);
9205         } else {
9206                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9207                         tp->timer_offset = HZ;
9208                 else
9209                         tp->timer_offset = HZ / 10;
9210
9211                 BUG_ON(tp->timer_offset > HZ);
9212                 tp->timer_counter = tp->timer_multiplier =
9213                         (HZ / tp->timer_offset);
9214                 tp->asf_counter = tp->asf_multiplier =
9215                         ((HZ / tp->timer_offset) * 2);
9216
9217                 init_timer(&tp->timer);
9218                 tp->timer.expires = jiffies + tp->timer_offset;
9219                 tp->timer.data = (unsigned long) tp;
9220                 tp->timer.function = tg3_timer;
9221         }
9222
9223         tg3_full_unlock(tp);
9224
9225         if (err)
9226                 goto err_out3;
9227
9228         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9229                 err = tg3_test_msi(tp);
9230
9231                 if (err) {
9232                         tg3_full_lock(tp, 0);
9233                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9234                         tg3_free_rings(tp);
9235                         tg3_full_unlock(tp);
9236
9237                         goto err_out2;
9238                 }
9239
9240                 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9241                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9242                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9243
9244                         tw32(PCIE_TRANSACTION_CFG,
9245                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9246                 }
9247         }
9248
9249         tg3_phy_start(tp);
9250
9251         tg3_full_lock(tp, 0);
9252
9253         add_timer(&tp->timer);
9254         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9255         tg3_enable_ints(tp);
9256
9257         tg3_full_unlock(tp);
9258
9259         netif_tx_start_all_queues(dev);
9260
9261         return 0;
9262
9263 err_out3:
9264         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9265                 struct tg3_napi *tnapi = &tp->napi[i];
9266                 free_irq(tnapi->irq_vec, tnapi);
9267         }
9268
9269 err_out2:
9270         tg3_napi_disable(tp);
9271         tg3_napi_fini(tp);
9272         tg3_free_consistent(tp);
9273
9274 err_out1:
9275         tg3_ints_fini(tp);
9276         return err;
9277 }
9278
9279 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9280                                                  struct rtnl_link_stats64 *);
9281 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9282
9283 static int tg3_close(struct net_device *dev)
9284 {
9285         int i;
9286         struct tg3 *tp = netdev_priv(dev);
9287
9288         tg3_napi_disable(tp);
9289         cancel_work_sync(&tp->reset_task);
9290
9291         netif_tx_stop_all_queues(dev);
9292
9293         del_timer_sync(&tp->timer);
9294
9295         tg3_phy_stop(tp);
9296
9297         tg3_full_lock(tp, 1);
9298
9299         tg3_disable_ints(tp);
9300
9301         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9302         tg3_free_rings(tp);
9303         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9304
9305         tg3_full_unlock(tp);
9306
9307         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9308                 struct tg3_napi *tnapi = &tp->napi[i];
9309                 free_irq(tnapi->irq_vec, tnapi);
9310         }
9311
9312         tg3_ints_fini(tp);
9313
9314         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9315
9316         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9317                sizeof(tp->estats_prev));
9318
9319         tg3_napi_fini(tp);
9320
9321         tg3_free_consistent(tp);
9322
9323         tg3_power_down(tp);
9324
9325         netif_carrier_off(tp->dev);
9326
9327         return 0;
9328 }
9329
9330 static inline u64 get_stat64(tg3_stat64_t *val)
9331 {
9332        return ((u64)val->high << 32) | ((u64)val->low);
9333 }
9334
9335 static u64 calc_crc_errors(struct tg3 *tp)
9336 {
9337         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9338
9339         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9340             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9341              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9342                 u32 val;
9343
9344                 spin_lock_bh(&tp->lock);
9345                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9346                         tg3_writephy(tp, MII_TG3_TEST1,
9347                                      val | MII_TG3_TEST1_CRC_EN);
9348                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9349                 } else
9350                         val = 0;
9351                 spin_unlock_bh(&tp->lock);
9352
9353                 tp->phy_crc_errors += val;
9354
9355                 return tp->phy_crc_errors;
9356         }
9357
9358         return get_stat64(&hw_stats->rx_fcs_errors);
9359 }
9360
9361 #define ESTAT_ADD(member) \
9362         estats->member =        old_estats->member + \
9363                                 get_stat64(&hw_stats->member)
9364
9365 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9366 {
9367         struct tg3_ethtool_stats *estats = &tp->estats;
9368         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9369         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9370
9371         if (!hw_stats)
9372                 return old_estats;
9373
9374         ESTAT_ADD(rx_octets);
9375         ESTAT_ADD(rx_fragments);
9376         ESTAT_ADD(rx_ucast_packets);
9377         ESTAT_ADD(rx_mcast_packets);
9378         ESTAT_ADD(rx_bcast_packets);
9379         ESTAT_ADD(rx_fcs_errors);
9380         ESTAT_ADD(rx_align_errors);
9381         ESTAT_ADD(rx_xon_pause_rcvd);
9382         ESTAT_ADD(rx_xoff_pause_rcvd);
9383         ESTAT_ADD(rx_mac_ctrl_rcvd);
9384         ESTAT_ADD(rx_xoff_entered);
9385         ESTAT_ADD(rx_frame_too_long_errors);
9386         ESTAT_ADD(rx_jabbers);
9387         ESTAT_ADD(rx_undersize_packets);
9388         ESTAT_ADD(rx_in_length_errors);
9389         ESTAT_ADD(rx_out_length_errors);
9390         ESTAT_ADD(rx_64_or_less_octet_packets);
9391         ESTAT_ADD(rx_65_to_127_octet_packets);
9392         ESTAT_ADD(rx_128_to_255_octet_packets);
9393         ESTAT_ADD(rx_256_to_511_octet_packets);
9394         ESTAT_ADD(rx_512_to_1023_octet_packets);
9395         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9396         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9397         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9398         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9399         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9400
9401         ESTAT_ADD(tx_octets);
9402         ESTAT_ADD(tx_collisions);
9403         ESTAT_ADD(tx_xon_sent);
9404         ESTAT_ADD(tx_xoff_sent);
9405         ESTAT_ADD(tx_flow_control);
9406         ESTAT_ADD(tx_mac_errors);
9407         ESTAT_ADD(tx_single_collisions);
9408         ESTAT_ADD(tx_mult_collisions);
9409         ESTAT_ADD(tx_deferred);
9410         ESTAT_ADD(tx_excessive_collisions);
9411         ESTAT_ADD(tx_late_collisions);
9412         ESTAT_ADD(tx_collide_2times);
9413         ESTAT_ADD(tx_collide_3times);
9414         ESTAT_ADD(tx_collide_4times);
9415         ESTAT_ADD(tx_collide_5times);
9416         ESTAT_ADD(tx_collide_6times);
9417         ESTAT_ADD(tx_collide_7times);
9418         ESTAT_ADD(tx_collide_8times);
9419         ESTAT_ADD(tx_collide_9times);
9420         ESTAT_ADD(tx_collide_10times);
9421         ESTAT_ADD(tx_collide_11times);
9422         ESTAT_ADD(tx_collide_12times);
9423         ESTAT_ADD(tx_collide_13times);
9424         ESTAT_ADD(tx_collide_14times);
9425         ESTAT_ADD(tx_collide_15times);
9426         ESTAT_ADD(tx_ucast_packets);
9427         ESTAT_ADD(tx_mcast_packets);
9428         ESTAT_ADD(tx_bcast_packets);
9429         ESTAT_ADD(tx_carrier_sense_errors);
9430         ESTAT_ADD(tx_discards);
9431         ESTAT_ADD(tx_errors);
9432
9433         ESTAT_ADD(dma_writeq_full);
9434         ESTAT_ADD(dma_write_prioq_full);
9435         ESTAT_ADD(rxbds_empty);
9436         ESTAT_ADD(rx_discards);
9437         ESTAT_ADD(rx_errors);
9438         ESTAT_ADD(rx_threshold_hit);
9439
9440         ESTAT_ADD(dma_readq_full);
9441         ESTAT_ADD(dma_read_prioq_full);
9442         ESTAT_ADD(tx_comp_queue_full);
9443
9444         ESTAT_ADD(ring_set_send_prod_index);
9445         ESTAT_ADD(ring_status_update);
9446         ESTAT_ADD(nic_irqs);
9447         ESTAT_ADD(nic_avoided_irqs);
9448         ESTAT_ADD(nic_tx_threshold_hit);
9449
9450         return estats;
9451 }
9452
9453 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9454                                                  struct rtnl_link_stats64 *stats)
9455 {
9456         struct tg3 *tp = netdev_priv(dev);
9457         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9458         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9459
9460         if (!hw_stats)
9461                 return old_stats;
9462
9463         stats->rx_packets = old_stats->rx_packets +
9464                 get_stat64(&hw_stats->rx_ucast_packets) +
9465                 get_stat64(&hw_stats->rx_mcast_packets) +
9466                 get_stat64(&hw_stats->rx_bcast_packets);
9467
9468         stats->tx_packets = old_stats->tx_packets +
9469                 get_stat64(&hw_stats->tx_ucast_packets) +
9470                 get_stat64(&hw_stats->tx_mcast_packets) +
9471                 get_stat64(&hw_stats->tx_bcast_packets);
9472
9473         stats->rx_bytes = old_stats->rx_bytes +
9474                 get_stat64(&hw_stats->rx_octets);
9475         stats->tx_bytes = old_stats->tx_bytes +
9476                 get_stat64(&hw_stats->tx_octets);
9477
9478         stats->rx_errors = old_stats->rx_errors +
9479                 get_stat64(&hw_stats->rx_errors);
9480         stats->tx_errors = old_stats->tx_errors +
9481                 get_stat64(&hw_stats->tx_errors) +
9482                 get_stat64(&hw_stats->tx_mac_errors) +
9483                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9484                 get_stat64(&hw_stats->tx_discards);
9485
9486         stats->multicast = old_stats->multicast +
9487                 get_stat64(&hw_stats->rx_mcast_packets);
9488         stats->collisions = old_stats->collisions +
9489                 get_stat64(&hw_stats->tx_collisions);
9490
9491         stats->rx_length_errors = old_stats->rx_length_errors +
9492                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9493                 get_stat64(&hw_stats->rx_undersize_packets);
9494
9495         stats->rx_over_errors = old_stats->rx_over_errors +
9496                 get_stat64(&hw_stats->rxbds_empty);
9497         stats->rx_frame_errors = old_stats->rx_frame_errors +
9498                 get_stat64(&hw_stats->rx_align_errors);
9499         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9500                 get_stat64(&hw_stats->tx_discards);
9501         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9502                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9503
9504         stats->rx_crc_errors = old_stats->rx_crc_errors +
9505                 calc_crc_errors(tp);
9506
9507         stats->rx_missed_errors = old_stats->rx_missed_errors +
9508                 get_stat64(&hw_stats->rx_discards);
9509
9510         stats->rx_dropped = tp->rx_dropped;
9511
9512         return stats;
9513 }
9514
9515 static inline u32 calc_crc(unsigned char *buf, int len)
9516 {
9517         u32 reg;
9518         u32 tmp;
9519         int j, k;
9520
9521         reg = 0xffffffff;
9522
9523         for (j = 0; j < len; j++) {
9524                 reg ^= buf[j];
9525
9526                 for (k = 0; k < 8; k++) {
9527                         tmp = reg & 0x01;
9528
9529                         reg >>= 1;
9530
9531                         if (tmp)
9532                                 reg ^= 0xedb88320;
9533                 }
9534         }
9535
9536         return ~reg;
9537 }
9538
9539 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9540 {
9541         /* accept or reject all multicast frames */
9542         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9543         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9544         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9545         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9546 }
9547
9548 static void __tg3_set_rx_mode(struct net_device *dev)
9549 {
9550         struct tg3 *tp = netdev_priv(dev);
9551         u32 rx_mode;
9552
9553         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9554                                   RX_MODE_KEEP_VLAN_TAG);
9555
9556 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9557         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9558          * flag clear.
9559          */
9560         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9561                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9562 #endif
9563
9564         if (dev->flags & IFF_PROMISC) {
9565                 /* Promiscuous mode. */
9566                 rx_mode |= RX_MODE_PROMISC;
9567         } else if (dev->flags & IFF_ALLMULTI) {
9568                 /* Accept all multicast. */
9569                 tg3_set_multi(tp, 1);
9570         } else if (netdev_mc_empty(dev)) {
9571                 /* Reject all multicast. */
9572                 tg3_set_multi(tp, 0);
9573         } else {
9574                 /* Accept one or more multicast(s). */
9575                 struct netdev_hw_addr *ha;
9576                 u32 mc_filter[4] = { 0, };
9577                 u32 regidx;
9578                 u32 bit;
9579                 u32 crc;
9580
9581                 netdev_for_each_mc_addr(ha, dev) {
9582                         crc = calc_crc(ha->addr, ETH_ALEN);
9583                         bit = ~crc & 0x7f;
9584                         regidx = (bit & 0x60) >> 5;
9585                         bit &= 0x1f;
9586                         mc_filter[regidx] |= (1 << bit);
9587                 }
9588
9589                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9590                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9591                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9592                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9593         }
9594
9595         if (rx_mode != tp->rx_mode) {
9596                 tp->rx_mode = rx_mode;
9597                 tw32_f(MAC_RX_MODE, rx_mode);
9598                 udelay(10);
9599         }
9600 }
9601
9602 static void tg3_set_rx_mode(struct net_device *dev)
9603 {
9604         struct tg3 *tp = netdev_priv(dev);
9605
9606         if (!netif_running(dev))
9607                 return;
9608
9609         tg3_full_lock(tp, 0);
9610         __tg3_set_rx_mode(dev);
9611         tg3_full_unlock(tp);
9612 }
9613
9614 #define TG3_REGDUMP_LEN         (32 * 1024)
9615
9616 static int tg3_get_regs_len(struct net_device *dev)
9617 {
9618         return TG3_REGDUMP_LEN;
9619 }
9620
9621 static void tg3_get_regs(struct net_device *dev,
9622                 struct ethtool_regs *regs, void *_p)
9623 {
9624         u32 *p = _p;
9625         struct tg3 *tp = netdev_priv(dev);
9626         u8 *orig_p = _p;
9627         int i;
9628
9629         regs->version = 0;
9630
9631         memset(p, 0, TG3_REGDUMP_LEN);
9632
9633         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9634                 return;
9635
9636         tg3_full_lock(tp, 0);
9637
9638 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9639 #define GET_REG32_LOOP(base, len)               \
9640 do {    p = (u32 *)(orig_p + (base));           \
9641         for (i = 0; i < len; i += 4)            \
9642                 __GET_REG32((base) + i);        \
9643 } while (0)
9644 #define GET_REG32_1(reg)                        \
9645 do {    p = (u32 *)(orig_p + (reg));            \
9646         __GET_REG32((reg));                     \
9647 } while (0)
9648
9649         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9650         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9651         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9652         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9653         GET_REG32_1(SNDDATAC_MODE);
9654         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9655         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9656         GET_REG32_1(SNDBDC_MODE);
9657         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9658         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9659         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9660         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9661         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9662         GET_REG32_1(RCVDCC_MODE);
9663         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9664         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9665         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9666         GET_REG32_1(MBFREE_MODE);
9667         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9668         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9669         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9670         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9671         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9672         GET_REG32_1(RX_CPU_MODE);
9673         GET_REG32_1(RX_CPU_STATE);
9674         GET_REG32_1(RX_CPU_PGMCTR);
9675         GET_REG32_1(RX_CPU_HWBKPT);
9676         GET_REG32_1(TX_CPU_MODE);
9677         GET_REG32_1(TX_CPU_STATE);
9678         GET_REG32_1(TX_CPU_PGMCTR);
9679         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9680         GET_REG32_LOOP(FTQ_RESET, 0x120);
9681         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9682         GET_REG32_1(DMAC_MODE);
9683         GET_REG32_LOOP(GRC_MODE, 0x4c);
9684         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9685                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9686
9687 #undef __GET_REG32
9688 #undef GET_REG32_LOOP
9689 #undef GET_REG32_1
9690
9691         tg3_full_unlock(tp);
9692 }
9693
9694 static int tg3_get_eeprom_len(struct net_device *dev)
9695 {
9696         struct tg3 *tp = netdev_priv(dev);
9697
9698         return tp->nvram_size;
9699 }
9700
9701 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9702 {
9703         struct tg3 *tp = netdev_priv(dev);
9704         int ret;
9705         u8  *pd;
9706         u32 i, offset, len, b_offset, b_count;
9707         __be32 val;
9708
9709         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9710                 return -EINVAL;
9711
9712         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9713                 return -EAGAIN;
9714
9715         offset = eeprom->offset;
9716         len = eeprom->len;
9717         eeprom->len = 0;
9718
9719         eeprom->magic = TG3_EEPROM_MAGIC;
9720
9721         if (offset & 3) {
9722                 /* adjustments to start on required 4 byte boundary */
9723                 b_offset = offset & 3;
9724                 b_count = 4 - b_offset;
9725                 if (b_count > len) {
9726                         /* i.e. offset=1 len=2 */
9727                         b_count = len;
9728                 }
9729                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9730                 if (ret)
9731                         return ret;
9732                 memcpy(data, ((char *)&val) + b_offset, b_count);
9733                 len -= b_count;
9734                 offset += b_count;
9735                 eeprom->len += b_count;
9736         }
9737
9738         /* read bytes upto the last 4 byte boundary */
9739         pd = &data[eeprom->len];
9740         for (i = 0; i < (len - (len & 3)); i += 4) {
9741                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9742                 if (ret) {
9743                         eeprom->len += i;
9744                         return ret;
9745                 }
9746                 memcpy(pd + i, &val, 4);
9747         }
9748         eeprom->len += i;
9749
9750         if (len & 3) {
9751                 /* read last bytes not ending on 4 byte boundary */
9752                 pd = &data[eeprom->len];
9753                 b_count = len & 3;
9754                 b_offset = offset + len - b_count;
9755                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9756                 if (ret)
9757                         return ret;
9758                 memcpy(pd, &val, b_count);
9759                 eeprom->len += b_count;
9760         }
9761         return 0;
9762 }
9763
9764 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9765
9766 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9767 {
9768         struct tg3 *tp = netdev_priv(dev);
9769         int ret;
9770         u32 offset, len, b_offset, odd_len;
9771         u8 *buf;
9772         __be32 start, end;
9773
9774         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9775                 return -EAGAIN;
9776
9777         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9778             eeprom->magic != TG3_EEPROM_MAGIC)
9779                 return -EINVAL;
9780
9781         offset = eeprom->offset;
9782         len = eeprom->len;
9783
9784         if ((b_offset = (offset & 3))) {
9785                 /* adjustments to start on required 4 byte boundary */
9786                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9787                 if (ret)
9788                         return ret;
9789                 len += b_offset;
9790                 offset &= ~3;
9791                 if (len < 4)
9792                         len = 4;
9793         }
9794
9795         odd_len = 0;
9796         if (len & 3) {
9797                 /* adjustments to end on required 4 byte boundary */
9798                 odd_len = 1;
9799                 len = (len + 3) & ~3;
9800                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9801                 if (ret)
9802                         return ret;
9803         }
9804
9805         buf = data;
9806         if (b_offset || odd_len) {
9807                 buf = kmalloc(len, GFP_KERNEL);
9808                 if (!buf)
9809                         return -ENOMEM;
9810                 if (b_offset)
9811                         memcpy(buf, &start, 4);
9812                 if (odd_len)
9813                         memcpy(buf+len-4, &end, 4);
9814                 memcpy(buf + b_offset, data, eeprom->len);
9815         }
9816
9817         ret = tg3_nvram_write_block(tp, offset, len, buf);
9818
9819         if (buf != data)
9820                 kfree(buf);
9821
9822         return ret;
9823 }
9824
9825 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9826 {
9827         struct tg3 *tp = netdev_priv(dev);
9828
9829         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9830                 struct phy_device *phydev;
9831                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9832                         return -EAGAIN;
9833                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9834                 return phy_ethtool_gset(phydev, cmd);
9835         }
9836
9837         cmd->supported = (SUPPORTED_Autoneg);
9838
9839         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9840                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9841                                    SUPPORTED_1000baseT_Full);
9842
9843         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9844                 cmd->supported |= (SUPPORTED_100baseT_Half |
9845                                   SUPPORTED_100baseT_Full |
9846                                   SUPPORTED_10baseT_Half |
9847                                   SUPPORTED_10baseT_Full |
9848                                   SUPPORTED_TP);
9849                 cmd->port = PORT_TP;
9850         } else {
9851                 cmd->supported |= SUPPORTED_FIBRE;
9852                 cmd->port = PORT_FIBRE;
9853         }
9854
9855         cmd->advertising = tp->link_config.advertising;
9856         if (netif_running(dev)) {
9857                 cmd->speed = tp->link_config.active_speed;
9858                 cmd->duplex = tp->link_config.active_duplex;
9859         } else {
9860                 cmd->speed = SPEED_INVALID;
9861                 cmd->duplex = DUPLEX_INVALID;
9862         }
9863         cmd->phy_address = tp->phy_addr;
9864         cmd->transceiver = XCVR_INTERNAL;
9865         cmd->autoneg = tp->link_config.autoneg;
9866         cmd->maxtxpkt = 0;
9867         cmd->maxrxpkt = 0;
9868         return 0;
9869 }
9870
9871 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9872 {
9873         struct tg3 *tp = netdev_priv(dev);
9874
9875         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9876                 struct phy_device *phydev;
9877                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9878                         return -EAGAIN;
9879                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9880                 return phy_ethtool_sset(phydev, cmd);
9881         }
9882
9883         if (cmd->autoneg != AUTONEG_ENABLE &&
9884             cmd->autoneg != AUTONEG_DISABLE)
9885                 return -EINVAL;
9886
9887         if (cmd->autoneg == AUTONEG_DISABLE &&
9888             cmd->duplex != DUPLEX_FULL &&
9889             cmd->duplex != DUPLEX_HALF)
9890                 return -EINVAL;
9891
9892         if (cmd->autoneg == AUTONEG_ENABLE) {
9893                 u32 mask = ADVERTISED_Autoneg |
9894                            ADVERTISED_Pause |
9895                            ADVERTISED_Asym_Pause;
9896
9897                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9898                         mask |= ADVERTISED_1000baseT_Half |
9899                                 ADVERTISED_1000baseT_Full;
9900
9901                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9902                         mask |= ADVERTISED_100baseT_Half |
9903                                 ADVERTISED_100baseT_Full |
9904                                 ADVERTISED_10baseT_Half |
9905                                 ADVERTISED_10baseT_Full |
9906                                 ADVERTISED_TP;
9907                 else
9908                         mask |= ADVERTISED_FIBRE;
9909
9910                 if (cmd->advertising & ~mask)
9911                         return -EINVAL;
9912
9913                 mask &= (ADVERTISED_1000baseT_Half |
9914                          ADVERTISED_1000baseT_Full |
9915                          ADVERTISED_100baseT_Half |
9916                          ADVERTISED_100baseT_Full |
9917                          ADVERTISED_10baseT_Half |
9918                          ADVERTISED_10baseT_Full);
9919
9920                 cmd->advertising &= mask;
9921         } else {
9922                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9923                         if (cmd->speed != SPEED_1000)
9924                                 return -EINVAL;
9925
9926                         if (cmd->duplex != DUPLEX_FULL)
9927                                 return -EINVAL;
9928                 } else {
9929                         if (cmd->speed != SPEED_100 &&
9930                             cmd->speed != SPEED_10)
9931                                 return -EINVAL;
9932                 }
9933         }
9934
9935         tg3_full_lock(tp, 0);
9936
9937         tp->link_config.autoneg = cmd->autoneg;
9938         if (cmd->autoneg == AUTONEG_ENABLE) {
9939                 tp->link_config.advertising = (cmd->advertising |
9940                                               ADVERTISED_Autoneg);
9941                 tp->link_config.speed = SPEED_INVALID;
9942                 tp->link_config.duplex = DUPLEX_INVALID;
9943         } else {
9944                 tp->link_config.advertising = 0;
9945                 tp->link_config.speed = cmd->speed;
9946                 tp->link_config.duplex = cmd->duplex;
9947         }
9948
9949         tp->link_config.orig_speed = tp->link_config.speed;
9950         tp->link_config.orig_duplex = tp->link_config.duplex;
9951         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9952
9953         if (netif_running(dev))
9954                 tg3_setup_phy(tp, 1);
9955
9956         tg3_full_unlock(tp);
9957
9958         return 0;
9959 }
9960
9961 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9962 {
9963         struct tg3 *tp = netdev_priv(dev);
9964
9965         strcpy(info->driver, DRV_MODULE_NAME);
9966         strcpy(info->version, DRV_MODULE_VERSION);
9967         strcpy(info->fw_version, tp->fw_ver);
9968         strcpy(info->bus_info, pci_name(tp->pdev));
9969 }
9970
9971 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9972 {
9973         struct tg3 *tp = netdev_priv(dev);
9974
9975         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9976             device_can_wakeup(&tp->pdev->dev))
9977                 wol->supported = WAKE_MAGIC;
9978         else
9979                 wol->supported = 0;
9980         wol->wolopts = 0;
9981         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9982             device_can_wakeup(&tp->pdev->dev))
9983                 wol->wolopts = WAKE_MAGIC;
9984         memset(&wol->sopass, 0, sizeof(wol->sopass));
9985 }
9986
9987 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9988 {
9989         struct tg3 *tp = netdev_priv(dev);
9990         struct device *dp = &tp->pdev->dev;
9991
9992         if (wol->wolopts & ~WAKE_MAGIC)
9993                 return -EINVAL;
9994         if ((wol->wolopts & WAKE_MAGIC) &&
9995             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9996                 return -EINVAL;
9997
9998         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9999
10000         spin_lock_bh(&tp->lock);
10001         if (device_may_wakeup(dp))
10002                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10003         else
10004                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10005         spin_unlock_bh(&tp->lock);
10006
10007
10008         return 0;
10009 }
10010
10011 static u32 tg3_get_msglevel(struct net_device *dev)
10012 {
10013         struct tg3 *tp = netdev_priv(dev);
10014         return tp->msg_enable;
10015 }
10016
10017 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10018 {
10019         struct tg3 *tp = netdev_priv(dev);
10020         tp->msg_enable = value;
10021 }
10022
10023 static int tg3_set_tso(struct net_device *dev, u32 value)
10024 {
10025         struct tg3 *tp = netdev_priv(dev);
10026
10027         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
10028                 if (value)
10029                         return -EINVAL;
10030                 return 0;
10031         }
10032         if ((dev->features & NETIF_F_IPV6_CSUM) &&
10033             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
10034              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
10035                 if (value) {
10036                         dev->features |= NETIF_F_TSO6;
10037                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
10038                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10039                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
10040                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10041                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10042                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10043                                 dev->features |= NETIF_F_TSO_ECN;
10044                 } else
10045                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10046         }
10047         return ethtool_op_set_tso(dev, value);
10048 }
10049
10050 static int tg3_nway_reset(struct net_device *dev)
10051 {
10052         struct tg3 *tp = netdev_priv(dev);
10053         int r;
10054
10055         if (!netif_running(dev))
10056                 return -EAGAIN;
10057
10058         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10059                 return -EINVAL;
10060
10061         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10062                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10063                         return -EAGAIN;
10064                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10065         } else {
10066                 u32 bmcr;
10067
10068                 spin_lock_bh(&tp->lock);
10069                 r = -EINVAL;
10070                 tg3_readphy(tp, MII_BMCR, &bmcr);
10071                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10072                     ((bmcr & BMCR_ANENABLE) ||
10073                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10074                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10075                                                    BMCR_ANENABLE);
10076                         r = 0;
10077                 }
10078                 spin_unlock_bh(&tp->lock);
10079         }
10080
10081         return r;
10082 }
10083
10084 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10085 {
10086         struct tg3 *tp = netdev_priv(dev);
10087
10088         ering->rx_max_pending = tp->rx_std_ring_mask;
10089         ering->rx_mini_max_pending = 0;
10090         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10091                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10092         else
10093                 ering->rx_jumbo_max_pending = 0;
10094
10095         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10096
10097         ering->rx_pending = tp->rx_pending;
10098         ering->rx_mini_pending = 0;
10099         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10100                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10101         else
10102                 ering->rx_jumbo_pending = 0;
10103
10104         ering->tx_pending = tp->napi[0].tx_pending;
10105 }
10106
10107 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10108 {
10109         struct tg3 *tp = netdev_priv(dev);
10110         int i, irq_sync = 0, err = 0;
10111
10112         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10113             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10114             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10115             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10116             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10117              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10118                 return -EINVAL;
10119
10120         if (netif_running(dev)) {
10121                 tg3_phy_stop(tp);
10122                 tg3_netif_stop(tp);
10123                 irq_sync = 1;
10124         }
10125
10126         tg3_full_lock(tp, irq_sync);
10127
10128         tp->rx_pending = ering->rx_pending;
10129
10130         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10131             tp->rx_pending > 63)
10132                 tp->rx_pending = 63;
10133         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10134
10135         for (i = 0; i < tp->irq_max; i++)
10136                 tp->napi[i].tx_pending = ering->tx_pending;
10137
10138         if (netif_running(dev)) {
10139                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10140                 err = tg3_restart_hw(tp, 1);
10141                 if (!err)
10142                         tg3_netif_start(tp);
10143         }
10144
10145         tg3_full_unlock(tp);
10146
10147         if (irq_sync && !err)
10148                 tg3_phy_start(tp);
10149
10150         return err;
10151 }
10152
10153 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10154 {
10155         struct tg3 *tp = netdev_priv(dev);
10156
10157         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10158
10159         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10160                 epause->rx_pause = 1;
10161         else
10162                 epause->rx_pause = 0;
10163
10164         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10165                 epause->tx_pause = 1;
10166         else
10167                 epause->tx_pause = 0;
10168 }
10169
10170 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10171 {
10172         struct tg3 *tp = netdev_priv(dev);
10173         int err = 0;
10174
10175         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10176                 u32 newadv;
10177                 struct phy_device *phydev;
10178
10179                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10180
10181                 if (!(phydev->supported & SUPPORTED_Pause) ||
10182                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10183                      (epause->rx_pause != epause->tx_pause)))
10184                         return -EINVAL;
10185
10186                 tp->link_config.flowctrl = 0;
10187                 if (epause->rx_pause) {
10188                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10189
10190                         if (epause->tx_pause) {
10191                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10192                                 newadv = ADVERTISED_Pause;
10193                         } else
10194                                 newadv = ADVERTISED_Pause |
10195                                          ADVERTISED_Asym_Pause;
10196                 } else if (epause->tx_pause) {
10197                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10198                         newadv = ADVERTISED_Asym_Pause;
10199                 } else
10200                         newadv = 0;
10201
10202                 if (epause->autoneg)
10203                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10204                 else
10205                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10206
10207                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10208                         u32 oldadv = phydev->advertising &
10209                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10210                         if (oldadv != newadv) {
10211                                 phydev->advertising &=
10212                                         ~(ADVERTISED_Pause |
10213                                           ADVERTISED_Asym_Pause);
10214                                 phydev->advertising |= newadv;
10215                                 if (phydev->autoneg) {
10216                                         /*
10217                                          * Always renegotiate the link to
10218                                          * inform our link partner of our
10219                                          * flow control settings, even if the
10220                                          * flow control is forced.  Let
10221                                          * tg3_adjust_link() do the final
10222                                          * flow control setup.
10223                                          */
10224                                         return phy_start_aneg(phydev);
10225                                 }
10226                         }
10227
10228                         if (!epause->autoneg)
10229                                 tg3_setup_flow_control(tp, 0, 0);
10230                 } else {
10231                         tp->link_config.orig_advertising &=
10232                                         ~(ADVERTISED_Pause |
10233                                           ADVERTISED_Asym_Pause);
10234                         tp->link_config.orig_advertising |= newadv;
10235                 }
10236         } else {
10237                 int irq_sync = 0;
10238
10239                 if (netif_running(dev)) {
10240                         tg3_netif_stop(tp);
10241                         irq_sync = 1;
10242                 }
10243
10244                 tg3_full_lock(tp, irq_sync);
10245
10246                 if (epause->autoneg)
10247                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10248                 else
10249                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10250                 if (epause->rx_pause)
10251                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10252                 else
10253                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10254                 if (epause->tx_pause)
10255                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10256                 else
10257                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10258
10259                 if (netif_running(dev)) {
10260                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10261                         err = tg3_restart_hw(tp, 1);
10262                         if (!err)
10263                                 tg3_netif_start(tp);
10264                 }
10265
10266                 tg3_full_unlock(tp);
10267         }
10268
10269         return err;
10270 }
10271
10272 static u32 tg3_get_rx_csum(struct net_device *dev)
10273 {
10274         struct tg3 *tp = netdev_priv(dev);
10275         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10276 }
10277
10278 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10279 {
10280         struct tg3 *tp = netdev_priv(dev);
10281
10282         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10283                 if (data != 0)
10284                         return -EINVAL;
10285                 return 0;
10286         }
10287
10288         spin_lock_bh(&tp->lock);
10289         if (data)
10290                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10291         else
10292                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10293         spin_unlock_bh(&tp->lock);
10294
10295         return 0;
10296 }
10297
10298 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10299 {
10300         struct tg3 *tp = netdev_priv(dev);
10301
10302         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10303                 if (data != 0)
10304                         return -EINVAL;
10305                 return 0;
10306         }
10307
10308         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10309                 ethtool_op_set_tx_ipv6_csum(dev, data);
10310         else
10311                 ethtool_op_set_tx_csum(dev, data);
10312
10313         return 0;
10314 }
10315
10316 static int tg3_get_sset_count(struct net_device *dev, int sset)
10317 {
10318         switch (sset) {
10319         case ETH_SS_TEST:
10320                 return TG3_NUM_TEST;
10321         case ETH_SS_STATS:
10322                 return TG3_NUM_STATS;
10323         default:
10324                 return -EOPNOTSUPP;
10325         }
10326 }
10327
10328 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10329 {
10330         switch (stringset) {
10331         case ETH_SS_STATS:
10332                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10333                 break;
10334         case ETH_SS_TEST:
10335                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10336                 break;
10337         default:
10338                 WARN_ON(1);     /* we need a WARN() */
10339                 break;
10340         }
10341 }
10342
10343 static int tg3_phys_id(struct net_device *dev, u32 data)
10344 {
10345         struct tg3 *tp = netdev_priv(dev);
10346         int i;
10347
10348         if (!netif_running(tp->dev))
10349                 return -EAGAIN;
10350
10351         if (data == 0)
10352                 data = UINT_MAX / 2;
10353
10354         for (i = 0; i < (data * 2); i++) {
10355                 if ((i % 2) == 0)
10356                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10357                                            LED_CTRL_1000MBPS_ON |
10358                                            LED_CTRL_100MBPS_ON |
10359                                            LED_CTRL_10MBPS_ON |
10360                                            LED_CTRL_TRAFFIC_OVERRIDE |
10361                                            LED_CTRL_TRAFFIC_BLINK |
10362                                            LED_CTRL_TRAFFIC_LED);
10363
10364                 else
10365                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10366                                            LED_CTRL_TRAFFIC_OVERRIDE);
10367
10368                 if (msleep_interruptible(500))
10369                         break;
10370         }
10371         tw32(MAC_LED_CTRL, tp->led_ctrl);
10372         return 0;
10373 }
10374
10375 static void tg3_get_ethtool_stats(struct net_device *dev,
10376                                    struct ethtool_stats *estats, u64 *tmp_stats)
10377 {
10378         struct tg3 *tp = netdev_priv(dev);
10379         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10380 }
10381
10382 #define NVRAM_TEST_SIZE 0x100
10383 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10384 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10385 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10386 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10387 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10388
10389 static int tg3_test_nvram(struct tg3 *tp)
10390 {
10391         u32 csum, magic;
10392         __be32 *buf;
10393         int i, j, k, err = 0, size;
10394
10395         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10396                 return 0;
10397
10398         if (tg3_nvram_read(tp, 0, &magic) != 0)
10399                 return -EIO;
10400
10401         if (magic == TG3_EEPROM_MAGIC)
10402                 size = NVRAM_TEST_SIZE;
10403         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10404                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10405                     TG3_EEPROM_SB_FORMAT_1) {
10406                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10407                         case TG3_EEPROM_SB_REVISION_0:
10408                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10409                                 break;
10410                         case TG3_EEPROM_SB_REVISION_2:
10411                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10412                                 break;
10413                         case TG3_EEPROM_SB_REVISION_3:
10414                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10415                                 break;
10416                         default:
10417                                 return 0;
10418                         }
10419                 } else
10420                         return 0;
10421         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10422                 size = NVRAM_SELFBOOT_HW_SIZE;
10423         else
10424                 return -EIO;
10425
10426         buf = kmalloc(size, GFP_KERNEL);
10427         if (buf == NULL)
10428                 return -ENOMEM;
10429
10430         err = -EIO;
10431         for (i = 0, j = 0; i < size; i += 4, j++) {
10432                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10433                 if (err)
10434                         break;
10435         }
10436         if (i < size)
10437                 goto out;
10438
10439         /* Selfboot format */
10440         magic = be32_to_cpu(buf[0]);
10441         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10442             TG3_EEPROM_MAGIC_FW) {
10443                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10444
10445                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10446                     TG3_EEPROM_SB_REVISION_2) {
10447                         /* For rev 2, the csum doesn't include the MBA. */
10448                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10449                                 csum8 += buf8[i];
10450                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10451                                 csum8 += buf8[i];
10452                 } else {
10453                         for (i = 0; i < size; i++)
10454                                 csum8 += buf8[i];
10455                 }
10456
10457                 if (csum8 == 0) {
10458                         err = 0;
10459                         goto out;
10460                 }
10461
10462                 err = -EIO;
10463                 goto out;
10464         }
10465
10466         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10467             TG3_EEPROM_MAGIC_HW) {
10468                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10469                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10470                 u8 *buf8 = (u8 *) buf;
10471
10472                 /* Separate the parity bits and the data bytes.  */
10473                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10474                         if ((i == 0) || (i == 8)) {
10475                                 int l;
10476                                 u8 msk;
10477
10478                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10479                                         parity[k++] = buf8[i] & msk;
10480                                 i++;
10481                         } else if (i == 16) {
10482                                 int l;
10483                                 u8 msk;
10484
10485                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10486                                         parity[k++] = buf8[i] & msk;
10487                                 i++;
10488
10489                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10490                                         parity[k++] = buf8[i] & msk;
10491                                 i++;
10492                         }
10493                         data[j++] = buf8[i];
10494                 }
10495
10496                 err = -EIO;
10497                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10498                         u8 hw8 = hweight8(data[i]);
10499
10500                         if ((hw8 & 0x1) && parity[i])
10501                                 goto out;
10502                         else if (!(hw8 & 0x1) && !parity[i])
10503                                 goto out;
10504                 }
10505                 err = 0;
10506                 goto out;
10507         }
10508
10509         err = -EIO;
10510
10511         /* Bootstrap checksum at offset 0x10 */
10512         csum = calc_crc((unsigned char *) buf, 0x10);
10513         if (csum != le32_to_cpu(buf[0x10/4]))
10514                 goto out;
10515
10516         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10517         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10518         if (csum != le32_to_cpu(buf[0xfc/4]))
10519                 goto out;
10520
10521         for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
10522                 /* The data is in little-endian format in NVRAM.
10523                  * Use the big-endian read routines to preserve
10524                  * the byte order as it exists in NVRAM.
10525                  */
10526                 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
10527                         goto out;
10528         }
10529
10530         i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10531                              PCI_VPD_LRDT_RO_DATA);
10532         if (i > 0) {
10533                 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10534                 if (j < 0)
10535                         goto out;
10536
10537                 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10538                         goto out;
10539
10540                 i += PCI_VPD_LRDT_TAG_SIZE;
10541                 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10542                                               PCI_VPD_RO_KEYWORD_CHKSUM);
10543                 if (j > 0) {
10544                         u8 csum8 = 0;
10545
10546                         j += PCI_VPD_INFO_FLD_HDR_SIZE;
10547
10548                         for (i = 0; i <= j; i++)
10549                                 csum8 += ((u8 *)buf)[i];
10550
10551                         if (csum8)
10552                                 goto out;
10553                 }
10554         }
10555
10556         err = 0;
10557
10558 out:
10559         kfree(buf);
10560         return err;
10561 }
10562
10563 #define TG3_SERDES_TIMEOUT_SEC  2
10564 #define TG3_COPPER_TIMEOUT_SEC  6
10565
10566 static int tg3_test_link(struct tg3 *tp)
10567 {
10568         int i, max;
10569
10570         if (!netif_running(tp->dev))
10571                 return -ENODEV;
10572
10573         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10574                 max = TG3_SERDES_TIMEOUT_SEC;
10575         else
10576                 max = TG3_COPPER_TIMEOUT_SEC;
10577
10578         for (i = 0; i < max; i++) {
10579                 if (netif_carrier_ok(tp->dev))
10580                         return 0;
10581
10582                 if (msleep_interruptible(1000))
10583                         break;
10584         }
10585
10586         return -EIO;
10587 }
10588
10589 /* Only test the commonly used registers */
10590 static int tg3_test_registers(struct tg3 *tp)
10591 {
10592         int i, is_5705, is_5750;
10593         u32 offset, read_mask, write_mask, val, save_val, read_val;
10594         static struct {
10595                 u16 offset;
10596                 u16 flags;
10597 #define TG3_FL_5705     0x1
10598 #define TG3_FL_NOT_5705 0x2
10599 #define TG3_FL_NOT_5788 0x4
10600 #define TG3_FL_NOT_5750 0x8
10601                 u32 read_mask;
10602                 u32 write_mask;
10603         } reg_tbl[] = {
10604                 /* MAC Control Registers */
10605                 { MAC_MODE, TG3_FL_NOT_5705,
10606                         0x00000000, 0x00ef6f8c },
10607                 { MAC_MODE, TG3_FL_5705,
10608                         0x00000000, 0x01ef6b8c },
10609                 { MAC_STATUS, TG3_FL_NOT_5705,
10610                         0x03800107, 0x00000000 },
10611                 { MAC_STATUS, TG3_FL_5705,
10612                         0x03800100, 0x00000000 },
10613                 { MAC_ADDR_0_HIGH, 0x0000,
10614                         0x00000000, 0x0000ffff },
10615                 { MAC_ADDR_0_LOW, 0x0000,
10616                         0x00000000, 0xffffffff },
10617                 { MAC_RX_MTU_SIZE, 0x0000,
10618                         0x00000000, 0x0000ffff },
10619                 { MAC_TX_MODE, 0x0000,
10620                         0x00000000, 0x00000070 },
10621                 { MAC_TX_LENGTHS, 0x0000,
10622                         0x00000000, 0x00003fff },
10623                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10624                         0x00000000, 0x000007fc },
10625                 { MAC_RX_MODE, TG3_FL_5705,
10626                         0x00000000, 0x000007dc },
10627                 { MAC_HASH_REG_0, 0x0000,
10628                         0x00000000, 0xffffffff },
10629                 { MAC_HASH_REG_1, 0x0000,
10630                         0x00000000, 0xffffffff },
10631                 { MAC_HASH_REG_2, 0x0000,
10632                         0x00000000, 0xffffffff },
10633                 { MAC_HASH_REG_3, 0x0000,
10634                         0x00000000, 0xffffffff },
10635
10636                 /* Receive Data and Receive BD Initiator Control Registers. */
10637                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10638                         0x00000000, 0xffffffff },
10639                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10640                         0x00000000, 0xffffffff },
10641                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10642                         0x00000000, 0x00000003 },
10643                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10644                         0x00000000, 0xffffffff },
10645                 { RCVDBDI_STD_BD+0, 0x0000,
10646                         0x00000000, 0xffffffff },
10647                 { RCVDBDI_STD_BD+4, 0x0000,
10648                         0x00000000, 0xffffffff },
10649                 { RCVDBDI_STD_BD+8, 0x0000,
10650                         0x00000000, 0xffff0002 },
10651                 { RCVDBDI_STD_BD+0xc, 0x0000,
10652                         0x00000000, 0xffffffff },
10653
10654                 /* Receive BD Initiator Control Registers. */
10655                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10656                         0x00000000, 0xffffffff },
10657                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10658                         0x00000000, 0x000003ff },
10659                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10660                         0x00000000, 0xffffffff },
10661
10662                 /* Host Coalescing Control Registers. */
10663                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10664                         0x00000000, 0x00000004 },
10665                 { HOSTCC_MODE, TG3_FL_5705,
10666                         0x00000000, 0x000000f6 },
10667                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10668                         0x00000000, 0xffffffff },
10669                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10670                         0x00000000, 0x000003ff },
10671                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10672                         0x00000000, 0xffffffff },
10673                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10674                         0x00000000, 0x000003ff },
10675                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10676                         0x00000000, 0xffffffff },
10677                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10678                         0x00000000, 0x000000ff },
10679                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10680                         0x00000000, 0xffffffff },
10681                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10682                         0x00000000, 0x000000ff },
10683                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10684                         0x00000000, 0xffffffff },
10685                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10686                         0x00000000, 0xffffffff },
10687                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10688                         0x00000000, 0xffffffff },
10689                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10690                         0x00000000, 0x000000ff },
10691                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10692                         0x00000000, 0xffffffff },
10693                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10694                         0x00000000, 0x000000ff },
10695                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10696                         0x00000000, 0xffffffff },
10697                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10698                         0x00000000, 0xffffffff },
10699                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10700                         0x00000000, 0xffffffff },
10701                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10702                         0x00000000, 0xffffffff },
10703                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10704                         0x00000000, 0xffffffff },
10705                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10706                         0xffffffff, 0x00000000 },
10707                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10708                         0xffffffff, 0x00000000 },
10709
10710                 /* Buffer Manager Control Registers. */
10711                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10712                         0x00000000, 0x007fff80 },
10713                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10714                         0x00000000, 0x007fffff },
10715                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10716                         0x00000000, 0x0000003f },
10717                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10718                         0x00000000, 0x000001ff },
10719                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10720                         0x00000000, 0x000001ff },
10721                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10722                         0xffffffff, 0x00000000 },
10723                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10724                         0xffffffff, 0x00000000 },
10725
10726                 /* Mailbox Registers */
10727                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10728                         0x00000000, 0x000001ff },
10729                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10730                         0x00000000, 0x000001ff },
10731                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10732                         0x00000000, 0x000007ff },
10733                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10734                         0x00000000, 0x000001ff },
10735
10736                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10737         };
10738
10739         is_5705 = is_5750 = 0;
10740         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10741                 is_5705 = 1;
10742                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10743                         is_5750 = 1;
10744         }
10745
10746         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10747                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10748                         continue;
10749
10750                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10751                         continue;
10752
10753                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10754                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10755                         continue;
10756
10757                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10758                         continue;
10759
10760                 offset = (u32) reg_tbl[i].offset;
10761                 read_mask = reg_tbl[i].read_mask;
10762                 write_mask = reg_tbl[i].write_mask;
10763
10764                 /* Save the original register content */
10765                 save_val = tr32(offset);
10766
10767                 /* Determine the read-only value. */
10768                 read_val = save_val & read_mask;
10769
10770                 /* Write zero to the register, then make sure the read-only bits
10771                  * are not changed and the read/write bits are all zeros.
10772                  */
10773                 tw32(offset, 0);
10774
10775                 val = tr32(offset);
10776
10777                 /* Test the read-only and read/write bits. */
10778                 if (((val & read_mask) != read_val) || (val & write_mask))
10779                         goto out;
10780
10781                 /* Write ones to all the bits defined by RdMask and WrMask, then
10782                  * make sure the read-only bits are not changed and the
10783                  * read/write bits are all ones.
10784                  */
10785                 tw32(offset, read_mask | write_mask);
10786
10787                 val = tr32(offset);
10788
10789                 /* Test the read-only bits. */
10790                 if ((val & read_mask) != read_val)
10791                         goto out;
10792
10793                 /* Test the read/write bits. */
10794                 if ((val & write_mask) != write_mask)
10795                         goto out;
10796
10797                 tw32(offset, save_val);
10798         }
10799
10800         return 0;
10801
10802 out:
10803         if (netif_msg_hw(tp))
10804                 netdev_err(tp->dev,
10805                            "Register test failed at offset %x\n", offset);
10806         tw32(offset, save_val);
10807         return -EIO;
10808 }
10809
10810 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10811 {
10812         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10813         int i;
10814         u32 j;
10815
10816         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10817                 for (j = 0; j < len; j += 4) {
10818                         u32 val;
10819
10820                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10821                         tg3_read_mem(tp, offset + j, &val);
10822                         if (val != test_pattern[i])
10823                                 return -EIO;
10824                 }
10825         }
10826         return 0;
10827 }
10828
10829 static int tg3_test_memory(struct tg3 *tp)
10830 {
10831         static struct mem_entry {
10832                 u32 offset;
10833                 u32 len;
10834         } mem_tbl_570x[] = {
10835                 { 0x00000000, 0x00b50},
10836                 { 0x00002000, 0x1c000},
10837                 { 0xffffffff, 0x00000}
10838         }, mem_tbl_5705[] = {
10839                 { 0x00000100, 0x0000c},
10840                 { 0x00000200, 0x00008},
10841                 { 0x00004000, 0x00800},
10842                 { 0x00006000, 0x01000},
10843                 { 0x00008000, 0x02000},
10844                 { 0x00010000, 0x0e000},
10845                 { 0xffffffff, 0x00000}
10846         }, mem_tbl_5755[] = {
10847                 { 0x00000200, 0x00008},
10848                 { 0x00004000, 0x00800},
10849                 { 0x00006000, 0x00800},
10850                 { 0x00008000, 0x02000},
10851                 { 0x00010000, 0x0c000},
10852                 { 0xffffffff, 0x00000}
10853         }, mem_tbl_5906[] = {
10854                 { 0x00000200, 0x00008},
10855                 { 0x00004000, 0x00400},
10856                 { 0x00006000, 0x00400},
10857                 { 0x00008000, 0x01000},
10858                 { 0x00010000, 0x01000},
10859                 { 0xffffffff, 0x00000}
10860         }, mem_tbl_5717[] = {
10861                 { 0x00000200, 0x00008},
10862                 { 0x00010000, 0x0a000},
10863                 { 0x00020000, 0x13c00},
10864                 { 0xffffffff, 0x00000}
10865         }, mem_tbl_57765[] = {
10866                 { 0x00000200, 0x00008},
10867                 { 0x00004000, 0x00800},
10868                 { 0x00006000, 0x09800},
10869                 { 0x00010000, 0x0a000},
10870                 { 0xffffffff, 0x00000}
10871         };
10872         struct mem_entry *mem_tbl;
10873         int err = 0;
10874         int i;
10875
10876         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
10877                 mem_tbl = mem_tbl_5717;
10878         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10879                 mem_tbl = mem_tbl_57765;
10880         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10881                 mem_tbl = mem_tbl_5755;
10882         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10883                 mem_tbl = mem_tbl_5906;
10884         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10885                 mem_tbl = mem_tbl_5705;
10886         else
10887                 mem_tbl = mem_tbl_570x;
10888
10889         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10890                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10891                 if (err)
10892                         break;
10893         }
10894
10895         return err;
10896 }
10897
10898 #define TG3_MAC_LOOPBACK        0
10899 #define TG3_PHY_LOOPBACK        1
10900
10901 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10902 {
10903         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10904         u32 desc_idx, coal_now;
10905         struct sk_buff *skb, *rx_skb;
10906         u8 *tx_data;
10907         dma_addr_t map;
10908         int num_pkts, tx_len, rx_len, i, err;
10909         struct tg3_rx_buffer_desc *desc;
10910         struct tg3_napi *tnapi, *rnapi;
10911         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10912
10913         tnapi = &tp->napi[0];
10914         rnapi = &tp->napi[0];
10915         if (tp->irq_cnt > 1) {
10916                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10917                         rnapi = &tp->napi[1];
10918                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10919                         tnapi = &tp->napi[1];
10920         }
10921         coal_now = tnapi->coal_now | rnapi->coal_now;
10922
10923         if (loopback_mode == TG3_MAC_LOOPBACK) {
10924                 /* HW errata - mac loopback fails in some cases on 5780.
10925                  * Normal traffic and PHY loopback are not affected by
10926                  * errata.  Also, the MAC loopback test is deprecated for
10927                  * all newer ASIC revisions.
10928                  */
10929                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10930                     (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
10931                         return 0;
10932
10933                 mac_mode = tp->mac_mode &
10934                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10935                 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
10936                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10937                         mac_mode |= MAC_MODE_LINK_POLARITY;
10938                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10939                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10940                 else
10941                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10942                 tw32(MAC_MODE, mac_mode);
10943         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10944                 u32 val;
10945
10946                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10947                         tg3_phy_fet_toggle_apd(tp, false);
10948                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10949                 } else
10950                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10951
10952                 tg3_phy_toggle_automdix(tp, 0);
10953
10954                 tg3_writephy(tp, MII_BMCR, val);
10955                 udelay(40);
10956
10957                 mac_mode = tp->mac_mode &
10958                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10959                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10960                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10961                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10962                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10963                         /* The write needs to be flushed for the AC131 */
10964                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10965                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10966                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10967                 } else
10968                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10969
10970                 /* reset to prevent losing 1st rx packet intermittently */
10971                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10972                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10973                         udelay(10);
10974                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10975                 }
10976                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10977                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10978                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10979                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10980                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10981                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10982                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10983                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10984                 }
10985                 tw32(MAC_MODE, mac_mode);
10986
10987                 /* Wait for link */
10988                 for (i = 0; i < 100; i++) {
10989                         if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
10990                                 break;
10991                         mdelay(1);
10992                 }
10993         } else {
10994                 return -EINVAL;
10995         }
10996
10997         err = -EIO;
10998
10999         tx_len = 1514;
11000         skb = netdev_alloc_skb(tp->dev, tx_len);
11001         if (!skb)
11002                 return -ENOMEM;
11003
11004         tx_data = skb_put(skb, tx_len);
11005         memcpy(tx_data, tp->dev->dev_addr, 6);
11006         memset(tx_data + 6, 0x0, 8);
11007
11008         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
11009
11010         for (i = 14; i < tx_len; i++)
11011                 tx_data[i] = (u8) (i & 0xff);
11012
11013         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11014         if (pci_dma_mapping_error(tp->pdev, map)) {
11015                 dev_kfree_skb(skb);
11016                 return -EIO;
11017         }
11018
11019         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11020                rnapi->coal_now);
11021
11022         udelay(10);
11023
11024         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11025
11026         num_pkts = 0;
11027
11028         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
11029
11030         tnapi->tx_prod++;
11031         num_pkts++;
11032
11033         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11034         tr32_mailbox(tnapi->prodmbox);
11035
11036         udelay(10);
11037
11038         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
11039         for (i = 0; i < 35; i++) {
11040                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11041                        coal_now);
11042
11043                 udelay(10);
11044
11045                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11046                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11047                 if ((tx_idx == tnapi->tx_prod) &&
11048                     (rx_idx == (rx_start_idx + num_pkts)))
11049                         break;
11050         }
11051
11052         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11053         dev_kfree_skb(skb);
11054
11055         if (tx_idx != tnapi->tx_prod)
11056                 goto out;
11057
11058         if (rx_idx != rx_start_idx + num_pkts)
11059                 goto out;
11060
11061         desc = &rnapi->rx_rcb[rx_start_idx];
11062         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11063         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11064         if (opaque_key != RXD_OPAQUE_RING_STD)
11065                 goto out;
11066
11067         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11068             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11069                 goto out;
11070
11071         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11072         if (rx_len != tx_len)
11073                 goto out;
11074
11075         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11076
11077         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11078         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11079
11080         for (i = 14; i < tx_len; i++) {
11081                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11082                         goto out;
11083         }
11084         err = 0;
11085
11086         /* tg3_free_rings will unmap and free the rx_skb */
11087 out:
11088         return err;
11089 }
11090
11091 #define TG3_MAC_LOOPBACK_FAILED         1
11092 #define TG3_PHY_LOOPBACK_FAILED         2
11093 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
11094                                          TG3_PHY_LOOPBACK_FAILED)
11095
11096 static int tg3_test_loopback(struct tg3 *tp)
11097 {
11098         int err = 0;
11099         u32 eee_cap, cpmuctrl = 0;
11100
11101         if (!netif_running(tp->dev))
11102                 return TG3_LOOPBACK_FAILED;
11103
11104         eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11105         tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11106
11107         err = tg3_reset_hw(tp, 1);
11108         if (err) {
11109                 err = TG3_LOOPBACK_FAILED;
11110                 goto done;
11111         }
11112
11113         /* Turn off gphy autopowerdown. */
11114         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11115                 tg3_phy_toggle_apd(tp, false);
11116
11117         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11118                 int i;
11119                 u32 status;
11120
11121                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11122
11123                 /* Wait for up to 40 microseconds to acquire lock. */
11124                 for (i = 0; i < 4; i++) {
11125                         status = tr32(TG3_CPMU_MUTEX_GNT);
11126                         if (status == CPMU_MUTEX_GNT_DRIVER)
11127                                 break;
11128                         udelay(10);
11129                 }
11130
11131                 if (status != CPMU_MUTEX_GNT_DRIVER) {
11132                         err = TG3_LOOPBACK_FAILED;
11133                         goto done;
11134                 }
11135
11136                 /* Turn off link-based power management. */
11137                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11138                 tw32(TG3_CPMU_CTRL,
11139                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11140                                   CPMU_CTRL_LINK_AWARE_MODE));
11141         }
11142
11143         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11144                 err |= TG3_MAC_LOOPBACK_FAILED;
11145
11146         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11147                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11148
11149                 /* Release the mutex */
11150                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11151         }
11152
11153         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11154             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11155                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11156                         err |= TG3_PHY_LOOPBACK_FAILED;
11157         }
11158
11159         /* Re-enable gphy autopowerdown. */
11160         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11161                 tg3_phy_toggle_apd(tp, true);
11162
11163 done:
11164         tp->phy_flags |= eee_cap;
11165
11166         return err;
11167 }
11168
11169 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11170                           u64 *data)
11171 {
11172         struct tg3 *tp = netdev_priv(dev);
11173
11174         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11175                 tg3_power_up(tp);
11176
11177         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11178
11179         if (tg3_test_nvram(tp) != 0) {
11180                 etest->flags |= ETH_TEST_FL_FAILED;
11181                 data[0] = 1;
11182         }
11183         if (tg3_test_link(tp) != 0) {
11184                 etest->flags |= ETH_TEST_FL_FAILED;
11185                 data[1] = 1;
11186         }
11187         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11188                 int err, err2 = 0, irq_sync = 0;
11189
11190                 if (netif_running(dev)) {
11191                         tg3_phy_stop(tp);
11192                         tg3_netif_stop(tp);
11193                         irq_sync = 1;
11194                 }
11195
11196                 tg3_full_lock(tp, irq_sync);
11197
11198                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11199                 err = tg3_nvram_lock(tp);
11200                 tg3_halt_cpu(tp, RX_CPU_BASE);
11201                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11202                         tg3_halt_cpu(tp, TX_CPU_BASE);
11203                 if (!err)
11204                         tg3_nvram_unlock(tp);
11205
11206                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11207                         tg3_phy_reset(tp);
11208
11209                 if (tg3_test_registers(tp) != 0) {
11210                         etest->flags |= ETH_TEST_FL_FAILED;
11211                         data[2] = 1;
11212                 }
11213                 if (tg3_test_memory(tp) != 0) {
11214                         etest->flags |= ETH_TEST_FL_FAILED;
11215                         data[3] = 1;
11216                 }
11217                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11218                         etest->flags |= ETH_TEST_FL_FAILED;
11219
11220                 tg3_full_unlock(tp);
11221
11222                 if (tg3_test_interrupt(tp) != 0) {
11223                         etest->flags |= ETH_TEST_FL_FAILED;
11224                         data[5] = 1;
11225                 }
11226
11227                 tg3_full_lock(tp, 0);
11228
11229                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11230                 if (netif_running(dev)) {
11231                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11232                         err2 = tg3_restart_hw(tp, 1);
11233                         if (!err2)
11234                                 tg3_netif_start(tp);
11235                 }
11236
11237                 tg3_full_unlock(tp);
11238
11239                 if (irq_sync && !err2)
11240                         tg3_phy_start(tp);
11241         }
11242         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11243                 tg3_power_down(tp);
11244
11245 }
11246
11247 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11248 {
11249         struct mii_ioctl_data *data = if_mii(ifr);
11250         struct tg3 *tp = netdev_priv(dev);
11251         int err;
11252
11253         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11254                 struct phy_device *phydev;
11255                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11256                         return -EAGAIN;
11257                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11258                 return phy_mii_ioctl(phydev, ifr, cmd);
11259         }
11260
11261         switch (cmd) {
11262         case SIOCGMIIPHY:
11263                 data->phy_id = tp->phy_addr;
11264
11265                 /* fallthru */
11266         case SIOCGMIIREG: {
11267                 u32 mii_regval;
11268
11269                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11270                         break;                  /* We have no PHY */
11271
11272                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11273                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11274                      !netif_running(dev)))
11275                         return -EAGAIN;
11276
11277                 spin_lock_bh(&tp->lock);
11278                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11279                 spin_unlock_bh(&tp->lock);
11280
11281                 data->val_out = mii_regval;
11282
11283                 return err;
11284         }
11285
11286         case SIOCSMIIREG:
11287                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11288                         break;                  /* We have no PHY */
11289
11290                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11291                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11292                      !netif_running(dev)))
11293                         return -EAGAIN;
11294
11295                 spin_lock_bh(&tp->lock);
11296                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11297                 spin_unlock_bh(&tp->lock);
11298
11299                 return err;
11300
11301         default:
11302                 /* do nothing */
11303                 break;
11304         }
11305         return -EOPNOTSUPP;
11306 }
11307
11308 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11309 {
11310         struct tg3 *tp = netdev_priv(dev);
11311
11312         memcpy(ec, &tp->coal, sizeof(*ec));
11313         return 0;
11314 }
11315
11316 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11317 {
11318         struct tg3 *tp = netdev_priv(dev);
11319         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11320         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11321
11322         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11323                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11324                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11325                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11326                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11327         }
11328
11329         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11330             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11331             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11332             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11333             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11334             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11335             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11336             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11337             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11338             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11339                 return -EINVAL;
11340
11341         /* No rx interrupts will be generated if both are zero */
11342         if ((ec->rx_coalesce_usecs == 0) &&
11343             (ec->rx_max_coalesced_frames == 0))
11344                 return -EINVAL;
11345
11346         /* No tx interrupts will be generated if both are zero */
11347         if ((ec->tx_coalesce_usecs == 0) &&
11348             (ec->tx_max_coalesced_frames == 0))
11349                 return -EINVAL;
11350
11351         /* Only copy relevant parameters, ignore all others. */
11352         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11353         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11354         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11355         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11356         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11357         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11358         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11359         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11360         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11361
11362         if (netif_running(dev)) {
11363                 tg3_full_lock(tp, 0);
11364                 __tg3_set_coalesce(tp, &tp->coal);
11365                 tg3_full_unlock(tp);
11366         }
11367         return 0;
11368 }
11369
11370 static const struct ethtool_ops tg3_ethtool_ops = {
11371         .get_settings           = tg3_get_settings,
11372         .set_settings           = tg3_set_settings,
11373         .get_drvinfo            = tg3_get_drvinfo,
11374         .get_regs_len           = tg3_get_regs_len,
11375         .get_regs               = tg3_get_regs,
11376         .get_wol                = tg3_get_wol,
11377         .set_wol                = tg3_set_wol,
11378         .get_msglevel           = tg3_get_msglevel,
11379         .set_msglevel           = tg3_set_msglevel,
11380         .nway_reset             = tg3_nway_reset,
11381         .get_link               = ethtool_op_get_link,
11382         .get_eeprom_len         = tg3_get_eeprom_len,
11383         .get_eeprom             = tg3_get_eeprom,
11384         .set_eeprom             = tg3_set_eeprom,
11385         .get_ringparam          = tg3_get_ringparam,
11386         .set_ringparam          = tg3_set_ringparam,
11387         .get_pauseparam         = tg3_get_pauseparam,
11388         .set_pauseparam         = tg3_set_pauseparam,
11389         .get_rx_csum            = tg3_get_rx_csum,
11390         .set_rx_csum            = tg3_set_rx_csum,
11391         .set_tx_csum            = tg3_set_tx_csum,
11392         .set_sg                 = ethtool_op_set_sg,
11393         .set_tso                = tg3_set_tso,
11394         .self_test              = tg3_self_test,
11395         .get_strings            = tg3_get_strings,
11396         .phys_id                = tg3_phys_id,
11397         .get_ethtool_stats      = tg3_get_ethtool_stats,
11398         .get_coalesce           = tg3_get_coalesce,
11399         .set_coalesce           = tg3_set_coalesce,
11400         .get_sset_count         = tg3_get_sset_count,
11401 };
11402
11403 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11404 {
11405         u32 cursize, val, magic;
11406
11407         tp->nvram_size = EEPROM_CHIP_SIZE;
11408
11409         if (tg3_nvram_read(tp, 0, &magic) != 0)
11410                 return;
11411
11412         if ((magic != TG3_EEPROM_MAGIC) &&
11413             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11414             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11415                 return;
11416
11417         /*
11418          * Size the chip by reading offsets at increasing powers of two.
11419          * When we encounter our validation signature, we know the addressing
11420          * has wrapped around, and thus have our chip size.
11421          */
11422         cursize = 0x10;
11423
11424         while (cursize < tp->nvram_size) {
11425                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11426                         return;
11427
11428                 if (val == magic)
11429                         break;
11430
11431                 cursize <<= 1;
11432         }
11433
11434         tp->nvram_size = cursize;
11435 }
11436
11437 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11438 {
11439         u32 val;
11440
11441         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11442             tg3_nvram_read(tp, 0, &val) != 0)
11443                 return;
11444
11445         /* Selfboot format */
11446         if (val != TG3_EEPROM_MAGIC) {
11447                 tg3_get_eeprom_size(tp);
11448                 return;
11449         }
11450
11451         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11452                 if (val != 0) {
11453                         /* This is confusing.  We want to operate on the
11454                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11455                          * call will read from NVRAM and byteswap the data
11456                          * according to the byteswapping settings for all
11457                          * other register accesses.  This ensures the data we
11458                          * want will always reside in the lower 16-bits.
11459                          * However, the data in NVRAM is in LE format, which
11460                          * means the data from the NVRAM read will always be
11461                          * opposite the endianness of the CPU.  The 16-bit
11462                          * byteswap then brings the data to CPU endianness.
11463                          */
11464                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11465                         return;
11466                 }
11467         }
11468         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11469 }
11470
11471 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11472 {
11473         u32 nvcfg1;
11474
11475         nvcfg1 = tr32(NVRAM_CFG1);
11476         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11477                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11478         } else {
11479                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11480                 tw32(NVRAM_CFG1, nvcfg1);
11481         }
11482
11483         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11484             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11485                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11486                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11487                         tp->nvram_jedecnum = JEDEC_ATMEL;
11488                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11489                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11490                         break;
11491                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11492                         tp->nvram_jedecnum = JEDEC_ATMEL;
11493                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11494                         break;
11495                 case FLASH_VENDOR_ATMEL_EEPROM:
11496                         tp->nvram_jedecnum = JEDEC_ATMEL;
11497                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11498                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11499                         break;
11500                 case FLASH_VENDOR_ST:
11501                         tp->nvram_jedecnum = JEDEC_ST;
11502                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11503                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11504                         break;
11505                 case FLASH_VENDOR_SAIFUN:
11506                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11507                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11508                         break;
11509                 case FLASH_VENDOR_SST_SMALL:
11510                 case FLASH_VENDOR_SST_LARGE:
11511                         tp->nvram_jedecnum = JEDEC_SST;
11512                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11513                         break;
11514                 }
11515         } else {
11516                 tp->nvram_jedecnum = JEDEC_ATMEL;
11517                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11518                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11519         }
11520 }
11521
11522 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11523 {
11524         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11525         case FLASH_5752PAGE_SIZE_256:
11526                 tp->nvram_pagesize = 256;
11527                 break;
11528         case FLASH_5752PAGE_SIZE_512:
11529                 tp->nvram_pagesize = 512;
11530                 break;
11531         case FLASH_5752PAGE_SIZE_1K:
11532                 tp->nvram_pagesize = 1024;
11533                 break;
11534         case FLASH_5752PAGE_SIZE_2K:
11535                 tp->nvram_pagesize = 2048;
11536                 break;
11537         case FLASH_5752PAGE_SIZE_4K:
11538                 tp->nvram_pagesize = 4096;
11539                 break;
11540         case FLASH_5752PAGE_SIZE_264:
11541                 tp->nvram_pagesize = 264;
11542                 break;
11543         case FLASH_5752PAGE_SIZE_528:
11544                 tp->nvram_pagesize = 528;
11545                 break;
11546         }
11547 }
11548
11549 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11550 {
11551         u32 nvcfg1;
11552
11553         nvcfg1 = tr32(NVRAM_CFG1);
11554
11555         /* NVRAM protection for TPM */
11556         if (nvcfg1 & (1 << 27))
11557                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11558
11559         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11560         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11561         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11562                 tp->nvram_jedecnum = JEDEC_ATMEL;
11563                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11564                 break;
11565         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11566                 tp->nvram_jedecnum = JEDEC_ATMEL;
11567                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11569                 break;
11570         case FLASH_5752VENDOR_ST_M45PE10:
11571         case FLASH_5752VENDOR_ST_M45PE20:
11572         case FLASH_5752VENDOR_ST_M45PE40:
11573                 tp->nvram_jedecnum = JEDEC_ST;
11574                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11575                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11576                 break;
11577         }
11578
11579         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11580                 tg3_nvram_get_pagesize(tp, nvcfg1);
11581         } else {
11582                 /* For eeprom, set pagesize to maximum eeprom size */
11583                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11584
11585                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11586                 tw32(NVRAM_CFG1, nvcfg1);
11587         }
11588 }
11589
11590 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11591 {
11592         u32 nvcfg1, protect = 0;
11593
11594         nvcfg1 = tr32(NVRAM_CFG1);
11595
11596         /* NVRAM protection for TPM */
11597         if (nvcfg1 & (1 << 27)) {
11598                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11599                 protect = 1;
11600         }
11601
11602         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11603         switch (nvcfg1) {
11604         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11605         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11606         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11607         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11608                 tp->nvram_jedecnum = JEDEC_ATMEL;
11609                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11610                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11611                 tp->nvram_pagesize = 264;
11612                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11613                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11614                         tp->nvram_size = (protect ? 0x3e200 :
11615                                           TG3_NVRAM_SIZE_512KB);
11616                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11617                         tp->nvram_size = (protect ? 0x1f200 :
11618                                           TG3_NVRAM_SIZE_256KB);
11619                 else
11620                         tp->nvram_size = (protect ? 0x1f200 :
11621                                           TG3_NVRAM_SIZE_128KB);
11622                 break;
11623         case FLASH_5752VENDOR_ST_M45PE10:
11624         case FLASH_5752VENDOR_ST_M45PE20:
11625         case FLASH_5752VENDOR_ST_M45PE40:
11626                 tp->nvram_jedecnum = JEDEC_ST;
11627                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11628                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11629                 tp->nvram_pagesize = 256;
11630                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11631                         tp->nvram_size = (protect ?
11632                                           TG3_NVRAM_SIZE_64KB :
11633                                           TG3_NVRAM_SIZE_128KB);
11634                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11635                         tp->nvram_size = (protect ?
11636                                           TG3_NVRAM_SIZE_64KB :
11637                                           TG3_NVRAM_SIZE_256KB);
11638                 else
11639                         tp->nvram_size = (protect ?
11640                                           TG3_NVRAM_SIZE_128KB :
11641                                           TG3_NVRAM_SIZE_512KB);
11642                 break;
11643         }
11644 }
11645
11646 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11647 {
11648         u32 nvcfg1;
11649
11650         nvcfg1 = tr32(NVRAM_CFG1);
11651
11652         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11653         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11654         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11655         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11656         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11657                 tp->nvram_jedecnum = JEDEC_ATMEL;
11658                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11659                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11660
11661                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11662                 tw32(NVRAM_CFG1, nvcfg1);
11663                 break;
11664         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11665         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11666         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11667         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11668                 tp->nvram_jedecnum = JEDEC_ATMEL;
11669                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11670                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11671                 tp->nvram_pagesize = 264;
11672                 break;
11673         case FLASH_5752VENDOR_ST_M45PE10:
11674         case FLASH_5752VENDOR_ST_M45PE20:
11675         case FLASH_5752VENDOR_ST_M45PE40:
11676                 tp->nvram_jedecnum = JEDEC_ST;
11677                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11678                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11679                 tp->nvram_pagesize = 256;
11680                 break;
11681         }
11682 }
11683
11684 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11685 {
11686         u32 nvcfg1, protect = 0;
11687
11688         nvcfg1 = tr32(NVRAM_CFG1);
11689
11690         /* NVRAM protection for TPM */
11691         if (nvcfg1 & (1 << 27)) {
11692                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11693                 protect = 1;
11694         }
11695
11696         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11697         switch (nvcfg1) {
11698         case FLASH_5761VENDOR_ATMEL_ADB021D:
11699         case FLASH_5761VENDOR_ATMEL_ADB041D:
11700         case FLASH_5761VENDOR_ATMEL_ADB081D:
11701         case FLASH_5761VENDOR_ATMEL_ADB161D:
11702         case FLASH_5761VENDOR_ATMEL_MDB021D:
11703         case FLASH_5761VENDOR_ATMEL_MDB041D:
11704         case FLASH_5761VENDOR_ATMEL_MDB081D:
11705         case FLASH_5761VENDOR_ATMEL_MDB161D:
11706                 tp->nvram_jedecnum = JEDEC_ATMEL;
11707                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11708                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11709                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11710                 tp->nvram_pagesize = 256;
11711                 break;
11712         case FLASH_5761VENDOR_ST_A_M45PE20:
11713         case FLASH_5761VENDOR_ST_A_M45PE40:
11714         case FLASH_5761VENDOR_ST_A_M45PE80:
11715         case FLASH_5761VENDOR_ST_A_M45PE16:
11716         case FLASH_5761VENDOR_ST_M_M45PE20:
11717         case FLASH_5761VENDOR_ST_M_M45PE40:
11718         case FLASH_5761VENDOR_ST_M_M45PE80:
11719         case FLASH_5761VENDOR_ST_M_M45PE16:
11720                 tp->nvram_jedecnum = JEDEC_ST;
11721                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11722                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11723                 tp->nvram_pagesize = 256;
11724                 break;
11725         }
11726
11727         if (protect) {
11728                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11729         } else {
11730                 switch (nvcfg1) {
11731                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11732                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11733                 case FLASH_5761VENDOR_ST_A_M45PE16:
11734                 case FLASH_5761VENDOR_ST_M_M45PE16:
11735                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11736                         break;
11737                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11738                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11739                 case FLASH_5761VENDOR_ST_A_M45PE80:
11740                 case FLASH_5761VENDOR_ST_M_M45PE80:
11741                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11742                         break;
11743                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11744                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11745                 case FLASH_5761VENDOR_ST_A_M45PE40:
11746                 case FLASH_5761VENDOR_ST_M_M45PE40:
11747                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11748                         break;
11749                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11750                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11751                 case FLASH_5761VENDOR_ST_A_M45PE20:
11752                 case FLASH_5761VENDOR_ST_M_M45PE20:
11753                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11754                         break;
11755                 }
11756         }
11757 }
11758
11759 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11760 {
11761         tp->nvram_jedecnum = JEDEC_ATMEL;
11762         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11763         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11764 }
11765
11766 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11767 {
11768         u32 nvcfg1;
11769
11770         nvcfg1 = tr32(NVRAM_CFG1);
11771
11772         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11773         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11774         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11775                 tp->nvram_jedecnum = JEDEC_ATMEL;
11776                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11777                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11778
11779                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11780                 tw32(NVRAM_CFG1, nvcfg1);
11781                 return;
11782         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11783         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11784         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11785         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11786         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11787         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11788         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11789                 tp->nvram_jedecnum = JEDEC_ATMEL;
11790                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11791                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11792
11793                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11794                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11795                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11796                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11797                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11798                         break;
11799                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11800                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11801                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11802                         break;
11803                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11804                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11805                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11806                         break;
11807                 }
11808                 break;
11809         case FLASH_5752VENDOR_ST_M45PE10:
11810         case FLASH_5752VENDOR_ST_M45PE20:
11811         case FLASH_5752VENDOR_ST_M45PE40:
11812                 tp->nvram_jedecnum = JEDEC_ST;
11813                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11814                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11815
11816                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11817                 case FLASH_5752VENDOR_ST_M45PE10:
11818                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11819                         break;
11820                 case FLASH_5752VENDOR_ST_M45PE20:
11821                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11822                         break;
11823                 case FLASH_5752VENDOR_ST_M45PE40:
11824                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11825                         break;
11826                 }
11827                 break;
11828         default:
11829                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11830                 return;
11831         }
11832
11833         tg3_nvram_get_pagesize(tp, nvcfg1);
11834         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11835                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11836 }
11837
11838
11839 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11840 {
11841         u32 nvcfg1;
11842
11843         nvcfg1 = tr32(NVRAM_CFG1);
11844
11845         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11846         case FLASH_5717VENDOR_ATMEL_EEPROM:
11847         case FLASH_5717VENDOR_MICRO_EEPROM:
11848                 tp->nvram_jedecnum = JEDEC_ATMEL;
11849                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11850                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11851
11852                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11853                 tw32(NVRAM_CFG1, nvcfg1);
11854                 return;
11855         case FLASH_5717VENDOR_ATMEL_MDB011D:
11856         case FLASH_5717VENDOR_ATMEL_ADB011B:
11857         case FLASH_5717VENDOR_ATMEL_ADB011D:
11858         case FLASH_5717VENDOR_ATMEL_MDB021D:
11859         case FLASH_5717VENDOR_ATMEL_ADB021B:
11860         case FLASH_5717VENDOR_ATMEL_ADB021D:
11861         case FLASH_5717VENDOR_ATMEL_45USPT:
11862                 tp->nvram_jedecnum = JEDEC_ATMEL;
11863                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11864                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11865
11866                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11867                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11868                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11869                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11870                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11871                         break;
11872                 default:
11873                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11874                         break;
11875                 }
11876                 break;
11877         case FLASH_5717VENDOR_ST_M_M25PE10:
11878         case FLASH_5717VENDOR_ST_A_M25PE10:
11879         case FLASH_5717VENDOR_ST_M_M45PE10:
11880         case FLASH_5717VENDOR_ST_A_M45PE10:
11881         case FLASH_5717VENDOR_ST_M_M25PE20:
11882         case FLASH_5717VENDOR_ST_A_M25PE20:
11883         case FLASH_5717VENDOR_ST_M_M45PE20:
11884         case FLASH_5717VENDOR_ST_A_M45PE20:
11885         case FLASH_5717VENDOR_ST_25USPT:
11886         case FLASH_5717VENDOR_ST_45USPT:
11887                 tp->nvram_jedecnum = JEDEC_ST;
11888                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11889                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11890
11891                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11892                 case FLASH_5717VENDOR_ST_M_M25PE20:
11893                 case FLASH_5717VENDOR_ST_A_M25PE20:
11894                 case FLASH_5717VENDOR_ST_M_M45PE20:
11895                 case FLASH_5717VENDOR_ST_A_M45PE20:
11896                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11897                         break;
11898                 default:
11899                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11900                         break;
11901                 }
11902                 break;
11903         default:
11904                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11905                 return;
11906         }
11907
11908         tg3_nvram_get_pagesize(tp, nvcfg1);
11909         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11910                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11911 }
11912
11913 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
11914 {
11915         u32 nvcfg1, nvmpinstrp;
11916
11917         nvcfg1 = tr32(NVRAM_CFG1);
11918         nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
11919
11920         switch (nvmpinstrp) {
11921         case FLASH_5720_EEPROM_HD:
11922         case FLASH_5720_EEPROM_LD:
11923                 tp->nvram_jedecnum = JEDEC_ATMEL;
11924                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11925
11926                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11927                 tw32(NVRAM_CFG1, nvcfg1);
11928                 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
11929                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11930                 else
11931                         tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
11932                 return;
11933         case FLASH_5720VENDOR_M_ATMEL_DB011D:
11934         case FLASH_5720VENDOR_A_ATMEL_DB011B:
11935         case FLASH_5720VENDOR_A_ATMEL_DB011D:
11936         case FLASH_5720VENDOR_M_ATMEL_DB021D:
11937         case FLASH_5720VENDOR_A_ATMEL_DB021B:
11938         case FLASH_5720VENDOR_A_ATMEL_DB021D:
11939         case FLASH_5720VENDOR_M_ATMEL_DB041D:
11940         case FLASH_5720VENDOR_A_ATMEL_DB041B:
11941         case FLASH_5720VENDOR_A_ATMEL_DB041D:
11942         case FLASH_5720VENDOR_M_ATMEL_DB081D:
11943         case FLASH_5720VENDOR_A_ATMEL_DB081D:
11944         case FLASH_5720VENDOR_ATMEL_45USPT:
11945                 tp->nvram_jedecnum = JEDEC_ATMEL;
11946                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11947                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11948
11949                 switch (nvmpinstrp) {
11950                 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11951                 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11952                 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11953                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11954                         break;
11955                 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11956                 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11957                 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11958                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11959                         break;
11960                 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11961                 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11962                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11963                         break;
11964                 default:
11965                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11966                         break;
11967                 }
11968                 break;
11969         case FLASH_5720VENDOR_M_ST_M25PE10:
11970         case FLASH_5720VENDOR_M_ST_M45PE10:
11971         case FLASH_5720VENDOR_A_ST_M25PE10:
11972         case FLASH_5720VENDOR_A_ST_M45PE10:
11973         case FLASH_5720VENDOR_M_ST_M25PE20:
11974         case FLASH_5720VENDOR_M_ST_M45PE20:
11975         case FLASH_5720VENDOR_A_ST_M25PE20:
11976         case FLASH_5720VENDOR_A_ST_M45PE20:
11977         case FLASH_5720VENDOR_M_ST_M25PE40:
11978         case FLASH_5720VENDOR_M_ST_M45PE40:
11979         case FLASH_5720VENDOR_A_ST_M25PE40:
11980         case FLASH_5720VENDOR_A_ST_M45PE40:
11981         case FLASH_5720VENDOR_M_ST_M25PE80:
11982         case FLASH_5720VENDOR_M_ST_M45PE80:
11983         case FLASH_5720VENDOR_A_ST_M25PE80:
11984         case FLASH_5720VENDOR_A_ST_M45PE80:
11985         case FLASH_5720VENDOR_ST_25USPT:
11986         case FLASH_5720VENDOR_ST_45USPT:
11987                 tp->nvram_jedecnum = JEDEC_ST;
11988                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11989                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11990
11991                 switch (nvmpinstrp) {
11992                 case FLASH_5720VENDOR_M_ST_M25PE20:
11993                 case FLASH_5720VENDOR_M_ST_M45PE20:
11994                 case FLASH_5720VENDOR_A_ST_M25PE20:
11995                 case FLASH_5720VENDOR_A_ST_M45PE20:
11996                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11997                         break;
11998                 case FLASH_5720VENDOR_M_ST_M25PE40:
11999                 case FLASH_5720VENDOR_M_ST_M45PE40:
12000                 case FLASH_5720VENDOR_A_ST_M25PE40:
12001                 case FLASH_5720VENDOR_A_ST_M45PE40:
12002                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12003                         break;
12004                 case FLASH_5720VENDOR_M_ST_M25PE80:
12005                 case FLASH_5720VENDOR_M_ST_M45PE80:
12006                 case FLASH_5720VENDOR_A_ST_M25PE80:
12007                 case FLASH_5720VENDOR_A_ST_M45PE80:
12008                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12009                         break;
12010                 default:
12011                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12012                         break;
12013                 }
12014                 break;
12015         default:
12016                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12017                 return;
12018         }
12019
12020         tg3_nvram_get_pagesize(tp, nvcfg1);
12021         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12022                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12023 }
12024
12025 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12026 static void __devinit tg3_nvram_init(struct tg3 *tp)
12027 {
12028         tw32_f(GRC_EEPROM_ADDR,
12029              (EEPROM_ADDR_FSM_RESET |
12030               (EEPROM_DEFAULT_CLOCK_PERIOD <<
12031                EEPROM_ADDR_CLKPERD_SHIFT)));
12032
12033         msleep(1);
12034
12035         /* Enable seeprom accesses. */
12036         tw32_f(GRC_LOCAL_CTRL,
12037              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12038         udelay(100);
12039
12040         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12041             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12042                 tp->tg3_flags |= TG3_FLAG_NVRAM;
12043
12044                 if (tg3_nvram_lock(tp)) {
12045                         netdev_warn(tp->dev,
12046                                     "Cannot get nvram lock, %s failed\n",
12047                                     __func__);
12048                         return;
12049                 }
12050                 tg3_enable_nvram_access(tp);
12051
12052                 tp->nvram_size = 0;
12053
12054                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12055                         tg3_get_5752_nvram_info(tp);
12056                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12057                         tg3_get_5755_nvram_info(tp);
12058                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12059                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12060                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12061                         tg3_get_5787_nvram_info(tp);
12062                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12063                         tg3_get_5761_nvram_info(tp);
12064                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12065                         tg3_get_5906_nvram_info(tp);
12066                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12067                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12068                         tg3_get_57780_nvram_info(tp);
12069                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12070                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12071                         tg3_get_5717_nvram_info(tp);
12072                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12073                         tg3_get_5720_nvram_info(tp);
12074                 else
12075                         tg3_get_nvram_info(tp);
12076
12077                 if (tp->nvram_size == 0)
12078                         tg3_get_nvram_size(tp);
12079
12080                 tg3_disable_nvram_access(tp);
12081                 tg3_nvram_unlock(tp);
12082
12083         } else {
12084                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
12085
12086                 tg3_get_eeprom_size(tp);
12087         }
12088 }
12089
12090 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12091                                     u32 offset, u32 len, u8 *buf)
12092 {
12093         int i, j, rc = 0;
12094         u32 val;
12095
12096         for (i = 0; i < len; i += 4) {
12097                 u32 addr;
12098                 __be32 data;
12099
12100                 addr = offset + i;
12101
12102                 memcpy(&data, buf + i, 4);
12103
12104                 /*
12105                  * The SEEPROM interface expects the data to always be opposite
12106                  * the native endian format.  We accomplish this by reversing
12107                  * all the operations that would have been performed on the
12108                  * data from a call to tg3_nvram_read_be32().
12109                  */
12110                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12111
12112                 val = tr32(GRC_EEPROM_ADDR);
12113                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12114
12115                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12116                         EEPROM_ADDR_READ);
12117                 tw32(GRC_EEPROM_ADDR, val |
12118                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
12119                         (addr & EEPROM_ADDR_ADDR_MASK) |
12120                         EEPROM_ADDR_START |
12121                         EEPROM_ADDR_WRITE);
12122
12123                 for (j = 0; j < 1000; j++) {
12124                         val = tr32(GRC_EEPROM_ADDR);
12125
12126                         if (val & EEPROM_ADDR_COMPLETE)
12127                                 break;
12128                         msleep(1);
12129                 }
12130                 if (!(val & EEPROM_ADDR_COMPLETE)) {
12131                         rc = -EBUSY;
12132                         break;
12133                 }
12134         }
12135
12136         return rc;
12137 }
12138
12139 /* offset and length are dword aligned */
12140 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12141                 u8 *buf)
12142 {
12143         int ret = 0;
12144         u32 pagesize = tp->nvram_pagesize;
12145         u32 pagemask = pagesize - 1;
12146         u32 nvram_cmd;
12147         u8 *tmp;
12148
12149         tmp = kmalloc(pagesize, GFP_KERNEL);
12150         if (tmp == NULL)
12151                 return -ENOMEM;
12152
12153         while (len) {
12154                 int j;
12155                 u32 phy_addr, page_off, size;
12156
12157                 phy_addr = offset & ~pagemask;
12158
12159                 for (j = 0; j < pagesize; j += 4) {
12160                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
12161                                                   (__be32 *) (tmp + j));
12162                         if (ret)
12163                                 break;
12164                 }
12165                 if (ret)
12166                         break;
12167
12168                 page_off = offset & pagemask;
12169                 size = pagesize;
12170                 if (len < size)
12171                         size = len;
12172
12173                 len -= size;
12174
12175                 memcpy(tmp + page_off, buf, size);
12176
12177                 offset = offset + (pagesize - page_off);
12178
12179                 tg3_enable_nvram_access(tp);
12180
12181                 /*
12182                  * Before we can erase the flash page, we need
12183                  * to issue a special "write enable" command.
12184                  */
12185                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12186
12187                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12188                         break;
12189
12190                 /* Erase the target page */
12191                 tw32(NVRAM_ADDR, phy_addr);
12192
12193                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12194                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12195
12196                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12197                         break;
12198
12199                 /* Issue another write enable to start the write. */
12200                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12201
12202                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12203                         break;
12204
12205                 for (j = 0; j < pagesize; j += 4) {
12206                         __be32 data;
12207
12208                         data = *((__be32 *) (tmp + j));
12209
12210                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12211
12212                         tw32(NVRAM_ADDR, phy_addr + j);
12213
12214                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12215                                 NVRAM_CMD_WR;
12216
12217                         if (j == 0)
12218                                 nvram_cmd |= NVRAM_CMD_FIRST;
12219                         else if (j == (pagesize - 4))
12220                                 nvram_cmd |= NVRAM_CMD_LAST;
12221
12222                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12223                                 break;
12224                 }
12225                 if (ret)
12226                         break;
12227         }
12228
12229         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12230         tg3_nvram_exec_cmd(tp, nvram_cmd);
12231
12232         kfree(tmp);
12233
12234         return ret;
12235 }
12236
12237 /* offset and length are dword aligned */
12238 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12239                 u8 *buf)
12240 {
12241         int i, ret = 0;
12242
12243         for (i = 0; i < len; i += 4, offset += 4) {
12244                 u32 page_off, phy_addr, nvram_cmd;
12245                 __be32 data;
12246
12247                 memcpy(&data, buf + i, 4);
12248                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12249
12250                 page_off = offset % tp->nvram_pagesize;
12251
12252                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12253
12254                 tw32(NVRAM_ADDR, phy_addr);
12255
12256                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12257
12258                 if (page_off == 0 || i == 0)
12259                         nvram_cmd |= NVRAM_CMD_FIRST;
12260                 if (page_off == (tp->nvram_pagesize - 4))
12261                         nvram_cmd |= NVRAM_CMD_LAST;
12262
12263                 if (i == (len - 4))
12264                         nvram_cmd |= NVRAM_CMD_LAST;
12265
12266                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12267                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12268                     (tp->nvram_jedecnum == JEDEC_ST) &&
12269                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12270
12271                         if ((ret = tg3_nvram_exec_cmd(tp,
12272                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12273                                 NVRAM_CMD_DONE)))
12274
12275                                 break;
12276                 }
12277                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12278                         /* We always do complete word writes to eeprom. */
12279                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12280                 }
12281
12282                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12283                         break;
12284         }
12285         return ret;
12286 }
12287
12288 /* offset and length are dword aligned */
12289 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12290 {
12291         int ret;
12292
12293         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12294                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12295                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12296                 udelay(40);
12297         }
12298
12299         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12300                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12301         } else {
12302                 u32 grc_mode;
12303
12304                 ret = tg3_nvram_lock(tp);
12305                 if (ret)
12306                         return ret;
12307
12308                 tg3_enable_nvram_access(tp);
12309                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12310                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12311                         tw32(NVRAM_WRITE1, 0x406);
12312
12313                 grc_mode = tr32(GRC_MODE);
12314                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12315
12316                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12317                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12318
12319                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12320                                 buf);
12321                 } else {
12322                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12323                                 buf);
12324                 }
12325
12326                 grc_mode = tr32(GRC_MODE);
12327                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12328
12329                 tg3_disable_nvram_access(tp);
12330                 tg3_nvram_unlock(tp);
12331         }
12332
12333         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12334                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12335                 udelay(40);
12336         }
12337
12338         return ret;
12339 }
12340
12341 struct subsys_tbl_ent {
12342         u16 subsys_vendor, subsys_devid;
12343         u32 phy_id;
12344 };
12345
12346 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12347         /* Broadcom boards. */
12348         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12349           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12350         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12351           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12352         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12353           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12354         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12355           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12356         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12357           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12358         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12359           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12360         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12361           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12362         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12363           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12364         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12365           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12366         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12367           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12368         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12369           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12370
12371         /* 3com boards. */
12372         { TG3PCI_SUBVENDOR_ID_3COM,
12373           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12374         { TG3PCI_SUBVENDOR_ID_3COM,
12375           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12376         { TG3PCI_SUBVENDOR_ID_3COM,
12377           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12378         { TG3PCI_SUBVENDOR_ID_3COM,
12379           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12380         { TG3PCI_SUBVENDOR_ID_3COM,
12381           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12382
12383         /* DELL boards. */
12384         { TG3PCI_SUBVENDOR_ID_DELL,
12385           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12386         { TG3PCI_SUBVENDOR_ID_DELL,
12387           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12388         { TG3PCI_SUBVENDOR_ID_DELL,
12389           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12390         { TG3PCI_SUBVENDOR_ID_DELL,
12391           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12392
12393         /* Compaq boards. */
12394         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12395           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12396         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12397           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12398         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12399           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12400         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12401           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12402         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12403           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12404
12405         /* IBM boards. */
12406         { TG3PCI_SUBVENDOR_ID_IBM,
12407           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12408 };
12409
12410 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12411 {
12412         int i;
12413
12414         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12415                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12416                      tp->pdev->subsystem_vendor) &&
12417                     (subsys_id_to_phy_id[i].subsys_devid ==
12418                      tp->pdev->subsystem_device))
12419                         return &subsys_id_to_phy_id[i];
12420         }
12421         return NULL;
12422 }
12423
12424 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12425 {
12426         u32 val;
12427         u16 pmcsr;
12428
12429         /* On some early chips the SRAM cannot be accessed in D3hot state,
12430          * so need make sure we're in D0.
12431          */
12432         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12433         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12434         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12435         msleep(1);
12436
12437         /* Make sure register accesses (indirect or otherwise)
12438          * will function correctly.
12439          */
12440         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12441                                tp->misc_host_ctrl);
12442
12443         /* The memory arbiter has to be enabled in order for SRAM accesses
12444          * to succeed.  Normally on powerup the tg3 chip firmware will make
12445          * sure it is enabled, but other entities such as system netboot
12446          * code might disable it.
12447          */
12448         val = tr32(MEMARB_MODE);
12449         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12450
12451         tp->phy_id = TG3_PHY_ID_INVALID;
12452         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12453
12454         /* Assume an onboard device and WOL capable by default.  */
12455         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12456
12457         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12458                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12459                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12460                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12461                 }
12462                 val = tr32(VCPU_CFGSHDW);
12463                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12464                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12465                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12466                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12467                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12468                 goto done;
12469         }
12470
12471         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12472         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12473                 u32 nic_cfg, led_cfg;
12474                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12475                 int eeprom_phy_serdes = 0;
12476
12477                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12478                 tp->nic_sram_data_cfg = nic_cfg;
12479
12480                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12481                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12482                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12483                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12484                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12485                     (ver > 0) && (ver < 0x100))
12486                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12487
12488                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12489                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12490
12491                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12492                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12493                         eeprom_phy_serdes = 1;
12494
12495                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12496                 if (nic_phy_id != 0) {
12497                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12498                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12499
12500                         eeprom_phy_id  = (id1 >> 16) << 10;
12501                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12502                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12503                 } else
12504                         eeprom_phy_id = 0;
12505
12506                 tp->phy_id = eeprom_phy_id;
12507                 if (eeprom_phy_serdes) {
12508                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12509                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12510                         else
12511                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12512                 }
12513
12514                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12515                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12516                                     SHASTA_EXT_LED_MODE_MASK);
12517                 else
12518                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12519
12520                 switch (led_cfg) {
12521                 default:
12522                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12523                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12524                         break;
12525
12526                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12527                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12528                         break;
12529
12530                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12531                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12532
12533                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12534                          * read on some older 5700/5701 bootcode.
12535                          */
12536                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12537                             ASIC_REV_5700 ||
12538                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12539                             ASIC_REV_5701)
12540                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12541
12542                         break;
12543
12544                 case SHASTA_EXT_LED_SHARED:
12545                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12546                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12547                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12548                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12549                                                  LED_CTRL_MODE_PHY_2);
12550                         break;
12551
12552                 case SHASTA_EXT_LED_MAC:
12553                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12554                         break;
12555
12556                 case SHASTA_EXT_LED_COMBO:
12557                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12558                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12559                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12560                                                  LED_CTRL_MODE_PHY_2);
12561                         break;
12562
12563                 }
12564
12565                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12566                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12567                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12568                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12569
12570                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12571                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12572
12573                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12574                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12575                         if ((tp->pdev->subsystem_vendor ==
12576                              PCI_VENDOR_ID_ARIMA) &&
12577                             (tp->pdev->subsystem_device == 0x205a ||
12578                              tp->pdev->subsystem_device == 0x2063))
12579                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12580                 } else {
12581                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12582                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12583                 }
12584
12585                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12586                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12587                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12588                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12589                 }
12590
12591                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12592                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12593                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12594
12595                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12596                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12597                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12598
12599                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12600                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12601                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12602
12603                 if (cfg2 & (1 << 17))
12604                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12605
12606                 /* serdes signal pre-emphasis in register 0x590 set by */
12607                 /* bootcode if bit 18 is set */
12608                 if (cfg2 & (1 << 18))
12609                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12610
12611                 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
12612                     ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12613                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12614                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12615                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12616
12617                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12618                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12619                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
12620                         u32 cfg3;
12621
12622                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12623                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12624                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12625                 }
12626
12627                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12628                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12629                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12630                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12631                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12632                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12633         }
12634 done:
12635         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12636                 device_set_wakeup_enable(&tp->pdev->dev,
12637                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12638         else
12639                 device_set_wakeup_capable(&tp->pdev->dev, false);
12640 }
12641
12642 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12643 {
12644         int i;
12645         u32 val;
12646
12647         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12648         tw32(OTP_CTRL, cmd);
12649
12650         /* Wait for up to 1 ms for command to execute. */
12651         for (i = 0; i < 100; i++) {
12652                 val = tr32(OTP_STATUS);
12653                 if (val & OTP_STATUS_CMD_DONE)
12654                         break;
12655                 udelay(10);
12656         }
12657
12658         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12659 }
12660
12661 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12662  * configuration is a 32-bit value that straddles the alignment boundary.
12663  * We do two 32-bit reads and then shift and merge the results.
12664  */
12665 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12666 {
12667         u32 bhalf_otp, thalf_otp;
12668
12669         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12670
12671         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12672                 return 0;
12673
12674         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12675
12676         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12677                 return 0;
12678
12679         thalf_otp = tr32(OTP_READ_DATA);
12680
12681         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12682
12683         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12684                 return 0;
12685
12686         bhalf_otp = tr32(OTP_READ_DATA);
12687
12688         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12689 }
12690
12691 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12692 {
12693         u32 adv = ADVERTISED_Autoneg |
12694                   ADVERTISED_Pause;
12695
12696         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12697                 adv |= ADVERTISED_1000baseT_Half |
12698                        ADVERTISED_1000baseT_Full;
12699
12700         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12701                 adv |= ADVERTISED_100baseT_Half |
12702                        ADVERTISED_100baseT_Full |
12703                        ADVERTISED_10baseT_Half |
12704                        ADVERTISED_10baseT_Full |
12705                        ADVERTISED_TP;
12706         else
12707                 adv |= ADVERTISED_FIBRE;
12708
12709         tp->link_config.advertising = adv;
12710         tp->link_config.speed = SPEED_INVALID;
12711         tp->link_config.duplex = DUPLEX_INVALID;
12712         tp->link_config.autoneg = AUTONEG_ENABLE;
12713         tp->link_config.active_speed = SPEED_INVALID;
12714         tp->link_config.active_duplex = DUPLEX_INVALID;
12715         tp->link_config.orig_speed = SPEED_INVALID;
12716         tp->link_config.orig_duplex = DUPLEX_INVALID;
12717         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12718 }
12719
12720 static int __devinit tg3_phy_probe(struct tg3 *tp)
12721 {
12722         u32 hw_phy_id_1, hw_phy_id_2;
12723         u32 hw_phy_id, hw_phy_id_masked;
12724         int err;
12725
12726         /* flow control autonegotiation is default behavior */
12727         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12728         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12729
12730         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12731                 return tg3_phy_init(tp);
12732
12733         /* Reading the PHY ID register can conflict with ASF
12734          * firmware access to the PHY hardware.
12735          */
12736         err = 0;
12737         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12738             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12739                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12740         } else {
12741                 /* Now read the physical PHY_ID from the chip and verify
12742                  * that it is sane.  If it doesn't look good, we fall back
12743                  * to either the hard-coded table based PHY_ID and failing
12744                  * that the value found in the eeprom area.
12745                  */
12746                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12747                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12748
12749                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12750                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12751                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12752
12753                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12754         }
12755
12756         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12757                 tp->phy_id = hw_phy_id;
12758                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12759                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12760                 else
12761                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12762         } else {
12763                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12764                         /* Do nothing, phy ID already set up in
12765                          * tg3_get_eeprom_hw_cfg().
12766                          */
12767                 } else {
12768                         struct subsys_tbl_ent *p;
12769
12770                         /* No eeprom signature?  Try the hardcoded
12771                          * subsys device table.
12772                          */
12773                         p = tg3_lookup_by_subsys(tp);
12774                         if (!p)
12775                                 return -ENODEV;
12776
12777                         tp->phy_id = p->phy_id;
12778                         if (!tp->phy_id ||
12779                             tp->phy_id == TG3_PHY_ID_BCM8002)
12780                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12781                 }
12782         }
12783
12784         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12785             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12786               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12787              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12788               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12789                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12790
12791         tg3_phy_init_link_config(tp);
12792
12793         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12794             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12795             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12796                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12797
12798                 tg3_readphy(tp, MII_BMSR, &bmsr);
12799                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12800                     (bmsr & BMSR_LSTATUS))
12801                         goto skip_phy_reset;
12802
12803                 err = tg3_phy_reset(tp);
12804                 if (err)
12805                         return err;
12806
12807                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12808                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12809                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12810                 tg3_ctrl = 0;
12811                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12812                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12813                                     MII_TG3_CTRL_ADV_1000_FULL);
12814                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12815                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12816                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12817                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12818                 }
12819
12820                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12821                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12822                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12823                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12824                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12825
12826                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12827                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12828
12829                         tg3_writephy(tp, MII_BMCR,
12830                                      BMCR_ANENABLE | BMCR_ANRESTART);
12831                 }
12832                 tg3_phy_set_wirespeed(tp);
12833
12834                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12835                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12836                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12837         }
12838
12839 skip_phy_reset:
12840         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12841                 err = tg3_init_5401phy_dsp(tp);
12842                 if (err)
12843                         return err;
12844
12845                 err = tg3_init_5401phy_dsp(tp);
12846         }
12847
12848         return err;
12849 }
12850
12851 static void __devinit tg3_read_vpd(struct tg3 *tp)
12852 {
12853         u8 *vpd_data;
12854         unsigned int block_end, rosize, len;
12855         int j, i = 0;
12856         u32 magic;
12857
12858         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12859             tg3_nvram_read(tp, 0x0, &magic))
12860                 goto out_no_vpd;
12861
12862         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12863         if (!vpd_data)
12864                 goto out_no_vpd;
12865
12866         if (magic == TG3_EEPROM_MAGIC) {
12867                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12868                         u32 tmp;
12869
12870                         /* The data is in little-endian format in NVRAM.
12871                          * Use the big-endian read routines to preserve
12872                          * the byte order as it exists in NVRAM.
12873                          */
12874                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12875                                 goto out_not_found;
12876
12877                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12878                 }
12879         } else {
12880                 ssize_t cnt;
12881                 unsigned int pos = 0;
12882
12883                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12884                         cnt = pci_read_vpd(tp->pdev, pos,
12885                                            TG3_NVM_VPD_LEN - pos,
12886                                            &vpd_data[pos]);
12887                         if (cnt == -ETIMEDOUT || cnt == -EINTR)
12888                                 cnt = 0;
12889                         else if (cnt < 0)
12890                                 goto out_not_found;
12891                 }
12892                 if (pos != TG3_NVM_VPD_LEN)
12893                         goto out_not_found;
12894         }
12895
12896         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12897                              PCI_VPD_LRDT_RO_DATA);
12898         if (i < 0)
12899                 goto out_not_found;
12900
12901         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12902         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12903         i += PCI_VPD_LRDT_TAG_SIZE;
12904
12905         if (block_end > TG3_NVM_VPD_LEN)
12906                 goto out_not_found;
12907
12908         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12909                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12910         if (j > 0) {
12911                 len = pci_vpd_info_field_size(&vpd_data[j]);
12912
12913                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12914                 if (j + len > block_end || len != 4 ||
12915                     memcmp(&vpd_data[j], "1028", 4))
12916                         goto partno;
12917
12918                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12919                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12920                 if (j < 0)
12921                         goto partno;
12922
12923                 len = pci_vpd_info_field_size(&vpd_data[j]);
12924
12925                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12926                 if (j + len > block_end)
12927                         goto partno;
12928
12929                 memcpy(tp->fw_ver, &vpd_data[j], len);
12930                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12931         }
12932
12933 partno:
12934         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12935                                       PCI_VPD_RO_KEYWORD_PARTNO);
12936         if (i < 0)
12937                 goto out_not_found;
12938
12939         len = pci_vpd_info_field_size(&vpd_data[i]);
12940
12941         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12942         if (len > TG3_BPN_SIZE ||
12943             (len + i) > TG3_NVM_VPD_LEN)
12944                 goto out_not_found;
12945
12946         memcpy(tp->board_part_number, &vpd_data[i], len);
12947
12948 out_not_found:
12949         kfree(vpd_data);
12950         if (tp->board_part_number[0])
12951                 return;
12952
12953 out_no_vpd:
12954         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12955                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12956                         strcpy(tp->board_part_number, "BCM5717");
12957                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12958                         strcpy(tp->board_part_number, "BCM5718");
12959                 else
12960                         goto nomatch;
12961         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12962                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12963                         strcpy(tp->board_part_number, "BCM57780");
12964                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12965                         strcpy(tp->board_part_number, "BCM57760");
12966                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12967                         strcpy(tp->board_part_number, "BCM57790");
12968                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12969                         strcpy(tp->board_part_number, "BCM57788");
12970                 else
12971                         goto nomatch;
12972         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12973                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12974                         strcpy(tp->board_part_number, "BCM57761");
12975                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12976                         strcpy(tp->board_part_number, "BCM57765");
12977                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12978                         strcpy(tp->board_part_number, "BCM57781");
12979                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12980                         strcpy(tp->board_part_number, "BCM57785");
12981                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12982                         strcpy(tp->board_part_number, "BCM57791");
12983                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12984                         strcpy(tp->board_part_number, "BCM57795");
12985                 else
12986                         goto nomatch;
12987         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12988                 strcpy(tp->board_part_number, "BCM95906");
12989         } else {
12990 nomatch:
12991                 strcpy(tp->board_part_number, "none");
12992         }
12993 }
12994
12995 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12996 {
12997         u32 val;
12998
12999         if (tg3_nvram_read(tp, offset, &val) ||
13000             (val & 0xfc000000) != 0x0c000000 ||
13001             tg3_nvram_read(tp, offset + 4, &val) ||
13002             val != 0)
13003                 return 0;
13004
13005         return 1;
13006 }
13007
13008 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13009 {
13010         u32 val, offset, start, ver_offset;
13011         int i, dst_off;
13012         bool newver = false;
13013
13014         if (tg3_nvram_read(tp, 0xc, &offset) ||
13015             tg3_nvram_read(tp, 0x4, &start))
13016                 return;
13017
13018         offset = tg3_nvram_logical_addr(tp, offset);
13019
13020         if (tg3_nvram_read(tp, offset, &val))
13021                 return;
13022
13023         if ((val & 0xfc000000) == 0x0c000000) {
13024                 if (tg3_nvram_read(tp, offset + 4, &val))
13025                         return;
13026
13027                 if (val == 0)
13028                         newver = true;
13029         }
13030
13031         dst_off = strlen(tp->fw_ver);
13032
13033         if (newver) {
13034                 if (TG3_VER_SIZE - dst_off < 16 ||
13035                     tg3_nvram_read(tp, offset + 8, &ver_offset))
13036                         return;
13037
13038                 offset = offset + ver_offset - start;
13039                 for (i = 0; i < 16; i += 4) {
13040                         __be32 v;
13041                         if (tg3_nvram_read_be32(tp, offset + i, &v))
13042                                 return;
13043
13044                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13045                 }
13046         } else {
13047                 u32 major, minor;
13048
13049                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13050                         return;
13051
13052                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13053                         TG3_NVM_BCVER_MAJSFT;
13054                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13055                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13056                          "v%d.%02d", major, minor);
13057         }
13058 }
13059
13060 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13061 {
13062         u32 val, major, minor;
13063
13064         /* Use native endian representation */
13065         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13066                 return;
13067
13068         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13069                 TG3_NVM_HWSB_CFG1_MAJSFT;
13070         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13071                 TG3_NVM_HWSB_CFG1_MINSFT;
13072
13073         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13074 }
13075
13076 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13077 {
13078         u32 offset, major, minor, build;
13079
13080         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13081
13082         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13083                 return;
13084
13085         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13086         case TG3_EEPROM_SB_REVISION_0:
13087                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13088                 break;
13089         case TG3_EEPROM_SB_REVISION_2:
13090                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13091                 break;
13092         case TG3_EEPROM_SB_REVISION_3:
13093                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13094                 break;
13095         case TG3_EEPROM_SB_REVISION_4:
13096                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13097                 break;
13098         case TG3_EEPROM_SB_REVISION_5:
13099                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13100                 break;
13101         case TG3_EEPROM_SB_REVISION_6:
13102                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13103                 break;
13104         default:
13105                 return;
13106         }
13107
13108         if (tg3_nvram_read(tp, offset, &val))
13109                 return;
13110
13111         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13112                 TG3_EEPROM_SB_EDH_BLD_SHFT;
13113         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13114                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13115         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
13116
13117         if (minor > 99 || build > 26)
13118                 return;
13119
13120         offset = strlen(tp->fw_ver);
13121         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13122                  " v%d.%02d", major, minor);
13123
13124         if (build > 0) {
13125                 offset = strlen(tp->fw_ver);
13126                 if (offset < TG3_VER_SIZE - 1)
13127                         tp->fw_ver[offset] = 'a' + build - 1;
13128         }
13129 }
13130
13131 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13132 {
13133         u32 val, offset, start;
13134         int i, vlen;
13135
13136         for (offset = TG3_NVM_DIR_START;
13137              offset < TG3_NVM_DIR_END;
13138              offset += TG3_NVM_DIRENT_SIZE) {
13139                 if (tg3_nvram_read(tp, offset, &val))
13140                         return;
13141
13142                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13143                         break;
13144         }
13145
13146         if (offset == TG3_NVM_DIR_END)
13147                 return;
13148
13149         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13150                 start = 0x08000000;
13151         else if (tg3_nvram_read(tp, offset - 4, &start))
13152                 return;
13153
13154         if (tg3_nvram_read(tp, offset + 4, &offset) ||
13155             !tg3_fw_img_is_valid(tp, offset) ||
13156             tg3_nvram_read(tp, offset + 8, &val))
13157                 return;
13158
13159         offset += val - start;
13160
13161         vlen = strlen(tp->fw_ver);
13162
13163         tp->fw_ver[vlen++] = ',';
13164         tp->fw_ver[vlen++] = ' ';
13165
13166         for (i = 0; i < 4; i++) {
13167                 __be32 v;
13168                 if (tg3_nvram_read_be32(tp, offset, &v))
13169                         return;
13170
13171                 offset += sizeof(v);
13172
13173                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13174                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13175                         break;
13176                 }
13177
13178                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13179                 vlen += sizeof(v);
13180         }
13181 }
13182
13183 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13184 {
13185         int vlen;
13186         u32 apedata;
13187         char *fwtype;
13188
13189         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13190             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
13191                 return;
13192
13193         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13194         if (apedata != APE_SEG_SIG_MAGIC)
13195                 return;
13196
13197         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13198         if (!(apedata & APE_FW_STATUS_READY))
13199                 return;
13200
13201         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13202
13203         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13204                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13205                 fwtype = "NCSI";
13206         } else {
13207                 fwtype = "DASH";
13208         }
13209
13210         vlen = strlen(tp->fw_ver);
13211
13212         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13213                  fwtype,
13214                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13215                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13216                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13217                  (apedata & APE_FW_VERSION_BLDMSK));
13218 }
13219
13220 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13221 {
13222         u32 val;
13223         bool vpd_vers = false;
13224
13225         if (tp->fw_ver[0] != 0)
13226                 vpd_vers = true;
13227
13228         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13229                 strcat(tp->fw_ver, "sb");
13230                 return;
13231         }
13232
13233         if (tg3_nvram_read(tp, 0, &val))
13234                 return;
13235
13236         if (val == TG3_EEPROM_MAGIC)
13237                 tg3_read_bc_ver(tp);
13238         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13239                 tg3_read_sb_ver(tp, val);
13240         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13241                 tg3_read_hwsb_ver(tp);
13242         else
13243                 return;
13244
13245         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13246              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13247                 goto done;
13248
13249         tg3_read_mgmtfw_ver(tp);
13250
13251 done:
13252         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13253 }
13254
13255 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13256
13257 static inline void vlan_features_add(struct net_device *dev, unsigned long flags)
13258 {
13259         dev->vlan_features |= flags;
13260 }
13261
13262 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13263 {
13264         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13265                 return TG3_RX_RET_MAX_SIZE_5717;
13266         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13267                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13268                 return TG3_RX_RET_MAX_SIZE_5700;
13269         else
13270                 return TG3_RX_RET_MAX_SIZE_5705;
13271 }
13272
13273 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13274         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13275         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13276         { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13277         { },
13278 };
13279
13280 static int __devinit tg3_get_invariants(struct tg3 *tp)
13281 {
13282         u32 misc_ctrl_reg;
13283         u32 pci_state_reg, grc_misc_cfg;
13284         u32 val;
13285         u16 pci_cmd;
13286         int err;
13287
13288         /* Force memory write invalidate off.  If we leave it on,
13289          * then on 5700_BX chips we have to enable a workaround.
13290          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13291          * to match the cacheline size.  The Broadcom driver have this
13292          * workaround but turns MWI off all the times so never uses
13293          * it.  This seems to suggest that the workaround is insufficient.
13294          */
13295         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13296         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13297         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13298
13299         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13300          * has the register indirect write enable bit set before
13301          * we try to access any of the MMIO registers.  It is also
13302          * critical that the PCI-X hw workaround situation is decided
13303          * before that as well.
13304          */
13305         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13306                               &misc_ctrl_reg);
13307
13308         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13309                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13310         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13311                 u32 prod_id_asic_rev;
13312
13313                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13314                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13315                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13316                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13317                         pci_read_config_dword(tp->pdev,
13318                                               TG3PCI_GEN2_PRODID_ASICREV,
13319                                               &prod_id_asic_rev);
13320                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13321                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13322                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13323                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13324                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13325                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13326                         pci_read_config_dword(tp->pdev,
13327                                               TG3PCI_GEN15_PRODID_ASICREV,
13328                                               &prod_id_asic_rev);
13329                 else
13330                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13331                                               &prod_id_asic_rev);
13332
13333                 tp->pci_chip_rev_id = prod_id_asic_rev;
13334         }
13335
13336         /* Wrong chip ID in 5752 A0. This code can be removed later
13337          * as A0 is not in production.
13338          */
13339         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13340                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13341
13342         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13343          * we need to disable memory and use config. cycles
13344          * only to access all registers. The 5702/03 chips
13345          * can mistakenly decode the special cycles from the
13346          * ICH chipsets as memory write cycles, causing corruption
13347          * of register and memory space. Only certain ICH bridges
13348          * will drive special cycles with non-zero data during the
13349          * address phase which can fall within the 5703's address
13350          * range. This is not an ICH bug as the PCI spec allows
13351          * non-zero address during special cycles. However, only
13352          * these ICH bridges are known to drive non-zero addresses
13353          * during special cycles.
13354          *
13355          * Since special cycles do not cross PCI bridges, we only
13356          * enable this workaround if the 5703 is on the secondary
13357          * bus of these ICH bridges.
13358          */
13359         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13360             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13361                 static struct tg3_dev_id {
13362                         u32     vendor;
13363                         u32     device;
13364                         u32     rev;
13365                 } ich_chipsets[] = {
13366                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13367                           PCI_ANY_ID },
13368                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13369                           PCI_ANY_ID },
13370                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13371                           0xa },
13372                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13373                           PCI_ANY_ID },
13374                         { },
13375                 };
13376                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13377                 struct pci_dev *bridge = NULL;
13378
13379                 while (pci_id->vendor != 0) {
13380                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13381                                                 bridge);
13382                         if (!bridge) {
13383                                 pci_id++;
13384                                 continue;
13385                         }
13386                         if (pci_id->rev != PCI_ANY_ID) {
13387                                 if (bridge->revision > pci_id->rev)
13388                                         continue;
13389                         }
13390                         if (bridge->subordinate &&
13391                             (bridge->subordinate->number ==
13392                              tp->pdev->bus->number)) {
13393
13394                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13395                                 pci_dev_put(bridge);
13396                                 break;
13397                         }
13398                 }
13399         }
13400
13401         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13402                 static struct tg3_dev_id {
13403                         u32     vendor;
13404                         u32     device;
13405                 } bridge_chipsets[] = {
13406                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13407                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13408                         { },
13409                 };
13410                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13411                 struct pci_dev *bridge = NULL;
13412
13413                 while (pci_id->vendor != 0) {
13414                         bridge = pci_get_device(pci_id->vendor,
13415                                                 pci_id->device,
13416                                                 bridge);
13417                         if (!bridge) {
13418                                 pci_id++;
13419                                 continue;
13420                         }
13421                         if (bridge->subordinate &&
13422                             (bridge->subordinate->number <=
13423                              tp->pdev->bus->number) &&
13424                             (bridge->subordinate->subordinate >=
13425                              tp->pdev->bus->number)) {
13426                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13427                                 pci_dev_put(bridge);
13428                                 break;
13429                         }
13430                 }
13431         }
13432
13433         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13434          * DMA addresses > 40-bit. This bridge may have other additional
13435          * 57xx devices behind it in some 4-port NIC designs for example.
13436          * Any tg3 device found behind the bridge will also need the 40-bit
13437          * DMA workaround.
13438          */
13439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13440             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13441                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13442                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13443                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13444         } else {
13445                 struct pci_dev *bridge = NULL;
13446
13447                 do {
13448                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13449                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13450                                                 bridge);
13451                         if (bridge && bridge->subordinate &&
13452                             (bridge->subordinate->number <=
13453                              tp->pdev->bus->number) &&
13454                             (bridge->subordinate->subordinate >=
13455                              tp->pdev->bus->number)) {
13456                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13457                                 pci_dev_put(bridge);
13458                                 break;
13459                         }
13460                 } while (bridge);
13461         }
13462
13463         /* Initialize misc host control in PCI block. */
13464         tp->misc_host_ctrl |= (misc_ctrl_reg &
13465                                MISC_HOST_CTRL_CHIPREV);
13466         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13467                                tp->misc_host_ctrl);
13468
13469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13470             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13471             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13472             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13473                 tp->pdev_peer = tg3_find_peer(tp);
13474
13475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13476             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13478                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13479
13480         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13481             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13482                 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
13483
13484         /* Intentionally exclude ASIC_REV_5906 */
13485         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13486             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13489             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13490             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13491             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13492                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13493
13494         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13495             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13496             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13497             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13498             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13499                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13500
13501         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13502             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13503                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13504
13505         /* 5700 B0 chips do not support checksumming correctly due
13506          * to hardware bugs.
13507          */
13508         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13509                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13510         else {
13511                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13512
13513                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13514                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13515                         features |= NETIF_F_IPV6_CSUM;
13516                 tp->dev->features |= features;
13517                 vlan_features_add(tp->dev, features);
13518         }
13519
13520         /* Determine TSO capabilities */
13521         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13522                 ; /* Do nothing. HW bug. */
13523         else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
13524                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13525         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13526                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13527                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13528         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13529                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13530                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13531                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13532                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13533         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13534                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13535                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13536                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13537                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13538                         tp->fw_needed = FIRMWARE_TG3TSO5;
13539                 else
13540                         tp->fw_needed = FIRMWARE_TG3TSO;
13541         }
13542
13543         tp->irq_max = 1;
13544
13545         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13546                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13547                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13548                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13549                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13550                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13551                      tp->pdev_peer == tp->pdev))
13552                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13553
13554                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13555                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13556                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13557                 }
13558
13559                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
13560                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13561                         tp->irq_max = TG3_IRQ_MAX_VECS;
13562                 }
13563         }
13564
13565         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13566             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13568                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13569         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13570                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13571                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13572         }
13573
13574         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13575                 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13576
13577         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
13578             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13579                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13580
13581         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13582             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13583             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13584                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13585
13586         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13587                               &pci_state_reg);
13588
13589         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13590         if (tp->pcie_cap != 0) {
13591                 u16 lnkctl;
13592
13593                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13594
13595                 tp->pcie_readrq = 4096;
13596                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13597                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13598                         tp->pcie_readrq = 2048;
13599
13600                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13601
13602                 pci_read_config_word(tp->pdev,
13603                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13604                                      &lnkctl);
13605                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13606                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13607                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13608                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13609                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13610                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13611                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13612                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13613                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13614                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13615                 }
13616         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13617                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13618         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13619                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13620                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13621                 if (!tp->pcix_cap) {
13622                         dev_err(&tp->pdev->dev,
13623                                 "Cannot find PCI-X capability, aborting\n");
13624                         return -EIO;
13625                 }
13626
13627                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13628                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13629         }
13630
13631         /* If we have an AMD 762 or VIA K8T800 chipset, write
13632          * reordering to the mailbox registers done by the host
13633          * controller can cause major troubles.  We read back from
13634          * every mailbox register write to force the writes to be
13635          * posted to the chip in order.
13636          */
13637         if (pci_dev_present(tg3_write_reorder_chipsets) &&
13638             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13639                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13640
13641         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13642                              &tp->pci_cacheline_sz);
13643         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13644                              &tp->pci_lat_timer);
13645         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13646             tp->pci_lat_timer < 64) {
13647                 tp->pci_lat_timer = 64;
13648                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13649                                       tp->pci_lat_timer);
13650         }
13651
13652         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13653                 /* 5700 BX chips need to have their TX producer index
13654                  * mailboxes written twice to workaround a bug.
13655                  */
13656                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13657
13658                 /* If we are in PCI-X mode, enable register write workaround.
13659                  *
13660                  * The workaround is to use indirect register accesses
13661                  * for all chip writes not to mailbox registers.
13662                  */
13663                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13664                         u32 pm_reg;
13665
13666                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13667
13668                         /* The chip can have it's power management PCI config
13669                          * space registers clobbered due to this bug.
13670                          * So explicitly force the chip into D0 here.
13671                          */
13672                         pci_read_config_dword(tp->pdev,
13673                                               tp->pm_cap + PCI_PM_CTRL,
13674                                               &pm_reg);
13675                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13676                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13677                         pci_write_config_dword(tp->pdev,
13678                                                tp->pm_cap + PCI_PM_CTRL,
13679                                                pm_reg);
13680
13681                         /* Also, force SERR#/PERR# in PCI command. */
13682                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13683                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13684                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13685                 }
13686         }
13687
13688         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13689                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13690         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13691                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13692
13693         /* Chip-specific fixup from Broadcom driver */
13694         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13695             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13696                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13697                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13698         }
13699
13700         /* Default fast path register access methods */
13701         tp->read32 = tg3_read32;
13702         tp->write32 = tg3_write32;
13703         tp->read32_mbox = tg3_read32;
13704         tp->write32_mbox = tg3_write32;
13705         tp->write32_tx_mbox = tg3_write32;
13706         tp->write32_rx_mbox = tg3_write32;
13707
13708         /* Various workaround register access methods */
13709         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13710                 tp->write32 = tg3_write_indirect_reg32;
13711         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13712                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13713                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13714                 /*
13715                  * Back to back register writes can cause problems on these
13716                  * chips, the workaround is to read back all reg writes
13717                  * except those to mailbox regs.
13718                  *
13719                  * See tg3_write_indirect_reg32().
13720                  */
13721                 tp->write32 = tg3_write_flush_reg32;
13722         }
13723
13724         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13725             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13726                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13727                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13728                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13729         }
13730
13731         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13732                 tp->read32 = tg3_read_indirect_reg32;
13733                 tp->write32 = tg3_write_indirect_reg32;
13734                 tp->read32_mbox = tg3_read_indirect_mbox;
13735                 tp->write32_mbox = tg3_write_indirect_mbox;
13736                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13737                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13738
13739                 iounmap(tp->regs);
13740                 tp->regs = NULL;
13741
13742                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13743                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13744                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13745         }
13746         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13747                 tp->read32_mbox = tg3_read32_mbox_5906;
13748                 tp->write32_mbox = tg3_write32_mbox_5906;
13749                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13750                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13751         }
13752
13753         if (tp->write32 == tg3_write_indirect_reg32 ||
13754             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13755              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13756               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13757                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13758
13759         /* Get eeprom hw config before calling tg3_set_power_state().
13760          * In particular, the TG3_FLG2_IS_NIC flag must be
13761          * determined before calling tg3_set_power_state() so that
13762          * we know whether or not to switch out of Vaux power.
13763          * When the flag is set, it means that GPIO1 is used for eeprom
13764          * write protect and also implies that it is a LOM where GPIOs
13765          * are not used to switch power.
13766          */
13767         tg3_get_eeprom_hw_cfg(tp);
13768
13769         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13770                 /* Allow reads and writes to the
13771                  * APE register and memory space.
13772                  */
13773                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13774                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13775                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13776                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13777                                        pci_state_reg);
13778         }
13779
13780         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13781             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13782             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13783             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13784             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13785                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13786
13787         /* Set up tp->grc_local_ctrl before calling tg_power_up().
13788          * GPIO1 driven high will bring 5700's external PHY out of reset.
13789          * It is also used as eeprom write protect on LOMs.
13790          */
13791         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13792         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13793             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13794                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13795                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13796         /* Unused GPIO3 must be driven as output on 5752 because there
13797          * are no pull-up resistors on unused GPIO pins.
13798          */
13799         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13800                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13801
13802         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13804             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13805                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13806
13807         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13808             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13809                 /* Turn off the debug UART. */
13810                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13811                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13812                         /* Keep VMain power. */
13813                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13814                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13815         }
13816
13817         /* Force the chip into D0. */
13818         err = tg3_power_up(tp);
13819         if (err) {
13820                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13821                 return err;
13822         }
13823
13824         /* Derive initial jumbo mode from MTU assigned in
13825          * ether_setup() via the alloc_etherdev() call
13826          */
13827         if (tp->dev->mtu > ETH_DATA_LEN &&
13828             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13829                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13830
13831         /* Determine WakeOnLan speed to use. */
13832         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13833             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13834             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13835             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13836                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13837         } else {
13838                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13839         }
13840
13841         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13842                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13843
13844         /* A few boards don't want Ethernet@WireSpeed phy feature */
13845         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13846             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13847              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13848              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13849             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13850             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13851                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13852
13853         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13854             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13855                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13856         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13857                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13858
13859         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13860             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13861             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13862             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13863             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
13864                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13865                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13866                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13867                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13868                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13869                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13870                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13871                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13872                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13873                 } else
13874                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13875         }
13876
13877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13878             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13879                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13880                 if (tp->phy_otp == 0)
13881                         tp->phy_otp = TG3_OTP_DEFAULT;
13882         }
13883
13884         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13885                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13886         else
13887                 tp->mi_mode = MAC_MI_MODE_BASE;
13888
13889         tp->coalesce_mode = 0;
13890         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13891             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13892                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13893
13894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13895             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13896                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13897
13898         err = tg3_mdio_init(tp);
13899         if (err)
13900                 return err;
13901
13902         /* Initialize data/descriptor byte/word swapping. */
13903         val = tr32(GRC_MODE);
13904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13905                 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
13906                         GRC_MODE_WORD_SWAP_B2HRX_DATA |
13907                         GRC_MODE_B2HRX_ENABLE |
13908                         GRC_MODE_HTX2B_ENABLE |
13909                         GRC_MODE_HOST_STACKUP);
13910         else
13911                 val &= GRC_MODE_HOST_STACKUP;
13912
13913         tw32(GRC_MODE, val | tp->grc_mode);
13914
13915         tg3_switch_clocks(tp);
13916
13917         /* Clear this out for sanity. */
13918         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13919
13920         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13921                               &pci_state_reg);
13922         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13923             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13924                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13925
13926                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13927                     chiprevid == CHIPREV_ID_5701_B0 ||
13928                     chiprevid == CHIPREV_ID_5701_B2 ||
13929                     chiprevid == CHIPREV_ID_5701_B5) {
13930                         void __iomem *sram_base;
13931
13932                         /* Write some dummy words into the SRAM status block
13933                          * area, see if it reads back correctly.  If the return
13934                          * value is bad, force enable the PCIX workaround.
13935                          */
13936                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13937
13938                         writel(0x00000000, sram_base);
13939                         writel(0x00000000, sram_base + 4);
13940                         writel(0xffffffff, sram_base + 4);
13941                         if (readl(sram_base) != 0x00000000)
13942                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13943                 }
13944         }
13945
13946         udelay(50);
13947         tg3_nvram_init(tp);
13948
13949         grc_misc_cfg = tr32(GRC_MISC_CFG);
13950         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13951
13952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13953             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13954              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13955                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13956
13957         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13958             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13959                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13960         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13961                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13962                                       HOSTCC_MODE_CLRTICK_TXBD);
13963
13964                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13965                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13966                                        tp->misc_host_ctrl);
13967         }
13968
13969         /* Preserve the APE MAC_MODE bits */
13970         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13971                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13972         else
13973                 tp->mac_mode = TG3_DEF_MAC_MODE;
13974
13975         /* these are limited to 10/100 only */
13976         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13977              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13978             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13979              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13980              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13981               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13982               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13983             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13984              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13985               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13986               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13987             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13988             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13989             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13990             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13991                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13992
13993         err = tg3_phy_probe(tp);
13994         if (err) {
13995                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13996                 /* ... but do not return immediately ... */
13997                 tg3_mdio_fini(tp);
13998         }
13999
14000         tg3_read_vpd(tp);
14001         tg3_read_fw_ver(tp);
14002
14003         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14004                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14005         } else {
14006                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14007                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14008                 else
14009                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14010         }
14011
14012         /* 5700 {AX,BX} chips have a broken status block link
14013          * change bit implementation, so we must use the
14014          * status register in those cases.
14015          */
14016         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14017                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14018         else
14019                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
14020
14021         /* The led_ctrl is set during tg3_phy_probe, here we might
14022          * have to force the link status polling mechanism based
14023          * upon subsystem IDs.
14024          */
14025         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14027             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14028                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14029                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14030         }
14031
14032         /* For all SERDES we poll the MAC status register. */
14033         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14034                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
14035         else
14036                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
14037
14038         tp->rx_offset = NET_IP_ALIGN;
14039         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14041             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
14042                 tp->rx_offset = 0;
14043 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14044                 tp->rx_copy_thresh = ~(u16)0;
14045 #endif
14046         }
14047
14048         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14049         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14050         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14051
14052         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14053
14054         /* Increment the rx prod index on the rx std ring by at most
14055          * 8 for these chips to workaround hw errata.
14056          */
14057         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14058             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14059             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14060                 tp->rx_std_max_post = 8;
14061
14062         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
14063                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14064                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
14065
14066         return err;
14067 }
14068
14069 #ifdef CONFIG_SPARC
14070 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14071 {
14072         struct net_device *dev = tp->dev;
14073         struct pci_dev *pdev = tp->pdev;
14074         struct device_node *dp = pci_device_to_OF_node(pdev);
14075         const unsigned char *addr;
14076         int len;
14077
14078         addr = of_get_property(dp, "local-mac-address", &len);
14079         if (addr && len == 6) {
14080                 memcpy(dev->dev_addr, addr, 6);
14081                 memcpy(dev->perm_addr, dev->dev_addr, 6);
14082                 return 0;
14083         }
14084         return -ENODEV;
14085 }
14086
14087 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14088 {
14089         struct net_device *dev = tp->dev;
14090
14091         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14092         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14093         return 0;
14094 }
14095 #endif
14096
14097 static int __devinit tg3_get_device_address(struct tg3 *tp)
14098 {
14099         struct net_device *dev = tp->dev;
14100         u32 hi, lo, mac_offset;
14101         int addr_ok = 0;
14102
14103 #ifdef CONFIG_SPARC
14104         if (!tg3_get_macaddr_sparc(tp))
14105                 return 0;
14106 #endif
14107
14108         mac_offset = 0x7c;
14109         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14110             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
14111                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14112                         mac_offset = 0xcc;
14113                 if (tg3_nvram_lock(tp))
14114                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14115                 else
14116                         tg3_nvram_unlock(tp);
14117         } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14118                 if (PCI_FUNC(tp->pdev->devfn) & 1)
14119                         mac_offset = 0xcc;
14120                 if (PCI_FUNC(tp->pdev->devfn) > 1)
14121                         mac_offset += 0x18c;
14122         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14123                 mac_offset = 0x10;
14124
14125         /* First try to get it from MAC address mailbox. */
14126         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14127         if ((hi >> 16) == 0x484b) {
14128                 dev->dev_addr[0] = (hi >>  8) & 0xff;
14129                 dev->dev_addr[1] = (hi >>  0) & 0xff;
14130
14131                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14132                 dev->dev_addr[2] = (lo >> 24) & 0xff;
14133                 dev->dev_addr[3] = (lo >> 16) & 0xff;
14134                 dev->dev_addr[4] = (lo >>  8) & 0xff;
14135                 dev->dev_addr[5] = (lo >>  0) & 0xff;
14136
14137                 /* Some old bootcode may report a 0 MAC address in SRAM */
14138                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14139         }
14140         if (!addr_ok) {
14141                 /* Next, try NVRAM. */
14142                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
14143                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14144                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14145                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14146                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14147                 }
14148                 /* Finally just fetch it out of the MAC control regs. */
14149                 else {
14150                         hi = tr32(MAC_ADDR_0_HIGH);
14151                         lo = tr32(MAC_ADDR_0_LOW);
14152
14153                         dev->dev_addr[5] = lo & 0xff;
14154                         dev->dev_addr[4] = (lo >> 8) & 0xff;
14155                         dev->dev_addr[3] = (lo >> 16) & 0xff;
14156                         dev->dev_addr[2] = (lo >> 24) & 0xff;
14157                         dev->dev_addr[1] = hi & 0xff;
14158                         dev->dev_addr[0] = (hi >> 8) & 0xff;
14159                 }
14160         }
14161
14162         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14163 #ifdef CONFIG_SPARC
14164                 if (!tg3_get_default_macaddr_sparc(tp))
14165                         return 0;
14166 #endif
14167                 return -EINVAL;
14168         }
14169         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14170         return 0;
14171 }
14172
14173 #define BOUNDARY_SINGLE_CACHELINE       1
14174 #define BOUNDARY_MULTI_CACHELINE        2
14175
14176 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14177 {
14178         int cacheline_size;
14179         u8 byte;
14180         int goal;
14181
14182         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14183         if (byte == 0)
14184                 cacheline_size = 1024;
14185         else
14186                 cacheline_size = (int) byte * 4;
14187
14188         /* On 5703 and later chips, the boundary bits have no
14189          * effect.
14190          */
14191         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14192             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14193             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14194                 goto out;
14195
14196 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14197         goal = BOUNDARY_MULTI_CACHELINE;
14198 #else
14199 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14200         goal = BOUNDARY_SINGLE_CACHELINE;
14201 #else
14202         goal = 0;
14203 #endif
14204 #endif
14205
14206         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14207                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14208                 goto out;
14209         }
14210
14211         if (!goal)
14212                 goto out;
14213
14214         /* PCI controllers on most RISC systems tend to disconnect
14215          * when a device tries to burst across a cache-line boundary.
14216          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14217          *
14218          * Unfortunately, for PCI-E there are only limited
14219          * write-side controls for this, and thus for reads
14220          * we will still get the disconnects.  We'll also waste
14221          * these PCI cycles for both read and write for chips
14222          * other than 5700 and 5701 which do not implement the
14223          * boundary bits.
14224          */
14225         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14226             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14227                 switch (cacheline_size) {
14228                 case 16:
14229                 case 32:
14230                 case 64:
14231                 case 128:
14232                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14233                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14234                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14235                         } else {
14236                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14237                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14238                         }
14239                         break;
14240
14241                 case 256:
14242                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14243                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14244                         break;
14245
14246                 default:
14247                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14248                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14249                         break;
14250                 }
14251         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14252                 switch (cacheline_size) {
14253                 case 16:
14254                 case 32:
14255                 case 64:
14256                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14257                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14258                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14259                                 break;
14260                         }
14261                         /* fallthrough */
14262                 case 128:
14263                 default:
14264                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14265                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14266                         break;
14267                 }
14268         } else {
14269                 switch (cacheline_size) {
14270                 case 16:
14271                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14272                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14273                                         DMA_RWCTRL_WRITE_BNDRY_16);
14274                                 break;
14275                         }
14276                         /* fallthrough */
14277                 case 32:
14278                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14279                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14280                                         DMA_RWCTRL_WRITE_BNDRY_32);
14281                                 break;
14282                         }
14283                         /* fallthrough */
14284                 case 64:
14285                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14286                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14287                                         DMA_RWCTRL_WRITE_BNDRY_64);
14288                                 break;
14289                         }
14290                         /* fallthrough */
14291                 case 128:
14292                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14293                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14294                                         DMA_RWCTRL_WRITE_BNDRY_128);
14295                                 break;
14296                         }
14297                         /* fallthrough */
14298                 case 256:
14299                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14300                                 DMA_RWCTRL_WRITE_BNDRY_256);
14301                         break;
14302                 case 512:
14303                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14304                                 DMA_RWCTRL_WRITE_BNDRY_512);
14305                         break;
14306                 case 1024:
14307                 default:
14308                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14309                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14310                         break;
14311                 }
14312         }
14313
14314 out:
14315         return val;
14316 }
14317
14318 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14319 {
14320         struct tg3_internal_buffer_desc test_desc;
14321         u32 sram_dma_descs;
14322         int i, ret;
14323
14324         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14325
14326         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14327         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14328         tw32(RDMAC_STATUS, 0);
14329         tw32(WDMAC_STATUS, 0);
14330
14331         tw32(BUFMGR_MODE, 0);
14332         tw32(FTQ_RESET, 0);
14333
14334         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14335         test_desc.addr_lo = buf_dma & 0xffffffff;
14336         test_desc.nic_mbuf = 0x00002100;
14337         test_desc.len = size;
14338
14339         /*
14340          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14341          * the *second* time the tg3 driver was getting loaded after an
14342          * initial scan.
14343          *
14344          * Broadcom tells me:
14345          *   ...the DMA engine is connected to the GRC block and a DMA
14346          *   reset may affect the GRC block in some unpredictable way...
14347          *   The behavior of resets to individual blocks has not been tested.
14348          *
14349          * Broadcom noted the GRC reset will also reset all sub-components.
14350          */
14351         if (to_device) {
14352                 test_desc.cqid_sqid = (13 << 8) | 2;
14353
14354                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14355                 udelay(40);
14356         } else {
14357                 test_desc.cqid_sqid = (16 << 8) | 7;
14358
14359                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14360                 udelay(40);
14361         }
14362         test_desc.flags = 0x00000005;
14363
14364         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14365                 u32 val;
14366
14367                 val = *(((u32 *)&test_desc) + i);
14368                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14369                                        sram_dma_descs + (i * sizeof(u32)));
14370                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14371         }
14372         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14373
14374         if (to_device)
14375                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14376         else
14377                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14378
14379         ret = -ENODEV;
14380         for (i = 0; i < 40; i++) {
14381                 u32 val;
14382
14383                 if (to_device)
14384                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14385                 else
14386                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14387                 if ((val & 0xffff) == sram_dma_descs) {
14388                         ret = 0;
14389                         break;
14390                 }
14391
14392                 udelay(100);
14393         }
14394
14395         return ret;
14396 }
14397
14398 #define TEST_BUFFER_SIZE        0x2000
14399
14400 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14401         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14402         { },
14403 };
14404
14405 static int __devinit tg3_test_dma(struct tg3 *tp)
14406 {
14407         dma_addr_t buf_dma;
14408         u32 *buf, saved_dma_rwctrl;
14409         int ret = 0;
14410
14411         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14412                                  &buf_dma, GFP_KERNEL);
14413         if (!buf) {
14414                 ret = -ENOMEM;
14415                 goto out_nofree;
14416         }
14417
14418         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14419                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14420
14421         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14422
14423         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
14424                 goto out;
14425
14426         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14427                 /* DMA read watermark not used on PCIE */
14428                 tp->dma_rwctrl |= 0x00180000;
14429         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14430                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14431                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14432                         tp->dma_rwctrl |= 0x003f0000;
14433                 else
14434                         tp->dma_rwctrl |= 0x003f000f;
14435         } else {
14436                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14437                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14438                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14439                         u32 read_water = 0x7;
14440
14441                         /* If the 5704 is behind the EPB bridge, we can
14442                          * do the less restrictive ONE_DMA workaround for
14443                          * better performance.
14444                          */
14445                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14446                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14447                                 tp->dma_rwctrl |= 0x8000;
14448                         else if (ccval == 0x6 || ccval == 0x7)
14449                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14450
14451                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14452                                 read_water = 4;
14453                         /* Set bit 23 to enable PCIX hw bug fix */
14454                         tp->dma_rwctrl |=
14455                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14456                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14457                                 (1 << 23);
14458                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14459                         /* 5780 always in PCIX mode */
14460                         tp->dma_rwctrl |= 0x00144000;
14461                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14462                         /* 5714 always in PCIX mode */
14463                         tp->dma_rwctrl |= 0x00148000;
14464                 } else {
14465                         tp->dma_rwctrl |= 0x001b000f;
14466                 }
14467         }
14468
14469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14470             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14471                 tp->dma_rwctrl &= 0xfffffff0;
14472
14473         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14474             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14475                 /* Remove this if it causes problems for some boards. */
14476                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14477
14478                 /* On 5700/5701 chips, we need to set this bit.
14479                  * Otherwise the chip will issue cacheline transactions
14480                  * to streamable DMA memory with not all the byte
14481                  * enables turned on.  This is an error on several
14482                  * RISC PCI controllers, in particular sparc64.
14483                  *
14484                  * On 5703/5704 chips, this bit has been reassigned
14485                  * a different meaning.  In particular, it is used
14486                  * on those chips to enable a PCI-X workaround.
14487                  */
14488                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14489         }
14490
14491         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14492
14493 #if 0
14494         /* Unneeded, already done by tg3_get_invariants.  */
14495         tg3_switch_clocks(tp);
14496 #endif
14497
14498         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14499             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14500                 goto out;
14501
14502         /* It is best to perform DMA test with maximum write burst size
14503          * to expose the 5700/5701 write DMA bug.
14504          */
14505         saved_dma_rwctrl = tp->dma_rwctrl;
14506         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14507         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14508
14509         while (1) {
14510                 u32 *p = buf, i;
14511
14512                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14513                         p[i] = i;
14514
14515                 /* Send the buffer to the chip. */
14516                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14517                 if (ret) {
14518                         dev_err(&tp->pdev->dev,
14519                                 "%s: Buffer write failed. err = %d\n",
14520                                 __func__, ret);
14521                         break;
14522                 }
14523
14524 #if 0
14525                 /* validate data reached card RAM correctly. */
14526                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14527                         u32 val;
14528                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14529                         if (le32_to_cpu(val) != p[i]) {
14530                                 dev_err(&tp->pdev->dev,
14531                                         "%s: Buffer corrupted on device! "
14532                                         "(%d != %d)\n", __func__, val, i);
14533                                 /* ret = -ENODEV here? */
14534                         }
14535                         p[i] = 0;
14536                 }
14537 #endif
14538                 /* Now read it back. */
14539                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14540                 if (ret) {
14541                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14542                                 "err = %d\n", __func__, ret);
14543                         break;
14544                 }
14545
14546                 /* Verify it. */
14547                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14548                         if (p[i] == i)
14549                                 continue;
14550
14551                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14552                             DMA_RWCTRL_WRITE_BNDRY_16) {
14553                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14554                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14555                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14556                                 break;
14557                         } else {
14558                                 dev_err(&tp->pdev->dev,
14559                                         "%s: Buffer corrupted on read back! "
14560                                         "(%d != %d)\n", __func__, p[i], i);
14561                                 ret = -ENODEV;
14562                                 goto out;
14563                         }
14564                 }
14565
14566                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14567                         /* Success. */
14568                         ret = 0;
14569                         break;
14570                 }
14571         }
14572         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14573             DMA_RWCTRL_WRITE_BNDRY_16) {
14574
14575                 /* DMA test passed without adjusting DMA boundary,
14576                  * now look for chipsets that are known to expose the
14577                  * DMA bug without failing the test.
14578                  */
14579                 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14580                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14581                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14582                 } else {
14583                         /* Safe to use the calculated DMA boundary. */
14584                         tp->dma_rwctrl = saved_dma_rwctrl;
14585                 }
14586
14587                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14588         }
14589
14590 out:
14591         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14592 out_nofree:
14593         return ret;
14594 }
14595
14596 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14597 {
14598         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14599                 tp->bufmgr_config.mbuf_read_dma_low_water =
14600                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14601                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14602                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14603                 tp->bufmgr_config.mbuf_high_water =
14604                         DEFAULT_MB_HIGH_WATER_57765;
14605
14606                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14607                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14608                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14609                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14610                 tp->bufmgr_config.mbuf_high_water_jumbo =
14611                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14612         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14613                 tp->bufmgr_config.mbuf_read_dma_low_water =
14614                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14615                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14616                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14617                 tp->bufmgr_config.mbuf_high_water =
14618                         DEFAULT_MB_HIGH_WATER_5705;
14619                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14620                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14621                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14622                         tp->bufmgr_config.mbuf_high_water =
14623                                 DEFAULT_MB_HIGH_WATER_5906;
14624                 }
14625
14626                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14627                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14628                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14629                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14630                 tp->bufmgr_config.mbuf_high_water_jumbo =
14631                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14632         } else {
14633                 tp->bufmgr_config.mbuf_read_dma_low_water =
14634                         DEFAULT_MB_RDMA_LOW_WATER;
14635                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14636                         DEFAULT_MB_MACRX_LOW_WATER;
14637                 tp->bufmgr_config.mbuf_high_water =
14638                         DEFAULT_MB_HIGH_WATER;
14639
14640                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14641                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14642                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14643                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14644                 tp->bufmgr_config.mbuf_high_water_jumbo =
14645                         DEFAULT_MB_HIGH_WATER_JUMBO;
14646         }
14647
14648         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14649         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14650 }
14651
14652 static char * __devinit tg3_phy_string(struct tg3 *tp)
14653 {
14654         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14655         case TG3_PHY_ID_BCM5400:        return "5400";
14656         case TG3_PHY_ID_BCM5401:        return "5401";
14657         case TG3_PHY_ID_BCM5411:        return "5411";
14658         case TG3_PHY_ID_BCM5701:        return "5701";
14659         case TG3_PHY_ID_BCM5703:        return "5703";
14660         case TG3_PHY_ID_BCM5704:        return "5704";
14661         case TG3_PHY_ID_BCM5705:        return "5705";
14662         case TG3_PHY_ID_BCM5750:        return "5750";
14663         case TG3_PHY_ID_BCM5752:        return "5752";
14664         case TG3_PHY_ID_BCM5714:        return "5714";
14665         case TG3_PHY_ID_BCM5780:        return "5780";
14666         case TG3_PHY_ID_BCM5755:        return "5755";
14667         case TG3_PHY_ID_BCM5787:        return "5787";
14668         case TG3_PHY_ID_BCM5784:        return "5784";
14669         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14670         case TG3_PHY_ID_BCM5906:        return "5906";
14671         case TG3_PHY_ID_BCM5761:        return "5761";
14672         case TG3_PHY_ID_BCM5718C:       return "5718C";
14673         case TG3_PHY_ID_BCM5718S:       return "5718S";
14674         case TG3_PHY_ID_BCM57765:       return "57765";
14675         case TG3_PHY_ID_BCM5719C:       return "5719C";
14676         case TG3_PHY_ID_BCM5720C:       return "5720C";
14677         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14678         case 0:                 return "serdes";
14679         default:                return "unknown";
14680         }
14681 }
14682
14683 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14684 {
14685         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14686                 strcpy(str, "PCI Express");
14687                 return str;
14688         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14689                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14690
14691                 strcpy(str, "PCIX:");
14692
14693                 if ((clock_ctrl == 7) ||
14694                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14695                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14696                         strcat(str, "133MHz");
14697                 else if (clock_ctrl == 0)
14698                         strcat(str, "33MHz");
14699                 else if (clock_ctrl == 2)
14700                         strcat(str, "50MHz");
14701                 else if (clock_ctrl == 4)
14702                         strcat(str, "66MHz");
14703                 else if (clock_ctrl == 6)
14704                         strcat(str, "100MHz");
14705         } else {
14706                 strcpy(str, "PCI:");
14707                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14708                         strcat(str, "66MHz");
14709                 else
14710                         strcat(str, "33MHz");
14711         }
14712         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14713                 strcat(str, ":32-bit");
14714         else
14715                 strcat(str, ":64-bit");
14716         return str;
14717 }
14718
14719 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14720 {
14721         struct pci_dev *peer;
14722         unsigned int func, devnr = tp->pdev->devfn & ~7;
14723
14724         for (func = 0; func < 8; func++) {
14725                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14726                 if (peer && peer != tp->pdev)
14727                         break;
14728                 pci_dev_put(peer);
14729         }
14730         /* 5704 can be configured in single-port mode, set peer to
14731          * tp->pdev in that case.
14732          */
14733         if (!peer) {
14734                 peer = tp->pdev;
14735                 return peer;
14736         }
14737
14738         /*
14739          * We don't need to keep the refcount elevated; there's no way
14740          * to remove one half of this device without removing the other
14741          */
14742         pci_dev_put(peer);
14743
14744         return peer;
14745 }
14746
14747 static void __devinit tg3_init_coal(struct tg3 *tp)
14748 {
14749         struct ethtool_coalesce *ec = &tp->coal;
14750
14751         memset(ec, 0, sizeof(*ec));
14752         ec->cmd = ETHTOOL_GCOALESCE;
14753         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14754         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14755         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14756         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14757         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14758         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14759         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14760         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14761         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14762
14763         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14764                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14765                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14766                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14767                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14768                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14769         }
14770
14771         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14772                 ec->rx_coalesce_usecs_irq = 0;
14773                 ec->tx_coalesce_usecs_irq = 0;
14774                 ec->stats_block_coalesce_usecs = 0;
14775         }
14776 }
14777
14778 static const struct net_device_ops tg3_netdev_ops = {
14779         .ndo_open               = tg3_open,
14780         .ndo_stop               = tg3_close,
14781         .ndo_start_xmit         = tg3_start_xmit,
14782         .ndo_get_stats64        = tg3_get_stats64,
14783         .ndo_validate_addr      = eth_validate_addr,
14784         .ndo_set_multicast_list = tg3_set_rx_mode,
14785         .ndo_set_mac_address    = tg3_set_mac_addr,
14786         .ndo_do_ioctl           = tg3_ioctl,
14787         .ndo_tx_timeout         = tg3_tx_timeout,
14788         .ndo_change_mtu         = tg3_change_mtu,
14789 #ifdef CONFIG_NET_POLL_CONTROLLER
14790         .ndo_poll_controller    = tg3_poll_controller,
14791 #endif
14792 };
14793
14794 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14795         .ndo_open               = tg3_open,
14796         .ndo_stop               = tg3_close,
14797         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14798         .ndo_get_stats64        = tg3_get_stats64,
14799         .ndo_validate_addr      = eth_validate_addr,
14800         .ndo_set_multicast_list = tg3_set_rx_mode,
14801         .ndo_set_mac_address    = tg3_set_mac_addr,
14802         .ndo_do_ioctl           = tg3_ioctl,
14803         .ndo_tx_timeout         = tg3_tx_timeout,
14804         .ndo_change_mtu         = tg3_change_mtu,
14805 #ifdef CONFIG_NET_POLL_CONTROLLER
14806         .ndo_poll_controller    = tg3_poll_controller,
14807 #endif
14808 };
14809
14810 static int __devinit tg3_init_one(struct pci_dev *pdev,
14811                                   const struct pci_device_id *ent)
14812 {
14813         struct net_device *dev;
14814         struct tg3 *tp;
14815         int i, err, pm_cap;
14816         u32 sndmbx, rcvmbx, intmbx;
14817         char str[40];
14818         u64 dma_mask, persist_dma_mask;
14819
14820         printk_once(KERN_INFO "%s\n", version);
14821
14822         err = pci_enable_device(pdev);
14823         if (err) {
14824                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14825                 return err;
14826         }
14827
14828         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14829         if (err) {
14830                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14831                 goto err_out_disable_pdev;
14832         }
14833
14834         pci_set_master(pdev);
14835
14836         /* Find power-management capability. */
14837         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14838         if (pm_cap == 0) {
14839                 dev_err(&pdev->dev,
14840                         "Cannot find Power Management capability, aborting\n");
14841                 err = -EIO;
14842                 goto err_out_free_res;
14843         }
14844
14845         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14846         if (!dev) {
14847                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14848                 err = -ENOMEM;
14849                 goto err_out_free_res;
14850         }
14851
14852         SET_NETDEV_DEV(dev, &pdev->dev);
14853
14854         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14855
14856         tp = netdev_priv(dev);
14857         tp->pdev = pdev;
14858         tp->dev = dev;
14859         tp->pm_cap = pm_cap;
14860         tp->rx_mode = TG3_DEF_RX_MODE;
14861         tp->tx_mode = TG3_DEF_TX_MODE;
14862
14863         if (tg3_debug > 0)
14864                 tp->msg_enable = tg3_debug;
14865         else
14866                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14867
14868         /* The word/byte swap controls here control register access byte
14869          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14870          * setting below.
14871          */
14872         tp->misc_host_ctrl =
14873                 MISC_HOST_CTRL_MASK_PCI_INT |
14874                 MISC_HOST_CTRL_WORD_SWAP |
14875                 MISC_HOST_CTRL_INDIR_ACCESS |
14876                 MISC_HOST_CTRL_PCISTATE_RW;
14877
14878         /* The NONFRM (non-frame) byte/word swap controls take effect
14879          * on descriptor entries, anything which isn't packet data.
14880          *
14881          * The StrongARM chips on the board (one for tx, one for rx)
14882          * are running in big-endian mode.
14883          */
14884         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14885                         GRC_MODE_WSWAP_NONFRM_DATA);
14886 #ifdef __BIG_ENDIAN
14887         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14888 #endif
14889         spin_lock_init(&tp->lock);
14890         spin_lock_init(&tp->indirect_lock);
14891         INIT_WORK(&tp->reset_task, tg3_reset_task);
14892
14893         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14894         if (!tp->regs) {
14895                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14896                 err = -ENOMEM;
14897                 goto err_out_free_dev;
14898         }
14899
14900         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14901         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14902
14903         dev->ethtool_ops = &tg3_ethtool_ops;
14904         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14905         dev->irq = pdev->irq;
14906
14907         err = tg3_get_invariants(tp);
14908         if (err) {
14909                 dev_err(&pdev->dev,
14910                         "Problem fetching invariants of chip, aborting\n");
14911                 goto err_out_iounmap;
14912         }
14913
14914         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14915             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
14916                 dev->netdev_ops = &tg3_netdev_ops;
14917         else
14918                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14919
14920
14921         /* The EPB bridge inside 5714, 5715, and 5780 and any
14922          * device behind the EPB cannot support DMA addresses > 40-bit.
14923          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14924          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14925          * do DMA address check in tg3_start_xmit().
14926          */
14927         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14928                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14929         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14930                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14931 #ifdef CONFIG_HIGHMEM
14932                 dma_mask = DMA_BIT_MASK(64);
14933 #endif
14934         } else
14935                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14936
14937         /* Configure DMA attributes. */
14938         if (dma_mask > DMA_BIT_MASK(32)) {
14939                 err = pci_set_dma_mask(pdev, dma_mask);
14940                 if (!err) {
14941                         dev->features |= NETIF_F_HIGHDMA;
14942                         err = pci_set_consistent_dma_mask(pdev,
14943                                                           persist_dma_mask);
14944                         if (err < 0) {
14945                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14946                                         "DMA for consistent allocations\n");
14947                                 goto err_out_iounmap;
14948                         }
14949                 }
14950         }
14951         if (err || dma_mask == DMA_BIT_MASK(32)) {
14952                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14953                 if (err) {
14954                         dev_err(&pdev->dev,
14955                                 "No usable DMA configuration, aborting\n");
14956                         goto err_out_iounmap;
14957                 }
14958         }
14959
14960         tg3_init_bufmgr_config(tp);
14961
14962         /* Selectively allow TSO based on operating conditions */
14963         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14964             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14965                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14966         else {
14967                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14968                 tp->fw_needed = NULL;
14969         }
14970
14971         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14972                 tp->fw_needed = FIRMWARE_TG3;
14973
14974         /* TSO is on by default on chips that support hardware TSO.
14975          * Firmware TSO on older chips gives lower performance, so it
14976          * is off by default, but can be enabled using ethtool.
14977          */
14978         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14979             (dev->features & NETIF_F_IP_CSUM)) {
14980                 dev->features |= NETIF_F_TSO;
14981                 vlan_features_add(dev, NETIF_F_TSO);
14982         }
14983         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14984             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14985                 if (dev->features & NETIF_F_IPV6_CSUM) {
14986                         dev->features |= NETIF_F_TSO6;
14987                         vlan_features_add(dev, NETIF_F_TSO6);
14988                 }
14989                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14990                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14991                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14992                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14993                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14994                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14995                         dev->features |= NETIF_F_TSO_ECN;
14996                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14997                 }
14998         }
14999
15000         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15001             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
15002             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15003                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
15004                 tp->rx_pending = 63;
15005         }
15006
15007         err = tg3_get_device_address(tp);
15008         if (err) {
15009                 dev_err(&pdev->dev,
15010                         "Could not obtain valid ethernet address, aborting\n");
15011                 goto err_out_iounmap;
15012         }
15013
15014         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
15015                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15016                 if (!tp->aperegs) {
15017                         dev_err(&pdev->dev,
15018                                 "Cannot map APE registers, aborting\n");
15019                         err = -ENOMEM;
15020                         goto err_out_iounmap;
15021                 }
15022
15023                 tg3_ape_lock_init(tp);
15024
15025                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
15026                         tg3_read_dash_ver(tp);
15027         }
15028
15029         /*
15030          * Reset chip in case UNDI or EFI driver did not shutdown
15031          * DMA self test will enable WDMAC and we'll see (spurious)
15032          * pending DMA on the PCI bus at that point.
15033          */
15034         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15035             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15036                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15037                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15038         }
15039
15040         err = tg3_test_dma(tp);
15041         if (err) {
15042                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15043                 goto err_out_apeunmap;
15044         }
15045
15046         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15047         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15048         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15049         for (i = 0; i < tp->irq_max; i++) {
15050                 struct tg3_napi *tnapi = &tp->napi[i];
15051
15052                 tnapi->tp = tp;
15053                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15054
15055                 tnapi->int_mbox = intmbx;
15056                 if (i < 4)
15057                         intmbx += 0x8;
15058                 else
15059                         intmbx += 0x4;
15060
15061                 tnapi->consmbox = rcvmbx;
15062                 tnapi->prodmbox = sndmbx;
15063
15064                 if (i)
15065                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15066                 else
15067                         tnapi->coal_now = HOSTCC_MODE_NOW;
15068
15069                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
15070                         break;
15071
15072                 /*
15073                  * If we support MSIX, we'll be using RSS.  If we're using
15074                  * RSS, the first vector only handles link interrupts and the
15075                  * remaining vectors handle rx and tx interrupts.  Reuse the
15076                  * mailbox values for the next iteration.  The values we setup
15077                  * above are still useful for the single vectored mode.
15078                  */
15079                 if (!i)
15080                         continue;
15081
15082                 rcvmbx += 0x8;
15083
15084                 if (sndmbx & 0x4)
15085                         sndmbx -= 0x4;
15086                 else
15087                         sndmbx += 0xc;
15088         }
15089
15090         tg3_init_coal(tp);
15091
15092         pci_set_drvdata(pdev, dev);
15093
15094         err = register_netdev(dev);
15095         if (err) {
15096                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15097                 goto err_out_apeunmap;
15098         }
15099
15100         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15101                     tp->board_part_number,
15102                     tp->pci_chip_rev_id,
15103                     tg3_bus_string(tp, str),
15104                     dev->dev_addr);
15105
15106         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15107                 struct phy_device *phydev;
15108                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15109                 netdev_info(dev,
15110                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15111                             phydev->drv->name, dev_name(&phydev->dev));
15112         } else {
15113                 char *ethtype;
15114
15115                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15116                         ethtype = "10/100Base-TX";
15117                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15118                         ethtype = "1000Base-SX";
15119                 else
15120                         ethtype = "10/100/1000Base-T";
15121
15122                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15123                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
15124                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
15125         }
15126
15127         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15128                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
15129                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
15130                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15131                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
15132                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
15133         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15134                     tp->dma_rwctrl,
15135                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15136                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15137
15138         return 0;
15139
15140 err_out_apeunmap:
15141         if (tp->aperegs) {
15142                 iounmap(tp->aperegs);
15143                 tp->aperegs = NULL;
15144         }
15145
15146 err_out_iounmap:
15147         if (tp->regs) {
15148                 iounmap(tp->regs);
15149                 tp->regs = NULL;
15150         }
15151
15152 err_out_free_dev:
15153         free_netdev(dev);
15154
15155 err_out_free_res:
15156         pci_release_regions(pdev);
15157
15158 err_out_disable_pdev:
15159         pci_disable_device(pdev);
15160         pci_set_drvdata(pdev, NULL);
15161         return err;
15162 }
15163
15164 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15165 {
15166         struct net_device *dev = pci_get_drvdata(pdev);
15167
15168         if (dev) {
15169                 struct tg3 *tp = netdev_priv(dev);
15170
15171                 if (tp->fw)
15172                         release_firmware(tp->fw);
15173
15174                 cancel_work_sync(&tp->reset_task);
15175
15176                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15177                         tg3_phy_fini(tp);
15178                         tg3_mdio_fini(tp);
15179                 }
15180
15181                 unregister_netdev(dev);
15182                 if (tp->aperegs) {
15183                         iounmap(tp->aperegs);
15184                         tp->aperegs = NULL;
15185                 }
15186                 if (tp->regs) {
15187                         iounmap(tp->regs);
15188                         tp->regs = NULL;
15189                 }
15190                 free_netdev(dev);
15191                 pci_release_regions(pdev);
15192                 pci_disable_device(pdev);
15193                 pci_set_drvdata(pdev, NULL);
15194         }
15195 }
15196
15197 #ifdef CONFIG_PM_SLEEP
15198 static int tg3_suspend(struct device *device)
15199 {
15200         struct pci_dev *pdev = to_pci_dev(device);
15201         struct net_device *dev = pci_get_drvdata(pdev);
15202         struct tg3 *tp = netdev_priv(dev);
15203         int err;
15204
15205         if (!netif_running(dev))
15206                 return 0;
15207
15208         flush_work_sync(&tp->reset_task);
15209         tg3_phy_stop(tp);
15210         tg3_netif_stop(tp);
15211
15212         del_timer_sync(&tp->timer);
15213
15214         tg3_full_lock(tp, 1);
15215         tg3_disable_ints(tp);
15216         tg3_full_unlock(tp);
15217
15218         netif_device_detach(dev);
15219
15220         tg3_full_lock(tp, 0);
15221         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15222         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15223         tg3_full_unlock(tp);
15224
15225         err = tg3_power_down_prepare(tp);
15226         if (err) {
15227                 int err2;
15228
15229                 tg3_full_lock(tp, 0);
15230
15231                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15232                 err2 = tg3_restart_hw(tp, 1);
15233                 if (err2)
15234                         goto out;
15235
15236                 tp->timer.expires = jiffies + tp->timer_offset;
15237                 add_timer(&tp->timer);
15238
15239                 netif_device_attach(dev);
15240                 tg3_netif_start(tp);
15241
15242 out:
15243                 tg3_full_unlock(tp);
15244
15245                 if (!err2)
15246                         tg3_phy_start(tp);
15247         }
15248
15249         return err;
15250 }
15251
15252 static int tg3_resume(struct device *device)
15253 {
15254         struct pci_dev *pdev = to_pci_dev(device);
15255         struct net_device *dev = pci_get_drvdata(pdev);
15256         struct tg3 *tp = netdev_priv(dev);
15257         int err;
15258
15259         if (!netif_running(dev))
15260                 return 0;
15261
15262         netif_device_attach(dev);
15263
15264         tg3_full_lock(tp, 0);
15265
15266         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15267         err = tg3_restart_hw(tp, 1);
15268         if (err)
15269                 goto out;
15270
15271         tp->timer.expires = jiffies + tp->timer_offset;
15272         add_timer(&tp->timer);
15273
15274         tg3_netif_start(tp);
15275
15276 out:
15277         tg3_full_unlock(tp);
15278
15279         if (!err)
15280                 tg3_phy_start(tp);
15281
15282         return err;
15283 }
15284
15285 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15286 #define TG3_PM_OPS (&tg3_pm_ops)
15287
15288 #else
15289
15290 #define TG3_PM_OPS NULL
15291
15292 #endif /* CONFIG_PM_SLEEP */
15293
15294 static struct pci_driver tg3_driver = {
15295         .name           = DRV_MODULE_NAME,
15296         .id_table       = tg3_pci_tbl,
15297         .probe          = tg3_init_one,
15298         .remove         = __devexit_p(tg3_remove_one),
15299         .driver.pm      = TG3_PM_OPS,
15300 };
15301
15302 static int __init tg3_init(void)
15303 {
15304         return pci_register_driver(&tg3_driver);
15305 }
15306
15307 static void __exit tg3_cleanup(void)
15308 {
15309         pci_unregister_driver(&tg3_driver);
15310 }
15311
15312 module_init(tg3_init);
15313 module_exit(tg3_cleanup);