2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.27"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
154 static void sky2_set_multicast(struct net_device *dev);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (!(ctrl & GM_SMI_CT_BUSY))
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
214 __gm_phy_read(hw, port, reg, &v);
219 static void sky2_power_on(struct sky2_hw *hw)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
261 sky2_read32(hw, B2_GP_IO);
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
268 static void sky2_power_aux(struct sky2_hw *hw)
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
290 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
307 /* flow control to advertise bits */
308 static const u16 copper_fc_adv[] = {
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
315 /* flow control to advertise bits when using 1000BaseX */
316 static const u16 fiber_fc_adv[] = {
317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
323 /* flow control to GMA disable bits */
324 static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
332 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
346 if (hw->chip_id == CHIP_ID_YUKON_EC)
347 /* set downshift counter to 3x and enable downshift */
348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
357 if (sky2_is_copper(hw)) {
358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378 /* downshift on PHY 88E1112 and 88E1149 is changed */
379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
381 /* set downshift counter to 3x and enable downshift */
382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395 /* special setup for PHY 88E1112 Fiber */
396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406 if (hw->pmd_type == 'P') {
407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
425 if (sky2_is_copper(hw)) {
426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
455 switch (sky2->speed) {
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
477 adv |= fiber_fc_adv[sky2->flow_mode];
479 reg |= GM_GPCR_AU_FCT_DIS;
480 reg |= gm_fc_disable[sky2->flow_mode];
482 /* Forward pause packets to GMAC? */
483 if (sky2->flow_mode & FC_RX)
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
489 gma_write16(hw, port, GM_GP_CTRL, reg);
491 if (hw->flags & SKY2_HW_GIGABIT)
492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
532 case CHIP_ID_YUKON_XL:
533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538 /* set LED Function Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
554 /* restore page register */
555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
558 case CHIP_ID_YUKON_EC_U:
559 case CHIP_ID_YUKON_EX:
560 case CHIP_ID_YUKON_SUPR:
561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
584 /* turn off the Rx LED (LED_RX) */
585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
589 /* apply fixes in PHY AFE */
590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592 /* increase differential signal amplitude in 10BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
602 /* set page register to 0 */
603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
621 /* no effect on Yukon-XL */
622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
626 /* turn on 100 Mbps LED (LED_LINK100) */
627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
642 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
645 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
651 reg1 &= ~phy_power[port];
653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
654 reg1 |= coma_mode[port];
656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
658 sky2_pci_read32(hw, PCI_DEV_REG1);
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
666 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
721 /* Force a renegotiation */
722 static void sky2_phy_reinit(struct sky2_port *sky2)
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_init(sky2->hw, sky2->port);
726 spin_unlock_bh(&sky2->phy_lock);
729 /* Put device in state to listen for Wake On Lan */
730 static void sky2_wol_init(struct sky2_port *sky2)
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
737 /* Bring hardware out of reset */
738 sky2_write16(hw, B0_CTST, CS_RST_CLR);
739 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
742 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
745 * sky2_reset will re-enable on resume
747 save_mode = sky2->flow_mode;
748 ctrl = sky2->advertising;
750 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
751 sky2->flow_mode = FC_NONE;
753 spin_lock_bh(&sky2->phy_lock);
754 sky2_phy_power_up(hw, port);
755 sky2_phy_init(hw, port);
756 spin_unlock_bh(&sky2->phy_lock);
758 sky2->flow_mode = save_mode;
759 sky2->advertising = ctrl;
761 /* Set GMAC to no flow control and auto update for speed/duplex */
762 gma_write16(hw, port, GM_GP_CTRL,
763 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
764 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
766 /* Set WOL address */
767 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
768 sky2->netdev->dev_addr, ETH_ALEN);
770 /* Turn on appropriate WOL control bits */
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
773 if (sky2->wol & WAKE_PHY)
774 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
776 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
778 if (sky2->wol & WAKE_MAGIC)
779 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
781 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
783 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
784 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
786 /* Disable PiG firmware */
787 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
790 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
793 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
795 struct net_device *dev = hw->dev[port];
797 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
798 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
799 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
800 /* Yukon-Extreme B0 and further Extreme devices */
801 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
802 } else if (dev->mtu > ETH_DATA_LEN) {
803 /* set Tx GMAC FIFO Almost Empty Threshold */
804 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
805 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
807 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
812 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
814 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
818 const u8 *addr = hw->dev[port]->dev_addr;
820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
825 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
826 /* WA DEV_472 -- looks like crossed wires on port 2 */
827 /* clear GMAC 1 Control reset */
828 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
830 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
832 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
833 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
834 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
837 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
839 /* Enable Transmit FIFO Underrun */
840 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
842 spin_lock_bh(&sky2->phy_lock);
843 sky2_phy_power_up(hw, port);
844 sky2_phy_init(hw, port);
845 spin_unlock_bh(&sky2->phy_lock);
848 reg = gma_read16(hw, port, GM_PHY_ADDR);
849 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
851 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
852 gma_read16(hw, port, i);
853 gma_write16(hw, port, GM_PHY_ADDR, reg);
855 /* transmit control */
856 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
858 /* receive control reg: unicast + multicast + no FCS */
859 gma_write16(hw, port, GM_RX_CTRL,
860 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
862 /* transmit flow control */
863 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
865 /* transmit parameter */
866 gma_write16(hw, port, GM_TX_PARAM,
867 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
868 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
869 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
870 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
872 /* serial mode register */
873 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
874 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
876 if (hw->dev[port]->mtu > ETH_DATA_LEN)
877 reg |= GM_SMOD_JUMBO_ENA;
879 gma_write16(hw, port, GM_SERIAL_MODE, reg);
881 /* virtual address for data */
882 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
884 /* physical address: used for pause frames */
885 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
887 /* ignore counter overflows */
888 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
889 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
890 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
892 /* Configure Rx MAC FIFO */
893 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
894 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
895 if (hw->chip_id == CHIP_ID_YUKON_EX ||
896 hw->chip_id == CHIP_ID_YUKON_FE_P)
897 rx_reg |= GMF_RX_OVER_ON;
899 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
901 if (hw->chip_id == CHIP_ID_YUKON_XL) {
902 /* Hardware errata - clear flush mask */
903 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
905 /* Flush Rx MAC FIFO on any flow control or error */
906 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
909 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
910 reg = RX_GMF_FL_THR_DEF + 1;
911 /* Another magic mystery workaround from sk98lin */
912 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
913 hw->chip_rev == CHIP_REV_YU_FE2_A0)
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
917 /* Configure Tx MAC FIFO */
918 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
919 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
921 /* On chips without ram buffer, pause is controled by MAC level */
922 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
923 /* Pause threshold is scaled by 8 in bytes */
924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
929 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
930 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
932 sky2_set_tx_stfwd(hw, port);
935 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
936 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
937 /* disable dynamic watermark */
938 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
939 reg &= ~TX_DYN_WM_ENA;
940 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
944 /* Assign Ram Buffer allocation to queue */
945 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
949 /* convert from K bytes to qwords used for hw register */
952 end = start + space - 1;
954 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
955 sky2_write32(hw, RB_ADDR(q, RB_START), start);
956 sky2_write32(hw, RB_ADDR(q, RB_END), end);
957 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
958 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
960 if (q == Q_R1 || q == Q_R2) {
961 u32 tp = space - space/4;
963 /* On receive queue's set the thresholds
964 * give receiver priority when > 3/4 full
965 * send pause when down to 2K
967 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
968 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
971 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
972 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
974 /* Enable store & forward on Tx queue's because
975 * Tx FIFO is only 1K on Yukon
977 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
980 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
981 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
984 /* Setup Bus Memory Interface */
985 static void sky2_qset(struct sky2_hw *hw, u16 q)
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
990 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
993 /* Setup prefetch unit registers. This is the interface between
994 * hardware and driver list elements
996 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
997 dma_addr_t addr, u32 last)
999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1003 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1006 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1009 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1011 struct sky2_tx_le *le = sky2->tx_le + *slot;
1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1018 static void tx_init(struct sky2_port *sky2)
1020 struct sky2_tx_le *le;
1022 sky2->tx_prod = sky2->tx_cons = 0;
1023 sky2->tx_tcpsum = 0;
1024 sky2->tx_last_mss = 0;
1026 le = get_tx_le(sky2, &sky2->tx_prod);
1028 le->opcode = OP_ADDR64 | HW_OWNER;
1029 sky2->tx_last_upper = 0;
1032 /* Update chip's next pointer */
1033 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1035 /* Make sure write' to descriptors are complete before we tell hardware */
1037 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1039 /* Synchronize I/O on since next processor may write to tail */
1044 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1046 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1047 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1052 static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1056 /* Space needed for frame data + headers rounded up */
1057 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1059 /* Stopping point for hardware truncation */
1060 return (size - 8) / sizeof(u32);
1063 static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1065 struct rx_ring_info *re;
1068 /* Space needed for frame data + headers rounded up */
1069 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1071 sky2->rx_nfrags = size >> PAGE_SHIFT;
1072 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1074 /* Compute residue after pages */
1075 size -= sky2->rx_nfrags << PAGE_SHIFT;
1077 /* Optimize to handle small packets and headers */
1078 if (size < copybreak)
1080 if (size < ETH_HLEN)
1086 /* Build description to hardware for one receive segment */
1087 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1088 dma_addr_t map, unsigned len)
1090 struct sky2_rx_le *le;
1092 if (sizeof(dma_addr_t) > sizeof(u32)) {
1093 le = sky2_next_rx(sky2);
1094 le->addr = cpu_to_le32(upper_32_bits(map));
1095 le->opcode = OP_ADDR64 | HW_OWNER;
1098 le = sky2_next_rx(sky2);
1099 le->addr = cpu_to_le32(lower_32_bits(map));
1100 le->length = cpu_to_le16(len);
1101 le->opcode = op | HW_OWNER;
1104 /* Build description to hardware for one possibly fragmented skb */
1105 static void sky2_rx_submit(struct sky2_port *sky2,
1106 const struct rx_ring_info *re)
1110 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1112 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1113 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1117 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1120 struct sk_buff *skb = re->skb;
1123 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1124 if (pci_dma_mapping_error(pdev, re->data_addr))
1127 pci_unmap_len_set(re, data_size, size);
1129 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1130 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1132 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1135 PCI_DMA_FROMDEVICE);
1137 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1138 goto map_page_error;
1144 pci_unmap_page(pdev, re->frag_addr[i],
1145 skb_shinfo(skb)->frags[i].size,
1146 PCI_DMA_FROMDEVICE);
1149 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1150 PCI_DMA_FROMDEVICE);
1153 if (net_ratelimit())
1154 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1159 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1161 struct sk_buff *skb = re->skb;
1164 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1167 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1168 pci_unmap_page(pdev, re->frag_addr[i],
1169 skb_shinfo(skb)->frags[i].size,
1170 PCI_DMA_FROMDEVICE);
1173 /* Tell chip where to start receive checksum.
1174 * Actually has two checksums, but set both same to avoid possible byte
1177 static void rx_set_checksum(struct sky2_port *sky2)
1179 struct sky2_rx_le *le = sky2_next_rx(sky2);
1181 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1183 le->opcode = OP_TCPSTART | HW_OWNER;
1185 sky2_write32(sky2->hw,
1186 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1187 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1188 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1192 * The RX Stop command will not work for Yukon-2 if the BMU does not
1193 * reach the end of packet and since we can't make sure that we have
1194 * incoming data, we must reset the BMU while it is not doing a DMA
1195 * transfer. Since it is possible that the RX path is still active,
1196 * the RX RAM buffer will be stopped first, so any possible incoming
1197 * data will not trigger a DMA. After the RAM buffer is stopped, the
1198 * BMU is polled until any DMA in progress is ended and only then it
1201 static void sky2_rx_stop(struct sky2_port *sky2)
1203 struct sky2_hw *hw = sky2->hw;
1204 unsigned rxq = rxqaddr[sky2->port];
1207 /* disable the RAM Buffer receive queue */
1208 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1210 for (i = 0; i < 0xffff; i++)
1211 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1212 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1215 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1216 sky2->netdev->name);
1218 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1220 /* reset the Rx prefetch unit */
1221 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1225 /* Clean out receive buffer area, assumes receiver hardware stopped */
1226 static void sky2_rx_clean(struct sky2_port *sky2)
1230 memset(sky2->rx_le, 0, RX_LE_BYTES);
1231 for (i = 0; i < sky2->rx_pending; i++) {
1232 struct rx_ring_info *re = sky2->rx_ring + i;
1235 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1242 /* Basic MII support */
1243 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1245 struct mii_ioctl_data *data = if_mii(ifr);
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 int err = -EOPNOTSUPP;
1250 if (!netif_running(dev))
1251 return -ENODEV; /* Phy still in reset */
1255 data->phy_id = PHY_ADDR_MARV;
1261 spin_lock_bh(&sky2->phy_lock);
1262 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1263 spin_unlock_bh(&sky2->phy_lock);
1265 data->val_out = val;
1270 spin_lock_bh(&sky2->phy_lock);
1271 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1273 spin_unlock_bh(&sky2->phy_lock);
1279 #ifdef SKY2_VLAN_TAG_USED
1280 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1283 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1285 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1288 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1290 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1295 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 u16 port = sky2->port;
1301 netif_tx_lock_bh(dev);
1302 napi_disable(&hw->napi);
1305 sky2_set_vlan_mode(hw, port, grp != NULL);
1307 sky2_read32(hw, B0_Y2_SP_LISR);
1308 napi_enable(&hw->napi);
1309 netif_tx_unlock_bh(dev);
1313 /* Amount of required worst case padding in rx buffer */
1314 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1316 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1320 * Allocate an skb for receiving. If the MTU is large enough
1321 * make the skb non-linear with a fragment list of pages.
1323 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1325 struct sk_buff *skb;
1328 skb = netdev_alloc_skb(sky2->netdev,
1329 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1333 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1334 unsigned char *start;
1336 * Workaround for a bug in FIFO that cause hang
1337 * if the FIFO if the receive buffer is not 64 byte aligned.
1338 * The buffer returned from netdev_alloc_skb is
1339 * aligned except if slab debugging is enabled.
1341 start = PTR_ALIGN(skb->data, 8);
1342 skb_reserve(skb, start - skb->data);
1344 skb_reserve(skb, NET_IP_ALIGN);
1346 for (i = 0; i < sky2->rx_nfrags; i++) {
1347 struct page *page = alloc_page(GFP_ATOMIC);
1351 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1361 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1363 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1366 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1368 struct sky2_hw *hw = sky2->hw;
1371 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1374 for (i = 0; i < sky2->rx_pending; i++) {
1375 struct rx_ring_info *re = sky2->rx_ring + i;
1377 re->skb = sky2_rx_alloc(sky2);
1381 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1382 dev_kfree_skb(re->skb);
1391 * Setup receiver buffer pool.
1392 * Normal case this ends up creating one list element for skb
1393 * in the receive ring. Worst case if using large MTU and each
1394 * allocation falls on a different 64 bit region, that results
1395 * in 6 list elements per ring entry.
1396 * One element is used for checksum enable/disable, and one
1397 * extra to avoid wrap.
1399 static void sky2_rx_start(struct sky2_port *sky2)
1401 struct sky2_hw *hw = sky2->hw;
1402 struct rx_ring_info *re;
1403 unsigned rxq = rxqaddr[sky2->port];
1406 sky2->rx_put = sky2->rx_next = 0;
1409 /* On PCI express lowering the watermark gives better performance */
1410 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1411 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1413 /* These chips have no ram buffer?
1414 * MAC Rx RAM Read is controlled by hardware */
1415 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1416 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1417 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1418 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1420 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1422 if (!(hw->flags & SKY2_HW_NEW_LE))
1423 rx_set_checksum(sky2);
1425 /* submit Rx ring */
1426 for (i = 0; i < sky2->rx_pending; i++) {
1427 re = sky2->rx_ring + i;
1428 sky2_rx_submit(sky2, re);
1432 * The receiver hangs if it receives frames larger than the
1433 * packet buffer. As a workaround, truncate oversize frames, but
1434 * the register is limited to 9 bits, so if you do frames > 2052
1435 * you better get the MTU right!
1437 thresh = sky2_get_rx_threshold(sky2);
1439 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1441 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1445 /* Tell chip about available buffers */
1446 sky2_rx_update(sky2, rxq);
1448 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1449 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1451 * Disable flushing of non ASF packets;
1452 * must be done after initializing the BMUs;
1453 * drivers without ASF support should do this too, otherwise
1454 * it may happen that they cannot run on ASF devices;
1455 * remember that the MAC FIFO isn't reset during initialization.
1457 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1460 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1461 /* Enable RX Home Address & Routing Header checksum fix */
1462 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1463 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1465 /* Enable TX Home Address & Routing Header checksum fix */
1466 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1467 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1471 static int sky2_alloc_buffers(struct sky2_port *sky2)
1473 struct sky2_hw *hw = sky2->hw;
1475 /* must be power of 2 */
1476 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1477 sky2->tx_ring_size *
1478 sizeof(struct sky2_tx_le),
1483 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1488 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1492 memset(sky2->rx_le, 0, RX_LE_BYTES);
1494 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1499 return sky2_alloc_rx_skbs(sky2);
1504 static void sky2_free_buffers(struct sky2_port *sky2)
1506 struct sky2_hw *hw = sky2->hw;
1508 sky2_rx_clean(sky2);
1511 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1512 sky2->rx_le, sky2->rx_le_map);
1516 pci_free_consistent(hw->pdev,
1517 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1518 sky2->tx_le, sky2->tx_le_map);
1521 kfree(sky2->tx_ring);
1522 kfree(sky2->rx_ring);
1524 sky2->tx_ring = NULL;
1525 sky2->rx_ring = NULL;
1528 static void sky2_hw_up(struct sky2_port *sky2)
1530 struct sky2_hw *hw = sky2->hw;
1531 unsigned port = sky2->port;
1534 struct net_device *otherdev = hw->dev[sky2->port^1];
1539 * On dual port PCI-X card, there is an problem where status
1540 * can be received out of order due to split transactions
1542 if (otherdev && netif_running(otherdev) &&
1543 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1546 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1547 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1548 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1551 sky2_mac_init(hw, port);
1553 /* Register is number of 4K blocks on internal RAM buffer. */
1554 ramsize = sky2_read8(hw, B2_E_0) * 4;
1558 pr_debug(PFX "%s: ram buffer %dK\n", sky2->netdev->name, ramsize);
1560 rxspace = ramsize / 2;
1562 rxspace = 8 + (2*(ramsize - 16))/3;
1564 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1565 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1567 /* Make sure SyncQ is disabled */
1568 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1572 sky2_qset(hw, txqaddr[port]);
1574 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1575 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1576 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1578 /* Set almost empty threshold */
1579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1580 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1581 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1583 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1584 sky2->tx_ring_size - 1);
1586 #ifdef SKY2_VLAN_TAG_USED
1587 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1590 sky2_rx_start(sky2);
1593 /* Bring up network interface. */
1594 static int sky2_up(struct net_device *dev)
1596 struct sky2_port *sky2 = netdev_priv(dev);
1597 struct sky2_hw *hw = sky2->hw;
1598 unsigned port = sky2->port;
1602 netif_carrier_off(dev);
1604 err = sky2_alloc_buffers(sky2);
1610 /* Enable interrupts from phy/mac for port */
1611 imask = sky2_read32(hw, B0_IMSK);
1612 imask |= portirq_msk[port];
1613 sky2_write32(hw, B0_IMSK, imask);
1614 sky2_read32(hw, B0_IMSK);
1616 netif_info(sky2, ifup, dev, "enabling interface\n");
1621 sky2_free_buffers(sky2);
1625 /* Modular subtraction in ring */
1626 static inline int tx_inuse(const struct sky2_port *sky2)
1628 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1631 /* Number of list elements available for next tx */
1632 static inline int tx_avail(const struct sky2_port *sky2)
1634 return sky2->tx_pending - tx_inuse(sky2);
1637 /* Estimate of number of transmit list elements required */
1638 static unsigned tx_le_req(const struct sk_buff *skb)
1642 count = (skb_shinfo(skb)->nr_frags + 1)
1643 * (sizeof(dma_addr_t) / sizeof(u32));
1645 if (skb_is_gso(skb))
1647 else if (sizeof(dma_addr_t) == sizeof(u32))
1648 ++count; /* possible vlan */
1650 if (skb->ip_summed == CHECKSUM_PARTIAL)
1656 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1658 if (re->flags & TX_MAP_SINGLE)
1659 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1660 pci_unmap_len(re, maplen),
1662 else if (re->flags & TX_MAP_PAGE)
1663 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1664 pci_unmap_len(re, maplen),
1670 * Put one packet in ring for transmit.
1671 * A single packet can generate multiple list elements, and
1672 * the number of ring elements will probably be less than the number
1673 * of list elements used.
1675 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1676 struct net_device *dev)
1678 struct sky2_port *sky2 = netdev_priv(dev);
1679 struct sky2_hw *hw = sky2->hw;
1680 struct sky2_tx_le *le = NULL;
1681 struct tx_ring_info *re;
1689 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1690 return NETDEV_TX_BUSY;
1692 len = skb_headlen(skb);
1693 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1695 if (pci_dma_mapping_error(hw->pdev, mapping))
1698 slot = sky2->tx_prod;
1699 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1700 "tx queued, slot %u, len %d\n", slot, skb->len);
1702 /* Send high bits if needed */
1703 upper = upper_32_bits(mapping);
1704 if (upper != sky2->tx_last_upper) {
1705 le = get_tx_le(sky2, &slot);
1706 le->addr = cpu_to_le32(upper);
1707 sky2->tx_last_upper = upper;
1708 le->opcode = OP_ADDR64 | HW_OWNER;
1711 /* Check for TCP Segmentation Offload */
1712 mss = skb_shinfo(skb)->gso_size;
1715 if (!(hw->flags & SKY2_HW_NEW_LE))
1716 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1718 if (mss != sky2->tx_last_mss) {
1719 le = get_tx_le(sky2, &slot);
1720 le->addr = cpu_to_le32(mss);
1722 if (hw->flags & SKY2_HW_NEW_LE)
1723 le->opcode = OP_MSS | HW_OWNER;
1725 le->opcode = OP_LRGLEN | HW_OWNER;
1726 sky2->tx_last_mss = mss;
1731 #ifdef SKY2_VLAN_TAG_USED
1732 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1733 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1735 le = get_tx_le(sky2, &slot);
1737 le->opcode = OP_VLAN|HW_OWNER;
1739 le->opcode |= OP_VLAN;
1740 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1745 /* Handle TCP checksum offload */
1746 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1747 /* On Yukon EX (some versions) encoding change. */
1748 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1749 ctrl |= CALSUM; /* auto checksum */
1751 const unsigned offset = skb_transport_offset(skb);
1754 tcpsum = offset << 16; /* sum start */
1755 tcpsum |= offset + skb->csum_offset; /* sum write */
1757 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1758 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1761 if (tcpsum != sky2->tx_tcpsum) {
1762 sky2->tx_tcpsum = tcpsum;
1764 le = get_tx_le(sky2, &slot);
1765 le->addr = cpu_to_le32(tcpsum);
1766 le->length = 0; /* initial checksum value */
1767 le->ctrl = 1; /* one packet */
1768 le->opcode = OP_TCPLISW | HW_OWNER;
1773 re = sky2->tx_ring + slot;
1774 re->flags = TX_MAP_SINGLE;
1775 pci_unmap_addr_set(re, mapaddr, mapping);
1776 pci_unmap_len_set(re, maplen, len);
1778 le = get_tx_le(sky2, &slot);
1779 le->addr = cpu_to_le32(lower_32_bits(mapping));
1780 le->length = cpu_to_le16(len);
1782 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1785 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1786 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1788 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1789 frag->size, PCI_DMA_TODEVICE);
1791 if (pci_dma_mapping_error(hw->pdev, mapping))
1792 goto mapping_unwind;
1794 upper = upper_32_bits(mapping);
1795 if (upper != sky2->tx_last_upper) {
1796 le = get_tx_le(sky2, &slot);
1797 le->addr = cpu_to_le32(upper);
1798 sky2->tx_last_upper = upper;
1799 le->opcode = OP_ADDR64 | HW_OWNER;
1802 re = sky2->tx_ring + slot;
1803 re->flags = TX_MAP_PAGE;
1804 pci_unmap_addr_set(re, mapaddr, mapping);
1805 pci_unmap_len_set(re, maplen, frag->size);
1807 le = get_tx_le(sky2, &slot);
1808 le->addr = cpu_to_le32(lower_32_bits(mapping));
1809 le->length = cpu_to_le16(frag->size);
1811 le->opcode = OP_BUFFER | HW_OWNER;
1817 sky2->tx_prod = slot;
1819 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1820 netif_stop_queue(dev);
1822 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1824 return NETDEV_TX_OK;
1827 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1828 re = sky2->tx_ring + i;
1830 sky2_tx_unmap(hw->pdev, re);
1834 if (net_ratelimit())
1835 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1837 return NETDEV_TX_OK;
1841 * Free ring elements from starting at tx_cons until "done"
1844 * 1. The hardware will tell us about partial completion of multi-part
1845 * buffers so make sure not to free skb to early.
1846 * 2. This may run in parallel start_xmit because the it only
1847 * looks at the tail of the queue of FIFO (tx_cons), not
1848 * the head (tx_prod)
1850 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1852 struct net_device *dev = sky2->netdev;
1855 BUG_ON(done >= sky2->tx_ring_size);
1857 for (idx = sky2->tx_cons; idx != done;
1858 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1859 struct tx_ring_info *re = sky2->tx_ring + idx;
1860 struct sk_buff *skb = re->skb;
1862 sky2_tx_unmap(sky2->hw->pdev, re);
1865 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1866 "tx done %u\n", idx);
1868 dev->stats.tx_packets++;
1869 dev->stats.tx_bytes += skb->len;
1872 dev_kfree_skb_any(skb);
1874 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1878 sky2->tx_cons = idx;
1882 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1884 /* Disable Force Sync bit and Enable Alloc bit */
1885 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1886 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1888 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1889 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1890 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1892 /* Reset the PCI FIFO of the async Tx queue */
1893 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1894 BMU_RST_SET | BMU_FIFO_RST);
1896 /* Reset the Tx prefetch units */
1897 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1900 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1901 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1904 static void sky2_hw_down(struct sky2_port *sky2)
1906 struct sky2_hw *hw = sky2->hw;
1907 unsigned port = sky2->port;
1910 /* Force flow control off */
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1913 /* Stop transmitter */
1914 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1915 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1917 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1918 RB_RST_SET | RB_DIS_OP_MD);
1920 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1921 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1922 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1924 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1926 /* Workaround shared GMAC reset */
1927 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1928 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1929 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1931 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1933 /* Force any delayed status interrrupt and NAPI */
1934 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1935 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1936 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1937 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1941 spin_lock_bh(&sky2->phy_lock);
1942 sky2_phy_power_down(hw, port);
1943 spin_unlock_bh(&sky2->phy_lock);
1945 sky2_tx_reset(hw, port);
1947 /* Free any pending frames stuck in HW queue */
1948 sky2_tx_complete(sky2, sky2->tx_prod);
1951 /* Network shutdown */
1952 static int sky2_down(struct net_device *dev)
1954 struct sky2_port *sky2 = netdev_priv(dev);
1955 struct sky2_hw *hw = sky2->hw;
1957 /* Never really got started! */
1961 netif_info(sky2, ifdown, dev, "disabling interface\n");
1963 /* Disable port IRQ */
1964 sky2_write32(hw, B0_IMSK,
1965 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1966 sky2_read32(hw, B0_IMSK);
1968 synchronize_irq(hw->pdev->irq);
1969 napi_synchronize(&hw->napi);
1973 sky2_free_buffers(sky2);
1978 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1980 if (hw->flags & SKY2_HW_FIBRE_PHY)
1983 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1984 if (aux & PHY_M_PS_SPEED_100)
1990 switch (aux & PHY_M_PS_SPEED_MSK) {
1991 case PHY_M_PS_SPEED_1000:
1993 case PHY_M_PS_SPEED_100:
2000 static void sky2_link_up(struct sky2_port *sky2)
2002 struct sky2_hw *hw = sky2->hw;
2003 unsigned port = sky2->port;
2005 static const char *fc_name[] = {
2013 reg = gma_read16(hw, port, GM_GP_CTRL);
2014 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2015 gma_write16(hw, port, GM_GP_CTRL, reg);
2017 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2019 netif_carrier_on(sky2->netdev);
2021 mod_timer(&hw->watchdog_timer, jiffies + 1);
2023 /* Turn on link LED */
2024 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2025 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2027 netif_info(sky2, link, sky2->netdev,
2028 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2030 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2031 fc_name[sky2->flow_status]);
2034 static void sky2_link_down(struct sky2_port *sky2)
2036 struct sky2_hw *hw = sky2->hw;
2037 unsigned port = sky2->port;
2040 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2042 reg = gma_read16(hw, port, GM_GP_CTRL);
2043 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2044 gma_write16(hw, port, GM_GP_CTRL, reg);
2046 netif_carrier_off(sky2->netdev);
2048 /* Turn off link LED */
2049 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2051 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2053 sky2_phy_init(hw, port);
2056 static enum flow_control sky2_flow(int rx, int tx)
2059 return tx ? FC_BOTH : FC_RX;
2061 return tx ? FC_TX : FC_NONE;
2064 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2066 struct sky2_hw *hw = sky2->hw;
2067 unsigned port = sky2->port;
2070 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2071 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2072 if (lpa & PHY_M_AN_RF) {
2073 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2077 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2078 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2079 sky2->netdev->name);
2083 sky2->speed = sky2_phy_speed(hw, aux);
2084 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2086 /* Since the pause result bits seem to in different positions on
2087 * different chips. look at registers.
2089 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2090 /* Shift for bits in fiber PHY */
2091 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2092 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2094 if (advert & ADVERTISE_1000XPAUSE)
2095 advert |= ADVERTISE_PAUSE_CAP;
2096 if (advert & ADVERTISE_1000XPSE_ASYM)
2097 advert |= ADVERTISE_PAUSE_ASYM;
2098 if (lpa & LPA_1000XPAUSE)
2099 lpa |= LPA_PAUSE_CAP;
2100 if (lpa & LPA_1000XPAUSE_ASYM)
2101 lpa |= LPA_PAUSE_ASYM;
2104 sky2->flow_status = FC_NONE;
2105 if (advert & ADVERTISE_PAUSE_CAP) {
2106 if (lpa & LPA_PAUSE_CAP)
2107 sky2->flow_status = FC_BOTH;
2108 else if (advert & ADVERTISE_PAUSE_ASYM)
2109 sky2->flow_status = FC_RX;
2110 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2111 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2112 sky2->flow_status = FC_TX;
2115 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2116 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2117 sky2->flow_status = FC_NONE;
2119 if (sky2->flow_status & FC_TX)
2120 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2122 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2127 /* Interrupt from PHY */
2128 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2130 struct net_device *dev = hw->dev[port];
2131 struct sky2_port *sky2 = netdev_priv(dev);
2132 u16 istatus, phystat;
2134 if (!netif_running(dev))
2137 spin_lock(&sky2->phy_lock);
2138 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2139 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2141 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2144 if (istatus & PHY_M_IS_AN_COMPL) {
2145 if (sky2_autoneg_done(sky2, phystat) == 0)
2150 if (istatus & PHY_M_IS_LSP_CHANGE)
2151 sky2->speed = sky2_phy_speed(hw, phystat);
2153 if (istatus & PHY_M_IS_DUP_CHANGE)
2155 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2157 if (istatus & PHY_M_IS_LST_CHANGE) {
2158 if (phystat & PHY_M_PS_LINK_UP)
2161 sky2_link_down(sky2);
2164 spin_unlock(&sky2->phy_lock);
2167 /* Special quick link interrupt (Yukon-2 Optima only) */
2168 static void sky2_qlink_intr(struct sky2_hw *hw)
2170 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2175 imask = sky2_read32(hw, B0_IMSK);
2176 imask &= ~Y2_IS_PHY_QLNK;
2177 sky2_write32(hw, B0_IMSK, imask);
2179 /* reset PHY Link Detect */
2180 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2181 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2182 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2183 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2188 /* Transmit timeout is only called if we are running, carrier is up
2189 * and tx queue is full (stopped).
2191 static void sky2_tx_timeout(struct net_device *dev)
2193 struct sky2_port *sky2 = netdev_priv(dev);
2194 struct sky2_hw *hw = sky2->hw;
2196 netif_err(sky2, timer, dev, "tx timeout\n");
2198 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2199 dev->name, sky2->tx_cons, sky2->tx_prod,
2200 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2201 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2203 /* can't restart safely under softirq */
2204 schedule_work(&hw->restart_work);
2207 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2209 struct sky2_port *sky2 = netdev_priv(dev);
2210 struct sky2_hw *hw = sky2->hw;
2211 unsigned port = sky2->port;
2216 /* MTU size outside the spec */
2217 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2220 /* MTU > 1500 on yukon FE and FE+ not allowed */
2221 if (new_mtu > ETH_DATA_LEN &&
2222 (hw->chip_id == CHIP_ID_YUKON_FE ||
2223 hw->chip_id == CHIP_ID_YUKON_FE_P))
2226 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2227 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2228 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2230 if (!netif_running(dev)) {
2235 imask = sky2_read32(hw, B0_IMSK);
2236 sky2_write32(hw, B0_IMSK, 0);
2238 dev->trans_start = jiffies; /* prevent tx timeout */
2239 netif_stop_queue(dev);
2240 napi_disable(&hw->napi);
2242 synchronize_irq(hw->pdev->irq);
2244 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2245 sky2_set_tx_stfwd(hw, port);
2247 ctl = gma_read16(hw, port, GM_GP_CTRL);
2248 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2250 sky2_rx_clean(sky2);
2254 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2255 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2257 if (dev->mtu > ETH_DATA_LEN)
2258 mode |= GM_SMOD_JUMBO_ENA;
2260 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2262 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2264 err = sky2_alloc_rx_skbs(sky2);
2266 sky2_rx_start(sky2);
2268 sky2_rx_clean(sky2);
2269 sky2_write32(hw, B0_IMSK, imask);
2271 sky2_read32(hw, B0_Y2_SP_LISR);
2272 napi_enable(&hw->napi);
2277 gma_write16(hw, port, GM_GP_CTRL, ctl);
2279 netif_wake_queue(dev);
2285 /* For small just reuse existing skb for next receive */
2286 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2287 const struct rx_ring_info *re,
2290 struct sk_buff *skb;
2292 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2294 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2295 length, PCI_DMA_FROMDEVICE);
2296 skb_copy_from_linear_data(re->skb, skb->data, length);
2297 skb->ip_summed = re->skb->ip_summed;
2298 skb->csum = re->skb->csum;
2299 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2300 length, PCI_DMA_FROMDEVICE);
2301 re->skb->ip_summed = CHECKSUM_NONE;
2302 skb_put(skb, length);
2307 /* Adjust length of skb with fragments to match received data */
2308 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2309 unsigned int length)
2314 /* put header into skb */
2315 size = min(length, hdr_space);
2320 num_frags = skb_shinfo(skb)->nr_frags;
2321 for (i = 0; i < num_frags; i++) {
2322 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2325 /* don't need this page */
2326 __free_page(frag->page);
2327 --skb_shinfo(skb)->nr_frags;
2329 size = min(length, (unsigned) PAGE_SIZE);
2332 skb->data_len += size;
2333 skb->truesize += size;
2340 /* Normal packet - take skb from ring element and put in a new one */
2341 static struct sk_buff *receive_new(struct sky2_port *sky2,
2342 struct rx_ring_info *re,
2343 unsigned int length)
2345 struct sk_buff *skb;
2346 struct rx_ring_info nre;
2347 unsigned hdr_space = sky2->rx_data_size;
2349 nre.skb = sky2_rx_alloc(sky2);
2350 if (unlikely(!nre.skb))
2353 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2357 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2358 prefetch(skb->data);
2361 if (skb_shinfo(skb)->nr_frags)
2362 skb_put_frags(skb, hdr_space, length);
2364 skb_put(skb, length);
2368 dev_kfree_skb(nre.skb);
2374 * Receive one packet.
2375 * For larger packets, get new buffer.
2377 static struct sk_buff *sky2_receive(struct net_device *dev,
2378 u16 length, u32 status)
2380 struct sky2_port *sky2 = netdev_priv(dev);
2381 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2382 struct sk_buff *skb = NULL;
2383 u16 count = (status & GMR_FS_LEN) >> 16;
2385 #ifdef SKY2_VLAN_TAG_USED
2386 /* Account for vlan tag */
2387 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2391 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2392 "rx slot %u status 0x%x len %d\n",
2393 sky2->rx_next, status, length);
2395 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2396 prefetch(sky2->rx_ring + sky2->rx_next);
2398 /* This chip has hardware problems that generates bogus status.
2399 * So do only marginal checking and expect higher level protocols
2400 * to handle crap frames.
2402 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2403 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2407 if (status & GMR_FS_ANY_ERR)
2410 if (!(status & GMR_FS_RX_OK))
2413 /* if length reported by DMA does not match PHY, packet was truncated */
2414 if (length != count)
2418 if (length < copybreak)
2419 skb = receive_copy(sky2, re, length);
2421 skb = receive_new(sky2, re, length);
2423 dev->stats.rx_dropped += (skb == NULL);
2426 sky2_rx_submit(sky2, re);
2431 /* Truncation of overlength packets
2432 causes PHY length to not match MAC length */
2433 ++dev->stats.rx_length_errors;
2434 if (net_ratelimit())
2435 netif_info(sky2, rx_err, dev,
2436 "rx length error: status %#x length %d\n",
2441 ++dev->stats.rx_errors;
2442 if (status & GMR_FS_RX_FF_OV) {
2443 dev->stats.rx_over_errors++;
2447 if (net_ratelimit())
2448 netif_info(sky2, rx_err, dev,
2449 "rx error, status 0x%x length %d\n", status, length);
2451 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2452 dev->stats.rx_length_errors++;
2453 if (status & GMR_FS_FRAGMENT)
2454 dev->stats.rx_frame_errors++;
2455 if (status & GMR_FS_CRC_ERR)
2456 dev->stats.rx_crc_errors++;
2461 /* Transmit complete */
2462 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2464 struct sky2_port *sky2 = netdev_priv(dev);
2466 if (netif_running(dev)) {
2467 sky2_tx_complete(sky2, last);
2469 /* Wake unless it's detached, and called e.g. from sky2_down() */
2470 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2471 netif_wake_queue(dev);
2475 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2476 u32 status, struct sk_buff *skb)
2478 #ifdef SKY2_VLAN_TAG_USED
2479 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2480 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2481 if (skb->ip_summed == CHECKSUM_NONE)
2482 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2484 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2489 if (skb->ip_summed == CHECKSUM_NONE)
2490 netif_receive_skb(skb);
2492 napi_gro_receive(&sky2->hw->napi, skb);
2495 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2496 unsigned packets, unsigned bytes)
2499 struct net_device *dev = hw->dev[port];
2501 dev->stats.rx_packets += packets;
2502 dev->stats.rx_bytes += bytes;
2503 dev->last_rx = jiffies;
2504 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2508 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2510 /* If this happens then driver assuming wrong format for chip type */
2511 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2513 /* Both checksum counters are programmed to start at
2514 * the same offset, so unless there is a problem they
2515 * should match. This failure is an early indication that
2516 * hardware receive checksumming won't work.
2518 if (likely((u16)(status >> 16) == (u16)status)) {
2519 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2520 skb->ip_summed = CHECKSUM_COMPLETE;
2521 skb->csum = le16_to_cpu(status);
2523 dev_notice(&sky2->hw->pdev->dev,
2524 "%s: receive checksum problem (status = %#x)\n",
2525 sky2->netdev->name, status);
2527 /* Disable checksum offload */
2528 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2529 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2534 /* Process status response ring */
2535 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2538 unsigned int total_bytes[2] = { 0 };
2539 unsigned int total_packets[2] = { 0 };
2543 struct sky2_port *sky2;
2544 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2546 struct net_device *dev;
2547 struct sk_buff *skb;
2550 u8 opcode = le->opcode;
2552 if (!(opcode & HW_OWNER))
2555 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2557 port = le->css & CSS_LINK_BIT;
2558 dev = hw->dev[port];
2559 sky2 = netdev_priv(dev);
2560 length = le16_to_cpu(le->length);
2561 status = le32_to_cpu(le->status);
2564 switch (opcode & ~HW_OWNER) {
2566 total_packets[port]++;
2567 total_bytes[port] += length;
2569 skb = sky2_receive(dev, length, status);
2573 /* This chip reports checksum status differently */
2574 if (hw->flags & SKY2_HW_NEW_LE) {
2575 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2576 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2577 (le->css & CSS_TCPUDPCSOK))
2578 skb->ip_summed = CHECKSUM_UNNECESSARY;
2580 skb->ip_summed = CHECKSUM_NONE;
2583 skb->protocol = eth_type_trans(skb, dev);
2585 sky2_skb_rx(sky2, status, skb);
2587 /* Stop after net poll weight */
2588 if (++work_done >= to_do)
2592 #ifdef SKY2_VLAN_TAG_USED
2594 sky2->rx_tag = length;
2598 sky2->rx_tag = length;
2602 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2603 sky2_rx_checksum(sky2, status);
2607 /* TX index reports status for both ports */
2608 sky2_tx_done(hw->dev[0], status & 0xfff);
2610 sky2_tx_done(hw->dev[1],
2611 ((status >> 24) & 0xff)
2612 | (u16)(length & 0xf) << 8);
2616 if (net_ratelimit())
2617 printk(KERN_WARNING PFX
2618 "unknown status opcode 0x%x\n", opcode);
2620 } while (hw->st_idx != idx);
2622 /* Fully processed status ring so clear irq */
2623 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2626 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2627 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2632 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2634 struct net_device *dev = hw->dev[port];
2636 if (net_ratelimit())
2637 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2640 if (status & Y2_IS_PAR_RD1) {
2641 if (net_ratelimit())
2642 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2645 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2648 if (status & Y2_IS_PAR_WR1) {
2649 if (net_ratelimit())
2650 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2653 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2656 if (status & Y2_IS_PAR_MAC1) {
2657 if (net_ratelimit())
2658 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2659 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2662 if (status & Y2_IS_PAR_RX1) {
2663 if (net_ratelimit())
2664 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2665 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2668 if (status & Y2_IS_TCP_TXA1) {
2669 if (net_ratelimit())
2670 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2672 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2676 static void sky2_hw_intr(struct sky2_hw *hw)
2678 struct pci_dev *pdev = hw->pdev;
2679 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2680 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2684 if (status & Y2_IS_TIST_OV)
2685 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2687 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2690 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2691 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2692 if (net_ratelimit())
2693 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2696 sky2_pci_write16(hw, PCI_STATUS,
2697 pci_err | PCI_STATUS_ERROR_BITS);
2698 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2701 if (status & Y2_IS_PCI_EXP) {
2702 /* PCI-Express uncorrectable Error occurred */
2705 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2706 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2707 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2709 if (net_ratelimit())
2710 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2712 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2716 if (status & Y2_HWE_L1_MASK)
2717 sky2_hw_error(hw, 0, status);
2719 if (status & Y2_HWE_L1_MASK)
2720 sky2_hw_error(hw, 1, status);
2723 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2725 struct net_device *dev = hw->dev[port];
2726 struct sky2_port *sky2 = netdev_priv(dev);
2727 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2729 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2731 if (status & GM_IS_RX_CO_OV)
2732 gma_read16(hw, port, GM_RX_IRQ_SRC);
2734 if (status & GM_IS_TX_CO_OV)
2735 gma_read16(hw, port, GM_TX_IRQ_SRC);
2737 if (status & GM_IS_RX_FF_OR) {
2738 ++dev->stats.rx_fifo_errors;
2739 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2742 if (status & GM_IS_TX_FF_UR) {
2743 ++dev->stats.tx_fifo_errors;
2744 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2748 /* This should never happen it is a bug. */
2749 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2751 struct net_device *dev = hw->dev[port];
2752 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2754 dev_err(&hw->pdev->dev, PFX
2755 "%s: descriptor error q=%#x get=%u put=%u\n",
2756 dev->name, (unsigned) q, (unsigned) idx,
2757 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2759 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2762 static int sky2_rx_hung(struct net_device *dev)
2764 struct sky2_port *sky2 = netdev_priv(dev);
2765 struct sky2_hw *hw = sky2->hw;
2766 unsigned port = sky2->port;
2767 unsigned rxq = rxqaddr[port];
2768 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2769 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2770 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2771 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2773 /* If idle and MAC or PCI is stuck */
2774 if (sky2->check.last == dev->last_rx &&
2775 ((mac_rp == sky2->check.mac_rp &&
2776 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2777 /* Check if the PCI RX hang */
2778 (fifo_rp == sky2->check.fifo_rp &&
2779 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2780 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2781 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2782 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2785 sky2->check.last = dev->last_rx;
2786 sky2->check.mac_rp = mac_rp;
2787 sky2->check.mac_lev = mac_lev;
2788 sky2->check.fifo_rp = fifo_rp;
2789 sky2->check.fifo_lev = fifo_lev;
2794 static void sky2_watchdog(unsigned long arg)
2796 struct sky2_hw *hw = (struct sky2_hw *) arg;
2798 /* Check for lost IRQ once a second */
2799 if (sky2_read32(hw, B0_ISRC)) {
2800 napi_schedule(&hw->napi);
2804 for (i = 0; i < hw->ports; i++) {
2805 struct net_device *dev = hw->dev[i];
2806 if (!netif_running(dev))
2810 /* For chips with Rx FIFO, check if stuck */
2811 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2812 sky2_rx_hung(dev)) {
2813 pr_info(PFX "%s: receiver hang detected\n",
2815 schedule_work(&hw->restart_work);
2824 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2827 /* Hardware/software error handling */
2828 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2830 if (net_ratelimit())
2831 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2833 if (status & Y2_IS_HW_ERR)
2836 if (status & Y2_IS_IRQ_MAC1)
2837 sky2_mac_intr(hw, 0);
2839 if (status & Y2_IS_IRQ_MAC2)
2840 sky2_mac_intr(hw, 1);
2842 if (status & Y2_IS_CHK_RX1)
2843 sky2_le_error(hw, 0, Q_R1);
2845 if (status & Y2_IS_CHK_RX2)
2846 sky2_le_error(hw, 1, Q_R2);
2848 if (status & Y2_IS_CHK_TXA1)
2849 sky2_le_error(hw, 0, Q_XA1);
2851 if (status & Y2_IS_CHK_TXA2)
2852 sky2_le_error(hw, 1, Q_XA2);
2855 static int sky2_poll(struct napi_struct *napi, int work_limit)
2857 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2858 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2862 if (unlikely(status & Y2_IS_ERROR))
2863 sky2_err_intr(hw, status);
2865 if (status & Y2_IS_IRQ_PHY1)
2866 sky2_phy_intr(hw, 0);
2868 if (status & Y2_IS_IRQ_PHY2)
2869 sky2_phy_intr(hw, 1);
2871 if (status & Y2_IS_PHY_QLNK)
2872 sky2_qlink_intr(hw);
2874 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2875 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2877 if (work_done >= work_limit)
2881 napi_complete(napi);
2882 sky2_read32(hw, B0_Y2_SP_LISR);
2888 static irqreturn_t sky2_intr(int irq, void *dev_id)
2890 struct sky2_hw *hw = dev_id;
2893 /* Reading this mask interrupts as side effect */
2894 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2895 if (status == 0 || status == ~0)
2898 prefetch(&hw->st_le[hw->st_idx]);
2900 napi_schedule(&hw->napi);
2905 #ifdef CONFIG_NET_POLL_CONTROLLER
2906 static void sky2_netpoll(struct net_device *dev)
2908 struct sky2_port *sky2 = netdev_priv(dev);
2910 napi_schedule(&sky2->hw->napi);
2914 /* Chip internal frequency for clock calculations */
2915 static u32 sky2_mhz(const struct sky2_hw *hw)
2917 switch (hw->chip_id) {
2918 case CHIP_ID_YUKON_EC:
2919 case CHIP_ID_YUKON_EC_U:
2920 case CHIP_ID_YUKON_EX:
2921 case CHIP_ID_YUKON_SUPR:
2922 case CHIP_ID_YUKON_UL_2:
2923 case CHIP_ID_YUKON_OPT:
2926 case CHIP_ID_YUKON_FE:
2929 case CHIP_ID_YUKON_FE_P:
2932 case CHIP_ID_YUKON_XL:
2940 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2942 return sky2_mhz(hw) * us;
2945 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2947 return clk / sky2_mhz(hw);
2951 static int __devinit sky2_init(struct sky2_hw *hw)
2955 /* Enable all clocks and check for bad PCI access */
2956 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2958 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2960 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2961 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2963 switch(hw->chip_id) {
2964 case CHIP_ID_YUKON_XL:
2965 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2968 case CHIP_ID_YUKON_EC_U:
2969 hw->flags = SKY2_HW_GIGABIT
2971 | SKY2_HW_ADV_POWER_CTL;
2974 case CHIP_ID_YUKON_EX:
2975 hw->flags = SKY2_HW_GIGABIT
2978 | SKY2_HW_ADV_POWER_CTL;
2980 /* New transmit checksum */
2981 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2982 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2985 case CHIP_ID_YUKON_EC:
2986 /* This rev is really old, and requires untested workarounds */
2987 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2988 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2991 hw->flags = SKY2_HW_GIGABIT;
2994 case CHIP_ID_YUKON_FE:
2997 case CHIP_ID_YUKON_FE_P:
2998 hw->flags = SKY2_HW_NEWER_PHY
3000 | SKY2_HW_AUTO_TX_SUM
3001 | SKY2_HW_ADV_POWER_CTL;
3004 case CHIP_ID_YUKON_SUPR:
3005 hw->flags = SKY2_HW_GIGABIT
3008 | SKY2_HW_AUTO_TX_SUM
3009 | SKY2_HW_ADV_POWER_CTL;
3012 case CHIP_ID_YUKON_UL_2:
3013 hw->flags = SKY2_HW_GIGABIT
3014 | SKY2_HW_ADV_POWER_CTL;
3017 case CHIP_ID_YUKON_OPT:
3018 hw->flags = SKY2_HW_GIGABIT
3020 | SKY2_HW_ADV_POWER_CTL;
3024 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3029 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3030 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3031 hw->flags |= SKY2_HW_FIBRE_PHY;
3034 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3035 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3036 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3040 if (sky2_read8(hw, B2_E_0))
3041 hw->flags |= SKY2_HW_RAM_BUFFER;
3046 static void sky2_reset(struct sky2_hw *hw)
3048 struct pci_dev *pdev = hw->pdev;
3051 u32 hwe_mask = Y2_HWE_ALL_MASK;
3054 if (hw->chip_id == CHIP_ID_YUKON_EX
3055 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3056 sky2_write32(hw, CPU_WDOG, 0);
3057 status = sky2_read16(hw, HCU_CCSR);
3058 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3059 HCU_CCSR_UC_STATE_MSK);
3061 * CPU clock divider shouldn't be used because
3062 * - ASF firmware may malfunction
3063 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3065 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3066 sky2_write16(hw, HCU_CCSR, status);
3067 sky2_write32(hw, CPU_WDOG, 0);
3069 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3070 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3073 sky2_write8(hw, B0_CTST, CS_RST_SET);
3074 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3076 /* allow writes to PCI config */
3077 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3079 /* clear PCI errors, if any */
3080 status = sky2_pci_read16(hw, PCI_STATUS);
3081 status |= PCI_STATUS_ERROR_BITS;
3082 sky2_pci_write16(hw, PCI_STATUS, status);
3084 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3086 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3088 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3091 /* If error bit is stuck on ignore it */
3092 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3093 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3095 hwe_mask |= Y2_IS_PCI_EXP;
3099 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3101 for (i = 0; i < hw->ports; i++) {
3102 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3103 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3105 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3106 hw->chip_id == CHIP_ID_YUKON_SUPR)
3107 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3108 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3113 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3114 /* enable MACSec clock gating */
3115 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3118 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3122 if (hw->chip_rev == 0) {
3123 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3124 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3126 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3129 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3133 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3135 /* reset PHY Link Detect */
3136 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3137 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3138 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3139 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3142 /* enable PHY Quick Link */
3143 msk = sky2_read32(hw, B0_IMSK);
3144 msk |= Y2_IS_PHY_QLNK;
3145 sky2_write32(hw, B0_IMSK, msk);
3147 /* check if PSMv2 was running before */
3148 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3149 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3150 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3151 /* restore the PCIe Link Control register */
3152 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3154 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3156 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3157 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3160 /* Clear I2C IRQ noise */
3161 sky2_write32(hw, B2_I2C_IRQ, 1);
3163 /* turn off hardware timer (unused) */
3164 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3165 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3167 /* Turn off descriptor polling */
3168 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3170 /* Turn off receive timestamp */
3171 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3172 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3174 /* enable the Tx Arbiters */
3175 for (i = 0; i < hw->ports; i++)
3176 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3178 /* Initialize ram interface */
3179 for (i = 0; i < hw->ports; i++) {
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3188 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3189 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3190 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3191 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3192 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3193 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3196 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3198 for (i = 0; i < hw->ports; i++)
3199 sky2_gmac_reset(hw, i);
3201 memset(hw->st_le, 0, STATUS_LE_BYTES);
3204 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3205 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3207 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3208 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3210 /* Set the list last index */
3211 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3213 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3214 sky2_write8(hw, STAT_FIFO_WM, 16);
3216 /* set Status-FIFO ISR watermark */
3217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3218 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3220 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3222 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3223 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3224 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3226 /* enable status unit */
3227 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3229 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3230 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3231 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3234 /* Take device down (offline).
3235 * Equivalent to doing dev_stop() but this does not
3236 * inform upper layers of the transistion.
3238 static void sky2_detach(struct net_device *dev)
3240 if (netif_running(dev)) {
3242 netif_device_detach(dev); /* stop txq */
3243 netif_tx_unlock(dev);
3248 /* Bring device back after doing sky2_detach */
3249 static int sky2_reattach(struct net_device *dev)
3253 if (netif_running(dev)) {
3256 printk(KERN_INFO PFX "%s: could not restart %d\n",
3260 netif_device_attach(dev);
3261 sky2_set_multicast(dev);
3268 static void sky2_restart(struct work_struct *work)
3270 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3276 napi_disable(&hw->napi);
3277 synchronize_irq(hw->pdev->irq);
3278 imask = sky2_read32(hw, B0_IMSK);
3279 sky2_write32(hw, B0_IMSK, 0);
3281 for (i = 0; i < hw->ports; i++) {
3282 struct net_device *dev = hw->dev[i];
3283 struct sky2_port *sky2 = netdev_priv(dev);
3285 if (!netif_running(dev))
3288 netif_carrier_off(dev);
3289 netif_tx_disable(dev);
3295 for (i = 0; i < hw->ports; i++) {
3296 struct net_device *dev = hw->dev[i];
3297 struct sky2_port *sky2 = netdev_priv(dev);
3299 if (!netif_running(dev))
3303 netif_wake_queue(dev);
3306 sky2_write32(hw, B0_IMSK, imask);
3307 sky2_read32(hw, B0_IMSK);
3309 sky2_read32(hw, B0_Y2_SP_LISR);
3310 napi_enable(&hw->napi);
3315 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3317 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3320 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3322 const struct sky2_port *sky2 = netdev_priv(dev);
3324 wol->supported = sky2_wol_supported(sky2->hw);
3325 wol->wolopts = sky2->wol;
3328 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3330 struct sky2_port *sky2 = netdev_priv(dev);
3331 struct sky2_hw *hw = sky2->hw;
3333 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3334 !device_can_wakeup(&hw->pdev->dev))
3337 sky2->wol = wol->wolopts;
3341 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3343 if (sky2_is_copper(hw)) {
3344 u32 modes = SUPPORTED_10baseT_Half
3345 | SUPPORTED_10baseT_Full
3346 | SUPPORTED_100baseT_Half
3347 | SUPPORTED_100baseT_Full
3348 | SUPPORTED_Autoneg | SUPPORTED_TP;
3350 if (hw->flags & SKY2_HW_GIGABIT)
3351 modes |= SUPPORTED_1000baseT_Half
3352 | SUPPORTED_1000baseT_Full;
3355 return SUPPORTED_1000baseT_Half
3356 | SUPPORTED_1000baseT_Full
3361 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3363 struct sky2_port *sky2 = netdev_priv(dev);
3364 struct sky2_hw *hw = sky2->hw;
3366 ecmd->transceiver = XCVR_INTERNAL;
3367 ecmd->supported = sky2_supported_modes(hw);
3368 ecmd->phy_address = PHY_ADDR_MARV;
3369 if (sky2_is_copper(hw)) {
3370 ecmd->port = PORT_TP;
3371 ecmd->speed = sky2->speed;
3373 ecmd->speed = SPEED_1000;
3374 ecmd->port = PORT_FIBRE;
3377 ecmd->advertising = sky2->advertising;
3378 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3379 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3380 ecmd->duplex = sky2->duplex;
3384 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3386 struct sky2_port *sky2 = netdev_priv(dev);
3387 const struct sky2_hw *hw = sky2->hw;
3388 u32 supported = sky2_supported_modes(hw);
3390 if (ecmd->autoneg == AUTONEG_ENABLE) {
3391 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3392 ecmd->advertising = supported;
3398 switch (ecmd->speed) {
3400 if (ecmd->duplex == DUPLEX_FULL)
3401 setting = SUPPORTED_1000baseT_Full;
3402 else if (ecmd->duplex == DUPLEX_HALF)
3403 setting = SUPPORTED_1000baseT_Half;
3408 if (ecmd->duplex == DUPLEX_FULL)
3409 setting = SUPPORTED_100baseT_Full;
3410 else if (ecmd->duplex == DUPLEX_HALF)
3411 setting = SUPPORTED_100baseT_Half;
3417 if (ecmd->duplex == DUPLEX_FULL)
3418 setting = SUPPORTED_10baseT_Full;
3419 else if (ecmd->duplex == DUPLEX_HALF)
3420 setting = SUPPORTED_10baseT_Half;
3428 if ((setting & supported) == 0)
3431 sky2->speed = ecmd->speed;
3432 sky2->duplex = ecmd->duplex;
3433 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3436 sky2->advertising = ecmd->advertising;
3438 if (netif_running(dev)) {
3439 sky2_phy_reinit(sky2);
3440 sky2_set_multicast(dev);
3446 static void sky2_get_drvinfo(struct net_device *dev,
3447 struct ethtool_drvinfo *info)
3449 struct sky2_port *sky2 = netdev_priv(dev);
3451 strcpy(info->driver, DRV_NAME);
3452 strcpy(info->version, DRV_VERSION);
3453 strcpy(info->fw_version, "N/A");
3454 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3457 static const struct sky2_stat {
3458 char name[ETH_GSTRING_LEN];
3461 { "tx_bytes", GM_TXO_OK_HI },
3462 { "rx_bytes", GM_RXO_OK_HI },
3463 { "tx_broadcast", GM_TXF_BC_OK },
3464 { "rx_broadcast", GM_RXF_BC_OK },
3465 { "tx_multicast", GM_TXF_MC_OK },
3466 { "rx_multicast", GM_RXF_MC_OK },
3467 { "tx_unicast", GM_TXF_UC_OK },
3468 { "rx_unicast", GM_RXF_UC_OK },
3469 { "tx_mac_pause", GM_TXF_MPAUSE },
3470 { "rx_mac_pause", GM_RXF_MPAUSE },
3471 { "collisions", GM_TXF_COL },
3472 { "late_collision",GM_TXF_LAT_COL },
3473 { "aborted", GM_TXF_ABO_COL },
3474 { "single_collisions", GM_TXF_SNG_COL },
3475 { "multi_collisions", GM_TXF_MUL_COL },
3477 { "rx_short", GM_RXF_SHT },
3478 { "rx_runt", GM_RXE_FRAG },
3479 { "rx_64_byte_packets", GM_RXF_64B },
3480 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3481 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3482 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3483 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3484 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3485 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3486 { "rx_too_long", GM_RXF_LNG_ERR },
3487 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3488 { "rx_jabber", GM_RXF_JAB_PKT },
3489 { "rx_fcs_error", GM_RXF_FCS_ERR },
3491 { "tx_64_byte_packets", GM_TXF_64B },
3492 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3493 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3494 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3495 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3496 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3497 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3498 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3501 static u32 sky2_get_rx_csum(struct net_device *dev)
3503 struct sky2_port *sky2 = netdev_priv(dev);
3505 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3508 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3510 struct sky2_port *sky2 = netdev_priv(dev);
3513 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3515 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3517 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3518 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3523 static u32 sky2_get_msglevel(struct net_device *netdev)
3525 struct sky2_port *sky2 = netdev_priv(netdev);
3526 return sky2->msg_enable;
3529 static int sky2_nway_reset(struct net_device *dev)
3531 struct sky2_port *sky2 = netdev_priv(dev);
3533 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3536 sky2_phy_reinit(sky2);
3537 sky2_set_multicast(dev);
3542 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3544 struct sky2_hw *hw = sky2->hw;
3545 unsigned port = sky2->port;
3548 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3549 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3550 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3551 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3553 for (i = 2; i < count; i++)
3554 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3557 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3559 struct sky2_port *sky2 = netdev_priv(netdev);
3560 sky2->msg_enable = value;
3563 static int sky2_get_sset_count(struct net_device *dev, int sset)
3567 return ARRAY_SIZE(sky2_stats);
3573 static void sky2_get_ethtool_stats(struct net_device *dev,
3574 struct ethtool_stats *stats, u64 * data)
3576 struct sky2_port *sky2 = netdev_priv(dev);
3578 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3581 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3585 switch (stringset) {
3587 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3588 memcpy(data + i * ETH_GSTRING_LEN,
3589 sky2_stats[i].name, ETH_GSTRING_LEN);
3594 static int sky2_set_mac_address(struct net_device *dev, void *p)
3596 struct sky2_port *sky2 = netdev_priv(dev);
3597 struct sky2_hw *hw = sky2->hw;
3598 unsigned port = sky2->port;
3599 const struct sockaddr *addr = p;
3601 if (!is_valid_ether_addr(addr->sa_data))
3602 return -EADDRNOTAVAIL;
3604 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3605 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3606 dev->dev_addr, ETH_ALEN);
3607 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3608 dev->dev_addr, ETH_ALEN);
3610 /* virtual address for data */
3611 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3613 /* physical address: used for pause frames */
3614 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3619 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3623 bit = ether_crc(ETH_ALEN, addr) & 63;
3624 filter[bit >> 3] |= 1 << (bit & 7);
3627 static void sky2_set_multicast(struct net_device *dev)
3629 struct sky2_port *sky2 = netdev_priv(dev);
3630 struct sky2_hw *hw = sky2->hw;
3631 unsigned port = sky2->port;
3632 struct dev_mc_list *list = dev->mc_list;
3636 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3638 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3639 memset(filter, 0, sizeof(filter));
3641 reg = gma_read16(hw, port, GM_RX_CTRL);
3642 reg |= GM_RXCR_UCF_ENA;
3644 if (dev->flags & IFF_PROMISC) /* promiscuous */
3645 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3646 else if (dev->flags & IFF_ALLMULTI)
3647 memset(filter, 0xff, sizeof(filter));
3648 else if (netdev_mc_empty(dev) && !rx_pause)
3649 reg &= ~GM_RXCR_MCF_ENA;
3652 reg |= GM_RXCR_MCF_ENA;
3655 sky2_add_filter(filter, pause_mc_addr);
3657 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
3658 sky2_add_filter(filter, list->dmi_addr);
3661 gma_write16(hw, port, GM_MC_ADDR_H1,
3662 (u16) filter[0] | ((u16) filter[1] << 8));
3663 gma_write16(hw, port, GM_MC_ADDR_H2,
3664 (u16) filter[2] | ((u16) filter[3] << 8));
3665 gma_write16(hw, port, GM_MC_ADDR_H3,
3666 (u16) filter[4] | ((u16) filter[5] << 8));
3667 gma_write16(hw, port, GM_MC_ADDR_H4,
3668 (u16) filter[6] | ((u16) filter[7] << 8));
3670 gma_write16(hw, port, GM_RX_CTRL, reg);
3673 /* Can have one global because blinking is controlled by
3674 * ethtool and that is always under RTNL mutex
3676 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3678 struct sky2_hw *hw = sky2->hw;
3679 unsigned port = sky2->port;
3681 spin_lock_bh(&sky2->phy_lock);
3682 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3683 hw->chip_id == CHIP_ID_YUKON_EX ||
3684 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3686 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3691 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3692 PHY_M_LEDC_LOS_CTRL(8) |
3693 PHY_M_LEDC_INIT_CTRL(8) |
3694 PHY_M_LEDC_STA1_CTRL(8) |
3695 PHY_M_LEDC_STA0_CTRL(8));
3698 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3699 PHY_M_LEDC_LOS_CTRL(9) |
3700 PHY_M_LEDC_INIT_CTRL(9) |
3701 PHY_M_LEDC_STA1_CTRL(9) |
3702 PHY_M_LEDC_STA0_CTRL(9));
3705 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3706 PHY_M_LEDC_LOS_CTRL(0xa) |
3707 PHY_M_LEDC_INIT_CTRL(0xa) |
3708 PHY_M_LEDC_STA1_CTRL(0xa) |
3709 PHY_M_LEDC_STA0_CTRL(0xa));
3712 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3713 PHY_M_LEDC_LOS_CTRL(1) |
3714 PHY_M_LEDC_INIT_CTRL(8) |
3715 PHY_M_LEDC_STA1_CTRL(7) |
3716 PHY_M_LEDC_STA0_CTRL(7));
3719 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3721 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3722 PHY_M_LED_MO_DUP(mode) |
3723 PHY_M_LED_MO_10(mode) |
3724 PHY_M_LED_MO_100(mode) |
3725 PHY_M_LED_MO_1000(mode) |
3726 PHY_M_LED_MO_RX(mode) |
3727 PHY_M_LED_MO_TX(mode));
3729 spin_unlock_bh(&sky2->phy_lock);
3732 /* blink LED's for finding board */
3733 static int sky2_phys_id(struct net_device *dev, u32 data)
3735 struct sky2_port *sky2 = netdev_priv(dev);
3741 for (i = 0; i < data; i++) {
3742 sky2_led(sky2, MO_LED_ON);
3743 if (msleep_interruptible(500))
3745 sky2_led(sky2, MO_LED_OFF);
3746 if (msleep_interruptible(500))
3749 sky2_led(sky2, MO_LED_NORM);
3754 static void sky2_get_pauseparam(struct net_device *dev,
3755 struct ethtool_pauseparam *ecmd)
3757 struct sky2_port *sky2 = netdev_priv(dev);
3759 switch (sky2->flow_mode) {
3761 ecmd->tx_pause = ecmd->rx_pause = 0;
3764 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3767 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3770 ecmd->tx_pause = ecmd->rx_pause = 1;
3773 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3774 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3777 static int sky2_set_pauseparam(struct net_device *dev,
3778 struct ethtool_pauseparam *ecmd)
3780 struct sky2_port *sky2 = netdev_priv(dev);
3782 if (ecmd->autoneg == AUTONEG_ENABLE)
3783 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3785 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3787 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3789 if (netif_running(dev))
3790 sky2_phy_reinit(sky2);
3795 static int sky2_get_coalesce(struct net_device *dev,
3796 struct ethtool_coalesce *ecmd)
3798 struct sky2_port *sky2 = netdev_priv(dev);
3799 struct sky2_hw *hw = sky2->hw;
3801 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3802 ecmd->tx_coalesce_usecs = 0;
3804 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3805 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3807 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3809 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3810 ecmd->rx_coalesce_usecs = 0;
3812 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3813 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3815 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3817 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3818 ecmd->rx_coalesce_usecs_irq = 0;
3820 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3821 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3824 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3829 /* Note: this affect both ports */
3830 static int sky2_set_coalesce(struct net_device *dev,
3831 struct ethtool_coalesce *ecmd)
3833 struct sky2_port *sky2 = netdev_priv(dev);
3834 struct sky2_hw *hw = sky2->hw;
3835 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3837 if (ecmd->tx_coalesce_usecs > tmax ||
3838 ecmd->rx_coalesce_usecs > tmax ||
3839 ecmd->rx_coalesce_usecs_irq > tmax)
3842 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3844 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3846 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3849 if (ecmd->tx_coalesce_usecs == 0)
3850 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3852 sky2_write32(hw, STAT_TX_TIMER_INI,
3853 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3854 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3856 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3858 if (ecmd->rx_coalesce_usecs == 0)
3859 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3861 sky2_write32(hw, STAT_LEV_TIMER_INI,
3862 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3863 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3865 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3867 if (ecmd->rx_coalesce_usecs_irq == 0)
3868 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3870 sky2_write32(hw, STAT_ISR_TIMER_INI,
3871 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3872 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3874 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3878 static void sky2_get_ringparam(struct net_device *dev,
3879 struct ethtool_ringparam *ering)
3881 struct sky2_port *sky2 = netdev_priv(dev);
3883 ering->rx_max_pending = RX_MAX_PENDING;
3884 ering->rx_mini_max_pending = 0;
3885 ering->rx_jumbo_max_pending = 0;
3886 ering->tx_max_pending = TX_MAX_PENDING;
3888 ering->rx_pending = sky2->rx_pending;
3889 ering->rx_mini_pending = 0;
3890 ering->rx_jumbo_pending = 0;
3891 ering->tx_pending = sky2->tx_pending;
3894 static int sky2_set_ringparam(struct net_device *dev,
3895 struct ethtool_ringparam *ering)
3897 struct sky2_port *sky2 = netdev_priv(dev);
3899 if (ering->rx_pending > RX_MAX_PENDING ||
3900 ering->rx_pending < 8 ||
3901 ering->tx_pending < TX_MIN_PENDING ||
3902 ering->tx_pending > TX_MAX_PENDING)
3907 sky2->rx_pending = ering->rx_pending;
3908 sky2->tx_pending = ering->tx_pending;
3909 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3911 return sky2_reattach(dev);
3914 static int sky2_get_regs_len(struct net_device *dev)
3919 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3921 /* This complicated switch statement is to make sure and
3922 * only access regions that are unreserved.
3923 * Some blocks are only valid on dual port cards.
3927 case 5: /* Tx Arbiter 2 */
3929 case 14 ... 15: /* TX2 */
3930 case 17: case 19: /* Ram Buffer 2 */
3931 case 22 ... 23: /* Tx Ram Buffer 2 */
3932 case 25: /* Rx MAC Fifo 1 */
3933 case 27: /* Tx MAC Fifo 2 */
3934 case 31: /* GPHY 2 */
3935 case 40 ... 47: /* Pattern Ram 2 */
3936 case 52: case 54: /* TCP Segmentation 2 */
3937 case 112 ... 116: /* GMAC 2 */
3938 return hw->ports > 1;
3940 case 0: /* Control */
3941 case 2: /* Mac address */
3942 case 4: /* Tx Arbiter 1 */
3943 case 7: /* PCI express reg */
3945 case 12 ... 13: /* TX1 */
3946 case 16: case 18:/* Rx Ram Buffer 1 */
3947 case 20 ... 21: /* Tx Ram Buffer 1 */
3948 case 24: /* Rx MAC Fifo 1 */
3949 case 26: /* Tx MAC Fifo 1 */
3950 case 28 ... 29: /* Descriptor and status unit */
3951 case 30: /* GPHY 1*/
3952 case 32 ... 39: /* Pattern Ram 1 */
3953 case 48: case 50: /* TCP Segmentation 1 */
3954 case 56 ... 60: /* PCI space */
3955 case 80 ... 84: /* GMAC 1 */
3964 * Returns copy of control register region
3965 * Note: ethtool_get_regs always provides full size (16k) buffer
3967 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3970 const struct sky2_port *sky2 = netdev_priv(dev);
3971 const void __iomem *io = sky2->hw->regs;
3976 for (b = 0; b < 128; b++) {
3977 /* skip poisonous diagnostic ram region in block 3 */
3979 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3980 else if (sky2_reg_access_ok(sky2->hw, b))
3981 memcpy_fromio(p, io, 128);
3990 /* In order to do Jumbo packets on these chips, need to turn off the
3991 * transmit store/forward. Therefore checksum offload won't work.
3993 static int no_tx_offload(struct net_device *dev)
3995 const struct sky2_port *sky2 = netdev_priv(dev);
3996 const struct sky2_hw *hw = sky2->hw;
3998 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
4001 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4003 if (data && no_tx_offload(dev))
4006 return ethtool_op_set_tx_csum(dev, data);
4010 static int sky2_set_tso(struct net_device *dev, u32 data)
4012 if (data && no_tx_offload(dev))
4015 return ethtool_op_set_tso(dev, data);
4018 static int sky2_get_eeprom_len(struct net_device *dev)
4020 struct sky2_port *sky2 = netdev_priv(dev);
4021 struct sky2_hw *hw = sky2->hw;
4024 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4025 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4028 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4030 unsigned long start = jiffies;
4032 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4033 /* Can take up to 10.6 ms for write */
4034 if (time_after(jiffies, start + HZ/4)) {
4035 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
4044 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4045 u16 offset, size_t length)
4049 while (length > 0) {
4052 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4053 rc = sky2_vpd_wait(hw, cap, 0);
4057 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4059 memcpy(data, &val, min(sizeof(val), length));
4060 offset += sizeof(u32);
4061 data += sizeof(u32);
4062 length -= sizeof(u32);
4068 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4069 u16 offset, unsigned int length)
4074 for (i = 0; i < length; i += sizeof(u32)) {
4075 u32 val = *(u32 *)(data + i);
4077 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4078 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4080 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4087 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4090 struct sky2_port *sky2 = netdev_priv(dev);
4091 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4096 eeprom->magic = SKY2_EEPROM_MAGIC;
4098 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4101 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4104 struct sky2_port *sky2 = netdev_priv(dev);
4105 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4110 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4113 /* Partial writes not supported */
4114 if ((eeprom->offset & 3) || (eeprom->len & 3))
4117 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4121 static const struct ethtool_ops sky2_ethtool_ops = {
4122 .get_settings = sky2_get_settings,
4123 .set_settings = sky2_set_settings,
4124 .get_drvinfo = sky2_get_drvinfo,
4125 .get_wol = sky2_get_wol,
4126 .set_wol = sky2_set_wol,
4127 .get_msglevel = sky2_get_msglevel,
4128 .set_msglevel = sky2_set_msglevel,
4129 .nway_reset = sky2_nway_reset,
4130 .get_regs_len = sky2_get_regs_len,
4131 .get_regs = sky2_get_regs,
4132 .get_link = ethtool_op_get_link,
4133 .get_eeprom_len = sky2_get_eeprom_len,
4134 .get_eeprom = sky2_get_eeprom,
4135 .set_eeprom = sky2_set_eeprom,
4136 .set_sg = ethtool_op_set_sg,
4137 .set_tx_csum = sky2_set_tx_csum,
4138 .set_tso = sky2_set_tso,
4139 .get_rx_csum = sky2_get_rx_csum,
4140 .set_rx_csum = sky2_set_rx_csum,
4141 .get_strings = sky2_get_strings,
4142 .get_coalesce = sky2_get_coalesce,
4143 .set_coalesce = sky2_set_coalesce,
4144 .get_ringparam = sky2_get_ringparam,
4145 .set_ringparam = sky2_set_ringparam,
4146 .get_pauseparam = sky2_get_pauseparam,
4147 .set_pauseparam = sky2_set_pauseparam,
4148 .phys_id = sky2_phys_id,
4149 .get_sset_count = sky2_get_sset_count,
4150 .get_ethtool_stats = sky2_get_ethtool_stats,
4153 #ifdef CONFIG_SKY2_DEBUG
4155 static struct dentry *sky2_debug;
4159 * Read and parse the first part of Vital Product Data
4161 #define VPD_SIZE 128
4162 #define VPD_MAGIC 0x82
4164 static const struct vpd_tag {
4168 { "PN", "Part Number" },
4169 { "EC", "Engineering Level" },
4170 { "MN", "Manufacturer" },
4171 { "SN", "Serial Number" },
4172 { "YA", "Asset Tag" },
4173 { "VL", "First Error Log Message" },
4174 { "VF", "Second Error Log Message" },
4175 { "VB", "Boot Agent ROM Configuration" },
4176 { "VE", "EFI UNDI Configuration" },
4179 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4187 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4188 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4190 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4191 buf = kmalloc(vpd_size, GFP_KERNEL);
4193 seq_puts(seq, "no memory!\n");
4197 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4198 seq_puts(seq, "VPD read failed\n");
4202 if (buf[0] != VPD_MAGIC) {
4203 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4207 if (len == 0 || len > vpd_size - 4) {
4208 seq_printf(seq, "Invalid id length: %d\n", len);
4212 seq_printf(seq, "%.*s\n", len, buf + 3);
4215 while (offs < vpd_size - 4) {
4218 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4220 len = buf[offs + 2];
4221 if (offs + len + 3 >= vpd_size)
4224 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4225 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4226 seq_printf(seq, " %s: %.*s\n",
4227 vpd_tags[i].label, len, buf + offs + 3);
4237 static int sky2_debug_show(struct seq_file *seq, void *v)
4239 struct net_device *dev = seq->private;
4240 const struct sky2_port *sky2 = netdev_priv(dev);
4241 struct sky2_hw *hw = sky2->hw;
4242 unsigned port = sky2->port;
4246 sky2_show_vpd(seq, hw);
4248 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4249 sky2_read32(hw, B0_ISRC),
4250 sky2_read32(hw, B0_IMSK),
4251 sky2_read32(hw, B0_Y2_SP_ICR));
4253 if (!netif_running(dev)) {
4254 seq_printf(seq, "network not running\n");
4258 napi_disable(&hw->napi);
4259 last = sky2_read16(hw, STAT_PUT_IDX);
4261 if (hw->st_idx == last)
4262 seq_puts(seq, "Status ring (empty)\n");
4264 seq_puts(seq, "Status ring\n");
4265 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4266 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4267 const struct sky2_status_le *le = hw->st_le + idx;
4268 seq_printf(seq, "[%d] %#x %d %#x\n",
4269 idx, le->opcode, le->length, le->status);
4271 seq_puts(seq, "\n");
4274 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4275 sky2->tx_cons, sky2->tx_prod,
4276 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4277 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4279 /* Dump contents of tx ring */
4281 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4282 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4283 const struct sky2_tx_le *le = sky2->tx_le + idx;
4284 u32 a = le32_to_cpu(le->addr);
4287 seq_printf(seq, "%u:", idx);
4290 switch(le->opcode & ~HW_OWNER) {
4292 seq_printf(seq, " %#x:", a);
4295 seq_printf(seq, " mtu=%d", a);
4298 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4301 seq_printf(seq, " csum=%#x", a);
4304 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4307 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4310 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4313 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4314 a, le16_to_cpu(le->length));
4317 if (le->ctrl & EOP) {
4318 seq_putc(seq, '\n');
4323 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4324 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4325 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4326 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4328 sky2_read32(hw, B0_Y2_SP_LISR);
4329 napi_enable(&hw->napi);
4333 static int sky2_debug_open(struct inode *inode, struct file *file)
4335 return single_open(file, sky2_debug_show, inode->i_private);
4338 static const struct file_operations sky2_debug_fops = {
4339 .owner = THIS_MODULE,
4340 .open = sky2_debug_open,
4342 .llseek = seq_lseek,
4343 .release = single_release,
4347 * Use network device events to create/remove/rename
4348 * debugfs file entries
4350 static int sky2_device_event(struct notifier_block *unused,
4351 unsigned long event, void *ptr)
4353 struct net_device *dev = ptr;
4354 struct sky2_port *sky2 = netdev_priv(dev);
4356 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4360 case NETDEV_CHANGENAME:
4361 if (sky2->debugfs) {
4362 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4363 sky2_debug, dev->name);
4367 case NETDEV_GOING_DOWN:
4368 if (sky2->debugfs) {
4369 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4371 debugfs_remove(sky2->debugfs);
4372 sky2->debugfs = NULL;
4377 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4380 if (IS_ERR(sky2->debugfs))
4381 sky2->debugfs = NULL;
4387 static struct notifier_block sky2_notifier = {
4388 .notifier_call = sky2_device_event,
4392 static __init void sky2_debug_init(void)
4396 ent = debugfs_create_dir("sky2", NULL);
4397 if (!ent || IS_ERR(ent))
4401 register_netdevice_notifier(&sky2_notifier);
4404 static __exit void sky2_debug_cleanup(void)
4407 unregister_netdevice_notifier(&sky2_notifier);
4408 debugfs_remove(sky2_debug);
4414 #define sky2_debug_init()
4415 #define sky2_debug_cleanup()
4418 /* Two copies of network device operations to handle special case of
4419 not allowing netpoll on second port */
4420 static const struct net_device_ops sky2_netdev_ops[2] = {
4422 .ndo_open = sky2_up,
4423 .ndo_stop = sky2_down,
4424 .ndo_start_xmit = sky2_xmit_frame,
4425 .ndo_do_ioctl = sky2_ioctl,
4426 .ndo_validate_addr = eth_validate_addr,
4427 .ndo_set_mac_address = sky2_set_mac_address,
4428 .ndo_set_multicast_list = sky2_set_multicast,
4429 .ndo_change_mtu = sky2_change_mtu,
4430 .ndo_tx_timeout = sky2_tx_timeout,
4431 #ifdef SKY2_VLAN_TAG_USED
4432 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4434 #ifdef CONFIG_NET_POLL_CONTROLLER
4435 .ndo_poll_controller = sky2_netpoll,
4439 .ndo_open = sky2_up,
4440 .ndo_stop = sky2_down,
4441 .ndo_start_xmit = sky2_xmit_frame,
4442 .ndo_do_ioctl = sky2_ioctl,
4443 .ndo_validate_addr = eth_validate_addr,
4444 .ndo_set_mac_address = sky2_set_mac_address,
4445 .ndo_set_multicast_list = sky2_set_multicast,
4446 .ndo_change_mtu = sky2_change_mtu,
4447 .ndo_tx_timeout = sky2_tx_timeout,
4448 #ifdef SKY2_VLAN_TAG_USED
4449 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4454 /* Initialize network device */
4455 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4457 int highmem, int wol)
4459 struct sky2_port *sky2;
4460 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4463 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4467 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4468 dev->irq = hw->pdev->irq;
4469 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4470 dev->watchdog_timeo = TX_WATCHDOG;
4471 dev->netdev_ops = &sky2_netdev_ops[port];
4473 sky2 = netdev_priv(dev);
4476 sky2->msg_enable = netif_msg_init(debug, default_msg);
4478 /* Auto speed and flow control */
4479 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4480 if (hw->chip_id != CHIP_ID_YUKON_XL)
4481 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4483 sky2->flow_mode = FC_BOTH;
4487 sky2->advertising = sky2_supported_modes(hw);
4490 spin_lock_init(&sky2->phy_lock);
4492 sky2->tx_pending = TX_DEF_PENDING;
4493 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4494 sky2->rx_pending = RX_DEF_PENDING;
4496 hw->dev[port] = dev;
4500 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4502 dev->features |= NETIF_F_HIGHDMA;
4504 #ifdef SKY2_VLAN_TAG_USED
4505 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4506 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4507 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4508 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4512 /* read the mac address */
4513 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4514 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4519 static void __devinit sky2_show_addr(struct net_device *dev)
4521 const struct sky2_port *sky2 = netdev_priv(dev);
4523 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4526 /* Handle software interrupt used during MSI test */
4527 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4529 struct sky2_hw *hw = dev_id;
4530 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4535 if (status & Y2_IS_IRQ_SW) {
4536 hw->flags |= SKY2_HW_USE_MSI;
4537 wake_up(&hw->msi_wait);
4538 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4540 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4545 /* Test interrupt path by forcing a a software IRQ */
4546 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4548 struct pci_dev *pdev = hw->pdev;
4551 init_waitqueue_head (&hw->msi_wait);
4553 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4555 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4557 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4561 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4562 sky2_read8(hw, B0_CTST);
4564 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4566 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4567 /* MSI test failed, go back to INTx mode */
4568 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4569 "switching to INTx mode.\n");
4572 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4575 sky2_write32(hw, B0_IMSK, 0);
4576 sky2_read32(hw, B0_IMSK);
4578 free_irq(pdev->irq, hw);
4583 /* This driver supports yukon2 chipset only */
4584 static const char *sky2_name(u8 chipid, char *buf, int sz)
4586 const char *name[] = {
4588 "EC Ultra", /* 0xb4 */
4589 "Extreme", /* 0xb5 */
4593 "Supreme", /* 0xb9 */
4595 "Unknown", /* 0xbb */
4596 "Optima", /* 0xbc */
4599 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4600 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4602 snprintf(buf, sz, "(chip %#x)", chipid);
4606 static int __devinit sky2_probe(struct pci_dev *pdev,
4607 const struct pci_device_id *ent)
4609 struct net_device *dev;
4611 int err, using_dac = 0, wol_default;
4615 err = pci_enable_device(pdev);
4617 dev_err(&pdev->dev, "cannot enable PCI device\n");
4621 /* Get configuration information
4622 * Note: only regular PCI config access once to test for HW issues
4623 * other PCI access through shared memory for speed and to
4624 * avoid MMCONFIG problems.
4626 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4628 dev_err(&pdev->dev, "PCI read config failed\n");
4633 dev_err(&pdev->dev, "PCI configuration read error\n");
4637 err = pci_request_regions(pdev, DRV_NAME);
4639 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4640 goto err_out_disable;
4643 pci_set_master(pdev);
4645 if (sizeof(dma_addr_t) > sizeof(u32) &&
4646 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4648 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4650 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4651 "for consistent allocations\n");
4652 goto err_out_free_regions;
4655 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4657 dev_err(&pdev->dev, "no usable DMA configuration\n");
4658 goto err_out_free_regions;
4664 /* The sk98lin vendor driver uses hardware byte swapping but
4665 * this driver uses software swapping.
4667 reg &= ~PCI_REV_DESC;
4668 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4670 dev_err(&pdev->dev, "PCI write config failed\n");
4671 goto err_out_free_regions;
4675 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4679 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4680 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4682 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4683 goto err_out_free_regions;
4687 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4689 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4691 dev_err(&pdev->dev, "cannot map device registers\n");
4692 goto err_out_free_hw;
4695 /* ring for status responses */
4696 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4698 goto err_out_iounmap;
4700 err = sky2_init(hw);
4702 goto err_out_iounmap;
4704 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4705 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4709 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4712 goto err_out_free_pci;
4715 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4716 err = sky2_test_msi(hw);
4717 if (err == -EOPNOTSUPP)
4718 pci_disable_msi(pdev);
4720 goto err_out_free_netdev;
4723 err = register_netdev(dev);
4725 dev_err(&pdev->dev, "cannot register net device\n");
4726 goto err_out_free_netdev;
4729 netif_carrier_off(dev);
4731 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4733 err = request_irq(pdev->irq, sky2_intr,
4734 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4737 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4738 goto err_out_unregister;
4740 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4741 napi_enable(&hw->napi);
4743 sky2_show_addr(dev);
4745 if (hw->ports > 1) {
4746 struct net_device *dev1;
4749 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4750 if (dev1 && (err = register_netdev(dev1)) == 0)
4751 sky2_show_addr(dev1);
4753 dev_warn(&pdev->dev,
4754 "register of second port failed (%d)\n", err);
4762 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4763 INIT_WORK(&hw->restart_work, sky2_restart);
4765 pci_set_drvdata(pdev, hw);
4766 pdev->d3_delay = 150;
4771 if (hw->flags & SKY2_HW_USE_MSI)
4772 pci_disable_msi(pdev);
4773 unregister_netdev(dev);
4774 err_out_free_netdev:
4777 sky2_write8(hw, B0_CTST, CS_RST_SET);
4778 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4783 err_out_free_regions:
4784 pci_release_regions(pdev);
4786 pci_disable_device(pdev);
4788 pci_set_drvdata(pdev, NULL);
4792 static void __devexit sky2_remove(struct pci_dev *pdev)
4794 struct sky2_hw *hw = pci_get_drvdata(pdev);
4800 del_timer_sync(&hw->watchdog_timer);
4801 cancel_work_sync(&hw->restart_work);
4803 for (i = hw->ports-1; i >= 0; --i)
4804 unregister_netdev(hw->dev[i]);
4806 sky2_write32(hw, B0_IMSK, 0);
4810 sky2_write8(hw, B0_CTST, CS_RST_SET);
4811 sky2_read8(hw, B0_CTST);
4813 free_irq(pdev->irq, hw);
4814 if (hw->flags & SKY2_HW_USE_MSI)
4815 pci_disable_msi(pdev);
4816 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4817 pci_release_regions(pdev);
4818 pci_disable_device(pdev);
4820 for (i = hw->ports-1; i >= 0; --i)
4821 free_netdev(hw->dev[i]);
4826 pci_set_drvdata(pdev, NULL);
4829 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4831 struct sky2_hw *hw = pci_get_drvdata(pdev);
4837 del_timer_sync(&hw->watchdog_timer);
4838 cancel_work_sync(&hw->restart_work);
4841 for (i = 0; i < hw->ports; i++) {
4842 struct net_device *dev = hw->dev[i];
4843 struct sky2_port *sky2 = netdev_priv(dev);
4848 sky2_wol_init(sky2);
4853 device_set_wakeup_enable(&pdev->dev, wol != 0);
4855 sky2_write32(hw, B0_IMSK, 0);
4856 napi_disable(&hw->napi);
4860 pci_save_state(pdev);
4861 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4862 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4868 static int sky2_resume(struct pci_dev *pdev)
4870 struct sky2_hw *hw = pci_get_drvdata(pdev);
4876 err = pci_set_power_state(pdev, PCI_D0);
4880 err = pci_restore_state(pdev);
4884 pci_enable_wake(pdev, PCI_D0, 0);
4886 /* Re-enable all clocks */
4887 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4889 dev_err(&pdev->dev, "PCI write config failed\n");
4894 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4895 napi_enable(&hw->napi);
4898 for (i = 0; i < hw->ports; i++) {
4899 err = sky2_reattach(hw->dev[i]);
4909 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4910 pci_disable_device(pdev);
4915 static void sky2_shutdown(struct pci_dev *pdev)
4917 sky2_suspend(pdev, PMSG_SUSPEND);
4920 static struct pci_driver sky2_driver = {
4922 .id_table = sky2_id_table,
4923 .probe = sky2_probe,
4924 .remove = __devexit_p(sky2_remove),
4926 .suspend = sky2_suspend,
4927 .resume = sky2_resume,
4929 .shutdown = sky2_shutdown,
4932 static int __init sky2_init_module(void)
4934 pr_info(PFX "driver version " DRV_VERSION "\n");
4937 return pci_register_driver(&sky2_driver);
4940 static void __exit sky2_cleanup_module(void)
4942 pci_unregister_driver(&sky2_driver);
4943 sky2_debug_cleanup();
4946 module_init(sky2_init_module);
4947 module_exit(sky2_cleanup_module);
4949 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4950 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4951 MODULE_LICENSE("GPL");
4952 MODULE_VERSION(DRV_VERSION);