2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
33 #include <asm/cacheflush.h>
37 /* There is CPU dependent code */
38 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
39 #define SH_ETH_RESET_DEFAULT 1
40 static void sh_eth_set_duplex(struct net_device *ndev)
42 struct sh_eth_private *mdp = netdev_priv(ndev);
43 u32 ioaddr = ndev->base_addr;
45 if (mdp->duplex) /* Full */
46 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
48 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
51 static void sh_eth_set_rate(struct net_device *ndev)
53 struct sh_eth_private *mdp = netdev_priv(ndev);
54 u32 ioaddr = ndev->base_addr;
58 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
60 case 100:/* 100BASE */
61 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
69 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
70 .set_duplex = sh_eth_set_duplex,
71 .set_rate = sh_eth_set_rate,
73 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
74 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
75 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
77 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
78 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
79 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
80 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
89 #define SH_ETH_HAS_TSU 1
90 static void sh_eth_chip_reset(struct net_device *ndev)
93 ctrl_outl(ARSTR_ARSTR, ARSTR);
97 static void sh_eth_reset(struct net_device *ndev)
99 u32 ioaddr = ndev->base_addr;
102 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
103 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
105 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
111 printk(KERN_ERR "Device reset fail\n");
114 ctrl_outl(0x0, ioaddr + TDLAR);
115 ctrl_outl(0x0, ioaddr + TDFAR);
116 ctrl_outl(0x0, ioaddr + TDFXR);
117 ctrl_outl(0x0, ioaddr + TDFFR);
118 ctrl_outl(0x0, ioaddr + RDLAR);
119 ctrl_outl(0x0, ioaddr + RDFAR);
120 ctrl_outl(0x0, ioaddr + RDFXR);
121 ctrl_outl(0x0, ioaddr + RDFFR);
124 static void sh_eth_set_duplex(struct net_device *ndev)
126 struct sh_eth_private *mdp = netdev_priv(ndev);
127 u32 ioaddr = ndev->base_addr;
129 if (mdp->duplex) /* Full */
130 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
132 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
135 static void sh_eth_set_rate(struct net_device *ndev)
137 struct sh_eth_private *mdp = netdev_priv(ndev);
138 u32 ioaddr = ndev->base_addr;
140 switch (mdp->speed) {
141 case 10: /* 10BASE */
142 ctrl_outl(GECMR_10, ioaddr + GECMR);
144 case 100:/* 100BASE */
145 ctrl_outl(GECMR_100, ioaddr + GECMR);
147 case 1000: /* 1000BASE */
148 ctrl_outl(GECMR_1000, ioaddr + GECMR);
156 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
157 .chip_reset = sh_eth_chip_reset,
158 .set_duplex = sh_eth_set_duplex,
159 .set_rate = sh_eth_set_rate,
161 .ecsr_value = ECSR_ICD | ECSR_MPD,
162 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
163 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
165 .tx_check = EESR_TC1 | EESR_FTC,
166 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
167 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
169 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
182 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
183 #define SH_ETH_RESET_DEFAULT 1
184 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
185 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
192 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
193 #define SH_ETH_RESET_DEFAULT 1
194 #define SH_ETH_HAS_TSU 1
195 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
196 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
200 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
203 cd->ecsr_value = DEFAULT_ECSR_INIT;
205 if (!cd->ecsipr_value)
206 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
208 if (!cd->fcftr_value)
209 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
210 DEFAULT_FIFO_F_D_RFD;
213 cd->fdr_value = DEFAULT_FDR_INIT;
216 cd->rmcr_value = DEFAULT_RMCR_VALUE;
219 cd->tx_check = DEFAULT_TX_CHECK;
221 if (!cd->eesr_err_check)
222 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
224 if (!cd->tx_error_check)
225 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
228 #if defined(SH_ETH_RESET_DEFAULT)
230 static void sh_eth_reset(struct net_device *ndev)
232 u32 ioaddr = ndev->base_addr;
234 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
236 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
240 #if defined(CONFIG_CPU_SH4)
241 static void sh_eth_set_receive_align(struct sk_buff *skb)
245 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
247 skb_reserve(skb, reserve);
250 static void sh_eth_set_receive_align(struct sk_buff *skb)
252 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
257 /* CPU <-> EDMAC endian convert */
258 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
260 switch (mdp->edmac_endian) {
261 case EDMAC_LITTLE_ENDIAN:
262 return cpu_to_le32(x);
263 case EDMAC_BIG_ENDIAN:
264 return cpu_to_be32(x);
269 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
271 switch (mdp->edmac_endian) {
272 case EDMAC_LITTLE_ENDIAN:
273 return le32_to_cpu(x);
274 case EDMAC_BIG_ENDIAN:
275 return be32_to_cpu(x);
281 * Program the hardware MAC address from dev->dev_addr.
283 static void update_mac_address(struct net_device *ndev)
285 u32 ioaddr = ndev->base_addr;
287 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
288 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
290 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
295 * Get MAC address from SuperH MAC address register
297 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
298 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
299 * When you want use this device, you must set MAC address in bootloader.
302 static void read_mac_address(struct net_device *ndev)
304 u32 ioaddr = ndev->base_addr;
306 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
307 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
308 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
309 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
310 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
311 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
315 struct mdiobb_ctrl ctrl;
317 u32 mmd_msk;/* MMD */
324 static void bb_set(u32 addr, u32 msk)
326 ctrl_outl(ctrl_inl(addr) | msk, addr);
330 static void bb_clr(u32 addr, u32 msk)
332 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
336 static int bb_read(u32 addr, u32 msk)
338 return (ctrl_inl(addr) & msk) != 0;
341 /* Data I/O pin control */
342 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
344 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
346 bb_set(bitbang->addr, bitbang->mmd_msk);
348 bb_clr(bitbang->addr, bitbang->mmd_msk);
352 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
354 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
357 bb_set(bitbang->addr, bitbang->mdo_msk);
359 bb_clr(bitbang->addr, bitbang->mdo_msk);
363 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
365 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
366 return bb_read(bitbang->addr, bitbang->mdi_msk);
369 /* MDC pin control */
370 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
372 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
375 bb_set(bitbang->addr, bitbang->mdc_msk);
377 bb_clr(bitbang->addr, bitbang->mdc_msk);
380 /* mdio bus control struct */
381 static struct mdiobb_ops bb_ops = {
382 .owner = THIS_MODULE,
383 .set_mdc = sh_mdc_ctrl,
384 .set_mdio_dir = sh_mmd_ctrl,
385 .set_mdio_data = sh_set_mdio,
386 .get_mdio_data = sh_get_mdio,
389 /* free skb and descriptor buffer */
390 static void sh_eth_ring_free(struct net_device *ndev)
392 struct sh_eth_private *mdp = netdev_priv(ndev);
395 /* Free Rx skb ringbuffer */
396 if (mdp->rx_skbuff) {
397 for (i = 0; i < RX_RING_SIZE; i++) {
398 if (mdp->rx_skbuff[i])
399 dev_kfree_skb(mdp->rx_skbuff[i]);
402 kfree(mdp->rx_skbuff);
404 /* Free Tx skb ringbuffer */
405 if (mdp->tx_skbuff) {
406 for (i = 0; i < TX_RING_SIZE; i++) {
407 if (mdp->tx_skbuff[i])
408 dev_kfree_skb(mdp->tx_skbuff[i]);
411 kfree(mdp->tx_skbuff);
414 /* format skb and descriptor buffer */
415 static void sh_eth_ring_format(struct net_device *ndev)
417 u32 ioaddr = ndev->base_addr;
418 struct sh_eth_private *mdp = netdev_priv(ndev);
421 struct sh_eth_rxdesc *rxdesc = NULL;
422 struct sh_eth_txdesc *txdesc = NULL;
423 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
424 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
426 mdp->cur_rx = mdp->cur_tx = 0;
427 mdp->dirty_rx = mdp->dirty_tx = 0;
429 memset(mdp->rx_ring, 0, rx_ringsize);
431 /* build Rx ring buffer */
432 for (i = 0; i < RX_RING_SIZE; i++) {
434 mdp->rx_skbuff[i] = NULL;
435 skb = dev_alloc_skb(mdp->rx_buf_sz);
436 mdp->rx_skbuff[i] = skb;
439 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
441 skb->dev = ndev; /* Mark as being used by this device. */
442 sh_eth_set_receive_align(skb);
445 rxdesc = &mdp->rx_ring[i];
446 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
447 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
449 /* The size of the buffer is 16 byte boundary. */
450 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
451 /* Rx descriptor address set */
453 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
454 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
455 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
460 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
462 /* Mark the last entry as wrapping the ring. */
463 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
465 memset(mdp->tx_ring, 0, tx_ringsize);
467 /* build Tx ring buffer */
468 for (i = 0; i < TX_RING_SIZE; i++) {
469 mdp->tx_skbuff[i] = NULL;
470 txdesc = &mdp->tx_ring[i];
471 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
472 txdesc->buffer_length = 0;
474 /* Tx descriptor address set */
475 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
476 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
477 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
482 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
485 /* Get skb and descriptor buffer */
486 static int sh_eth_ring_init(struct net_device *ndev)
488 struct sh_eth_private *mdp = netdev_priv(ndev);
489 int rx_ringsize, tx_ringsize, ret = 0;
492 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
493 * card needs room to do 8 byte alignment, +2 so we can reserve
494 * the first 2 bytes, and +16 gets room for the status word from the
497 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
498 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
500 /* Allocate RX and TX skb rings */
501 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
503 if (!mdp->rx_skbuff) {
504 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
509 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
511 if (!mdp->tx_skbuff) {
512 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
517 /* Allocate all Rx descriptors. */
518 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
519 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
523 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
531 /* Allocate all Tx descriptors. */
532 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
533 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
536 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
544 /* free DMA buffer */
545 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
548 /* Free Rx and Tx skb ring buffer */
549 sh_eth_ring_free(ndev);
554 static int sh_eth_dev_init(struct net_device *ndev)
557 struct sh_eth_private *mdp = netdev_priv(ndev);
558 u32 ioaddr = ndev->base_addr;
559 u_int32_t rx_int_var, tx_int_var;
565 /* Descriptor format */
566 sh_eth_ring_format(ndev);
568 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
570 /* all sh_eth int mask */
571 ctrl_outl(0, ioaddr + EESIPR);
573 #if defined(__LITTLE_ENDIAN__)
574 if (mdp->cd->hw_swap)
575 ctrl_outl(EDMR_EL, ioaddr + EDMR);
578 ctrl_outl(0, ioaddr + EDMR);
581 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
582 ctrl_outl(0, ioaddr + TFTR);
584 /* Frame recv control */
585 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
587 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
588 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
589 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
592 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
594 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
596 if (!mdp->cd->no_trimd)
597 ctrl_outl(0, ioaddr + TRIMD);
599 /* Recv frame limit set register */
600 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
602 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
603 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
605 /* PAUSE Prohibition */
606 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
607 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
609 ctrl_outl(val, ioaddr + ECMR);
611 if (mdp->cd->set_rate)
612 mdp->cd->set_rate(ndev);
614 /* E-MAC Status Register clear */
615 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
617 /* E-MAC Interrupt Enable register */
618 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
620 /* Set MAC address */
621 update_mac_address(ndev);
625 ctrl_outl(APR_AP, ioaddr + APR);
627 ctrl_outl(MPR_MP, ioaddr + MPR);
628 if (mdp->cd->tpauser)
629 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
631 /* Setting the Rx mode will start the Rx process. */
632 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
634 netif_start_queue(ndev);
639 /* free Tx skb function */
640 static int sh_eth_txfree(struct net_device *ndev)
642 struct sh_eth_private *mdp = netdev_priv(ndev);
643 struct sh_eth_txdesc *txdesc;
647 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
648 entry = mdp->dirty_tx % TX_RING_SIZE;
649 txdesc = &mdp->tx_ring[entry];
650 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
652 /* Free the original skb. */
653 if (mdp->tx_skbuff[entry]) {
654 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
655 mdp->tx_skbuff[entry] = NULL;
658 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
659 if (entry >= TX_RING_SIZE - 1)
660 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
662 mdp->stats.tx_packets++;
663 mdp->stats.tx_bytes += txdesc->buffer_length;
668 /* Packet receive function */
669 static int sh_eth_rx(struct net_device *ndev)
671 struct sh_eth_private *mdp = netdev_priv(ndev);
672 struct sh_eth_rxdesc *rxdesc;
674 int entry = mdp->cur_rx % RX_RING_SIZE;
675 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
680 rxdesc = &mdp->rx_ring[entry];
681 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
682 desc_status = edmac_to_cpu(mdp, rxdesc->status);
683 pkt_len = rxdesc->frame_length;
688 if (!(desc_status & RDFEND))
689 mdp->stats.rx_length_errors++;
691 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
692 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
693 mdp->stats.rx_errors++;
694 if (desc_status & RD_RFS1)
695 mdp->stats.rx_crc_errors++;
696 if (desc_status & RD_RFS2)
697 mdp->stats.rx_frame_errors++;
698 if (desc_status & RD_RFS3)
699 mdp->stats.rx_length_errors++;
700 if (desc_status & RD_RFS4)
701 mdp->stats.rx_length_errors++;
702 if (desc_status & RD_RFS6)
703 mdp->stats.rx_missed_errors++;
704 if (desc_status & RD_RFS10)
705 mdp->stats.rx_over_errors++;
707 if (!mdp->cd->hw_swap)
709 phys_to_virt(ALIGN(rxdesc->addr, 4)),
711 skb = mdp->rx_skbuff[entry];
712 mdp->rx_skbuff[entry] = NULL;
713 skb_put(skb, pkt_len);
714 skb->protocol = eth_type_trans(skb, ndev);
716 mdp->stats.rx_packets++;
717 mdp->stats.rx_bytes += pkt_len;
719 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
720 entry = (++mdp->cur_rx) % RX_RING_SIZE;
721 rxdesc = &mdp->rx_ring[entry];
724 /* Refill the Rx ring buffers. */
725 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
726 entry = mdp->dirty_rx % RX_RING_SIZE;
727 rxdesc = &mdp->rx_ring[entry];
728 /* The size of the buffer is 16 byte boundary. */
729 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
731 if (mdp->rx_skbuff[entry] == NULL) {
732 skb = dev_alloc_skb(mdp->rx_buf_sz);
733 mdp->rx_skbuff[entry] = skb;
735 break; /* Better luck next round. */
736 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
739 sh_eth_set_receive_align(skb);
741 skb->ip_summed = CHECKSUM_NONE;
742 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
744 if (entry >= RX_RING_SIZE - 1)
746 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
749 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
752 /* Restart Rx engine if stopped. */
753 /* If we don't need to check status, don't. -KDU */
754 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
755 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
760 /* error control function */
761 static void sh_eth_error(struct net_device *ndev, int intr_status)
763 struct sh_eth_private *mdp = netdev_priv(ndev);
764 u32 ioaddr = ndev->base_addr;
769 if (intr_status & EESR_ECI) {
770 felic_stat = ctrl_inl(ioaddr + ECSR);
771 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
772 if (felic_stat & ECSR_ICD)
773 mdp->stats.tx_carrier_errors++;
774 if (felic_stat & ECSR_LCHNG) {
776 if (mdp->cd->no_psr || mdp->no_ether_link) {
777 if (mdp->link == PHY_DOWN)
780 link_stat = PHY_ST_LINK;
782 link_stat = (ctrl_inl(ioaddr + PSR));
783 if (mdp->ether_link_active_low)
784 link_stat = ~link_stat;
786 if (!(link_stat & PHY_ST_LINK)) {
787 /* Link Down : disable tx and rx */
788 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
789 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
792 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
793 ~DMAC_M_ECI, ioaddr + EESIPR);
795 ctrl_outl(ctrl_inl(ioaddr + ECSR),
797 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
798 DMAC_M_ECI, ioaddr + EESIPR);
799 /* enable tx and rx */
800 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
801 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
806 if (intr_status & EESR_TWB) {
807 /* Write buck end. unused write back interrupt */
808 if (intr_status & EESR_TABT) /* Transmit Abort int */
809 mdp->stats.tx_aborted_errors++;
812 if (intr_status & EESR_RABT) {
813 /* Receive Abort int */
814 if (intr_status & EESR_RFRMER) {
815 /* Receive Frame Overflow int */
816 mdp->stats.rx_frame_errors++;
817 dev_err(&ndev->dev, "Receive Frame Overflow\n");
821 if (!mdp->cd->no_ade) {
822 if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
823 intr_status & EESR_TFE)
824 mdp->stats.tx_fifo_errors++;
827 if (intr_status & EESR_RDE) {
828 /* Receive Descriptor Empty int */
829 mdp->stats.rx_over_errors++;
831 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
832 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
833 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
835 if (intr_status & EESR_RFE) {
836 /* Receive FIFO Overflow int */
837 mdp->stats.rx_fifo_errors++;
838 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
841 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
844 if (intr_status & mask) {
846 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
848 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
849 intr_status, mdp->cur_tx);
850 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
851 mdp->dirty_tx, (u32) ndev->state, edtrr);
852 /* dirty buffer free */
856 if (edtrr ^ EDTRR_TRNS) {
858 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
861 netif_wake_queue(ndev);
865 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
867 struct net_device *ndev = netdev;
868 struct sh_eth_private *mdp = netdev_priv(ndev);
869 struct sh_eth_cpu_data *cd = mdp->cd;
870 irqreturn_t ret = IRQ_NONE;
871 u32 ioaddr, intr_status = 0;
873 ioaddr = ndev->base_addr;
874 spin_lock(&mdp->lock);
876 /* Get interrpt stat */
877 intr_status = ctrl_inl(ioaddr + EESR);
878 /* Clear interrupt */
879 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
880 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
881 cd->tx_check | cd->eesr_err_check)) {
882 ctrl_outl(intr_status, ioaddr + EESR);
887 if (intr_status & (EESR_FRC | /* Frame recv*/
888 EESR_RMAF | /* Multi cast address recv*/
889 EESR_RRF | /* Bit frame recv */
890 EESR_RTLF | /* Long frame recv*/
891 EESR_RTSF | /* short frame recv */
892 EESR_PRE | /* PHY-LSI recv error */
893 EESR_CERF)){ /* recv frame CRC error */
898 if (intr_status & cd->tx_check) {
900 netif_wake_queue(ndev);
903 if (intr_status & cd->eesr_err_check)
904 sh_eth_error(ndev, intr_status);
907 spin_unlock(&mdp->lock);
912 static void sh_eth_timer(unsigned long data)
914 struct net_device *ndev = (struct net_device *)data;
915 struct sh_eth_private *mdp = netdev_priv(ndev);
917 mod_timer(&mdp->timer, jiffies + (10 * HZ));
920 /* PHY state control function */
921 static void sh_eth_adjust_link(struct net_device *ndev)
923 struct sh_eth_private *mdp = netdev_priv(ndev);
924 struct phy_device *phydev = mdp->phydev;
925 u32 ioaddr = ndev->base_addr;
928 if (phydev->link != PHY_DOWN) {
929 if (phydev->duplex != mdp->duplex) {
931 mdp->duplex = phydev->duplex;
932 if (mdp->cd->set_duplex)
933 mdp->cd->set_duplex(ndev);
936 if (phydev->speed != mdp->speed) {
938 mdp->speed = phydev->speed;
939 if (mdp->cd->set_rate)
940 mdp->cd->set_rate(ndev);
942 if (mdp->link == PHY_DOWN) {
943 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
944 | ECMR_DM, ioaddr + ECMR);
946 mdp->link = phydev->link;
948 } else if (mdp->link) {
950 mdp->link = PHY_DOWN;
956 phy_print_status(phydev);
959 /* PHY init function */
960 static int sh_eth_phy_init(struct net_device *ndev)
962 struct sh_eth_private *mdp = netdev_priv(ndev);
963 char phy_id[MII_BUS_ID_SIZE + 3];
964 struct phy_device *phydev = NULL;
966 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
967 mdp->mii_bus->id , mdp->phy_id);
969 mdp->link = PHY_DOWN;
973 /* Try connect to PHY */
974 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
975 0, PHY_INTERFACE_MODE_MII);
976 if (IS_ERR(phydev)) {
977 dev_err(&ndev->dev, "phy_connect failed\n");
978 return PTR_ERR(phydev);
981 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
982 phydev->addr, phydev->drv->name);
984 mdp->phydev = phydev;
989 /* PHY control start function */
990 static int sh_eth_phy_start(struct net_device *ndev)
992 struct sh_eth_private *mdp = netdev_priv(ndev);
995 ret = sh_eth_phy_init(ndev);
999 /* reset phy - this also wakes it from PDOWN */
1000 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1001 phy_start(mdp->phydev);
1006 /* network device open function */
1007 static int sh_eth_open(struct net_device *ndev)
1010 struct sh_eth_private *mdp = netdev_priv(ndev);
1012 ret = request_irq(ndev->irq, &sh_eth_interrupt,
1013 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
1020 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1024 /* Descriptor set */
1025 ret = sh_eth_ring_init(ndev);
1030 ret = sh_eth_dev_init(ndev);
1034 /* PHY control start*/
1035 ret = sh_eth_phy_start(ndev);
1039 /* Set the timer to check for link beat. */
1040 init_timer(&mdp->timer);
1041 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1042 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1047 free_irq(ndev->irq, ndev);
1051 /* Timeout function */
1052 static void sh_eth_tx_timeout(struct net_device *ndev)
1054 struct sh_eth_private *mdp = netdev_priv(ndev);
1055 u32 ioaddr = ndev->base_addr;
1056 struct sh_eth_rxdesc *rxdesc;
1059 netif_stop_queue(ndev);
1061 /* worning message out. */
1062 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
1063 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
1065 /* tx_errors count up */
1066 mdp->stats.tx_errors++;
1069 del_timer_sync(&mdp->timer);
1071 /* Free all the skbuffs in the Rx queue. */
1072 for (i = 0; i < RX_RING_SIZE; i++) {
1073 rxdesc = &mdp->rx_ring[i];
1075 rxdesc->addr = 0xBADF00D0;
1076 if (mdp->rx_skbuff[i])
1077 dev_kfree_skb(mdp->rx_skbuff[i]);
1078 mdp->rx_skbuff[i] = NULL;
1080 for (i = 0; i < TX_RING_SIZE; i++) {
1081 if (mdp->tx_skbuff[i])
1082 dev_kfree_skb(mdp->tx_skbuff[i]);
1083 mdp->tx_skbuff[i] = NULL;
1087 sh_eth_dev_init(ndev);
1090 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1091 add_timer(&mdp->timer);
1094 /* Packet transmit function */
1095 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1097 struct sh_eth_private *mdp = netdev_priv(ndev);
1098 struct sh_eth_txdesc *txdesc;
1100 unsigned long flags;
1102 spin_lock_irqsave(&mdp->lock, flags);
1103 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1104 if (!sh_eth_txfree(ndev)) {
1105 netif_stop_queue(ndev);
1106 spin_unlock_irqrestore(&mdp->lock, flags);
1107 return NETDEV_TX_BUSY;
1110 spin_unlock_irqrestore(&mdp->lock, flags);
1112 entry = mdp->cur_tx % TX_RING_SIZE;
1113 mdp->tx_skbuff[entry] = skb;
1114 txdesc = &mdp->tx_ring[entry];
1115 txdesc->addr = virt_to_phys(skb->data);
1117 if (!mdp->cd->hw_swap)
1118 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1121 __flush_purge_region(skb->data, skb->len);
1122 if (skb->len < ETHERSMALL)
1123 txdesc->buffer_length = ETHERSMALL;
1125 txdesc->buffer_length = skb->len;
1127 if (entry >= TX_RING_SIZE - 1)
1128 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1130 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1134 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
1135 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
1137 ndev->trans_start = jiffies;
1139 return NETDEV_TX_OK;
1142 /* device close function */
1143 static int sh_eth_close(struct net_device *ndev)
1145 struct sh_eth_private *mdp = netdev_priv(ndev);
1146 u32 ioaddr = ndev->base_addr;
1149 netif_stop_queue(ndev);
1151 /* Disable interrupts by clearing the interrupt mask. */
1152 ctrl_outl(0x0000, ioaddr + EESIPR);
1154 /* Stop the chip's Tx and Rx processes. */
1155 ctrl_outl(0, ioaddr + EDTRR);
1156 ctrl_outl(0, ioaddr + EDRRR);
1158 /* PHY Disconnect */
1160 phy_stop(mdp->phydev);
1161 phy_disconnect(mdp->phydev);
1164 free_irq(ndev->irq, ndev);
1166 del_timer_sync(&mdp->timer);
1168 /* Free all the skbuffs in the Rx queue. */
1169 sh_eth_ring_free(ndev);
1171 /* free DMA buffer */
1172 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1173 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1175 /* free DMA buffer */
1176 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1177 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1182 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1184 struct sh_eth_private *mdp = netdev_priv(ndev);
1185 u32 ioaddr = ndev->base_addr;
1187 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
1188 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1189 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
1190 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1191 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
1192 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
1193 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1194 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1195 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1196 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1197 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1199 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
1200 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
1205 /* ioctl to device funciotn*/
1206 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1209 struct sh_eth_private *mdp = netdev_priv(ndev);
1210 struct phy_device *phydev = mdp->phydev;
1212 if (!netif_running(ndev))
1218 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1221 #if defined(SH_ETH_HAS_TSU)
1222 /* Multicast reception directions set */
1223 static void sh_eth_set_multicast_list(struct net_device *ndev)
1225 u32 ioaddr = ndev->base_addr;
1227 if (ndev->flags & IFF_PROMISC) {
1228 /* Set promiscuous. */
1229 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1232 /* Normal, unicast/broadcast-only mode. */
1233 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1238 /* SuperH's TSU register init function */
1239 static void sh_eth_tsu_init(u32 ioaddr)
1241 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1242 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1243 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1244 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1245 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1246 ctrl_outl(0, ioaddr + TSU_PRISL0);
1247 ctrl_outl(0, ioaddr + TSU_PRISL1);
1248 ctrl_outl(0, ioaddr + TSU_FWSL0);
1249 ctrl_outl(0, ioaddr + TSU_FWSL1);
1250 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1251 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1252 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1253 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1255 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1256 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1258 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1259 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1260 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1261 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1262 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1263 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1264 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1266 #endif /* SH_ETH_HAS_TSU */
1268 /* MDIO bus release function */
1269 static int sh_mdio_release(struct net_device *ndev)
1271 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1273 /* unregister mdio bus */
1274 mdiobus_unregister(bus);
1276 /* remove mdio bus info from net_device */
1277 dev_set_drvdata(&ndev->dev, NULL);
1279 /* free bitbang info */
1280 free_mdio_bitbang(bus);
1285 /* MDIO bus init function */
1286 static int sh_mdio_init(struct net_device *ndev, int id)
1289 struct bb_info *bitbang;
1290 struct sh_eth_private *mdp = netdev_priv(ndev);
1292 /* create bit control struct for PHY */
1293 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1300 bitbang->addr = ndev->base_addr + PIR;
1301 bitbang->mdi_msk = 0x08;
1302 bitbang->mdo_msk = 0x04;
1303 bitbang->mmd_msk = 0x02;/* MMD */
1304 bitbang->mdc_msk = 0x01;
1305 bitbang->ctrl.ops = &bb_ops;
1307 /* MII contorller setting */
1308 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1309 if (!mdp->mii_bus) {
1311 goto out_free_bitbang;
1314 /* Hook up MII support for ethtool */
1315 mdp->mii_bus->name = "sh_mii";
1316 mdp->mii_bus->parent = &ndev->dev;
1317 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1320 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1321 if (!mdp->mii_bus->irq) {
1326 for (i = 0; i < PHY_MAX_ADDR; i++)
1327 mdp->mii_bus->irq[i] = PHY_POLL;
1329 /* regist mdio bus */
1330 ret = mdiobus_register(mdp->mii_bus);
1334 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1339 kfree(mdp->mii_bus->irq);
1342 free_mdio_bitbang(mdp->mii_bus);
1351 static const struct net_device_ops sh_eth_netdev_ops = {
1352 .ndo_open = sh_eth_open,
1353 .ndo_stop = sh_eth_close,
1354 .ndo_start_xmit = sh_eth_start_xmit,
1355 .ndo_get_stats = sh_eth_get_stats,
1356 #if defined(SH_ETH_HAS_TSU)
1357 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1359 .ndo_tx_timeout = sh_eth_tx_timeout,
1360 .ndo_do_ioctl = sh_eth_do_ioctl,
1361 .ndo_validate_addr = eth_validate_addr,
1362 .ndo_set_mac_address = eth_mac_addr,
1363 .ndo_change_mtu = eth_change_mtu,
1366 static int sh_eth_drv_probe(struct platform_device *pdev)
1368 int ret, i, devno = 0;
1369 struct resource *res;
1370 struct net_device *ndev = NULL;
1371 struct sh_eth_private *mdp;
1372 struct sh_eth_plat_data *pd;
1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1376 if (unlikely(res == NULL)) {
1377 dev_err(&pdev->dev, "invalid resource\n");
1382 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1384 dev_err(&pdev->dev, "Could not allocate device.\n");
1389 /* The sh Ether-specific entries in the device structure. */
1390 ndev->base_addr = res->start;
1396 ret = platform_get_irq(pdev, 0);
1403 SET_NETDEV_DEV(ndev, &pdev->dev);
1405 /* Fill in the fields of the device structure with ethernet values. */
1408 mdp = netdev_priv(ndev);
1409 spin_lock_init(&mdp->lock);
1411 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1413 mdp->phy_id = pd->phy;
1415 mdp->edmac_endian = pd->edmac_endian;
1416 mdp->no_ether_link = pd->no_ether_link;
1417 mdp->ether_link_active_low = pd->ether_link_active_low;
1420 mdp->cd = &sh_eth_my_cpu_data;
1421 sh_eth_set_default_cpu_data(mdp->cd);
1424 ndev->netdev_ops = &sh_eth_netdev_ops;
1425 ndev->watchdog_timeo = TX_TIMEOUT;
1427 mdp->post_rx = POST_RX >> (devno << 1);
1428 mdp->post_fw = POST_FW >> (devno << 1);
1430 /* read and set MAC address */
1431 read_mac_address(ndev);
1433 /* First device only init */
1435 if (mdp->cd->chip_reset)
1436 mdp->cd->chip_reset(ndev);
1438 #if defined(SH_ETH_HAS_TSU)
1439 /* TSU init (Init only)*/
1440 sh_eth_tsu_init(SH_TSU_ADDR);
1444 /* network device register */
1445 ret = register_netdev(ndev);
1450 ret = sh_mdio_init(ndev, pdev->id);
1452 goto out_unregister;
1454 /* pritnt device infomation */
1455 pr_info("Base address at 0x%x, ",
1456 (u32)ndev->base_addr);
1458 for (i = 0; i < 5; i++)
1459 printk("%02X:", ndev->dev_addr[i]);
1460 printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1462 platform_set_drvdata(pdev, ndev);
1467 unregister_netdev(ndev);
1478 static int sh_eth_drv_remove(struct platform_device *pdev)
1480 struct net_device *ndev = platform_get_drvdata(pdev);
1482 sh_mdio_release(ndev);
1483 unregister_netdev(ndev);
1484 flush_scheduled_work();
1487 platform_set_drvdata(pdev, NULL);
1492 static struct platform_driver sh_eth_driver = {
1493 .probe = sh_eth_drv_probe,
1494 .remove = sh_eth_drv_remove,
1500 static int __init sh_eth_init(void)
1502 return platform_driver_register(&sh_eth_driver);
1505 static void __exit sh_eth_cleanup(void)
1507 platform_driver_unregister(&sh_eth_driver);
1510 module_init(sh_eth_init);
1511 module_exit(sh_eth_cleanup);
1513 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1514 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1515 MODULE_LICENSE("GPL v2");