1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
53 ************************************************************************/
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
80 #include <linux/slab.h>
83 #include <asm/system.h>
84 #include <asm/div64.h>
89 #include "s2io-regs.h"
91 #define DRV_VERSION "2.0.26.28"
93 /* S2io Driver name & version. */
94 static const char s2io_driver_name[] = "Neterion";
95 static const char s2io_driver_version[] = DRV_VERSION;
97 static const int rxd_size[2] = {32, 48};
98 static const int rxd_count[2] = {127, 85};
100 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
104 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
105 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
111 * Cards with following subsystem_id have a link state indication
112 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
113 * macro below identifies these cards given the subsystem_id.
115 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
116 (dev_type == XFRAME_I_DEVICE) ? \
117 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
118 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
121 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
123 static inline int is_s2io_card_up(const struct s2io_nic *sp)
125 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128 /* Ethtool related variables and Macros. */
129 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
130 "Register test\t(offline)",
131 "Eeprom test\t(offline)",
132 "Link test\t(online)",
133 "RLDRAM test\t(offline)",
134 "BIST Test\t(offline)"
137 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
139 {"tmac_data_octets"},
143 {"tmac_pause_ctrl_frms"},
147 {"tmac_any_err_frms"},
148 {"tmac_ttl_less_fb_octets"},
149 {"tmac_vld_ip_octets"},
157 {"rmac_data_octets"},
158 {"rmac_fcs_err_frms"},
160 {"rmac_vld_mcst_frms"},
161 {"rmac_vld_bcst_frms"},
162 {"rmac_in_rng_len_err_frms"},
163 {"rmac_out_rng_len_err_frms"},
165 {"rmac_pause_ctrl_frms"},
166 {"rmac_unsup_ctrl_frms"},
168 {"rmac_accepted_ucst_frms"},
169 {"rmac_accepted_nucst_frms"},
170 {"rmac_discarded_frms"},
171 {"rmac_drop_events"},
172 {"rmac_ttl_less_fb_octets"},
174 {"rmac_usized_frms"},
175 {"rmac_osized_frms"},
177 {"rmac_jabber_frms"},
178 {"rmac_ttl_64_frms"},
179 {"rmac_ttl_65_127_frms"},
180 {"rmac_ttl_128_255_frms"},
181 {"rmac_ttl_256_511_frms"},
182 {"rmac_ttl_512_1023_frms"},
183 {"rmac_ttl_1024_1518_frms"},
191 {"rmac_err_drp_udp"},
192 {"rmac_xgmii_err_sym"},
210 {"rmac_xgmii_data_err_cnt"},
211 {"rmac_xgmii_ctrl_err_cnt"},
212 {"rmac_accepted_ip"},
216 {"new_rd_req_rtry_cnt"},
218 {"wr_rtry_rd_ack_cnt"},
221 {"new_wr_req_rtry_cnt"},
224 {"rd_rtry_wr_ack_cnt"},
234 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
235 {"rmac_ttl_1519_4095_frms"},
236 {"rmac_ttl_4096_8191_frms"},
237 {"rmac_ttl_8192_max_frms"},
238 {"rmac_ttl_gt_max_frms"},
239 {"rmac_osized_alt_frms"},
240 {"rmac_jabber_alt_frms"},
241 {"rmac_gt_max_alt_frms"},
243 {"rmac_len_discard"},
244 {"rmac_fcs_discard"},
247 {"rmac_red_discard"},
248 {"rmac_rts_discard"},
249 {"rmac_ingm_full_discard"},
253 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
254 {"\n DRIVER STATISTICS"},
255 {"single_bit_ecc_errs"},
256 {"double_bit_ecc_errs"},
269 {"alarm_transceiver_temp_high"},
270 {"alarm_transceiver_temp_low"},
271 {"alarm_laser_bias_current_high"},
272 {"alarm_laser_bias_current_low"},
273 {"alarm_laser_output_power_high"},
274 {"alarm_laser_output_power_low"},
275 {"warn_transceiver_temp_high"},
276 {"warn_transceiver_temp_low"},
277 {"warn_laser_bias_current_high"},
278 {"warn_laser_bias_current_low"},
279 {"warn_laser_output_power_high"},
280 {"warn_laser_output_power_low"},
281 {"lro_aggregated_pkts"},
282 {"lro_flush_both_count"},
283 {"lro_out_of_sequence_pkts"},
284 {"lro_flush_due_to_max_pkts"},
285 {"lro_avg_aggr_pkts"},
286 {"mem_alloc_fail_cnt"},
287 {"pci_map_fail_cnt"},
288 {"watchdog_timer_cnt"},
295 {"tx_tcode_buf_abort_cnt"},
296 {"tx_tcode_desc_abort_cnt"},
297 {"tx_tcode_parity_err_cnt"},
298 {"tx_tcode_link_loss_cnt"},
299 {"tx_tcode_list_proc_err_cnt"},
300 {"rx_tcode_parity_err_cnt"},
301 {"rx_tcode_abort_cnt"},
302 {"rx_tcode_parity_abort_cnt"},
303 {"rx_tcode_rda_fail_cnt"},
304 {"rx_tcode_unkn_prot_cnt"},
305 {"rx_tcode_fcs_err_cnt"},
306 {"rx_tcode_buf_size_err_cnt"},
307 {"rx_tcode_rxd_corrupt_cnt"},
308 {"rx_tcode_unkn_err_cnt"},
316 {"mac_tmac_err_cnt"},
317 {"mac_rmac_err_cnt"},
318 {"xgxs_txgxs_err_cnt"},
319 {"xgxs_rxgxs_err_cnt"},
321 {"prc_pcix_err_cnt"},
328 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
329 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
330 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
332 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
333 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
335 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
336 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
338 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
339 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
341 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
342 init_timer(&timer); \
343 timer.function = handle; \
344 timer.data = (unsigned long)arg; \
345 mod_timer(&timer, (jiffies + exp)) \
347 /* copy mac addr to def_mac_addr array */
348 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
351 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
352 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
353 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
354 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
355 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
359 static void s2io_vlan_rx_register(struct net_device *dev,
360 struct vlan_group *grp)
363 struct s2io_nic *nic = netdev_priv(dev);
364 unsigned long flags[MAX_TX_FIFOS];
365 struct config_param *config = &nic->config;
366 struct mac_info *mac_control = &nic->mac_control;
368 for (i = 0; i < config->tx_fifo_num; i++) {
369 struct fifo_info *fifo = &mac_control->fifos[i];
371 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
376 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
377 struct fifo_info *fifo = &mac_control->fifos[i];
379 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
383 /* Unregister the vlan */
384 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
387 struct s2io_nic *nic = netdev_priv(dev);
388 unsigned long flags[MAX_TX_FIFOS];
389 struct config_param *config = &nic->config;
390 struct mac_info *mac_control = &nic->mac_control;
392 for (i = 0; i < config->tx_fifo_num; i++) {
393 struct fifo_info *fifo = &mac_control->fifos[i];
395 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
399 vlan_group_set_device(nic->vlgrp, vid, NULL);
401 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
402 struct fifo_info *fifo = &mac_control->fifos[i];
404 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
409 * Constants to be programmed into the Xena's registers, to configure
414 static const u64 herc_act_dtx_cfg[] = {
416 0x8000051536750000ULL, 0x80000515367500E0ULL,
418 0x8000051536750004ULL, 0x80000515367500E4ULL,
420 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424 0x801205150D440000ULL, 0x801205150D4400E0ULL,
426 0x801205150D440004ULL, 0x801205150D4400E4ULL,
428 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
435 static const u64 xena_dtx_cfg[] = {
437 0x8000051500000000ULL, 0x80000515000000E0ULL,
439 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441 0x8001051500000000ULL, 0x80010515000000E0ULL,
443 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445 0x8002051500000000ULL, 0x80020515000000E0ULL,
447 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
452 * Constants for Fixing the MacAddress problem seen mostly on
455 static const u64 fix_mac[] = {
456 0x0060000000000000ULL, 0x0060600000000000ULL,
457 0x0040600000000000ULL, 0x0000600000000000ULL,
458 0x0020600000000000ULL, 0x0060600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0000600000000000ULL,
469 0x0040600000000000ULL, 0x0060600000000000ULL,
473 MODULE_LICENSE("GPL");
474 MODULE_VERSION(DRV_VERSION);
477 /* Module Loadable parameters. */
478 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
479 S2IO_PARM_INT(rx_ring_num, 1);
480 S2IO_PARM_INT(multiq, 0);
481 S2IO_PARM_INT(rx_ring_mode, 1);
482 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
483 S2IO_PARM_INT(rmac_pause_time, 0x100);
484 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
485 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
486 S2IO_PARM_INT(shared_splits, 0);
487 S2IO_PARM_INT(tmac_util_period, 5);
488 S2IO_PARM_INT(rmac_util_period, 5);
489 S2IO_PARM_INT(l3l4hdr_size, 128);
490 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
491 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
492 /* Frequency of Rx desc syncs expressed as power of 2 */
493 S2IO_PARM_INT(rxsync_frequency, 3);
494 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
495 S2IO_PARM_INT(intr_type, 2);
496 /* Large receive offload feature */
498 /* Max pkts to be aggregated by LRO at one time. If not specified,
499 * aggregation happens until we hit max IP pkt size(64K)
501 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
502 S2IO_PARM_INT(indicate_max_pkts, 0);
504 S2IO_PARM_INT(napi, 1);
505 S2IO_PARM_INT(ufo, 0);
506 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
508 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
509 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
510 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
511 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
512 static unsigned int rts_frm_len[MAX_RX_RINGS] =
513 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
515 module_param_array(tx_fifo_len, uint, NULL, 0);
516 module_param_array(rx_ring_sz, uint, NULL, 0);
517 module_param_array(rts_frm_len, uint, NULL, 0);
521 * This table lists all the devices that this driver supports.
523 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
524 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
525 PCI_ANY_ID, PCI_ANY_ID},
526 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
527 PCI_ANY_ID, PCI_ANY_ID},
528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
535 MODULE_DEVICE_TABLE(pci, s2io_tbl);
537 static struct pci_error_handlers s2io_err_handler = {
538 .error_detected = s2io_io_error_detected,
539 .slot_reset = s2io_io_slot_reset,
540 .resume = s2io_io_resume,
543 static struct pci_driver s2io_driver = {
545 .id_table = s2io_tbl,
546 .probe = s2io_init_nic,
547 .remove = __devexit_p(s2io_rem_nic),
548 .err_handler = &s2io_err_handler,
551 /* A simplifier macro used both by init and free shared_mem Fns(). */
552 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554 /* netqueue manipulation helper functions */
555 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557 if (!sp->config.multiq) {
560 for (i = 0; i < sp->config.tx_fifo_num; i++)
561 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
563 netif_tx_stop_all_queues(sp->dev);
566 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568 if (!sp->config.multiq)
569 sp->mac_control.fifos[fifo_no].queue_state =
572 netif_tx_stop_all_queues(sp->dev);
575 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577 if (!sp->config.multiq) {
580 for (i = 0; i < sp->config.tx_fifo_num; i++)
581 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
583 netif_tx_start_all_queues(sp->dev);
586 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588 if (!sp->config.multiq)
589 sp->mac_control.fifos[fifo_no].queue_state =
592 netif_tx_start_all_queues(sp->dev);
595 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597 if (!sp->config.multiq) {
600 for (i = 0; i < sp->config.tx_fifo_num; i++)
601 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
603 netif_tx_wake_all_queues(sp->dev);
606 static inline void s2io_wake_tx_queue(
607 struct fifo_info *fifo, int cnt, u8 multiq)
611 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
612 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
613 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
614 if (netif_queue_stopped(fifo->dev)) {
615 fifo->queue_state = FIFO_QUEUE_START;
616 netif_wake_queue(fifo->dev);
622 * init_shared_mem - Allocation and Initialization of Memory
623 * @nic: Device private variable.
624 * Description: The function allocates all the memory areas shared
625 * between the NIC and the driver. This includes Tx descriptors,
626 * Rx descriptors and the statistics block.
629 static int init_shared_mem(struct s2io_nic *nic)
632 void *tmp_v_addr, *tmp_v_addr_next;
633 dma_addr_t tmp_p_addr, tmp_p_addr_next;
634 struct RxD_block *pre_rxd_blk = NULL;
636 int lst_size, lst_per_page;
637 struct net_device *dev = nic->dev;
640 struct config_param *config = &nic->config;
641 struct mac_info *mac_control = &nic->mac_control;
642 unsigned long long mem_allocated = 0;
644 /* Allocation and initialization of TXDLs in FIFOs */
646 for (i = 0; i < config->tx_fifo_num; i++) {
647 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
649 size += tx_cfg->fifo_len;
651 if (size > MAX_AVAILABLE_TXDS) {
653 "Too many TxDs requested: %d, max supported: %d\n",
654 size, MAX_AVAILABLE_TXDS);
659 for (i = 0; i < config->tx_fifo_num; i++) {
660 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
662 size = tx_cfg->fifo_len;
664 * Legal values are from 2 to 8192
667 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
668 "Valid lengths are 2 through 8192\n",
674 lst_size = (sizeof(struct TxD) * config->max_txds);
675 lst_per_page = PAGE_SIZE / lst_size;
677 for (i = 0; i < config->tx_fifo_num; i++) {
678 struct fifo_info *fifo = &mac_control->fifos[i];
679 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
680 int fifo_len = tx_cfg->fifo_len;
681 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
683 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
684 if (!fifo->list_info) {
685 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
688 mem_allocated += list_holder_size;
690 for (i = 0; i < config->tx_fifo_num; i++) {
691 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
693 struct fifo_info *fifo = &mac_control->fifos[i];
694 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
696 fifo->tx_curr_put_info.offset = 0;
697 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
698 fifo->tx_curr_get_info.offset = 0;
699 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->max_txds = MAX_SKB_FRAGS + 2;
705 for (j = 0; j < page_num; j++) {
709 tmp_v = pci_alloc_consistent(nic->pdev,
713 "pci_alloc_consistent failed for TxDL\n");
716 /* If we got a zero DMA address(can happen on
717 * certain platforms like PPC), reallocate.
718 * Store virtual address of page we don't want,
722 mac_control->zerodma_virt_addr = tmp_v;
724 "%s: Zero DMA address for TxDL. "
725 "Virtual address %p\n",
727 tmp_v = pci_alloc_consistent(nic->pdev,
731 "pci_alloc_consistent failed for TxDL\n");
734 mem_allocated += PAGE_SIZE;
736 while (k < lst_per_page) {
737 int l = (j * lst_per_page) + k;
738 if (l == tx_cfg->fifo_len)
740 fifo->list_info[l].list_virt_addr =
741 tmp_v + (k * lst_size);
742 fifo->list_info[l].list_phy_addr =
743 tmp_p + (k * lst_size);
749 for (i = 0; i < config->tx_fifo_num; i++) {
750 struct fifo_info *fifo = &mac_control->fifos[i];
751 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
753 size = tx_cfg->fifo_len;
754 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
755 if (!fifo->ufo_in_band_v)
757 mem_allocated += (size * sizeof(u64));
760 /* Allocation and initialization of RXDs in Rings */
762 for (i = 0; i < config->rx_ring_num; i++) {
763 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
764 struct ring_info *ring = &mac_control->rings[i];
766 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
767 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
768 "multiple of RxDs per Block\n",
772 size += rx_cfg->num_rxd;
773 ring->block_count = rx_cfg->num_rxd /
774 (rxd_count[nic->rxd_mode] + 1);
775 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
777 if (nic->rxd_mode == RXD_MODE_1)
778 size = (size * (sizeof(struct RxD1)));
780 size = (size * (sizeof(struct RxD3)));
782 for (i = 0; i < config->rx_ring_num; i++) {
783 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
784 struct ring_info *ring = &mac_control->rings[i];
786 ring->rx_curr_get_info.block_index = 0;
787 ring->rx_curr_get_info.offset = 0;
788 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
789 ring->rx_curr_put_info.block_index = 0;
790 ring->rx_curr_put_info.offset = 0;
791 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
795 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
796 /* Allocating all the Rx blocks */
797 for (j = 0; j < blk_cnt; j++) {
798 struct rx_block_info *rx_blocks;
801 rx_blocks = &ring->rx_blocks[j];
802 size = SIZE_OF_BLOCK; /* size is always page size */
803 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
805 if (tmp_v_addr == NULL) {
807 * In case of failure, free_shared_mem()
808 * is called, which should free any
809 * memory that was alloced till the
812 rx_blocks->block_virt_addr = tmp_v_addr;
815 mem_allocated += size;
816 memset(tmp_v_addr, 0, size);
818 size = sizeof(struct rxd_info) *
819 rxd_count[nic->rxd_mode];
820 rx_blocks->block_virt_addr = tmp_v_addr;
821 rx_blocks->block_dma_addr = tmp_p_addr;
822 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
823 if (!rx_blocks->rxds)
825 mem_allocated += size;
826 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
827 rx_blocks->rxds[l].virt_addr =
828 rx_blocks->block_virt_addr +
829 (rxd_size[nic->rxd_mode] * l);
830 rx_blocks->rxds[l].dma_addr =
831 rx_blocks->block_dma_addr +
832 (rxd_size[nic->rxd_mode] * l);
835 /* Interlinking all Rx Blocks */
836 for (j = 0; j < blk_cnt; j++) {
837 int next = (j + 1) % blk_cnt;
838 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
839 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
840 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
841 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
843 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
844 pre_rxd_blk->reserved_2_pNext_RxD_block =
845 (unsigned long)tmp_v_addr_next;
846 pre_rxd_blk->pNext_RxD_Blk_physical =
847 (u64)tmp_p_addr_next;
850 if (nic->rxd_mode == RXD_MODE_3B) {
852 * Allocation of Storages for buffer addresses in 2BUFF mode
853 * and the buffers as well.
855 for (i = 0; i < config->rx_ring_num; i++) {
856 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
857 struct ring_info *ring = &mac_control->rings[i];
859 blk_cnt = rx_cfg->num_rxd /
860 (rxd_count[nic->rxd_mode] + 1);
861 size = sizeof(struct buffAdd *) * blk_cnt;
862 ring->ba = kmalloc(size, GFP_KERNEL);
865 mem_allocated += size;
866 for (j = 0; j < blk_cnt; j++) {
869 size = sizeof(struct buffAdd) *
870 (rxd_count[nic->rxd_mode] + 1);
871 ring->ba[j] = kmalloc(size, GFP_KERNEL);
874 mem_allocated += size;
875 while (k != rxd_count[nic->rxd_mode]) {
876 ba = &ring->ba[j][k];
877 size = BUF0_LEN + ALIGN_SIZE;
878 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
881 mem_allocated += size;
882 tmp = (unsigned long)ba->ba_0_org;
884 tmp &= ~((unsigned long)ALIGN_SIZE);
885 ba->ba_0 = (void *)tmp;
887 size = BUF1_LEN + ALIGN_SIZE;
888 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
891 mem_allocated += size;
892 tmp = (unsigned long)ba->ba_1_org;
894 tmp &= ~((unsigned long)ALIGN_SIZE);
895 ba->ba_1 = (void *)tmp;
902 /* Allocation and initialization of Statistics block */
903 size = sizeof(struct stat_block);
904 mac_control->stats_mem =
905 pci_alloc_consistent(nic->pdev, size,
906 &mac_control->stats_mem_phy);
908 if (!mac_control->stats_mem) {
910 * In case of failure, free_shared_mem() is called, which
911 * should free any memory that was alloced till the
916 mem_allocated += size;
917 mac_control->stats_mem_sz = size;
919 tmp_v_addr = mac_control->stats_mem;
920 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
921 memset(tmp_v_addr, 0, size);
922 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
923 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
924 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
929 * free_shared_mem - Free the allocated Memory
930 * @nic: Device private variable.
931 * Description: This function is to free all memory locations allocated by
932 * the init_shared_mem() function and return it to the kernel.
935 static void free_shared_mem(struct s2io_nic *nic)
937 int i, j, blk_cnt, size;
939 dma_addr_t tmp_p_addr;
940 int lst_size, lst_per_page;
941 struct net_device *dev;
943 struct config_param *config;
944 struct mac_info *mac_control;
945 struct stat_block *stats;
946 struct swStat *swstats;
953 config = &nic->config;
954 mac_control = &nic->mac_control;
955 stats = mac_control->stats_info;
956 swstats = &stats->sw_stat;
958 lst_size = sizeof(struct TxD) * config->max_txds;
959 lst_per_page = PAGE_SIZE / lst_size;
961 for (i = 0; i < config->tx_fifo_num; i++) {
962 struct fifo_info *fifo = &mac_control->fifos[i];
963 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
965 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
966 for (j = 0; j < page_num; j++) {
967 int mem_blks = (j * lst_per_page);
968 struct list_info_hold *fli;
970 if (!fifo->list_info)
973 fli = &fifo->list_info[mem_blks];
974 if (!fli->list_virt_addr)
976 pci_free_consistent(nic->pdev, PAGE_SIZE,
979 swstats->mem_freed += PAGE_SIZE;
981 /* If we got a zero DMA address during allocation,
984 if (mac_control->zerodma_virt_addr) {
985 pci_free_consistent(nic->pdev, PAGE_SIZE,
986 mac_control->zerodma_virt_addr,
989 "%s: Freeing TxDL with zero DMA address. "
990 "Virtual address %p\n",
991 dev->name, mac_control->zerodma_virt_addr);
992 swstats->mem_freed += PAGE_SIZE;
994 kfree(fifo->list_info);
995 swstats->mem_freed += tx_cfg->fifo_len *
996 sizeof(struct list_info_hold);
999 size = SIZE_OF_BLOCK;
1000 for (i = 0; i < config->rx_ring_num; i++) {
1001 struct ring_info *ring = &mac_control->rings[i];
1003 blk_cnt = ring->block_count;
1004 for (j = 0; j < blk_cnt; j++) {
1005 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1006 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1007 if (tmp_v_addr == NULL)
1009 pci_free_consistent(nic->pdev, size,
1010 tmp_v_addr, tmp_p_addr);
1011 swstats->mem_freed += size;
1012 kfree(ring->rx_blocks[j].rxds);
1013 swstats->mem_freed += sizeof(struct rxd_info) *
1014 rxd_count[nic->rxd_mode];
1018 if (nic->rxd_mode == RXD_MODE_3B) {
1019 /* Freeing buffer storage addresses in 2BUFF mode. */
1020 for (i = 0; i < config->rx_ring_num; i++) {
1021 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1022 struct ring_info *ring = &mac_control->rings[i];
1024 blk_cnt = rx_cfg->num_rxd /
1025 (rxd_count[nic->rxd_mode] + 1);
1026 for (j = 0; j < blk_cnt; j++) {
1030 while (k != rxd_count[nic->rxd_mode]) {
1031 struct buffAdd *ba = &ring->ba[j][k];
1032 kfree(ba->ba_0_org);
1033 swstats->mem_freed +=
1034 BUF0_LEN + ALIGN_SIZE;
1035 kfree(ba->ba_1_org);
1036 swstats->mem_freed +=
1037 BUF1_LEN + ALIGN_SIZE;
1041 swstats->mem_freed += sizeof(struct buffAdd) *
1042 (rxd_count[nic->rxd_mode] + 1);
1045 swstats->mem_freed += sizeof(struct buffAdd *) *
1050 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1051 struct fifo_info *fifo = &mac_control->fifos[i];
1052 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1054 if (fifo->ufo_in_band_v) {
1055 swstats->mem_freed += tx_cfg->fifo_len *
1057 kfree(fifo->ufo_in_band_v);
1061 if (mac_control->stats_mem) {
1062 swstats->mem_freed += mac_control->stats_mem_sz;
1063 pci_free_consistent(nic->pdev,
1064 mac_control->stats_mem_sz,
1065 mac_control->stats_mem,
1066 mac_control->stats_mem_phy);
1071 * s2io_verify_pci_mode -
1074 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1076 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1077 register u64 val64 = 0;
1080 val64 = readq(&bar0->pci_mode);
1081 mode = (u8)GET_PCI_MODE(val64);
1083 if (val64 & PCI_MODE_UNKNOWN_MODE)
1084 return -1; /* Unknown PCI mode */
1088 #define NEC_VENID 0x1033
1089 #define NEC_DEVID 0x0125
1090 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1092 struct pci_dev *tdev = NULL;
1093 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1094 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1095 if (tdev->bus == s2io_pdev->bus->parent) {
1104 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1106 * s2io_print_pci_mode -
1108 static int s2io_print_pci_mode(struct s2io_nic *nic)
1110 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1111 register u64 val64 = 0;
1113 struct config_param *config = &nic->config;
1114 const char *pcimode;
1116 val64 = readq(&bar0->pci_mode);
1117 mode = (u8)GET_PCI_MODE(val64);
1119 if (val64 & PCI_MODE_UNKNOWN_MODE)
1120 return -1; /* Unknown PCI mode */
1122 config->bus_speed = bus_speed[mode];
1124 if (s2io_on_nec_bridge(nic->pdev)) {
1125 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1131 case PCI_MODE_PCI_33:
1132 pcimode = "33MHz PCI bus";
1134 case PCI_MODE_PCI_66:
1135 pcimode = "66MHz PCI bus";
1137 case PCI_MODE_PCIX_M1_66:
1138 pcimode = "66MHz PCIX(M1) bus";
1140 case PCI_MODE_PCIX_M1_100:
1141 pcimode = "100MHz PCIX(M1) bus";
1143 case PCI_MODE_PCIX_M1_133:
1144 pcimode = "133MHz PCIX(M1) bus";
1146 case PCI_MODE_PCIX_M2_66:
1147 pcimode = "133MHz PCIX(M2) bus";
1149 case PCI_MODE_PCIX_M2_100:
1150 pcimode = "200MHz PCIX(M2) bus";
1152 case PCI_MODE_PCIX_M2_133:
1153 pcimode = "266MHz PCIX(M2) bus";
1156 pcimode = "unsupported bus!";
1160 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1161 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1167 * init_tti - Initialization transmit traffic interrupt scheme
1168 * @nic: device private variable
1169 * @link: link status (UP/DOWN) used to enable/disable continuous
1170 * transmit interrupts
1171 * Description: The function configures transmit traffic interrupts
1172 * Return Value: SUCCESS on success and
1176 static int init_tti(struct s2io_nic *nic, int link)
1178 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1179 register u64 val64 = 0;
1181 struct config_param *config = &nic->config;
1183 for (i = 0; i < config->tx_fifo_num; i++) {
1185 * TTI Initialization. Default Tx timer gets us about
1186 * 250 interrupts per sec. Continuous interrupts are enabled
1189 if (nic->device_type == XFRAME_II_DEVICE) {
1190 int count = (nic->config.bus_speed * 125)/2;
1191 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1193 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1195 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1196 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1197 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1198 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1200 if (use_continuous_tx_intrs && (link == LINK_UP))
1201 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1202 writeq(val64, &bar0->tti_data1_mem);
1204 if (nic->config.intr_type == MSI_X) {
1205 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1206 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1207 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1208 TTI_DATA2_MEM_TX_UFC_D(0x300);
1210 if ((nic->config.tx_steering_type ==
1211 TX_DEFAULT_STEERING) &&
1212 (config->tx_fifo_num > 1) &&
1213 (i >= nic->udp_fifo_idx) &&
1214 (i < (nic->udp_fifo_idx +
1215 nic->total_udp_fifos)))
1216 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1217 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1218 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1219 TTI_DATA2_MEM_TX_UFC_D(0x120);
1221 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1222 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1223 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1224 TTI_DATA2_MEM_TX_UFC_D(0x80);
1227 writeq(val64, &bar0->tti_data2_mem);
1229 val64 = TTI_CMD_MEM_WE |
1230 TTI_CMD_MEM_STROBE_NEW_CMD |
1231 TTI_CMD_MEM_OFFSET(i);
1232 writeq(val64, &bar0->tti_command_mem);
1234 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1235 TTI_CMD_MEM_STROBE_NEW_CMD,
1236 S2IO_BIT_RESET) != SUCCESS)
1244 * init_nic - Initialization of hardware
1245 * @nic: device private variable
1246 * Description: The function sequentially configures every block
1247 * of the H/W from their reset values.
1248 * Return Value: SUCCESS on success and
1249 * '-1' on failure (endian settings incorrect).
1252 static int init_nic(struct s2io_nic *nic)
1254 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1255 struct net_device *dev = nic->dev;
1256 register u64 val64 = 0;
1261 unsigned long long mem_share;
1263 struct config_param *config = &nic->config;
1264 struct mac_info *mac_control = &nic->mac_control;
1266 /* to set the swapper controle on the card */
1267 if (s2io_set_swapper(nic)) {
1268 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1273 * Herc requires EOI to be removed from reset before XGXS, so..
1275 if (nic->device_type & XFRAME_II_DEVICE) {
1276 val64 = 0xA500000000ULL;
1277 writeq(val64, &bar0->sw_reset);
1279 val64 = readq(&bar0->sw_reset);
1282 /* Remove XGXS from reset state */
1284 writeq(val64, &bar0->sw_reset);
1286 val64 = readq(&bar0->sw_reset);
1288 /* Ensure that it's safe to access registers by checking
1289 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1291 if (nic->device_type == XFRAME_II_DEVICE) {
1292 for (i = 0; i < 50; i++) {
1293 val64 = readq(&bar0->adapter_status);
1294 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1302 /* Enable Receiving broadcasts */
1303 add = &bar0->mac_cfg;
1304 val64 = readq(&bar0->mac_cfg);
1305 val64 |= MAC_RMAC_BCAST_ENABLE;
1306 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1307 writel((u32)val64, add);
1308 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1309 writel((u32) (val64 >> 32), (add + 4));
1311 /* Read registers in all blocks */
1312 val64 = readq(&bar0->mac_int_mask);
1313 val64 = readq(&bar0->mc_int_mask);
1314 val64 = readq(&bar0->xgxs_int_mask);
1318 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1320 if (nic->device_type & XFRAME_II_DEVICE) {
1321 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1322 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1323 &bar0->dtx_control, UF);
1325 msleep(1); /* Necessary!! */
1329 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1330 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1331 &bar0->dtx_control, UF);
1332 val64 = readq(&bar0->dtx_control);
1337 /* Tx DMA Initialization */
1339 writeq(val64, &bar0->tx_fifo_partition_0);
1340 writeq(val64, &bar0->tx_fifo_partition_1);
1341 writeq(val64, &bar0->tx_fifo_partition_2);
1342 writeq(val64, &bar0->tx_fifo_partition_3);
1344 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1345 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1347 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1348 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1350 if (i == (config->tx_fifo_num - 1)) {
1357 writeq(val64, &bar0->tx_fifo_partition_0);
1362 writeq(val64, &bar0->tx_fifo_partition_1);
1367 writeq(val64, &bar0->tx_fifo_partition_2);
1372 writeq(val64, &bar0->tx_fifo_partition_3);
1383 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1384 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1386 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1387 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1389 val64 = readq(&bar0->tx_fifo_partition_0);
1390 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1391 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1394 * Initialization of Tx_PA_CONFIG register to ignore packet
1395 * integrity checking.
1397 val64 = readq(&bar0->tx_pa_cfg);
1398 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1399 TX_PA_CFG_IGNORE_SNAP_OUI |
1400 TX_PA_CFG_IGNORE_LLC_CTRL |
1401 TX_PA_CFG_IGNORE_L2_ERR;
1402 writeq(val64, &bar0->tx_pa_cfg);
1404 /* Rx DMA intialization. */
1406 for (i = 0; i < config->rx_ring_num; i++) {
1407 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1409 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1411 writeq(val64, &bar0->rx_queue_priority);
1414 * Allocating equal share of memory to all the
1418 if (nic->device_type & XFRAME_II_DEVICE)
1423 for (i = 0; i < config->rx_ring_num; i++) {
1426 mem_share = (mem_size / config->rx_ring_num +
1427 mem_size % config->rx_ring_num);
1428 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1431 mem_share = (mem_size / config->rx_ring_num);
1432 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1435 mem_share = (mem_size / config->rx_ring_num);
1436 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1439 mem_share = (mem_size / config->rx_ring_num);
1440 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1443 mem_share = (mem_size / config->rx_ring_num);
1444 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1447 mem_share = (mem_size / config->rx_ring_num);
1448 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1451 mem_share = (mem_size / config->rx_ring_num);
1452 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1455 mem_share = (mem_size / config->rx_ring_num);
1456 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1460 writeq(val64, &bar0->rx_queue_cfg);
1463 * Filling Tx round robin registers
1464 * as per the number of FIFOs for equal scheduling priority
1466 switch (config->tx_fifo_num) {
1469 writeq(val64, &bar0->tx_w_round_robin_0);
1470 writeq(val64, &bar0->tx_w_round_robin_1);
1471 writeq(val64, &bar0->tx_w_round_robin_2);
1472 writeq(val64, &bar0->tx_w_round_robin_3);
1473 writeq(val64, &bar0->tx_w_round_robin_4);
1476 val64 = 0x0001000100010001ULL;
1477 writeq(val64, &bar0->tx_w_round_robin_0);
1478 writeq(val64, &bar0->tx_w_round_robin_1);
1479 writeq(val64, &bar0->tx_w_round_robin_2);
1480 writeq(val64, &bar0->tx_w_round_robin_3);
1481 val64 = 0x0001000100000000ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_4);
1485 val64 = 0x0001020001020001ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_0);
1487 val64 = 0x0200010200010200ULL;
1488 writeq(val64, &bar0->tx_w_round_robin_1);
1489 val64 = 0x0102000102000102ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_2);
1491 val64 = 0x0001020001020001ULL;
1492 writeq(val64, &bar0->tx_w_round_robin_3);
1493 val64 = 0x0200010200000000ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_4);
1497 val64 = 0x0001020300010203ULL;
1498 writeq(val64, &bar0->tx_w_round_robin_0);
1499 writeq(val64, &bar0->tx_w_round_robin_1);
1500 writeq(val64, &bar0->tx_w_round_robin_2);
1501 writeq(val64, &bar0->tx_w_round_robin_3);
1502 val64 = 0x0001020300000000ULL;
1503 writeq(val64, &bar0->tx_w_round_robin_4);
1506 val64 = 0x0001020304000102ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_0);
1508 val64 = 0x0304000102030400ULL;
1509 writeq(val64, &bar0->tx_w_round_robin_1);
1510 val64 = 0x0102030400010203ULL;
1511 writeq(val64, &bar0->tx_w_round_robin_2);
1512 val64 = 0x0400010203040001ULL;
1513 writeq(val64, &bar0->tx_w_round_robin_3);
1514 val64 = 0x0203040000000000ULL;
1515 writeq(val64, &bar0->tx_w_round_robin_4);
1518 val64 = 0x0001020304050001ULL;
1519 writeq(val64, &bar0->tx_w_round_robin_0);
1520 val64 = 0x0203040500010203ULL;
1521 writeq(val64, &bar0->tx_w_round_robin_1);
1522 val64 = 0x0405000102030405ULL;
1523 writeq(val64, &bar0->tx_w_round_robin_2);
1524 val64 = 0x0001020304050001ULL;
1525 writeq(val64, &bar0->tx_w_round_robin_3);
1526 val64 = 0x0203040500000000ULL;
1527 writeq(val64, &bar0->tx_w_round_robin_4);
1530 val64 = 0x0001020304050600ULL;
1531 writeq(val64, &bar0->tx_w_round_robin_0);
1532 val64 = 0x0102030405060001ULL;
1533 writeq(val64, &bar0->tx_w_round_robin_1);
1534 val64 = 0x0203040506000102ULL;
1535 writeq(val64, &bar0->tx_w_round_robin_2);
1536 val64 = 0x0304050600010203ULL;
1537 writeq(val64, &bar0->tx_w_round_robin_3);
1538 val64 = 0x0405060000000000ULL;
1539 writeq(val64, &bar0->tx_w_round_robin_4);
1542 val64 = 0x0001020304050607ULL;
1543 writeq(val64, &bar0->tx_w_round_robin_0);
1544 writeq(val64, &bar0->tx_w_round_robin_1);
1545 writeq(val64, &bar0->tx_w_round_robin_2);
1546 writeq(val64, &bar0->tx_w_round_robin_3);
1547 val64 = 0x0001020300000000ULL;
1548 writeq(val64, &bar0->tx_w_round_robin_4);
1552 /* Enable all configured Tx FIFO partitions */
1553 val64 = readq(&bar0->tx_fifo_partition_0);
1554 val64 |= (TX_FIFO_PARTITION_EN);
1555 writeq(val64, &bar0->tx_fifo_partition_0);
1557 /* Filling the Rx round robin registers as per the
1558 * number of Rings and steering based on QoS with
1561 switch (config->rx_ring_num) {
1564 writeq(val64, &bar0->rx_w_round_robin_0);
1565 writeq(val64, &bar0->rx_w_round_robin_1);
1566 writeq(val64, &bar0->rx_w_round_robin_2);
1567 writeq(val64, &bar0->rx_w_round_robin_3);
1568 writeq(val64, &bar0->rx_w_round_robin_4);
1570 val64 = 0x8080808080808080ULL;
1571 writeq(val64, &bar0->rts_qos_steering);
1574 val64 = 0x0001000100010001ULL;
1575 writeq(val64, &bar0->rx_w_round_robin_0);
1576 writeq(val64, &bar0->rx_w_round_robin_1);
1577 writeq(val64, &bar0->rx_w_round_robin_2);
1578 writeq(val64, &bar0->rx_w_round_robin_3);
1579 val64 = 0x0001000100000000ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_4);
1582 val64 = 0x8080808040404040ULL;
1583 writeq(val64, &bar0->rts_qos_steering);
1586 val64 = 0x0001020001020001ULL;
1587 writeq(val64, &bar0->rx_w_round_robin_0);
1588 val64 = 0x0200010200010200ULL;
1589 writeq(val64, &bar0->rx_w_round_robin_1);
1590 val64 = 0x0102000102000102ULL;
1591 writeq(val64, &bar0->rx_w_round_robin_2);
1592 val64 = 0x0001020001020001ULL;
1593 writeq(val64, &bar0->rx_w_round_robin_3);
1594 val64 = 0x0200010200000000ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_4);
1597 val64 = 0x8080804040402020ULL;
1598 writeq(val64, &bar0->rts_qos_steering);
1601 val64 = 0x0001020300010203ULL;
1602 writeq(val64, &bar0->rx_w_round_robin_0);
1603 writeq(val64, &bar0->rx_w_round_robin_1);
1604 writeq(val64, &bar0->rx_w_round_robin_2);
1605 writeq(val64, &bar0->rx_w_round_robin_3);
1606 val64 = 0x0001020300000000ULL;
1607 writeq(val64, &bar0->rx_w_round_robin_4);
1609 val64 = 0x8080404020201010ULL;
1610 writeq(val64, &bar0->rts_qos_steering);
1613 val64 = 0x0001020304000102ULL;
1614 writeq(val64, &bar0->rx_w_round_robin_0);
1615 val64 = 0x0304000102030400ULL;
1616 writeq(val64, &bar0->rx_w_round_robin_1);
1617 val64 = 0x0102030400010203ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_2);
1619 val64 = 0x0400010203040001ULL;
1620 writeq(val64, &bar0->rx_w_round_robin_3);
1621 val64 = 0x0203040000000000ULL;
1622 writeq(val64, &bar0->rx_w_round_robin_4);
1624 val64 = 0x8080404020201008ULL;
1625 writeq(val64, &bar0->rts_qos_steering);
1628 val64 = 0x0001020304050001ULL;
1629 writeq(val64, &bar0->rx_w_round_robin_0);
1630 val64 = 0x0203040500010203ULL;
1631 writeq(val64, &bar0->rx_w_round_robin_1);
1632 val64 = 0x0405000102030405ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_2);
1634 val64 = 0x0001020304050001ULL;
1635 writeq(val64, &bar0->rx_w_round_robin_3);
1636 val64 = 0x0203040500000000ULL;
1637 writeq(val64, &bar0->rx_w_round_robin_4);
1639 val64 = 0x8080404020100804ULL;
1640 writeq(val64, &bar0->rts_qos_steering);
1643 val64 = 0x0001020304050600ULL;
1644 writeq(val64, &bar0->rx_w_round_robin_0);
1645 val64 = 0x0102030405060001ULL;
1646 writeq(val64, &bar0->rx_w_round_robin_1);
1647 val64 = 0x0203040506000102ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_2);
1649 val64 = 0x0304050600010203ULL;
1650 writeq(val64, &bar0->rx_w_round_robin_3);
1651 val64 = 0x0405060000000000ULL;
1652 writeq(val64, &bar0->rx_w_round_robin_4);
1654 val64 = 0x8080402010080402ULL;
1655 writeq(val64, &bar0->rts_qos_steering);
1658 val64 = 0x0001020304050607ULL;
1659 writeq(val64, &bar0->rx_w_round_robin_0);
1660 writeq(val64, &bar0->rx_w_round_robin_1);
1661 writeq(val64, &bar0->rx_w_round_robin_2);
1662 writeq(val64, &bar0->rx_w_round_robin_3);
1663 val64 = 0x0001020300000000ULL;
1664 writeq(val64, &bar0->rx_w_round_robin_4);
1666 val64 = 0x8040201008040201ULL;
1667 writeq(val64, &bar0->rts_qos_steering);
1673 for (i = 0; i < 8; i++)
1674 writeq(val64, &bar0->rts_frm_len_n[i]);
1676 /* Set the default rts frame length for the rings configured */
1677 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1678 for (i = 0 ; i < config->rx_ring_num ; i++)
1679 writeq(val64, &bar0->rts_frm_len_n[i]);
1681 /* Set the frame length for the configured rings
1682 * desired by the user
1684 for (i = 0; i < config->rx_ring_num; i++) {
1685 /* If rts_frm_len[i] == 0 then it is assumed that user not
1686 * specified frame length steering.
1687 * If the user provides the frame length then program
1688 * the rts_frm_len register for those values or else
1689 * leave it as it is.
1691 if (rts_frm_len[i] != 0) {
1692 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1693 &bar0->rts_frm_len_n[i]);
1697 /* Disable differentiated services steering logic */
1698 for (i = 0; i < 64; i++) {
1699 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1701 "%s: rts_ds_steer failed on codepoint %d\n",
1707 /* Program statistics memory */
1708 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1710 if (nic->device_type == XFRAME_II_DEVICE) {
1711 val64 = STAT_BC(0x320);
1712 writeq(val64, &bar0->stat_byte_cnt);
1716 * Initializing the sampling rate for the device to calculate the
1717 * bandwidth utilization.
1719 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1720 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1721 writeq(val64, &bar0->mac_link_util);
1724 * Initializing the Transmit and Receive Traffic Interrupt
1728 /* Initialize TTI */
1729 if (SUCCESS != init_tti(nic, nic->last_link_state))
1732 /* RTI Initialization */
1733 if (nic->device_type == XFRAME_II_DEVICE) {
1735 * Programmed to generate Apprx 500 Intrs per
1738 int count = (nic->config.bus_speed * 125)/4;
1739 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1741 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1742 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1743 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1744 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1745 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1747 writeq(val64, &bar0->rti_data1_mem);
1749 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1750 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1751 if (nic->config.intr_type == MSI_X)
1752 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1753 RTI_DATA2_MEM_RX_UFC_D(0x40));
1755 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1756 RTI_DATA2_MEM_RX_UFC_D(0x80));
1757 writeq(val64, &bar0->rti_data2_mem);
1759 for (i = 0; i < config->rx_ring_num; i++) {
1760 val64 = RTI_CMD_MEM_WE |
1761 RTI_CMD_MEM_STROBE_NEW_CMD |
1762 RTI_CMD_MEM_OFFSET(i);
1763 writeq(val64, &bar0->rti_command_mem);
1766 * Once the operation completes, the Strobe bit of the
1767 * command register will be reset. We poll for this
1768 * particular condition. We wait for a maximum of 500ms
1769 * for the operation to complete, if it's not complete
1770 * by then we return error.
1774 val64 = readq(&bar0->rti_command_mem);
1775 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1779 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1789 * Initializing proper values as Pause threshold into all
1790 * the 8 Queues on Rx side.
1792 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1793 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1795 /* Disable RMAC PAD STRIPPING */
1796 add = &bar0->mac_cfg;
1797 val64 = readq(&bar0->mac_cfg);
1798 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1799 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1800 writel((u32) (val64), add);
1801 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1802 writel((u32) (val64 >> 32), (add + 4));
1803 val64 = readq(&bar0->mac_cfg);
1805 /* Enable FCS stripping by adapter */
1806 add = &bar0->mac_cfg;
1807 val64 = readq(&bar0->mac_cfg);
1808 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1809 if (nic->device_type == XFRAME_II_DEVICE)
1810 writeq(val64, &bar0->mac_cfg);
1812 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1813 writel((u32) (val64), add);
1814 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1815 writel((u32) (val64 >> 32), (add + 4));
1819 * Set the time value to be inserted in the pause frame
1820 * generated by xena.
1822 val64 = readq(&bar0->rmac_pause_cfg);
1823 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1824 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1825 writeq(val64, &bar0->rmac_pause_cfg);
1828 * Set the Threshold Limit for Generating the pause frame
1829 * If the amount of data in any Queue exceeds ratio of
1830 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1831 * pause frame is generated
1834 for (i = 0; i < 4; i++) {
1835 val64 |= (((u64)0xFF00 |
1836 nic->mac_control.mc_pause_threshold_q0q3)
1839 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1842 for (i = 0; i < 4; i++) {
1843 val64 |= (((u64)0xFF00 |
1844 nic->mac_control.mc_pause_threshold_q4q7)
1847 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1850 * TxDMA will stop Read request if the number of read split has
1851 * exceeded the limit pointed by shared_splits
1853 val64 = readq(&bar0->pic_control);
1854 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1855 writeq(val64, &bar0->pic_control);
1857 if (nic->config.bus_speed == 266) {
1858 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1859 writeq(0x0, &bar0->read_retry_delay);
1860 writeq(0x0, &bar0->write_retry_delay);
1864 * Programming the Herc to split every write transaction
1865 * that does not start on an ADB to reduce disconnects.
1867 if (nic->device_type == XFRAME_II_DEVICE) {
1868 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1869 MISC_LINK_STABILITY_PRD(3);
1870 writeq(val64, &bar0->misc_control);
1871 val64 = readq(&bar0->pic_control2);
1872 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1873 writeq(val64, &bar0->pic_control2);
1875 if (strstr(nic->product_name, "CX4")) {
1876 val64 = TMAC_AVG_IPG(0x17);
1877 writeq(val64, &bar0->tmac_avg_ipg);
1882 #define LINK_UP_DOWN_INTERRUPT 1
1883 #define MAC_RMAC_ERR_TIMER 2
1885 static int s2io_link_fault_indication(struct s2io_nic *nic)
1887 if (nic->device_type == XFRAME_II_DEVICE)
1888 return LINK_UP_DOWN_INTERRUPT;
1890 return MAC_RMAC_ERR_TIMER;
1894 * do_s2io_write_bits - update alarm bits in alarm register
1895 * @value: alarm bits
1896 * @flag: interrupt status
1897 * @addr: address value
1898 * Description: update alarm bits in alarm register
1902 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1906 temp64 = readq(addr);
1908 if (flag == ENABLE_INTRS)
1909 temp64 &= ~((u64)value);
1911 temp64 |= ((u64)value);
1912 writeq(temp64, addr);
1915 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1917 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1918 register u64 gen_int_mask = 0;
1921 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1922 if (mask & TX_DMA_INTR) {
1923 gen_int_mask |= TXDMA_INT_M;
1925 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1926 TXDMA_PCC_INT | TXDMA_TTI_INT |
1927 TXDMA_LSO_INT | TXDMA_TPA_INT |
1928 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1930 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1931 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1932 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1933 &bar0->pfc_err_mask);
1935 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1936 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1937 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1939 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1940 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1941 PCC_N_SERR | PCC_6_COF_OV_ERR |
1942 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1943 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1945 flag, &bar0->pcc_err_mask);
1947 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1948 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1950 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1951 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1952 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1953 flag, &bar0->lso_err_mask);
1955 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1956 flag, &bar0->tpa_err_mask);
1958 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1961 if (mask & TX_MAC_INTR) {
1962 gen_int_mask |= TXMAC_INT_M;
1963 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1964 &bar0->mac_int_mask);
1965 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1966 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1967 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1968 flag, &bar0->mac_tmac_err_mask);
1971 if (mask & TX_XGXS_INTR) {
1972 gen_int_mask |= TXXGXS_INT_M;
1973 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1974 &bar0->xgxs_int_mask);
1975 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1976 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1977 flag, &bar0->xgxs_txgxs_err_mask);
1980 if (mask & RX_DMA_INTR) {
1981 gen_int_mask |= RXDMA_INT_M;
1982 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1983 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1984 flag, &bar0->rxdma_int_mask);
1985 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1986 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1987 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1988 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1989 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1990 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1991 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1992 &bar0->prc_pcix_err_mask);
1993 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1994 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1995 &bar0->rpa_err_mask);
1996 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1997 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1998 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1999 RDA_FRM_ECC_SG_ERR |
2000 RDA_MISC_ERR|RDA_PCIX_ERR,
2001 flag, &bar0->rda_err_mask);
2002 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2003 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2004 flag, &bar0->rti_err_mask);
2007 if (mask & RX_MAC_INTR) {
2008 gen_int_mask |= RXMAC_INT_M;
2009 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2010 &bar0->mac_int_mask);
2011 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2012 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2013 RMAC_DOUBLE_ECC_ERR);
2014 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2015 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2016 do_s2io_write_bits(interruptible,
2017 flag, &bar0->mac_rmac_err_mask);
2020 if (mask & RX_XGXS_INTR) {
2021 gen_int_mask |= RXXGXS_INT_M;
2022 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2023 &bar0->xgxs_int_mask);
2024 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2025 &bar0->xgxs_rxgxs_err_mask);
2028 if (mask & MC_INTR) {
2029 gen_int_mask |= MC_INT_M;
2030 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2031 flag, &bar0->mc_int_mask);
2032 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2033 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2034 &bar0->mc_err_mask);
2036 nic->general_int_mask = gen_int_mask;
2038 /* Remove this line when alarm interrupts are enabled */
2039 nic->general_int_mask = 0;
2043 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2044 * @nic: device private variable,
2045 * @mask: A mask indicating which Intr block must be modified and,
2046 * @flag: A flag indicating whether to enable or disable the Intrs.
2047 * Description: This function will either disable or enable the interrupts
2048 * depending on the flag argument. The mask argument can be used to
2049 * enable/disable any Intr block.
2050 * Return Value: NONE.
2053 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2055 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2056 register u64 temp64 = 0, intr_mask = 0;
2058 intr_mask = nic->general_int_mask;
2060 /* Top level interrupt classification */
2061 /* PIC Interrupts */
2062 if (mask & TX_PIC_INTR) {
2063 /* Enable PIC Intrs in the general intr mask register */
2064 intr_mask |= TXPIC_INT_M;
2065 if (flag == ENABLE_INTRS) {
2067 * If Hercules adapter enable GPIO otherwise
2068 * disable all PCIX, Flash, MDIO, IIC and GPIO
2069 * interrupts for now.
2072 if (s2io_link_fault_indication(nic) ==
2073 LINK_UP_DOWN_INTERRUPT) {
2074 do_s2io_write_bits(PIC_INT_GPIO, flag,
2075 &bar0->pic_int_mask);
2076 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2077 &bar0->gpio_int_mask);
2079 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2080 } else if (flag == DISABLE_INTRS) {
2082 * Disable PIC Intrs in the general
2083 * intr mask register
2085 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2089 /* Tx traffic interrupts */
2090 if (mask & TX_TRAFFIC_INTR) {
2091 intr_mask |= TXTRAFFIC_INT_M;
2092 if (flag == ENABLE_INTRS) {
2094 * Enable all the Tx side interrupts
2095 * writing 0 Enables all 64 TX interrupt levels
2097 writeq(0x0, &bar0->tx_traffic_mask);
2098 } else if (flag == DISABLE_INTRS) {
2100 * Disable Tx Traffic Intrs in the general intr mask
2103 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2107 /* Rx traffic interrupts */
2108 if (mask & RX_TRAFFIC_INTR) {
2109 intr_mask |= RXTRAFFIC_INT_M;
2110 if (flag == ENABLE_INTRS) {
2111 /* writing 0 Enables all 8 RX interrupt levels */
2112 writeq(0x0, &bar0->rx_traffic_mask);
2113 } else if (flag == DISABLE_INTRS) {
2115 * Disable Rx Traffic Intrs in the general intr mask
2118 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2122 temp64 = readq(&bar0->general_int_mask);
2123 if (flag == ENABLE_INTRS)
2124 temp64 &= ~((u64)intr_mask);
2126 temp64 = DISABLE_ALL_INTRS;
2127 writeq(temp64, &bar0->general_int_mask);
2129 nic->general_int_mask = readq(&bar0->general_int_mask);
2133 * verify_pcc_quiescent- Checks for PCC quiescent state
2134 * Return: 1 If PCC is quiescence
2135 * 0 If PCC is not quiescence
2137 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2140 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2141 u64 val64 = readq(&bar0->adapter_status);
2143 herc = (sp->device_type == XFRAME_II_DEVICE);
2145 if (flag == false) {
2146 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2147 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2150 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2154 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2155 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2156 ADAPTER_STATUS_RMAC_PCC_IDLE))
2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2160 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2168 * verify_xena_quiescence - Checks whether the H/W is ready
2169 * Description: Returns whether the H/W is ready to go or not. Depending
2170 * on whether adapter enable bit was written or not the comparison
2171 * differs and the calling function passes the input argument flag to
2173 * Return: 1 If xena is quiescence
2174 * 0 If Xena is not quiescence
2177 static int verify_xena_quiescence(struct s2io_nic *sp)
2180 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2181 u64 val64 = readq(&bar0->adapter_status);
2182 mode = s2io_verify_pci_mode(sp);
2184 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2185 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2188 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2189 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2192 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2193 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2196 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2197 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2200 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2201 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2204 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2205 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2208 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2209 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2212 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2213 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2218 * In PCI 33 mode, the P_PLL is not used, and therefore,
2219 * the the P_PLL_LOCK bit in the adapter_status register will
2222 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2223 sp->device_type == XFRAME_II_DEVICE &&
2224 mode != PCI_MODE_PCI_33) {
2225 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2228 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2229 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2230 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2237 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2238 * @sp: Pointer to device specifc structure
2240 * New procedure to clear mac address reading problems on Alpha platforms
2244 static void fix_mac_address(struct s2io_nic *sp)
2246 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2250 while (fix_mac[i] != END_SIGN) {
2251 writeq(fix_mac[i++], &bar0->gpio_control);
2253 val64 = readq(&bar0->gpio_control);
2258 * start_nic - Turns the device on
2259 * @nic : device private variable.
2261 * This function actually turns the device on. Before this function is
2262 * called,all Registers are configured from their reset states
2263 * and shared memory is allocated but the NIC is still quiescent. On
2264 * calling this function, the device interrupts are cleared and the NIC is
2265 * literally switched on by writing into the adapter control register.
2267 * SUCCESS on success and -1 on failure.
2270 static int start_nic(struct s2io_nic *nic)
2272 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2273 struct net_device *dev = nic->dev;
2274 register u64 val64 = 0;
2276 struct config_param *config = &nic->config;
2277 struct mac_info *mac_control = &nic->mac_control;
2279 /* PRC Initialization and configuration */
2280 for (i = 0; i < config->rx_ring_num; i++) {
2281 struct ring_info *ring = &mac_control->rings[i];
2283 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2284 &bar0->prc_rxd0_n[i]);
2286 val64 = readq(&bar0->prc_ctrl_n[i]);
2287 if (nic->rxd_mode == RXD_MODE_1)
2288 val64 |= PRC_CTRL_RC_ENABLED;
2290 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2291 if (nic->device_type == XFRAME_II_DEVICE)
2292 val64 |= PRC_CTRL_GROUP_READS;
2293 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2294 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2295 writeq(val64, &bar0->prc_ctrl_n[i]);
2298 if (nic->rxd_mode == RXD_MODE_3B) {
2299 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2300 val64 = readq(&bar0->rx_pa_cfg);
2301 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2302 writeq(val64, &bar0->rx_pa_cfg);
2305 if (vlan_tag_strip == 0) {
2306 val64 = readq(&bar0->rx_pa_cfg);
2307 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2308 writeq(val64, &bar0->rx_pa_cfg);
2309 nic->vlan_strip_flag = 0;
2313 * Enabling MC-RLDRAM. After enabling the device, we timeout
2314 * for around 100ms, which is approximately the time required
2315 * for the device to be ready for operation.
2317 val64 = readq(&bar0->mc_rldram_mrs);
2318 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2319 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2320 val64 = readq(&bar0->mc_rldram_mrs);
2322 msleep(100); /* Delay by around 100 ms. */
2324 /* Enabling ECC Protection. */
2325 val64 = readq(&bar0->adapter_control);
2326 val64 &= ~ADAPTER_ECC_EN;
2327 writeq(val64, &bar0->adapter_control);
2330 * Verify if the device is ready to be enabled, if so enable
2333 val64 = readq(&bar0->adapter_status);
2334 if (!verify_xena_quiescence(nic)) {
2335 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2336 "Adapter status reads: 0x%llx\n",
2337 dev->name, (unsigned long long)val64);
2342 * With some switches, link might be already up at this point.
2343 * Because of this weird behavior, when we enable laser,
2344 * we may not get link. We need to handle this. We cannot
2345 * figure out which switch is misbehaving. So we are forced to
2346 * make a global change.
2349 /* Enabling Laser. */
2350 val64 = readq(&bar0->adapter_control);
2351 val64 |= ADAPTER_EOI_TX_ON;
2352 writeq(val64, &bar0->adapter_control);
2354 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2356 * Dont see link state interrupts initially on some switches,
2357 * so directly scheduling the link state task here.
2359 schedule_work(&nic->set_link_task);
2361 /* SXE-002: Initialize link and activity LED */
2362 subid = nic->pdev->subsystem_device;
2363 if (((subid & 0xFF) >= 0x07) &&
2364 (nic->device_type == XFRAME_I_DEVICE)) {
2365 val64 = readq(&bar0->gpio_control);
2366 val64 |= 0x0000800000000000ULL;
2367 writeq(val64, &bar0->gpio_control);
2368 val64 = 0x0411040400000000ULL;
2369 writeq(val64, (void __iomem *)bar0 + 0x2700);
2375 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2377 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2378 struct TxD *txdlp, int get_off)
2380 struct s2io_nic *nic = fifo_data->nic;
2381 struct sk_buff *skb;
2386 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2387 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2388 sizeof(u64), PCI_DMA_TODEVICE);
2392 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2394 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2397 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2398 skb_headlen(skb), PCI_DMA_TODEVICE);
2399 frg_cnt = skb_shinfo(skb)->nr_frags;
2402 for (j = 0; j < frg_cnt; j++, txds++) {
2403 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404 if (!txds->Buffer_Pointer)
2406 pci_unmap_page(nic->pdev,
2407 (dma_addr_t)txds->Buffer_Pointer,
2408 frag->size, PCI_DMA_TODEVICE);
2411 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416 * free_tx_buffers - Free all queued Tx buffers
2417 * @nic : device private variable.
2419 * Free all queued Tx buffers.
2420 * Return Value: void
2423 static void free_tx_buffers(struct s2io_nic *nic)
2425 struct net_device *dev = nic->dev;
2426 struct sk_buff *skb;
2430 struct config_param *config = &nic->config;
2431 struct mac_info *mac_control = &nic->mac_control;
2432 struct stat_block *stats = mac_control->stats_info;
2433 struct swStat *swstats = &stats->sw_stat;
2435 for (i = 0; i < config->tx_fifo_num; i++) {
2436 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2437 struct fifo_info *fifo = &mac_control->fifos[i];
2438 unsigned long flags;
2440 spin_lock_irqsave(&fifo->tx_lock, flags);
2441 for (j = 0; j < tx_cfg->fifo_len; j++) {
2442 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2443 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2445 swstats->mem_freed += skb->truesize;
2451 "%s: forcibly freeing %d skbs on FIFO%d\n",
2453 fifo->tx_curr_get_info.offset = 0;
2454 fifo->tx_curr_put_info.offset = 0;
2455 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2460 * stop_nic - To stop the nic
2461 * @nic ; device private variable.
2463 * This function does exactly the opposite of what the start_nic()
2464 * function does. This function is called to stop the device.
2469 static void stop_nic(struct s2io_nic *nic)
2471 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2472 register u64 val64 = 0;
2475 /* Disable all interrupts */
2476 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2477 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2478 interruptible |= TX_PIC_INTR;
2479 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2481 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2482 val64 = readq(&bar0->adapter_control);
2483 val64 &= ~(ADAPTER_CNTL_EN);
2484 writeq(val64, &bar0->adapter_control);
2488 * fill_rx_buffers - Allocates the Rx side skbs
2489 * @ring_info: per ring structure
2490 * @from_card_up: If this is true, we will map the buffer to get
2491 * the dma address for buf0 and buf1 to give it to the card.
2492 * Else we will sync the already mapped buffer to give it to the card.
2494 * The function allocates Rx side skbs and puts the physical
2495 * address of these buffers into the RxD buffer pointers, so that the NIC
2496 * can DMA the received frame into these locations.
2497 * The NIC supports 3 receive modes, viz
2499 * 2. three buffer and
2500 * 3. Five buffer modes.
2501 * Each mode defines how many fragments the received frame will be split
2502 * up into by the NIC. The frame is split into L3 header, L4 Header,
2503 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2504 * is split into 3 fragments. As of now only single buffer mode is
2507 * SUCCESS on success or an appropriate -ve value on failure.
2509 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2512 struct sk_buff *skb;
2514 int off, size, block_no, block_no1;
2519 struct RxD_t *first_rxdp = NULL;
2520 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2524 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2526 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2528 block_no1 = ring->rx_curr_get_info.block_index;
2529 while (alloc_tab < alloc_cnt) {
2530 block_no = ring->rx_curr_put_info.block_index;
2532 off = ring->rx_curr_put_info.offset;
2534 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2536 rxd_index = off + 1;
2538 rxd_index += (block_no * ring->rxd_count);
2540 if ((block_no == block_no1) &&
2541 (off == ring->rx_curr_get_info.offset) &&
2542 (rxdp->Host_Control)) {
2543 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2547 if (off && (off == ring->rxd_count)) {
2548 ring->rx_curr_put_info.block_index++;
2549 if (ring->rx_curr_put_info.block_index ==
2551 ring->rx_curr_put_info.block_index = 0;
2552 block_no = ring->rx_curr_put_info.block_index;
2554 ring->rx_curr_put_info.offset = off;
2555 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2556 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2557 ring->dev->name, rxdp);
2561 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2562 ((ring->rxd_mode == RXD_MODE_3B) &&
2563 (rxdp->Control_2 & s2BIT(0)))) {
2564 ring->rx_curr_put_info.offset = off;
2567 /* calculate size of skb based on ring mode */
2569 HEADER_ETHERNET_II_802_3_SIZE +
2570 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2571 if (ring->rxd_mode == RXD_MODE_1)
2572 size += NET_IP_ALIGN;
2574 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2577 skb = dev_alloc_skb(size);
2579 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2583 first_rxdp->Control_1 |= RXD_OWN_XENA;
2585 swstats->mem_alloc_fail_cnt++;
2589 swstats->mem_allocated += skb->truesize;
2591 if (ring->rxd_mode == RXD_MODE_1) {
2592 /* 1 buffer mode - normal operation mode */
2593 rxdp1 = (struct RxD1 *)rxdp;
2594 memset(rxdp, 0, sizeof(struct RxD1));
2595 skb_reserve(skb, NET_IP_ALIGN);
2596 rxdp1->Buffer0_ptr =
2597 pci_map_single(ring->pdev, skb->data,
2598 size - NET_IP_ALIGN,
2599 PCI_DMA_FROMDEVICE);
2600 if (pci_dma_mapping_error(nic->pdev,
2601 rxdp1->Buffer0_ptr))
2602 goto pci_map_failed;
2605 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2606 rxdp->Host_Control = (unsigned long)skb;
2607 } else if (ring->rxd_mode == RXD_MODE_3B) {
2610 * 2 buffer mode provides 128
2611 * byte aligned receive buffers.
2614 rxdp3 = (struct RxD3 *)rxdp;
2615 /* save buffer pointers to avoid frequent dma mapping */
2616 Buffer0_ptr = rxdp3->Buffer0_ptr;
2617 Buffer1_ptr = rxdp3->Buffer1_ptr;
2618 memset(rxdp, 0, sizeof(struct RxD3));
2619 /* restore the buffer pointers for dma sync*/
2620 rxdp3->Buffer0_ptr = Buffer0_ptr;
2621 rxdp3->Buffer1_ptr = Buffer1_ptr;
2623 ba = &ring->ba[block_no][off];
2624 skb_reserve(skb, BUF0_LEN);
2625 tmp = (u64)(unsigned long)skb->data;
2628 skb->data = (void *) (unsigned long)tmp;
2629 skb_reset_tail_pointer(skb);
2632 rxdp3->Buffer0_ptr =
2633 pci_map_single(ring->pdev, ba->ba_0,
2635 PCI_DMA_FROMDEVICE);
2636 if (pci_dma_mapping_error(nic->pdev,
2637 rxdp3->Buffer0_ptr))
2638 goto pci_map_failed;
2640 pci_dma_sync_single_for_device(ring->pdev,
2641 (dma_addr_t)rxdp3->Buffer0_ptr,
2643 PCI_DMA_FROMDEVICE);
2645 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2646 if (ring->rxd_mode == RXD_MODE_3B) {
2647 /* Two buffer mode */
2650 * Buffer2 will have L3/L4 header plus
2653 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2656 PCI_DMA_FROMDEVICE);
2658 if (pci_dma_mapping_error(nic->pdev,
2659 rxdp3->Buffer2_ptr))
2660 goto pci_map_failed;
2663 rxdp3->Buffer1_ptr =
2664 pci_map_single(ring->pdev,
2667 PCI_DMA_FROMDEVICE);
2669 if (pci_dma_mapping_error(nic->pdev,
2670 rxdp3->Buffer1_ptr)) {
2671 pci_unmap_single(ring->pdev,
2672 (dma_addr_t)(unsigned long)
2675 PCI_DMA_FROMDEVICE);
2676 goto pci_map_failed;
2679 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2683 rxdp->Control_2 |= s2BIT(0);
2684 rxdp->Host_Control = (unsigned long) (skb);
2686 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687 rxdp->Control_1 |= RXD_OWN_XENA;
2689 if (off == (ring->rxd_count + 1))
2691 ring->rx_curr_put_info.offset = off;
2693 rxdp->Control_2 |= SET_RXD_MARKER;
2694 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2697 first_rxdp->Control_1 |= RXD_OWN_XENA;
2701 ring->rx_bufs_left += 1;
2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2712 first_rxdp->Control_1 |= RXD_OWN_XENA;
2718 swstats->pci_map_fail_cnt++;
2719 swstats->mem_freed += skb->truesize;
2720 dev_kfree_skb_irq(skb);
2724 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2726 struct net_device *dev = sp->dev;
2728 struct sk_buff *skb;
2733 struct mac_info *mac_control = &sp->mac_control;
2734 struct stat_block *stats = mac_control->stats_info;
2735 struct swStat *swstats = &stats->sw_stat;
2737 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2738 rxdp = mac_control->rings[ring_no].
2739 rx_blocks[blk].rxds[j].virt_addr;
2740 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2743 if (sp->rxd_mode == RXD_MODE_1) {
2744 rxdp1 = (struct RxD1 *)rxdp;
2745 pci_unmap_single(sp->pdev,
2746 (dma_addr_t)rxdp1->Buffer0_ptr,
2748 HEADER_ETHERNET_II_802_3_SIZE +
2749 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2750 PCI_DMA_FROMDEVICE);
2751 memset(rxdp, 0, sizeof(struct RxD1));
2752 } else if (sp->rxd_mode == RXD_MODE_3B) {
2753 rxdp3 = (struct RxD3 *)rxdp;
2754 ba = &mac_control->rings[ring_no].ba[blk][j];
2755 pci_unmap_single(sp->pdev,
2756 (dma_addr_t)rxdp3->Buffer0_ptr,
2758 PCI_DMA_FROMDEVICE);
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer1_ptr,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer2_ptr,
2766 PCI_DMA_FROMDEVICE);
2767 memset(rxdp, 0, sizeof(struct RxD3));
2769 swstats->mem_freed += skb->truesize;
2771 mac_control->rings[ring_no].rx_bufs_left -= 1;
2776 * free_rx_buffers - Frees all Rx buffers
2777 * @sp: device private variable.
2779 * This function will free all Rx buffers allocated by host.
2784 static void free_rx_buffers(struct s2io_nic *sp)
2786 struct net_device *dev = sp->dev;
2787 int i, blk = 0, buf_cnt = 0;
2788 struct config_param *config = &sp->config;
2789 struct mac_info *mac_control = &sp->mac_control;
2791 for (i = 0; i < config->rx_ring_num; i++) {
2792 struct ring_info *ring = &mac_control->rings[i];
2794 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2795 free_rxd_blk(sp, i, blk);
2797 ring->rx_curr_put_info.block_index = 0;
2798 ring->rx_curr_get_info.block_index = 0;
2799 ring->rx_curr_put_info.offset = 0;
2800 ring->rx_curr_get_info.offset = 0;
2801 ring->rx_bufs_left = 0;
2802 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2803 dev->name, buf_cnt, i);
2807 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2809 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2810 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2817 * s2io_poll - Rx interrupt handler for NAPI support
2818 * @napi : pointer to the napi structure.
2819 * @budget : The number of packets that were budgeted to be processed
2820 * during one pass through the 'Poll" function.
2822 * Comes into picture only if NAPI support has been incorporated. It does
2823 * the same thing that rx_intr_handler does, but not in a interrupt context
2824 * also It will process only a given number of packets.
2826 * 0 on success and 1 if there are No Rx packets to be processed.
2829 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2831 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2832 struct net_device *dev = ring->dev;
2833 int pkts_processed = 0;
2834 u8 __iomem *addr = NULL;
2836 struct s2io_nic *nic = netdev_priv(dev);
2837 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2838 int budget_org = budget;
2840 if (unlikely(!is_s2io_card_up(nic)))
2843 pkts_processed = rx_intr_handler(ring, budget);
2844 s2io_chk_rx_buffers(nic, ring);
2846 if (pkts_processed < budget_org) {
2847 napi_complete(napi);
2848 /*Re Enable MSI-Rx Vector*/
2849 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2850 addr += 7 - ring->ring_no;
2851 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2855 return pkts_processed;
2858 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2860 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2861 int pkts_processed = 0;
2862 int ring_pkts_processed, i;
2863 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2864 int budget_org = budget;
2865 struct config_param *config = &nic->config;
2866 struct mac_info *mac_control = &nic->mac_control;
2868 if (unlikely(!is_s2io_card_up(nic)))
2871 for (i = 0; i < config->rx_ring_num; i++) {
2872 struct ring_info *ring = &mac_control->rings[i];
2873 ring_pkts_processed = rx_intr_handler(ring, budget);
2874 s2io_chk_rx_buffers(nic, ring);
2875 pkts_processed += ring_pkts_processed;
2876 budget -= ring_pkts_processed;
2880 if (pkts_processed < budget_org) {
2881 napi_complete(napi);
2882 /* Re enable the Rx interrupts for the ring */
2883 writeq(0, &bar0->rx_traffic_mask);
2884 readl(&bar0->rx_traffic_mask);
2886 return pkts_processed;
2889 #ifdef CONFIG_NET_POLL_CONTROLLER
2891 * s2io_netpoll - netpoll event handler entry point
2892 * @dev : pointer to the device structure.
2894 * This function will be called by upper layer to check for events on the
2895 * interface in situations where interrupts are disabled. It is used for
2896 * specific in-kernel networking tasks, such as remote consoles and kernel
2897 * debugging over the network (example netdump in RedHat).
2899 static void s2io_netpoll(struct net_device *dev)
2901 struct s2io_nic *nic = netdev_priv(dev);
2902 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2903 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2905 struct config_param *config = &nic->config;
2906 struct mac_info *mac_control = &nic->mac_control;
2908 if (pci_channel_offline(nic->pdev))
2911 disable_irq(dev->irq);
2913 writeq(val64, &bar0->rx_traffic_int);
2914 writeq(val64, &bar0->tx_traffic_int);
2916 /* we need to free up the transmitted skbufs or else netpoll will
2917 * run out of skbs and will fail and eventually netpoll application such
2918 * as netdump will fail.
2920 for (i = 0; i < config->tx_fifo_num; i++)
2921 tx_intr_handler(&mac_control->fifos[i]);
2923 /* check for received packet and indicate up to network */
2924 for (i = 0; i < config->rx_ring_num; i++) {
2925 struct ring_info *ring = &mac_control->rings[i];
2927 rx_intr_handler(ring, 0);
2930 for (i = 0; i < config->rx_ring_num; i++) {
2931 struct ring_info *ring = &mac_control->rings[i];
2933 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2935 "%s: Out of memory in Rx Netpoll!!\n",
2940 enable_irq(dev->irq);
2945 * rx_intr_handler - Rx interrupt handler
2946 * @ring_info: per ring structure.
2947 * @budget: budget for napi processing.
2949 * If the interrupt is because of a received frame or if the
2950 * receive ring contains fresh as yet un-processed frames,this function is
2951 * called. It picks out the RxD at which place the last Rx processing had
2952 * stopped and sends the skb to the OSM's Rx handler and then increments
2955 * No. of napi packets processed.
2957 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2959 int get_block, put_block;
2960 struct rx_curr_get_info get_info, put_info;
2962 struct sk_buff *skb;
2963 int pkt_cnt = 0, napi_pkts = 0;
2968 get_info = ring_data->rx_curr_get_info;
2969 get_block = get_info.block_index;
2970 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2971 put_block = put_info.block_index;
2972 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2974 while (RXD_IS_UP2DT(rxdp)) {
2976 * If your are next to put index then it's
2977 * FIFO full condition
2979 if ((get_block == put_block) &&
2980 (get_info.offset + 1) == put_info.offset) {
2981 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2982 ring_data->dev->name);
2985 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2987 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2988 ring_data->dev->name);
2991 if (ring_data->rxd_mode == RXD_MODE_1) {
2992 rxdp1 = (struct RxD1 *)rxdp;
2993 pci_unmap_single(ring_data->pdev, (dma_addr_t)
2996 HEADER_ETHERNET_II_802_3_SIZE +
2999 PCI_DMA_FROMDEVICE);
3000 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3001 rxdp3 = (struct RxD3 *)rxdp;
3002 pci_dma_sync_single_for_cpu(ring_data->pdev,
3003 (dma_addr_t)rxdp3->Buffer0_ptr,
3005 PCI_DMA_FROMDEVICE);
3006 pci_unmap_single(ring_data->pdev,
3007 (dma_addr_t)rxdp3->Buffer2_ptr,
3009 PCI_DMA_FROMDEVICE);
3011 prefetch(skb->data);
3012 rx_osm_handler(ring_data, rxdp);
3014 ring_data->rx_curr_get_info.offset = get_info.offset;
3015 rxdp = ring_data->rx_blocks[get_block].
3016 rxds[get_info.offset].virt_addr;
3017 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3018 get_info.offset = 0;
3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3021 if (get_block == ring_data->block_count)
3023 ring_data->rx_curr_get_info.block_index = get_block;
3024 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3027 if (ring_data->nic->config.napi) {
3034 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3037 if (ring_data->lro) {
3038 /* Clear all LRO sessions before exiting */
3039 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3040 struct lro *lro = &ring_data->lro0_n[i];
3042 update_L3L4_header(ring_data->nic, lro);
3043 queue_rx_frame(lro->parent, lro->vlan_tag);
3044 clear_lro_session(lro);
3052 * tx_intr_handler - Transmit interrupt handler
3053 * @nic : device private variable
3055 * If an interrupt was raised to indicate DMA complete of the
3056 * Tx packet, this function is called. It identifies the last TxD
3057 * whose buffer was freed and frees all skbs whose data have already
3058 * DMA'ed into the NICs internal memory.
3063 static void tx_intr_handler(struct fifo_info *fifo_data)
3065 struct s2io_nic *nic = fifo_data->nic;
3066 struct tx_curr_get_info get_info, put_info;
3067 struct sk_buff *skb = NULL;
3070 unsigned long flags = 0;
3072 struct stat_block *stats = nic->mac_control.stats_info;
3073 struct swStat *swstats = &stats->sw_stat;
3075 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3078 get_info = fifo_data->tx_curr_get_info;
3079 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3080 txdlp = (struct TxD *)
3081 fifo_data->list_info[get_info.offset].list_virt_addr;
3082 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3083 (get_info.offset != put_info.offset) &&
3084 (txdlp->Host_Control)) {
3085 /* Check for TxD errors */
3086 if (txdlp->Control_1 & TXD_T_CODE) {
3087 unsigned long long err;
3088 err = txdlp->Control_1 & TXD_T_CODE;
3090 swstats->parity_err_cnt++;
3093 /* update t_code statistics */
3094 err_mask = err >> 48;
3097 swstats->tx_buf_abort_cnt++;
3101 swstats->tx_desc_abort_cnt++;
3105 swstats->tx_parity_err_cnt++;
3109 swstats->tx_link_loss_cnt++;
3113 swstats->tx_list_proc_err_cnt++;
3118 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3120 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3121 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3127 /* Updating the statistics block */
3128 swstats->mem_freed += skb->truesize;
3129 dev_kfree_skb_irq(skb);
3132 if (get_info.offset == get_info.fifo_len + 1)
3133 get_info.offset = 0;
3134 txdlp = (struct TxD *)
3135 fifo_data->list_info[get_info.offset].list_virt_addr;
3136 fifo_data->tx_curr_get_info.offset = get_info.offset;
3139 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3141 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3145 * s2io_mdio_write - Function to write in to MDIO registers
3146 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3147 * @addr : address value
3148 * @value : data value
3149 * @dev : pointer to net_device structure
3151 * This function is used to write values to the MDIO registers
3154 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3155 struct net_device *dev)
3158 struct s2io_nic *sp = netdev_priv(dev);
3159 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3161 /* address transaction */
3162 val64 = MDIO_MMD_INDX_ADDR(addr) |
3163 MDIO_MMD_DEV_ADDR(mmd_type) |
3164 MDIO_MMS_PRT_ADDR(0x0);
3165 writeq(val64, &bar0->mdio_control);
3166 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3167 writeq(val64, &bar0->mdio_control);
3170 /* Data transaction */
3171 val64 = MDIO_MMD_INDX_ADDR(addr) |
3172 MDIO_MMD_DEV_ADDR(mmd_type) |
3173 MDIO_MMS_PRT_ADDR(0x0) |
3174 MDIO_MDIO_DATA(value) |
3175 MDIO_OP(MDIO_OP_WRITE_TRANS);
3176 writeq(val64, &bar0->mdio_control);
3177 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3178 writeq(val64, &bar0->mdio_control);
3181 val64 = MDIO_MMD_INDX_ADDR(addr) |
3182 MDIO_MMD_DEV_ADDR(mmd_type) |
3183 MDIO_MMS_PRT_ADDR(0x0) |
3184 MDIO_OP(MDIO_OP_READ_TRANS);
3185 writeq(val64, &bar0->mdio_control);
3186 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3187 writeq(val64, &bar0->mdio_control);
3192 * s2io_mdio_read - Function to write in to MDIO registers
3193 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3194 * @addr : address value
3195 * @dev : pointer to net_device structure
3197 * This function is used to read values to the MDIO registers
3200 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3204 struct s2io_nic *sp = netdev_priv(dev);
3205 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3207 /* address transaction */
3208 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3209 | MDIO_MMD_DEV_ADDR(mmd_type)
3210 | MDIO_MMS_PRT_ADDR(0x0));
3211 writeq(val64, &bar0->mdio_control);
3212 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3213 writeq(val64, &bar0->mdio_control);
3216 /* Data transaction */
3217 val64 = MDIO_MMD_INDX_ADDR(addr) |
3218 MDIO_MMD_DEV_ADDR(mmd_type) |
3219 MDIO_MMS_PRT_ADDR(0x0) |
3220 MDIO_OP(MDIO_OP_READ_TRANS);
3221 writeq(val64, &bar0->mdio_control);
3222 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3223 writeq(val64, &bar0->mdio_control);
3226 /* Read the value from regs */
3227 rval64 = readq(&bar0->mdio_control);
3228 rval64 = rval64 & 0xFFFF0000;
3229 rval64 = rval64 >> 16;
3234 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3235 * @counter : counter value to be updated
3236 * @flag : flag to indicate the status
3237 * @type : counter type
3239 * This function is to check the status of the xpak counters value
3243 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3249 for (i = 0; i < index; i++)
3253 *counter = *counter + 1;
3254 val64 = *regs_stat & mask;
3255 val64 = val64 >> (index * 0x2);
3261 "Take Xframe NIC out of service.\n");
3263 "Excessive temperatures may result in premature transceiver failure.\n");
3267 "Take Xframe NIC out of service.\n");
3269 "Excessive bias currents may indicate imminent laser diode failure.\n");
3273 "Take Xframe NIC out of service.\n");
3275 "Excessive laser output power may saturate far-end receiver.\n");
3279 "Incorrect XPAK Alarm type\n");
3283 val64 = val64 << (index * 0x2);
3284 *regs_stat = (*regs_stat & (~mask)) | (val64);
3287 *regs_stat = *regs_stat & (~mask);
3292 * s2io_updt_xpak_counter - Function to update the xpak counters
3293 * @dev : pointer to net_device struct
3295 * This function is to upate the status of the xpak counters value
3298 static void s2io_updt_xpak_counter(struct net_device *dev)
3306 struct s2io_nic *sp = netdev_priv(dev);
3307 struct stat_block *stats = sp->mac_control.stats_info;
3308 struct xpakStat *xstats = &stats->xpak_stat;
3310 /* Check the communication with the MDIO slave */
3313 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3314 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3316 "ERR: MDIO slave access failed - Returned %llx\n",
3317 (unsigned long long)val64);
3321 /* Check for the expected value of control reg 1 */
3322 if (val64 != MDIO_CTRL1_SPEED10G) {
3323 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3324 "Returned: %llx- Expected: 0x%x\n",
3325 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3329 /* Loading the DOM register to MDIO register */
3331 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3332 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3334 /* Reading the Alarm flags */
3337 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3339 flag = CHECKBIT(val64, 0x7);
3341 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3342 &xstats->xpak_regs_stat,
3345 if (CHECKBIT(val64, 0x6))
3346 xstats->alarm_transceiver_temp_low++;
3348 flag = CHECKBIT(val64, 0x3);
3350 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3351 &xstats->xpak_regs_stat,
3354 if (CHECKBIT(val64, 0x2))
3355 xstats->alarm_laser_bias_current_low++;
3357 flag = CHECKBIT(val64, 0x1);
3359 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3360 &xstats->xpak_regs_stat,
3363 if (CHECKBIT(val64, 0x0))
3364 xstats->alarm_laser_output_power_low++;
3366 /* Reading the Warning flags */
3369 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3371 if (CHECKBIT(val64, 0x7))
3372 xstats->warn_transceiver_temp_high++;
3374 if (CHECKBIT(val64, 0x6))
3375 xstats->warn_transceiver_temp_low++;
3377 if (CHECKBIT(val64, 0x3))
3378 xstats->warn_laser_bias_current_high++;
3380 if (CHECKBIT(val64, 0x2))
3381 xstats->warn_laser_bias_current_low++;
3383 if (CHECKBIT(val64, 0x1))
3384 xstats->warn_laser_output_power_high++;
3386 if (CHECKBIT(val64, 0x0))
3387 xstats->warn_laser_output_power_low++;
3391 * wait_for_cmd_complete - waits for a command to complete.
3392 * @sp : private member of the device structure, which is a pointer to the
3393 * s2io_nic structure.
3394 * Description: Function that waits for a command to Write into RMAC
3395 * ADDR DATA registers to be completed and returns either success or
3396 * error depending on whether the command was complete or not.
3398 * SUCCESS on success and FAILURE on failure.
3401 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3404 int ret = FAILURE, cnt = 0, delay = 1;
3407 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3411 val64 = readq(addr);
3412 if (bit_state == S2IO_BIT_RESET) {
3413 if (!(val64 & busy_bit)) {
3418 if (val64 & busy_bit) {
3435 * check_pci_device_id - Checks if the device id is supported
3437 * Description: Function to check if the pci device id is supported by driver.
3438 * Return value: Actual device id if supported else PCI_ANY_ID
3440 static u16 check_pci_device_id(u16 id)
3443 case PCI_DEVICE_ID_HERC_WIN:
3444 case PCI_DEVICE_ID_HERC_UNI:
3445 return XFRAME_II_DEVICE;
3446 case PCI_DEVICE_ID_S2IO_UNI:
3447 case PCI_DEVICE_ID_S2IO_WIN:
3448 return XFRAME_I_DEVICE;
3455 * s2io_reset - Resets the card.
3456 * @sp : private member of the device structure.
3457 * Description: Function to Reset the card. This function then also
3458 * restores the previously saved PCI configuration space registers as
3459 * the card reset also resets the configuration space.
3464 static void s2io_reset(struct s2io_nic *sp)
3466 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3471 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3472 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3473 struct stat_block *stats;
3474 struct swStat *swstats;
3476 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3477 __func__, pci_name(sp->pdev));
3479 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3480 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3482 val64 = SW_RESET_ALL;
3483 writeq(val64, &bar0->sw_reset);
3484 if (strstr(sp->product_name, "CX4"))
3487 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3489 /* Restore the PCI state saved during initialization. */
3490 pci_restore_state(sp->pdev);
3491 pci_save_state(sp->pdev);
3492 pci_read_config_word(sp->pdev, 0x2, &val16);
3493 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3498 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3499 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3501 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3505 /* Set swapper to enable I/O register access */
3506 s2io_set_swapper(sp);
3508 /* restore mac_addr entries */
3509 do_s2io_restore_unicast_mc(sp);
3511 /* Restore the MSIX table entries from local variables */
3512 restore_xmsi_data(sp);
3514 /* Clear certain PCI/PCI-X fields after reset */
3515 if (sp->device_type == XFRAME_II_DEVICE) {
3516 /* Clear "detected parity error" bit */
3517 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3519 /* Clearing PCIX Ecc status register */
3520 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3522 /* Clearing PCI_STATUS error reflected here */
3523 writeq(s2BIT(62), &bar0->txpic_int_reg);
3526 /* Reset device statistics maintained by OS */
3527 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3529 stats = sp->mac_control.stats_info;
3530 swstats = &stats->sw_stat;
3532 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3533 up_cnt = swstats->link_up_cnt;
3534 down_cnt = swstats->link_down_cnt;
3535 up_time = swstats->link_up_time;
3536 down_time = swstats->link_down_time;
3537 reset_cnt = swstats->soft_reset_cnt;
3538 mem_alloc_cnt = swstats->mem_allocated;
3539 mem_free_cnt = swstats->mem_freed;
3540 watchdog_cnt = swstats->watchdog_timer_cnt;
3542 memset(stats, 0, sizeof(struct stat_block));
3544 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3545 swstats->link_up_cnt = up_cnt;
3546 swstats->link_down_cnt = down_cnt;
3547 swstats->link_up_time = up_time;
3548 swstats->link_down_time = down_time;
3549 swstats->soft_reset_cnt = reset_cnt;
3550 swstats->mem_allocated = mem_alloc_cnt;
3551 swstats->mem_freed = mem_free_cnt;
3552 swstats->watchdog_timer_cnt = watchdog_cnt;
3554 /* SXE-002: Configure link and activity LED to turn it off */
3555 subid = sp->pdev->subsystem_device;
3556 if (((subid & 0xFF) >= 0x07) &&
3557 (sp->device_type == XFRAME_I_DEVICE)) {
3558 val64 = readq(&bar0->gpio_control);
3559 val64 |= 0x0000800000000000ULL;
3560 writeq(val64, &bar0->gpio_control);
3561 val64 = 0x0411040400000000ULL;
3562 writeq(val64, (void __iomem *)bar0 + 0x2700);
3566 * Clear spurious ECC interrupts that would have occurred on
3567 * XFRAME II cards after reset.
3569 if (sp->device_type == XFRAME_II_DEVICE) {
3570 val64 = readq(&bar0->pcc_err_reg);
3571 writeq(val64, &bar0->pcc_err_reg);
3574 sp->device_enabled_once = false;
3578 * s2io_set_swapper - to set the swapper controle on the card
3579 * @sp : private member of the device structure,
3580 * pointer to the s2io_nic structure.
3581 * Description: Function to set the swapper control on the card
3582 * correctly depending on the 'endianness' of the system.
3584 * SUCCESS on success and FAILURE on failure.
3587 static int s2io_set_swapper(struct s2io_nic *sp)
3589 struct net_device *dev = sp->dev;
3590 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3591 u64 val64, valt, valr;
3594 * Set proper endian settings and verify the same by reading
3595 * the PIF Feed-back register.
3598 val64 = readq(&bar0->pif_rd_swapper_fb);
3599 if (val64 != 0x0123456789ABCDEFULL) {
3601 static const u64 value[] = {
3602 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3603 0x8100008181000081ULL, /* FE=1, SE=0 */
3604 0x4200004242000042ULL, /* FE=0, SE=1 */
3609 writeq(value[i], &bar0->swapper_ctrl);
3610 val64 = readq(&bar0->pif_rd_swapper_fb);
3611 if (val64 == 0x0123456789ABCDEFULL)
3616 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3617 "feedback read %llx\n",
3618 dev->name, (unsigned long long)val64);
3623 valr = readq(&bar0->swapper_ctrl);
3626 valt = 0x0123456789ABCDEFULL;
3627 writeq(valt, &bar0->xmsi_address);
3628 val64 = readq(&bar0->xmsi_address);
3630 if (val64 != valt) {
3632 static const u64 value[] = {
3633 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3634 0x0081810000818100ULL, /* FE=1, SE=0 */
3635 0x0042420000424200ULL, /* FE=0, SE=1 */
3640 writeq((value[i] | valr), &bar0->swapper_ctrl);
3641 writeq(valt, &bar0->xmsi_address);
3642 val64 = readq(&bar0->xmsi_address);
3648 unsigned long long x = val64;
3650 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3654 val64 = readq(&bar0->swapper_ctrl);
3655 val64 &= 0xFFFF000000000000ULL;
3659 * The device by default set to a big endian format, so a
3660 * big endian driver need not set anything.
3662 val64 |= (SWAPPER_CTRL_TXP_FE |
3663 SWAPPER_CTRL_TXP_SE |
3664 SWAPPER_CTRL_TXD_R_FE |
3665 SWAPPER_CTRL_TXD_W_FE |
3666 SWAPPER_CTRL_TXF_R_FE |
3667 SWAPPER_CTRL_RXD_R_FE |
3668 SWAPPER_CTRL_RXD_W_FE |
3669 SWAPPER_CTRL_RXF_W_FE |
3670 SWAPPER_CTRL_XMSI_FE |
3671 SWAPPER_CTRL_STATS_FE |
3672 SWAPPER_CTRL_STATS_SE);
3673 if (sp->config.intr_type == INTA)
3674 val64 |= SWAPPER_CTRL_XMSI_SE;
3675 writeq(val64, &bar0->swapper_ctrl);
3678 * Initially we enable all bits to make it accessible by the
3679 * driver, then we selectively enable only those bits that
3682 val64 |= (SWAPPER_CTRL_TXP_FE |
3683 SWAPPER_CTRL_TXP_SE |
3684 SWAPPER_CTRL_TXD_R_FE |
3685 SWAPPER_CTRL_TXD_R_SE |
3686 SWAPPER_CTRL_TXD_W_FE |
3687 SWAPPER_CTRL_TXD_W_SE |
3688 SWAPPER_CTRL_TXF_R_FE |
3689 SWAPPER_CTRL_RXD_R_FE |
3690 SWAPPER_CTRL_RXD_R_SE |
3691 SWAPPER_CTRL_RXD_W_FE |
3692 SWAPPER_CTRL_RXD_W_SE |
3693 SWAPPER_CTRL_RXF_W_FE |
3694 SWAPPER_CTRL_XMSI_FE |
3695 SWAPPER_CTRL_STATS_FE |
3696 SWAPPER_CTRL_STATS_SE);
3697 if (sp->config.intr_type == INTA)
3698 val64 |= SWAPPER_CTRL_XMSI_SE;
3699 writeq(val64, &bar0->swapper_ctrl);
3701 val64 = readq(&bar0->swapper_ctrl);
3704 * Verifying if endian settings are accurate by reading a
3705 * feedback register.
3707 val64 = readq(&bar0->pif_rd_swapper_fb);
3708 if (val64 != 0x0123456789ABCDEFULL) {
3709 /* Endian settings are incorrect, calls for another dekko. */
3711 "%s: Endian settings are wrong, feedback read %llx\n",
3712 dev->name, (unsigned long long)val64);
3719 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3721 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3723 int ret = 0, cnt = 0;
3726 val64 = readq(&bar0->xmsi_access);
3727 if (!(val64 & s2BIT(15)))
3733 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3740 static void restore_xmsi_data(struct s2io_nic *nic)
3742 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3746 if (nic->device_type == XFRAME_I_DEVICE)
3749 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3750 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3751 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3752 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3753 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3754 writeq(val64, &bar0->xmsi_access);
3755 if (wait_for_msix_trans(nic, msix_index)) {
3756 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3757 __func__, msix_index);
3763 static void store_xmsi_data(struct s2io_nic *nic)
3765 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3766 u64 val64, addr, data;
3769 if (nic->device_type == XFRAME_I_DEVICE)
3772 /* Store and display */
3773 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3774 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3775 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3776 writeq(val64, &bar0->xmsi_access);
3777 if (wait_for_msix_trans(nic, msix_index)) {
3778 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3779 __func__, msix_index);
3782 addr = readq(&bar0->xmsi_address);
3783 data = readq(&bar0->xmsi_data);
3785 nic->msix_info[i].addr = addr;
3786 nic->msix_info[i].data = data;
3791 static int s2io_enable_msi_x(struct s2io_nic *nic)
3793 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3795 u16 msi_control; /* Temp variable */
3796 int ret, i, j, msix_indx = 1;
3798 struct stat_block *stats = nic->mac_control.stats_info;
3799 struct swStat *swstats = &stats->sw_stat;
3801 size = nic->num_entries * sizeof(struct msix_entry);
3802 nic->entries = kzalloc(size, GFP_KERNEL);
3803 if (!nic->entries) {
3804 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3806 swstats->mem_alloc_fail_cnt++;
3809 swstats->mem_allocated += size;
3811 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3812 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3813 if (!nic->s2io_entries) {
3814 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3816 swstats->mem_alloc_fail_cnt++;
3817 kfree(nic->entries);
3819 += (nic->num_entries * sizeof(struct msix_entry));
3822 swstats->mem_allocated += size;
3824 nic->entries[0].entry = 0;
3825 nic->s2io_entries[0].entry = 0;
3826 nic->s2io_entries[0].in_use = MSIX_FLG;
3827 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3828 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3830 for (i = 1; i < nic->num_entries; i++) {
3831 nic->entries[i].entry = ((i - 1) * 8) + 1;
3832 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3833 nic->s2io_entries[i].arg = NULL;
3834 nic->s2io_entries[i].in_use = 0;
3837 rx_mat = readq(&bar0->rx_mat);
3838 for (j = 0; j < nic->config.rx_ring_num; j++) {
3839 rx_mat |= RX_MAT_SET(j, msix_indx);
3840 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3841 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3842 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3845 writeq(rx_mat, &bar0->rx_mat);
3846 readq(&bar0->rx_mat);
3848 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3849 /* We fail init if error or we get less vectors than min required */
3851 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3852 kfree(nic->entries);
3853 swstats->mem_freed += nic->num_entries *
3854 sizeof(struct msix_entry);
3855 kfree(nic->s2io_entries);
3856 swstats->mem_freed += nic->num_entries *
3857 sizeof(struct s2io_msix_entry);
3858 nic->entries = NULL;
3859 nic->s2io_entries = NULL;
3864 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3865 * in the herc NIC. (Temp change, needs to be removed later)
3867 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3868 msi_control |= 0x1; /* Enable MSI */
3869 pci_write_config_word(nic->pdev, 0x42, msi_control);
3874 /* Handle software interrupt used during MSI(X) test */
3875 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3877 struct s2io_nic *sp = dev_id;
3879 sp->msi_detected = 1;
3880 wake_up(&sp->msi_wait);
3885 /* Test interrupt path by forcing a a software IRQ */
3886 static int s2io_test_msi(struct s2io_nic *sp)
3888 struct pci_dev *pdev = sp->pdev;
3889 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3893 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3896 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3897 sp->dev->name, pci_name(pdev), pdev->irq);
3901 init_waitqueue_head(&sp->msi_wait);
3902 sp->msi_detected = 0;
3904 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3905 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3906 val64 |= SCHED_INT_CTRL_TIMER_EN;
3907 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3908 writeq(val64, &bar0->scheduled_int_ctrl);
3910 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3912 if (!sp->msi_detected) {
3913 /* MSI(X) test failed, go back to INTx mode */
3914 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3915 "using MSI(X) during test\n",
3916 sp->dev->name, pci_name(pdev));
3921 free_irq(sp->entries[1].vector, sp);
3923 writeq(saved64, &bar0->scheduled_int_ctrl);
3928 static void remove_msix_isr(struct s2io_nic *sp)
3933 for (i = 0; i < sp->num_entries; i++) {
3934 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3935 int vector = sp->entries[i].vector;
3936 void *arg = sp->s2io_entries[i].arg;
3937 free_irq(vector, arg);
3942 kfree(sp->s2io_entries);
3944 sp->s2io_entries = NULL;
3946 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3947 msi_control &= 0xFFFE; /* Disable MSI */
3948 pci_write_config_word(sp->pdev, 0x42, msi_control);
3950 pci_disable_msix(sp->pdev);
3953 static void remove_inta_isr(struct s2io_nic *sp)
3955 struct net_device *dev = sp->dev;
3957 free_irq(sp->pdev->irq, dev);
3960 /* ********************************************************* *
3961 * Functions defined below concern the OS part of the driver *
3962 * ********************************************************* */
3965 * s2io_open - open entry point of the driver
3966 * @dev : pointer to the device structure.
3968 * This function is the open entry point of the driver. It mainly calls a
3969 * function to allocate Rx buffers and inserts them into the buffer
3970 * descriptors and then enables the Rx part of the NIC.
3972 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3976 static int s2io_open(struct net_device *dev)
3978 struct s2io_nic *sp = netdev_priv(dev);
3979 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3983 * Make sure you have link off by default every time
3984 * Nic is initialized
3986 netif_carrier_off(dev);
3987 sp->last_link_state = 0;
3989 /* Initialize H/W and enable interrupts */
3990 err = s2io_card_up(sp);
3992 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3994 goto hw_init_failed;
3997 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3998 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4001 goto hw_init_failed;
4003 s2io_start_all_tx_queue(sp);
4007 if (sp->config.intr_type == MSI_X) {
4010 swstats->mem_freed += sp->num_entries *
4011 sizeof(struct msix_entry);
4013 if (sp->s2io_entries) {
4014 kfree(sp->s2io_entries);
4015 swstats->mem_freed += sp->num_entries *
4016 sizeof(struct s2io_msix_entry);
4023 * s2io_close -close entry point of the driver
4024 * @dev : device pointer.
4026 * This is the stop entry point of the driver. It needs to undo exactly
4027 * whatever was done by the open entry point,thus it's usually referred to
4028 * as the close function.Among other things this function mainly stops the
4029 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4031 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4035 static int s2io_close(struct net_device *dev)
4037 struct s2io_nic *sp = netdev_priv(dev);
4038 struct config_param *config = &sp->config;
4042 /* Return if the device is already closed *
4043 * Can happen when s2io_card_up failed in change_mtu *
4045 if (!is_s2io_card_up(sp))
4048 s2io_stop_all_tx_queue(sp);
4049 /* delete all populated mac entries */
4050 for (offset = 1; offset < config->max_mc_addr; offset++) {
4051 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4052 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4053 do_s2io_delete_unicast_mc(sp, tmp64);
4062 * s2io_xmit - Tx entry point of te driver
4063 * @skb : the socket buffer containing the Tx data.
4064 * @dev : device pointer.
4066 * This function is the Tx entry point of the driver. S2IO NIC supports
4067 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4068 * NOTE: when device can't queue the pkt,just the trans_start variable will
4071 * 0 on success & 1 on failure.
4074 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4076 struct s2io_nic *sp = netdev_priv(dev);
4077 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4080 struct TxFIFO_element __iomem *tx_fifo;
4081 unsigned long flags = 0;
4083 struct fifo_info *fifo = NULL;
4084 int do_spin_lock = 1;
4086 int enable_per_list_interrupt = 0;
4087 struct config_param *config = &sp->config;
4088 struct mac_info *mac_control = &sp->mac_control;
4089 struct stat_block *stats = mac_control->stats_info;
4090 struct swStat *swstats = &stats->sw_stat;
4092 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4094 if (unlikely(skb->len <= 0)) {
4095 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4096 dev_kfree_skb_any(skb);
4097 return NETDEV_TX_OK;
4100 if (!is_s2io_card_up(sp)) {
4101 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4104 return NETDEV_TX_OK;
4108 if (vlan_tx_tag_present(skb))
4109 vlan_tag = vlan_tx_tag_get(skb);
4110 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4111 if (skb->protocol == htons(ETH_P_IP)) {
4116 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4117 th = (struct tcphdr *)(((unsigned char *)ip) +
4120 if (ip->protocol == IPPROTO_TCP) {
4121 queue_len = sp->total_tcp_fifos;
4122 queue = (ntohs(th->source) +
4124 sp->fifo_selector[queue_len - 1];
4125 if (queue >= queue_len)
4126 queue = queue_len - 1;
4127 } else if (ip->protocol == IPPROTO_UDP) {
4128 queue_len = sp->total_udp_fifos;
4129 queue = (ntohs(th->source) +
4131 sp->fifo_selector[queue_len - 1];
4132 if (queue >= queue_len)
4133 queue = queue_len - 1;
4134 queue += sp->udp_fifo_idx;
4135 if (skb->len > 1024)
4136 enable_per_list_interrupt = 1;
4141 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4142 /* get fifo number based on skb->priority value */
4143 queue = config->fifo_mapping
4144 [skb->priority & (MAX_TX_FIFOS - 1)];
4145 fifo = &mac_control->fifos[queue];
4148 spin_lock_irqsave(&fifo->tx_lock, flags);
4150 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4151 return NETDEV_TX_LOCKED;
4154 if (sp->config.multiq) {
4155 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4156 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4157 return NETDEV_TX_BUSY;
4159 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4160 if (netif_queue_stopped(dev)) {
4161 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4162 return NETDEV_TX_BUSY;
4166 put_off = (u16)fifo->tx_curr_put_info.offset;
4167 get_off = (u16)fifo->tx_curr_get_info.offset;
4168 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4170 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4171 /* Avoid "put" pointer going beyond "get" pointer */
4172 if (txdp->Host_Control ||
4173 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4174 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4175 s2io_stop_tx_queue(sp, fifo->fifo_no);
4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178 return NETDEV_TX_OK;
4181 offload_type = s2io_offload_type(skb);
4182 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4183 txdp->Control_1 |= TXD_TCP_LSO_EN;
4184 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4186 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4187 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4191 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4192 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4193 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4194 if (enable_per_list_interrupt)
4195 if (put_off & (queue_len >> 5))
4196 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4198 txdp->Control_2 |= TXD_VLAN_ENABLE;
4199 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4202 frg_len = skb_headlen(skb);
4203 if (offload_type == SKB_GSO_UDP) {
4206 ufo_size = s2io_udp_mss(skb);
4208 txdp->Control_1 |= TXD_UFO_EN;
4209 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4210 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4212 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4213 fifo->ufo_in_band_v[put_off] =
4214 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4216 fifo->ufo_in_band_v[put_off] =
4217 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4219 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4220 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4221 fifo->ufo_in_band_v,
4224 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4225 goto pci_map_failed;
4229 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4230 frg_len, PCI_DMA_TODEVICE);
4231 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4232 goto pci_map_failed;
4234 txdp->Host_Control = (unsigned long)skb;
4235 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4236 if (offload_type == SKB_GSO_UDP)
4237 txdp->Control_1 |= TXD_UFO_EN;
4239 frg_cnt = skb_shinfo(skb)->nr_frags;
4240 /* For fragmented SKB. */
4241 for (i = 0; i < frg_cnt; i++) {
4242 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4243 /* A '0' length fragment will be ignored */
4247 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4251 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4252 if (offload_type == SKB_GSO_UDP)
4253 txdp->Control_1 |= TXD_UFO_EN;
4255 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4257 if (offload_type == SKB_GSO_UDP)
4258 frg_cnt++; /* as Txd0 was used for inband header */
4260 tx_fifo = mac_control->tx_FIFO_start[queue];
4261 val64 = fifo->list_info[put_off].list_phy_addr;
4262 writeq(val64, &tx_fifo->TxDL_Pointer);
4264 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4267 val64 |= TX_FIFO_SPECIAL_FUNC;
4269 writeq(val64, &tx_fifo->List_Control);
4274 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4276 fifo->tx_curr_put_info.offset = put_off;
4278 /* Avoid "put" pointer going beyond "get" pointer */
4279 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4280 swstats->fifo_full_cnt++;
4282 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4284 s2io_stop_tx_queue(sp, fifo->fifo_no);
4286 swstats->mem_allocated += skb->truesize;
4287 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4289 if (sp->config.intr_type == MSI_X)
4290 tx_intr_handler(fifo);
4292 return NETDEV_TX_OK;
4295 swstats->pci_map_fail_cnt++;
4296 s2io_stop_tx_queue(sp, fifo->fifo_no);
4297 swstats->mem_freed += skb->truesize;
4299 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4300 return NETDEV_TX_OK;
4304 s2io_alarm_handle(unsigned long data)
4306 struct s2io_nic *sp = (struct s2io_nic *)data;
4307 struct net_device *dev = sp->dev;
4309 s2io_handle_errors(dev);
4310 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4313 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4315 struct ring_info *ring = (struct ring_info *)dev_id;
4316 struct s2io_nic *sp = ring->nic;
4317 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4319 if (unlikely(!is_s2io_card_up(sp)))
4322 if (sp->config.napi) {
4323 u8 __iomem *addr = NULL;
4326 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4327 addr += (7 - ring->ring_no);
4328 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4331 napi_schedule(&ring->napi);
4333 rx_intr_handler(ring, 0);
4334 s2io_chk_rx_buffers(sp, ring);
4340 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4343 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4344 struct s2io_nic *sp = fifos->nic;
4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4346 struct config_param *config = &sp->config;
4349 if (unlikely(!is_s2io_card_up(sp)))
4352 reason = readq(&bar0->general_int_status);
4353 if (unlikely(reason == S2IO_MINUS_ONE))
4354 /* Nothing much can be done. Get out */
4357 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4358 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4360 if (reason & GEN_INTR_TXPIC)
4361 s2io_txpic_intr_handle(sp);
4363 if (reason & GEN_INTR_TXTRAFFIC)
4364 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4366 for (i = 0; i < config->tx_fifo_num; i++)
4367 tx_intr_handler(&fifos[i]);
4369 writeq(sp->general_int_mask, &bar0->general_int_mask);
4370 readl(&bar0->general_int_status);
4373 /* The interrupt was not raised by us */
4377 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4379 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4382 val64 = readq(&bar0->pic_int_status);
4383 if (val64 & PIC_INT_GPIO) {
4384 val64 = readq(&bar0->gpio_int_reg);
4385 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4386 (val64 & GPIO_INT_REG_LINK_UP)) {
4388 * This is unstable state so clear both up/down
4389 * interrupt and adapter to re-evaluate the link state.
4391 val64 |= GPIO_INT_REG_LINK_DOWN;
4392 val64 |= GPIO_INT_REG_LINK_UP;
4393 writeq(val64, &bar0->gpio_int_reg);
4394 val64 = readq(&bar0->gpio_int_mask);
4395 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4396 GPIO_INT_MASK_LINK_DOWN);
4397 writeq(val64, &bar0->gpio_int_mask);
4398 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4399 val64 = readq(&bar0->adapter_status);
4400 /* Enable Adapter */
4401 val64 = readq(&bar0->adapter_control);
4402 val64 |= ADAPTER_CNTL_EN;
4403 writeq(val64, &bar0->adapter_control);
4404 val64 |= ADAPTER_LED_ON;
4405 writeq(val64, &bar0->adapter_control);
4406 if (!sp->device_enabled_once)
4407 sp->device_enabled_once = 1;
4409 s2io_link(sp, LINK_UP);
4411 * unmask link down interrupt and mask link-up
4414 val64 = readq(&bar0->gpio_int_mask);
4415 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4416 val64 |= GPIO_INT_MASK_LINK_UP;
4417 writeq(val64, &bar0->gpio_int_mask);
4419 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4420 val64 = readq(&bar0->adapter_status);
4421 s2io_link(sp, LINK_DOWN);
4422 /* Link is down so unmaks link up interrupt */
4423 val64 = readq(&bar0->gpio_int_mask);
4424 val64 &= ~GPIO_INT_MASK_LINK_UP;
4425 val64 |= GPIO_INT_MASK_LINK_DOWN;
4426 writeq(val64, &bar0->gpio_int_mask);
4429 val64 = readq(&bar0->adapter_control);
4430 val64 = val64 & (~ADAPTER_LED_ON);
4431 writeq(val64, &bar0->adapter_control);
4434 val64 = readq(&bar0->gpio_int_mask);
4438 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4439 * @value: alarm bits
4440 * @addr: address value
4441 * @cnt: counter variable
4442 * Description: Check for alarm and increment the counter
4444 * 1 - if alarm bit set
4445 * 0 - if alarm bit is not set
4447 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4448 unsigned long long *cnt)
4451 val64 = readq(addr);
4452 if (val64 & value) {
4453 writeq(val64, addr);
4462 * s2io_handle_errors - Xframe error indication handler
4463 * @nic: device private variable
4464 * Description: Handle alarms such as loss of link, single or
4465 * double ECC errors, critical and serious errors.
4469 static void s2io_handle_errors(void *dev_id)
4471 struct net_device *dev = (struct net_device *)dev_id;
4472 struct s2io_nic *sp = netdev_priv(dev);
4473 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4474 u64 temp64 = 0, val64 = 0;
4477 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4478 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4480 if (!is_s2io_card_up(sp))
4483 if (pci_channel_offline(sp->pdev))
4486 memset(&sw_stat->ring_full_cnt, 0,
4487 sizeof(sw_stat->ring_full_cnt));
4489 /* Handling the XPAK counters update */
4490 if (stats->xpak_timer_count < 72000) {
4491 /* waiting for an hour */
4492 stats->xpak_timer_count++;
4494 s2io_updt_xpak_counter(dev);
4495 /* reset the count to zero */
4496 stats->xpak_timer_count = 0;
4499 /* Handling link status change error Intr */
4500 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4501 val64 = readq(&bar0->mac_rmac_err_reg);
4502 writeq(val64, &bar0->mac_rmac_err_reg);
4503 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4504 schedule_work(&sp->set_link_task);
4507 /* In case of a serious error, the device will be Reset. */
4508 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4509 &sw_stat->serious_err_cnt))
4512 /* Check for data parity error */
4513 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4514 &sw_stat->parity_err_cnt))
4517 /* Check for ring full counter */
4518 if (sp->device_type == XFRAME_II_DEVICE) {
4519 val64 = readq(&bar0->ring_bump_counter1);
4520 for (i = 0; i < 4; i++) {
4521 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4522 temp64 >>= 64 - ((i+1)*16);
4523 sw_stat->ring_full_cnt[i] += temp64;
4526 val64 = readq(&bar0->ring_bump_counter2);
4527 for (i = 0; i < 4; i++) {
4528 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4529 temp64 >>= 64 - ((i+1)*16);
4530 sw_stat->ring_full_cnt[i+4] += temp64;
4534 val64 = readq(&bar0->txdma_int_status);
4535 /*check for pfc_err*/
4536 if (val64 & TXDMA_PFC_INT) {
4537 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4538 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4541 &sw_stat->pfc_err_cnt))
4543 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4545 &sw_stat->pfc_err_cnt);
4548 /*check for tda_err*/
4549 if (val64 & TXDMA_TDA_INT) {
4550 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4554 &sw_stat->tda_err_cnt))
4556 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4558 &sw_stat->tda_err_cnt);
4560 /*check for pcc_err*/
4561 if (val64 & TXDMA_PCC_INT) {
4562 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4563 PCC_N_SERR | PCC_6_COF_OV_ERR |
4564 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4565 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4568 &sw_stat->pcc_err_cnt))
4570 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4572 &sw_stat->pcc_err_cnt);
4575 /*check for tti_err*/
4576 if (val64 & TXDMA_TTI_INT) {
4577 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4579 &sw_stat->tti_err_cnt))
4581 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4583 &sw_stat->tti_err_cnt);
4586 /*check for lso_err*/
4587 if (val64 & TXDMA_LSO_INT) {
4588 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4589 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4591 &sw_stat->lso_err_cnt))
4593 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4595 &sw_stat->lso_err_cnt);
4598 /*check for tpa_err*/
4599 if (val64 & TXDMA_TPA_INT) {
4600 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4602 &sw_stat->tpa_err_cnt))
4604 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4606 &sw_stat->tpa_err_cnt);
4609 /*check for sm_err*/
4610 if (val64 & TXDMA_SM_INT) {
4611 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4613 &sw_stat->sm_err_cnt))
4617 val64 = readq(&bar0->mac_int_status);
4618 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4619 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4620 &bar0->mac_tmac_err_reg,
4621 &sw_stat->mac_tmac_err_cnt))
4623 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4624 TMAC_DESC_ECC_SG_ERR |
4625 TMAC_DESC_ECC_DB_ERR,
4626 &bar0->mac_tmac_err_reg,
4627 &sw_stat->mac_tmac_err_cnt);
4630 val64 = readq(&bar0->xgxs_int_status);
4631 if (val64 & XGXS_INT_STATUS_TXGXS) {
4632 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt))
4636 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt);
4641 val64 = readq(&bar0->rxdma_int_status);
4642 if (val64 & RXDMA_INT_RC_INT_M) {
4643 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4645 RC_PRCn_SM_ERR_ALARM |
4646 RC_FTC_SM_ERR_ALARM,
4648 &sw_stat->rc_err_cnt))
4650 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4652 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4653 &sw_stat->rc_err_cnt);
4654 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4657 &bar0->prc_pcix_err_reg,
4658 &sw_stat->prc_pcix_err_cnt))
4660 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4663 &bar0->prc_pcix_err_reg,
4664 &sw_stat->prc_pcix_err_cnt);
4667 if (val64 & RXDMA_INT_RPA_INT_M) {
4668 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4670 &sw_stat->rpa_err_cnt))
4672 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4674 &sw_stat->rpa_err_cnt);
4677 if (val64 & RXDMA_INT_RDA_INT_M) {
4678 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4679 RDA_FRM_ECC_DB_N_AERR |
4682 RDA_RXD_ECC_DB_SERR,
4684 &sw_stat->rda_err_cnt))
4686 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4687 RDA_FRM_ECC_SG_ERR |
4691 &sw_stat->rda_err_cnt);
4694 if (val64 & RXDMA_INT_RTI_INT_M) {
4695 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4697 &sw_stat->rti_err_cnt))
4699 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4701 &sw_stat->rti_err_cnt);
4704 val64 = readq(&bar0->mac_int_status);
4705 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4706 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4707 &bar0->mac_rmac_err_reg,
4708 &sw_stat->mac_rmac_err_cnt))
4710 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4711 RMAC_SINGLE_ECC_ERR |
4712 RMAC_DOUBLE_ECC_ERR,
4713 &bar0->mac_rmac_err_reg,
4714 &sw_stat->mac_rmac_err_cnt);
4717 val64 = readq(&bar0->xgxs_int_status);
4718 if (val64 & XGXS_INT_STATUS_RXGXS) {
4719 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4720 &bar0->xgxs_rxgxs_err_reg,
4721 &sw_stat->xgxs_rxgxs_err_cnt))
4725 val64 = readq(&bar0->mc_int_status);
4726 if (val64 & MC_INT_STATUS_MC_INT) {
4727 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4729 &sw_stat->mc_err_cnt))
4732 /* Handling Ecc errors */
4733 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4734 writeq(val64, &bar0->mc_err_reg);
4735 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4736 sw_stat->double_ecc_errs++;
4737 if (sp->device_type != XFRAME_II_DEVICE) {
4739 * Reset XframeI only if critical error
4742 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4743 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4747 sw_stat->single_ecc_errs++;
4753 s2io_stop_all_tx_queue(sp);
4754 schedule_work(&sp->rst_timer_task);
4755 sw_stat->soft_reset_cnt++;
4759 * s2io_isr - ISR handler of the device .
4760 * @irq: the irq of the device.
4761 * @dev_id: a void pointer to the dev structure of the NIC.
4762 * Description: This function is the ISR handler of the device. It
4763 * identifies the reason for the interrupt and calls the relevant
4764 * service routines. As a contongency measure, this ISR allocates the
4765 * recv buffers, if their numbers are below the panic value which is
4766 * presently set to 25% of the original number of rcv buffers allocated.
4768 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4769 * IRQ_NONE: will be returned if interrupt is not from our device
4771 static irqreturn_t s2io_isr(int irq, void *dev_id)
4773 struct net_device *dev = (struct net_device *)dev_id;
4774 struct s2io_nic *sp = netdev_priv(dev);
4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4778 struct mac_info *mac_control;
4779 struct config_param *config;
4781 /* Pretend we handled any irq's from a disconnected card */
4782 if (pci_channel_offline(sp->pdev))
4785 if (!is_s2io_card_up(sp))
4788 config = &sp->config;
4789 mac_control = &sp->mac_control;
4792 * Identify the cause for interrupt and call the appropriate
4793 * interrupt handler. Causes for the interrupt could be;
4798 reason = readq(&bar0->general_int_status);
4800 if (unlikely(reason == S2IO_MINUS_ONE))
4801 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4804 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4805 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4808 if (reason & GEN_INTR_RXTRAFFIC) {
4809 napi_schedule(&sp->napi);
4810 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4812 readl(&bar0->rx_traffic_int);
4816 * rx_traffic_int reg is an R1 register, writing all 1's
4817 * will ensure that the actual interrupt causing bit
4818 * get's cleared and hence a read can be avoided.
4820 if (reason & GEN_INTR_RXTRAFFIC)
4821 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4823 for (i = 0; i < config->rx_ring_num; i++) {
4824 struct ring_info *ring = &mac_control->rings[i];
4826 rx_intr_handler(ring, 0);
4831 * tx_traffic_int reg is an R1 register, writing all 1's
4832 * will ensure that the actual interrupt causing bit get's
4833 * cleared and hence a read can be avoided.
4835 if (reason & GEN_INTR_TXTRAFFIC)
4836 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4838 for (i = 0; i < config->tx_fifo_num; i++)
4839 tx_intr_handler(&mac_control->fifos[i]);
4841 if (reason & GEN_INTR_TXPIC)
4842 s2io_txpic_intr_handle(sp);
4845 * Reallocate the buffers from the interrupt handler itself.
4847 if (!config->napi) {
4848 for (i = 0; i < config->rx_ring_num; i++) {
4849 struct ring_info *ring = &mac_control->rings[i];
4851 s2io_chk_rx_buffers(sp, ring);
4854 writeq(sp->general_int_mask, &bar0->general_int_mask);
4855 readl(&bar0->general_int_status);
4859 } else if (!reason) {
4860 /* The interrupt was not raised by us */
4870 static void s2io_updt_stats(struct s2io_nic *sp)
4872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4876 if (is_s2io_card_up(sp)) {
4877 /* Apprx 30us on a 133 MHz bus */
4878 val64 = SET_UPDT_CLICKS(10) |
4879 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4880 writeq(val64, &bar0->stat_cfg);
4883 val64 = readq(&bar0->stat_cfg);
4884 if (!(val64 & s2BIT(0)))
4888 break; /* Updt failed */
4894 * s2io_get_stats - Updates the device statistics structure.
4895 * @dev : pointer to the device structure.
4897 * This function updates the device statistics structure in the s2io_nic
4898 * structure and returns a pointer to the same.
4900 * pointer to the updated net_device_stats structure.
4902 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4904 struct s2io_nic *sp = netdev_priv(dev);
4905 struct mac_info *mac_control = &sp->mac_control;
4906 struct stat_block *stats = mac_control->stats_info;
4909 /* Configure Stats for immediate updt */
4910 s2io_updt_stats(sp);
4912 /* A device reset will cause the on-adapter statistics to be zero'ed.
4913 * This can be done while running by changing the MTU. To prevent the
4914 * system from having the stats zero'ed, the driver keeps a copy of the
4915 * last update to the system (which is also zero'ed on reset). This
4916 * enables the driver to accurately know the delta between the last
4917 * update and the current update.
4919 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4920 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4921 sp->stats.rx_packets += delta;
4922 dev->stats.rx_packets += delta;
4924 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4925 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4926 sp->stats.tx_packets += delta;
4927 dev->stats.tx_packets += delta;
4929 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4930 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4931 sp->stats.rx_bytes += delta;
4932 dev->stats.rx_bytes += delta;
4934 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4935 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4936 sp->stats.tx_bytes += delta;
4937 dev->stats.tx_bytes += delta;
4939 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4940 sp->stats.rx_errors += delta;
4941 dev->stats.rx_errors += delta;
4943 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4944 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4945 sp->stats.tx_errors += delta;
4946 dev->stats.tx_errors += delta;
4948 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4949 sp->stats.rx_dropped += delta;
4950 dev->stats.rx_dropped += delta;
4952 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4953 sp->stats.tx_dropped += delta;
4954 dev->stats.tx_dropped += delta;
4956 /* The adapter MAC interprets pause frames as multicast packets, but
4957 * does not pass them up. This erroneously increases the multicast
4958 * packet count and needs to be deducted when the multicast frame count
4961 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4962 le32_to_cpu(stats->rmac_vld_mcst_frms);
4963 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4964 delta -= sp->stats.multicast;
4965 sp->stats.multicast += delta;
4966 dev->stats.multicast += delta;
4968 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4969 le32_to_cpu(stats->rmac_usized_frms)) +
4970 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4971 sp->stats.rx_length_errors += delta;
4972 dev->stats.rx_length_errors += delta;
4974 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4975 sp->stats.rx_crc_errors += delta;
4976 dev->stats.rx_crc_errors += delta;
4982 * s2io_set_multicast - entry point for multicast address enable/disable.
4983 * @dev : pointer to the device structure
4985 * This function is a driver entry point which gets called by the kernel
4986 * whenever multicast addresses must be enabled/disabled. This also gets
4987 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4988 * determine, if multicast address must be enabled or if promiscuous mode
4989 * is to be disabled etc.
4994 static void s2io_set_multicast(struct net_device *dev)
4997 struct netdev_hw_addr *ha;
4998 struct s2io_nic *sp = netdev_priv(dev);
4999 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5000 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
5002 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
5004 struct config_param *config = &sp->config;
5006 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5007 /* Enable all Multicast addresses */
5008 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5009 &bar0->rmac_addr_data0_mem);
5010 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5011 &bar0->rmac_addr_data1_mem);
5012 val64 = RMAC_ADDR_CMD_MEM_WE |
5013 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
5015 writeq(val64, &bar0->rmac_addr_cmd_mem);
5016 /* Wait till command completes */
5017 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5018 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5022 sp->all_multi_pos = config->max_mc_addr - 1;
5023 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5024 /* Disable all Multicast addresses */
5025 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5026 &bar0->rmac_addr_data0_mem);
5027 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5028 &bar0->rmac_addr_data1_mem);
5029 val64 = RMAC_ADDR_CMD_MEM_WE |
5030 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5032 writeq(val64, &bar0->rmac_addr_cmd_mem);
5033 /* Wait till command completes */
5034 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5035 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5039 sp->all_multi_pos = 0;
5042 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5043 /* Put the NIC into promiscuous mode */
5044 add = &bar0->mac_cfg;
5045 val64 = readq(&bar0->mac_cfg);
5046 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5048 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5049 writel((u32)val64, add);
5050 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5051 writel((u32) (val64 >> 32), (add + 4));
5053 if (vlan_tag_strip != 1) {
5054 val64 = readq(&bar0->rx_pa_cfg);
5055 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5056 writeq(val64, &bar0->rx_pa_cfg);
5057 sp->vlan_strip_flag = 0;
5060 val64 = readq(&bar0->mac_cfg);
5061 sp->promisc_flg = 1;
5062 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5064 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5065 /* Remove the NIC from promiscuous mode */
5066 add = &bar0->mac_cfg;
5067 val64 = readq(&bar0->mac_cfg);
5068 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5070 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5071 writel((u32)val64, add);
5072 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5073 writel((u32) (val64 >> 32), (add + 4));
5075 if (vlan_tag_strip != 0) {
5076 val64 = readq(&bar0->rx_pa_cfg);
5077 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5078 writeq(val64, &bar0->rx_pa_cfg);
5079 sp->vlan_strip_flag = 1;
5082 val64 = readq(&bar0->mac_cfg);
5083 sp->promisc_flg = 0;
5084 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5087 /* Update individual M_CAST address list */
5088 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5089 if (netdev_mc_count(dev) >
5090 (config->max_mc_addr - config->max_mac_addr)) {
5092 "%s: No more Rx filters can be added - "
5093 "please enable ALL_MULTI instead\n",
5098 prev_cnt = sp->mc_addr_count;
5099 sp->mc_addr_count = netdev_mc_count(dev);
5101 /* Clear out the previous list of Mc in the H/W. */
5102 for (i = 0; i < prev_cnt; i++) {
5103 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5104 &bar0->rmac_addr_data0_mem);
5105 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5106 &bar0->rmac_addr_data1_mem);
5107 val64 = RMAC_ADDR_CMD_MEM_WE |
5108 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5109 RMAC_ADDR_CMD_MEM_OFFSET
5110 (config->mc_start_offset + i);
5111 writeq(val64, &bar0->rmac_addr_cmd_mem);
5113 /* Wait for command completes */
5114 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5115 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5118 "%s: Adding Multicasts failed\n",
5124 /* Create the new Rx filter list and update the same in H/W. */
5126 netdev_for_each_mc_addr(ha, dev) {
5128 for (j = 0; j < ETH_ALEN; j++) {
5129 mac_addr |= ha->addr[j];
5133 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5134 &bar0->rmac_addr_data0_mem);
5135 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5136 &bar0->rmac_addr_data1_mem);
5137 val64 = RMAC_ADDR_CMD_MEM_WE |
5138 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5139 RMAC_ADDR_CMD_MEM_OFFSET
5140 (i + config->mc_start_offset);
5141 writeq(val64, &bar0->rmac_addr_cmd_mem);
5143 /* Wait for command completes */
5144 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5145 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5148 "%s: Adding Multicasts failed\n",
5157 /* read from CAM unicast & multicast addresses and store it in
5158 * def_mac_addr structure
5160 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5164 struct config_param *config = &sp->config;
5166 /* store unicast & multicast mac addresses */
5167 for (offset = 0; offset < config->max_mc_addr; offset++) {
5168 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5169 /* if read fails disable the entry */
5170 if (mac_addr == FAILURE)
5171 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5172 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5176 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5177 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5180 struct config_param *config = &sp->config;
5181 /* restore unicast mac address */
5182 for (offset = 0; offset < config->max_mac_addr; offset++)
5183 do_s2io_prog_unicast(sp->dev,
5184 sp->def_mac_addr[offset].mac_addr);
5186 /* restore multicast mac address */
5187 for (offset = config->mc_start_offset;
5188 offset < config->max_mc_addr; offset++)
5189 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5192 /* add a multicast MAC address to CAM */
5193 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5197 struct config_param *config = &sp->config;
5199 for (i = 0; i < ETH_ALEN; i++) {
5201 mac_addr |= addr[i];
5203 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5206 /* check if the multicast mac already preset in CAM */
5207 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5209 tmp64 = do_s2io_read_unicast_mc(sp, i);
5210 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5213 if (tmp64 == mac_addr)
5216 if (i == config->max_mc_addr) {
5218 "CAM full no space left for multicast MAC\n");
5221 /* Update the internal structure with this new mac address */
5222 do_s2io_copy_mac_addr(sp, i, mac_addr);
5224 return do_s2io_add_mac(sp, mac_addr, i);
5227 /* add MAC address to CAM */
5228 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5231 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5233 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5234 &bar0->rmac_addr_data0_mem);
5236 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5237 RMAC_ADDR_CMD_MEM_OFFSET(off);
5238 writeq(val64, &bar0->rmac_addr_cmd_mem);
5240 /* Wait till command completes */
5241 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5242 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5244 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5249 /* deletes a specified unicast/multicast mac entry from CAM */
5250 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5253 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5254 struct config_param *config = &sp->config;
5257 offset < config->max_mc_addr; offset++) {
5258 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5259 if (tmp64 == addr) {
5260 /* disable the entry by writing 0xffffffffffffULL */
5261 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5263 /* store the new mac list from CAM */
5264 do_s2io_store_unicast_mc(sp);
5268 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5269 (unsigned long long)addr);
5273 /* read mac entries from CAM */
5274 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5276 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5277 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5280 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5281 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5282 writeq(val64, &bar0->rmac_addr_cmd_mem);
5284 /* Wait till command completes */
5285 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5286 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5288 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5291 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5297 * s2io_set_mac_addr driver entry point
5300 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5302 struct sockaddr *addr = p;
5304 if (!is_valid_ether_addr(addr->sa_data))
5307 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5309 /* store the MAC address in CAM */
5310 return do_s2io_prog_unicast(dev, dev->dev_addr);
5313 * do_s2io_prog_unicast - Programs the Xframe mac address
5314 * @dev : pointer to the device structure.
5315 * @addr: a uchar pointer to the new mac address which is to be set.
5316 * Description : This procedure will program the Xframe to receive
5317 * frames with new Mac Address
5318 * Return value: SUCCESS on success and an appropriate (-)ve integer
5319 * as defined in errno.h file on failure.
5322 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5324 struct s2io_nic *sp = netdev_priv(dev);
5325 register u64 mac_addr = 0, perm_addr = 0;
5328 struct config_param *config = &sp->config;
5331 * Set the new MAC address as the new unicast filter and reflect this
5332 * change on the device address registered with the OS. It will be
5335 for (i = 0; i < ETH_ALEN; i++) {
5337 mac_addr |= addr[i];
5339 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5342 /* check if the dev_addr is different than perm_addr */
5343 if (mac_addr == perm_addr)
5346 /* check if the mac already preset in CAM */
5347 for (i = 1; i < config->max_mac_addr; i++) {
5348 tmp64 = do_s2io_read_unicast_mc(sp, i);
5349 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5352 if (tmp64 == mac_addr) {
5354 "MAC addr:0x%llx already present in CAM\n",
5355 (unsigned long long)mac_addr);
5359 if (i == config->max_mac_addr) {
5360 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5363 /* Update the internal structure with this new mac address */
5364 do_s2io_copy_mac_addr(sp, i, mac_addr);
5366 return do_s2io_add_mac(sp, mac_addr, i);
5370 * s2io_ethtool_sset - Sets different link parameters.
5371 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5372 * @info: pointer to the structure with parameters given by ethtool to set
5375 * The function sets different link parameters provided by the user onto
5381 static int s2io_ethtool_sset(struct net_device *dev,
5382 struct ethtool_cmd *info)
5384 struct s2io_nic *sp = netdev_priv(dev);
5385 if ((info->autoneg == AUTONEG_ENABLE) ||
5386 (info->speed != SPEED_10000) ||
5387 (info->duplex != DUPLEX_FULL))
5390 s2io_close(sp->dev);
5398 * s2io_ethtol_gset - Return link specific information.
5399 * @sp : private member of the device structure, pointer to the
5400 * s2io_nic structure.
5401 * @info : pointer to the structure with parameters given by ethtool
5402 * to return link information.
5404 * Returns link specific information like speed, duplex etc.. to ethtool.
5406 * return 0 on success.
5409 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5411 struct s2io_nic *sp = netdev_priv(dev);
5412 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5413 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5414 info->port = PORT_FIBRE;
5416 /* info->transceiver */
5417 info->transceiver = XCVR_EXTERNAL;
5419 if (netif_carrier_ok(sp->dev)) {
5420 info->speed = 10000;
5421 info->duplex = DUPLEX_FULL;
5427 info->autoneg = AUTONEG_DISABLE;
5432 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5433 * @sp : private member of the device structure, which is a pointer to the
5434 * s2io_nic structure.
5435 * @info : pointer to the structure with parameters given by ethtool to
5436 * return driver information.
5438 * Returns driver specefic information like name, version etc.. to ethtool.
5443 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5444 struct ethtool_drvinfo *info)
5446 struct s2io_nic *sp = netdev_priv(dev);
5448 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5449 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5450 strncpy(info->fw_version, "", sizeof(info->fw_version));
5451 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5452 info->regdump_len = XENA_REG_SPACE;
5453 info->eedump_len = XENA_EEPROM_SPACE;
5457 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5458 * @sp: private member of the device structure, which is a pointer to the
5459 * s2io_nic structure.
5460 * @regs : pointer to the structure with parameters given by ethtool for
5461 * dumping the registers.
5462 * @reg_space: The input argumnet into which all the registers are dumped.
5464 * Dumps the entire register space of xFrame NIC into the user given
5470 static void s2io_ethtool_gregs(struct net_device *dev,
5471 struct ethtool_regs *regs, void *space)
5475 u8 *reg_space = (u8 *)space;
5476 struct s2io_nic *sp = netdev_priv(dev);
5478 regs->len = XENA_REG_SPACE;
5479 regs->version = sp->pdev->subsystem_device;
5481 for (i = 0; i < regs->len; i += 8) {
5482 reg = readq(sp->bar0 + i);
5483 memcpy((reg_space + i), ®, 8);
5488 * s2io_set_led - control NIC led
5490 static void s2io_set_led(struct s2io_nic *sp, bool on)
5492 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5493 u16 subid = sp->pdev->subsystem_device;
5496 if ((sp->device_type == XFRAME_II_DEVICE) ||
5497 ((subid & 0xFF) >= 0x07)) {
5498 val64 = readq(&bar0->gpio_control);
5500 val64 |= GPIO_CTRL_GPIO_0;
5502 val64 &= ~GPIO_CTRL_GPIO_0;
5504 writeq(val64, &bar0->gpio_control);
5506 val64 = readq(&bar0->adapter_control);
5508 val64 |= ADAPTER_LED_ON;
5510 val64 &= ~ADAPTER_LED_ON;
5512 writeq(val64, &bar0->adapter_control);
5518 * s2io_ethtool_set_led - To physically identify the nic on the system.
5519 * @dev : network device
5520 * @state: led setting
5522 * Description: Used to physically identify the NIC on the system.
5523 * The Link LED will blink for a time specified by the user for
5525 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5526 * identification is possible only if it's link is up.
5529 static int s2io_ethtool_set_led(struct net_device *dev,
5530 enum ethtool_phys_id_state state)
5532 struct s2io_nic *sp = netdev_priv(dev);
5533 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5534 u16 subid = sp->pdev->subsystem_device;
5536 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5537 u64 val64 = readq(&bar0->adapter_control);
5538 if (!(val64 & ADAPTER_CNTL_EN)) {
5539 pr_err("Adapter Link down, cannot blink LED\n");
5545 case ETHTOOL_ID_ACTIVE:
5546 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5550 s2io_set_led(sp, true);
5553 case ETHTOOL_ID_OFF:
5554 s2io_set_led(sp, false);
5557 case ETHTOOL_ID_INACTIVE:
5558 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5559 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5565 static void s2io_ethtool_gringparam(struct net_device *dev,
5566 struct ethtool_ringparam *ering)
5568 struct s2io_nic *sp = netdev_priv(dev);
5569 int i, tx_desc_count = 0, rx_desc_count = 0;
5571 if (sp->rxd_mode == RXD_MODE_1) {
5572 ering->rx_max_pending = MAX_RX_DESC_1;
5573 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5575 ering->rx_max_pending = MAX_RX_DESC_2;
5576 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5579 ering->rx_mini_max_pending = 0;
5580 ering->tx_max_pending = MAX_TX_DESC;
5582 for (i = 0; i < sp->config.rx_ring_num; i++)
5583 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5584 ering->rx_pending = rx_desc_count;
5585 ering->rx_jumbo_pending = rx_desc_count;
5586 ering->rx_mini_pending = 0;
5588 for (i = 0; i < sp->config.tx_fifo_num; i++)
5589 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5590 ering->tx_pending = tx_desc_count;
5591 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5595 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5596 * @sp : private member of the device structure, which is a pointer to the
5597 * s2io_nic structure.
5598 * @ep : pointer to the structure with pause parameters given by ethtool.
5600 * Returns the Pause frame generation and reception capability of the NIC.
5604 static void s2io_ethtool_getpause_data(struct net_device *dev,
5605 struct ethtool_pauseparam *ep)
5608 struct s2io_nic *sp = netdev_priv(dev);
5609 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5611 val64 = readq(&bar0->rmac_pause_cfg);
5612 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5613 ep->tx_pause = true;
5614 if (val64 & RMAC_PAUSE_RX_ENABLE)
5615 ep->rx_pause = true;
5616 ep->autoneg = false;
5620 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5621 * @sp : private member of the device structure, which is a pointer to the
5622 * s2io_nic structure.
5623 * @ep : pointer to the structure with pause parameters given by ethtool.
5625 * It can be used to set or reset Pause frame generation or reception
5626 * support of the NIC.
5628 * int, returns 0 on Success
5631 static int s2io_ethtool_setpause_data(struct net_device *dev,
5632 struct ethtool_pauseparam *ep)
5635 struct s2io_nic *sp = netdev_priv(dev);
5636 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5638 val64 = readq(&bar0->rmac_pause_cfg);
5640 val64 |= RMAC_PAUSE_GEN_ENABLE;
5642 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5644 val64 |= RMAC_PAUSE_RX_ENABLE;
5646 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5647 writeq(val64, &bar0->rmac_pause_cfg);
5652 * read_eeprom - reads 4 bytes of data from user given offset.
5653 * @sp : private member of the device structure, which is a pointer to the
5654 * s2io_nic structure.
5655 * @off : offset at which the data must be written
5656 * @data : Its an output parameter where the data read at the given
5659 * Will read 4 bytes of data from the user given offset and return the
5661 * NOTE: Will allow to read only part of the EEPROM visible through the
5664 * -1 on failure and 0 on success.
5667 #define S2IO_DEV_ID 5
5668 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5673 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5675 if (sp->device_type == XFRAME_I_DEVICE) {
5676 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5677 I2C_CONTROL_ADDR(off) |
5678 I2C_CONTROL_BYTE_CNT(0x3) |
5680 I2C_CONTROL_CNTL_START;
5681 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5683 while (exit_cnt < 5) {
5684 val64 = readq(&bar0->i2c_control);
5685 if (I2C_CONTROL_CNTL_END(val64)) {
5686 *data = I2C_CONTROL_GET_DATA(val64);
5695 if (sp->device_type == XFRAME_II_DEVICE) {
5696 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5697 SPI_CONTROL_BYTECNT(0x3) |
5698 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5699 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5700 val64 |= SPI_CONTROL_REQ;
5701 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5702 while (exit_cnt < 5) {
5703 val64 = readq(&bar0->spi_control);
5704 if (val64 & SPI_CONTROL_NACK) {
5707 } else if (val64 & SPI_CONTROL_DONE) {
5708 *data = readq(&bar0->spi_data);
5721 * write_eeprom - actually writes the relevant part of the data value.
5722 * @sp : private member of the device structure, which is a pointer to the
5723 * s2io_nic structure.
5724 * @off : offset at which the data must be written
5725 * @data : The data that is to be written
5726 * @cnt : Number of bytes of the data that are actually to be written into
5727 * the Eeprom. (max of 3)
5729 * Actually writes the relevant part of the data value into the Eeprom
5730 * through the I2C bus.
5732 * 0 on success, -1 on failure.
5735 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5737 int exit_cnt = 0, ret = -1;
5739 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5741 if (sp->device_type == XFRAME_I_DEVICE) {
5742 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5743 I2C_CONTROL_ADDR(off) |
5744 I2C_CONTROL_BYTE_CNT(cnt) |
5745 I2C_CONTROL_SET_DATA((u32)data) |
5746 I2C_CONTROL_CNTL_START;
5747 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5749 while (exit_cnt < 5) {
5750 val64 = readq(&bar0->i2c_control);
5751 if (I2C_CONTROL_CNTL_END(val64)) {
5752 if (!(val64 & I2C_CONTROL_NACK))
5761 if (sp->device_type == XFRAME_II_DEVICE) {
5762 int write_cnt = (cnt == 8) ? 0 : cnt;
5763 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5765 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5766 SPI_CONTROL_BYTECNT(write_cnt) |
5767 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5768 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5769 val64 |= SPI_CONTROL_REQ;
5770 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5771 while (exit_cnt < 5) {
5772 val64 = readq(&bar0->spi_control);
5773 if (val64 & SPI_CONTROL_NACK) {
5776 } else if (val64 & SPI_CONTROL_DONE) {
5786 static void s2io_vpd_read(struct s2io_nic *nic)
5790 int i = 0, cnt, len, fail = 0;
5791 int vpd_addr = 0x80;
5792 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5794 if (nic->device_type == XFRAME_II_DEVICE) {
5795 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5798 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5801 strcpy(nic->serial_num, "NOT AVAILABLE");
5803 vpd_data = kmalloc(256, GFP_KERNEL);
5805 swstats->mem_alloc_fail_cnt++;
5808 swstats->mem_allocated += 256;
5810 for (i = 0; i < 256; i += 4) {
5811 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5812 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5813 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5814 for (cnt = 0; cnt < 5; cnt++) {
5816 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5821 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5825 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5826 (u32 *)&vpd_data[i]);
5830 /* read serial number of adapter */
5831 for (cnt = 0; cnt < 252; cnt++) {
5832 if ((vpd_data[cnt] == 'S') &&
5833 (vpd_data[cnt+1] == 'N')) {
5834 len = vpd_data[cnt+2];
5835 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5836 memcpy(nic->serial_num,
5839 memset(nic->serial_num+len,
5841 VPD_STRING_LEN-len);
5848 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5850 memcpy(nic->product_name, &vpd_data[3], len);
5851 nic->product_name[len] = 0;
5854 swstats->mem_freed += 256;
5858 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5859 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5860 * @eeprom : pointer to the user level structure provided by ethtool,
5861 * containing all relevant information.
5862 * @data_buf : user defined value to be written into Eeprom.
5863 * Description: Reads the values stored in the Eeprom at given offset
5864 * for a given length. Stores these values int the input argument data
5865 * buffer 'data_buf' and returns these to the caller (ethtool.)
5870 static int s2io_ethtool_geeprom(struct net_device *dev,
5871 struct ethtool_eeprom *eeprom, u8 * data_buf)
5875 struct s2io_nic *sp = netdev_priv(dev);
5877 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5879 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5880 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5882 for (i = 0; i < eeprom->len; i += 4) {
5883 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5884 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5888 memcpy((data_buf + i), &valid, 4);
5894 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5895 * @sp : private member of the device structure, which is a pointer to the
5896 * s2io_nic structure.
5897 * @eeprom : pointer to the user level structure provided by ethtool,
5898 * containing all relevant information.
5899 * @data_buf ; user defined value to be written into Eeprom.
5901 * Tries to write the user provided value in the Eeprom, at the offset
5902 * given by the user.
5904 * 0 on success, -EFAULT on failure.
5907 static int s2io_ethtool_seeprom(struct net_device *dev,
5908 struct ethtool_eeprom *eeprom,
5911 int len = eeprom->len, cnt = 0;
5912 u64 valid = 0, data;
5913 struct s2io_nic *sp = netdev_priv(dev);
5915 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5917 "ETHTOOL_WRITE_EEPROM Err: "
5918 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5919 (sp->pdev->vendor | (sp->pdev->device << 16)),
5925 data = (u32)data_buf[cnt] & 0x000000FF;
5927 valid = (u32)(data << 24);
5931 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5933 "ETHTOOL_WRITE_EEPROM Err: "
5934 "Cannot write into the specified offset\n");
5945 * s2io_register_test - reads and writes into all clock domains.
5946 * @sp : private member of the device structure, which is a pointer to the
5947 * s2io_nic structure.
5948 * @data : variable that returns the result of each of the test conducted b
5951 * Read and write into all clock domains. The NIC has 3 clock domains,
5952 * see that registers in all the three regions are accessible.
5957 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5959 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5960 u64 val64 = 0, exp_val;
5963 val64 = readq(&bar0->pif_rd_swapper_fb);
5964 if (val64 != 0x123456789abcdefULL) {
5966 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5969 val64 = readq(&bar0->rmac_pause_cfg);
5970 if (val64 != 0xc000ffff00000000ULL) {
5972 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5975 val64 = readq(&bar0->rx_queue_cfg);
5976 if (sp->device_type == XFRAME_II_DEVICE)
5977 exp_val = 0x0404040404040404ULL;
5979 exp_val = 0x0808080808080808ULL;
5980 if (val64 != exp_val) {
5982 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5985 val64 = readq(&bar0->xgxs_efifo_cfg);
5986 if (val64 != 0x000000001923141EULL) {
5988 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5991 val64 = 0x5A5A5A5A5A5A5A5AULL;
5992 writeq(val64, &bar0->xmsi_data);
5993 val64 = readq(&bar0->xmsi_data);
5994 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5996 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5999 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6000 writeq(val64, &bar0->xmsi_data);
6001 val64 = readq(&bar0->xmsi_data);
6002 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6004 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
6012 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
6013 * @sp : private member of the device structure, which is a pointer to the
6014 * s2io_nic structure.
6015 * @data:variable that returns the result of each of the test conducted by
6018 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
6024 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
6027 u64 ret_data, org_4F0, org_7F0;
6028 u8 saved_4F0 = 0, saved_7F0 = 0;
6029 struct net_device *dev = sp->dev;
6031 /* Test Write Error at offset 0 */
6032 /* Note that SPI interface allows write access to all areas
6033 * of EEPROM. Hence doing all negative testing only for Xframe I.
6035 if (sp->device_type == XFRAME_I_DEVICE)
6036 if (!write_eeprom(sp, 0, 0, 3))
6039 /* Save current values at offsets 0x4F0 and 0x7F0 */
6040 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6042 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6045 /* Test Write at offset 4f0 */
6046 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6048 if (read_eeprom(sp, 0x4F0, &ret_data))
6051 if (ret_data != 0x012345) {
6052 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6053 "Data written %llx Data read %llx\n",
6054 dev->name, (unsigned long long)0x12345,
6055 (unsigned long long)ret_data);
6059 /* Reset the EEPROM data go FFFF */
6060 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6062 /* Test Write Request Error at offset 0x7c */
6063 if (sp->device_type == XFRAME_I_DEVICE)
6064 if (!write_eeprom(sp, 0x07C, 0, 3))
6067 /* Test Write Request at offset 0x7f0 */
6068 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6070 if (read_eeprom(sp, 0x7F0, &ret_data))
6073 if (ret_data != 0x012345) {
6074 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6075 "Data written %llx Data read %llx\n",
6076 dev->name, (unsigned long long)0x12345,
6077 (unsigned long long)ret_data);
6081 /* Reset the EEPROM data go FFFF */
6082 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6084 if (sp->device_type == XFRAME_I_DEVICE) {
6085 /* Test Write Error at offset 0x80 */
6086 if (!write_eeprom(sp, 0x080, 0, 3))
6089 /* Test Write Error at offset 0xfc */
6090 if (!write_eeprom(sp, 0x0FC, 0, 3))
6093 /* Test Write Error at offset 0x100 */
6094 if (!write_eeprom(sp, 0x100, 0, 3))
6097 /* Test Write Error at offset 4ec */
6098 if (!write_eeprom(sp, 0x4EC, 0, 3))
6102 /* Restore values at offsets 0x4F0 and 0x7F0 */
6104 write_eeprom(sp, 0x4F0, org_4F0, 3);
6106 write_eeprom(sp, 0x7F0, org_7F0, 3);
6113 * s2io_bist_test - invokes the MemBist test of the card .
6114 * @sp : private member of the device structure, which is a pointer to the
6115 * s2io_nic structure.
6116 * @data:variable that returns the result of each of the test conducted by
6119 * This invokes the MemBist test of the card. We give around
6120 * 2 secs time for the Test to complete. If it's still not complete
6121 * within this peiod, we consider that the test failed.
6123 * 0 on success and -1 on failure.
6126 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6129 int cnt = 0, ret = -1;
6131 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6132 bist |= PCI_BIST_START;
6133 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6136 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6137 if (!(bist & PCI_BIST_START)) {
6138 *data = (bist & PCI_BIST_CODE_MASK);
6150 * s2io-link_test - verifies the link state of the nic
6151 * @sp ; private member of the device structure, which is a pointer to the
6152 * s2io_nic structure.
6153 * @data: variable that returns the result of each of the test conducted by
6156 * The function verifies the link state of the NIC and updates the input
6157 * argument 'data' appropriately.
6162 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6164 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6167 val64 = readq(&bar0->adapter_status);
6168 if (!(LINK_IS_UP(val64)))
6177 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6178 * @sp - private member of the device structure, which is a pointer to the
6179 * s2io_nic structure.
6180 * @data - variable that returns the result of each of the test
6181 * conducted by the driver.
6183 * This is one of the offline test that tests the read and write
6184 * access to the RldRam chip on the NIC.
6189 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6191 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6193 int cnt, iteration = 0, test_fail = 0;
6195 val64 = readq(&bar0->adapter_control);
6196 val64 &= ~ADAPTER_ECC_EN;
6197 writeq(val64, &bar0->adapter_control);
6199 val64 = readq(&bar0->mc_rldram_test_ctrl);
6200 val64 |= MC_RLDRAM_TEST_MODE;
6201 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6203 val64 = readq(&bar0->mc_rldram_mrs);
6204 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6205 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6207 val64 |= MC_RLDRAM_MRS_ENABLE;
6208 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6210 while (iteration < 2) {
6211 val64 = 0x55555555aaaa0000ULL;
6213 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6214 writeq(val64, &bar0->mc_rldram_test_d0);
6216 val64 = 0xaaaa5a5555550000ULL;
6218 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6219 writeq(val64, &bar0->mc_rldram_test_d1);
6221 val64 = 0x55aaaaaaaa5a0000ULL;
6223 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6224 writeq(val64, &bar0->mc_rldram_test_d2);
6226 val64 = (u64) (0x0000003ffffe0100ULL);
6227 writeq(val64, &bar0->mc_rldram_test_add);
6229 val64 = MC_RLDRAM_TEST_MODE |
6230 MC_RLDRAM_TEST_WRITE |
6232 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6234 for (cnt = 0; cnt < 5; cnt++) {
6235 val64 = readq(&bar0->mc_rldram_test_ctrl);
6236 if (val64 & MC_RLDRAM_TEST_DONE)
6244 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6245 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6247 for (cnt = 0; cnt < 5; cnt++) {
6248 val64 = readq(&bar0->mc_rldram_test_ctrl);
6249 if (val64 & MC_RLDRAM_TEST_DONE)
6257 val64 = readq(&bar0->mc_rldram_test_ctrl);
6258 if (!(val64 & MC_RLDRAM_TEST_PASS))
6266 /* Bring the adapter out of test mode */
6267 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6273 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6274 * @sp : private member of the device structure, which is a pointer to the
6275 * s2io_nic structure.
6276 * @ethtest : pointer to a ethtool command specific structure that will be
6277 * returned to the user.
6278 * @data : variable that returns the result of each of the test
6279 * conducted by the driver.
6281 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6282 * the health of the card.
6287 static void s2io_ethtool_test(struct net_device *dev,
6288 struct ethtool_test *ethtest,
6291 struct s2io_nic *sp = netdev_priv(dev);
6292 int orig_state = netif_running(sp->dev);
6294 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6295 /* Offline Tests. */
6297 s2io_close(sp->dev);
6299 if (s2io_register_test(sp, &data[0]))
6300 ethtest->flags |= ETH_TEST_FL_FAILED;
6304 if (s2io_rldram_test(sp, &data[3]))
6305 ethtest->flags |= ETH_TEST_FL_FAILED;
6309 if (s2io_eeprom_test(sp, &data[1]))
6310 ethtest->flags |= ETH_TEST_FL_FAILED;
6312 if (s2io_bist_test(sp, &data[4]))
6313 ethtest->flags |= ETH_TEST_FL_FAILED;
6322 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6331 if (s2io_link_test(sp, &data[2]))
6332 ethtest->flags |= ETH_TEST_FL_FAILED;
6341 static void s2io_get_ethtool_stats(struct net_device *dev,
6342 struct ethtool_stats *estats,
6346 struct s2io_nic *sp = netdev_priv(dev);
6347 struct stat_block *stats = sp->mac_control.stats_info;
6348 struct swStat *swstats = &stats->sw_stat;
6349 struct xpakStat *xstats = &stats->xpak_stat;
6351 s2io_updt_stats(sp);
6353 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6354 le32_to_cpu(stats->tmac_frms);
6356 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6357 le32_to_cpu(stats->tmac_data_octets);
6358 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6360 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6361 le32_to_cpu(stats->tmac_mcst_frms);
6363 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6364 le32_to_cpu(stats->tmac_bcst_frms);
6365 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6367 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6368 le32_to_cpu(stats->tmac_ttl_octets);
6370 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6371 le32_to_cpu(stats->tmac_ucst_frms);
6373 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6374 le32_to_cpu(stats->tmac_nucst_frms);
6376 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6377 le32_to_cpu(stats->tmac_any_err_frms);
6378 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6379 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6381 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6382 le32_to_cpu(stats->tmac_vld_ip);
6384 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6385 le32_to_cpu(stats->tmac_drop_ip);
6387 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6388 le32_to_cpu(stats->tmac_icmp);
6390 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6391 le32_to_cpu(stats->tmac_rst_tcp);
6392 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6393 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6394 le32_to_cpu(stats->tmac_udp);
6396 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6397 le32_to_cpu(stats->rmac_vld_frms);
6399 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6400 le32_to_cpu(stats->rmac_data_octets);
6401 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6402 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6404 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6405 le32_to_cpu(stats->rmac_vld_mcst_frms);
6407 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6408 le32_to_cpu(stats->rmac_vld_bcst_frms);
6409 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6410 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6411 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6412 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6415 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6416 le32_to_cpu(stats->rmac_ttl_octets);
6418 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6419 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6421 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6422 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6424 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6425 le32_to_cpu(stats->rmac_discarded_frms);
6427 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6428 << 32 | le32_to_cpu(stats->rmac_drop_events);
6429 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6430 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6432 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6433 le32_to_cpu(stats->rmac_usized_frms);
6435 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6436 le32_to_cpu(stats->rmac_osized_frms);
6438 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6439 le32_to_cpu(stats->rmac_frag_frms);
6441 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6442 le32_to_cpu(stats->rmac_jabber_frms);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6447 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6448 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6450 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6451 le32_to_cpu(stats->rmac_ip);
6452 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6453 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6455 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6456 le32_to_cpu(stats->rmac_drop_ip);
6458 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6459 le32_to_cpu(stats->rmac_icmp);
6460 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6462 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6463 le32_to_cpu(stats->rmac_udp);
6465 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6466 le32_to_cpu(stats->rmac_err_drp_udp);
6467 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6468 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6469 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6470 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6471 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6472 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6473 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6474 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6475 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6476 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6477 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6478 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6479 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6480 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6481 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6482 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6483 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6485 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6486 le32_to_cpu(stats->rmac_pause_cnt);
6487 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6488 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6490 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6491 le32_to_cpu(stats->rmac_accepted_ip);
6492 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6493 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6494 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6495 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6496 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6512 /* Enhanced statistics exist only for Hercules */
6513 if (sp->device_type == XFRAME_II_DEVICE) {
6515 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6517 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6519 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6520 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6521 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6522 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6523 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6524 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6525 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6526 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6527 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6528 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6529 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6530 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6531 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6532 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6536 tmp_stats[i++] = swstats->single_ecc_errs;
6537 tmp_stats[i++] = swstats->double_ecc_errs;
6538 tmp_stats[i++] = swstats->parity_err_cnt;
6539 tmp_stats[i++] = swstats->serious_err_cnt;
6540 tmp_stats[i++] = swstats->soft_reset_cnt;
6541 tmp_stats[i++] = swstats->fifo_full_cnt;
6542 for (k = 0; k < MAX_RX_RINGS; k++)
6543 tmp_stats[i++] = swstats->ring_full_cnt[k];
6544 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6545 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6546 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6547 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6548 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6549 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6550 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6551 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6552 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6553 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6554 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6555 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6556 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6557 tmp_stats[i++] = swstats->sending_both;
6558 tmp_stats[i++] = swstats->outof_sequence_pkts;
6559 tmp_stats[i++] = swstats->flush_max_pkts;
6560 if (swstats->num_aggregations) {
6561 u64 tmp = swstats->sum_avg_pkts_aggregated;
6564 * Since 64-bit divide does not work on all platforms,
6565 * do repeated subtraction.
6567 while (tmp >= swstats->num_aggregations) {
6568 tmp -= swstats->num_aggregations;
6571 tmp_stats[i++] = count;
6574 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6575 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6576 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6577 tmp_stats[i++] = swstats->mem_allocated;
6578 tmp_stats[i++] = swstats->mem_freed;
6579 tmp_stats[i++] = swstats->link_up_cnt;
6580 tmp_stats[i++] = swstats->link_down_cnt;
6581 tmp_stats[i++] = swstats->link_up_time;
6582 tmp_stats[i++] = swstats->link_down_time;
6584 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6585 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6586 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6587 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6588 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6590 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6591 tmp_stats[i++] = swstats->rx_abort_cnt;
6592 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6593 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6594 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6595 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6596 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6597 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6598 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6599 tmp_stats[i++] = swstats->tda_err_cnt;
6600 tmp_stats[i++] = swstats->pfc_err_cnt;
6601 tmp_stats[i++] = swstats->pcc_err_cnt;
6602 tmp_stats[i++] = swstats->tti_err_cnt;
6603 tmp_stats[i++] = swstats->tpa_err_cnt;
6604 tmp_stats[i++] = swstats->sm_err_cnt;
6605 tmp_stats[i++] = swstats->lso_err_cnt;
6606 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6607 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6608 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6609 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6610 tmp_stats[i++] = swstats->rc_err_cnt;
6611 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6612 tmp_stats[i++] = swstats->rpa_err_cnt;
6613 tmp_stats[i++] = swstats->rda_err_cnt;
6614 tmp_stats[i++] = swstats->rti_err_cnt;
6615 tmp_stats[i++] = swstats->mc_err_cnt;
6618 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6620 return XENA_REG_SPACE;
6624 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6626 struct s2io_nic *sp = netdev_priv(dev);
6631 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6633 struct s2io_nic *sp = netdev_priv(dev);
6643 static int s2io_get_eeprom_len(struct net_device *dev)
6645 return XENA_EEPROM_SPACE;
6648 static int s2io_get_sset_count(struct net_device *dev, int sset)
6650 struct s2io_nic *sp = netdev_priv(dev);
6654 return S2IO_TEST_LEN;
6656 switch (sp->device_type) {
6657 case XFRAME_I_DEVICE:
6658 return XFRAME_I_STAT_LEN;
6659 case XFRAME_II_DEVICE:
6660 return XFRAME_II_STAT_LEN;
6669 static void s2io_ethtool_get_strings(struct net_device *dev,
6670 u32 stringset, u8 *data)
6673 struct s2io_nic *sp = netdev_priv(dev);
6675 switch (stringset) {
6677 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6680 stat_size = sizeof(ethtool_xena_stats_keys);
6681 memcpy(data, ðtool_xena_stats_keys, stat_size);
6682 if (sp->device_type == XFRAME_II_DEVICE) {
6683 memcpy(data + stat_size,
6684 ðtool_enhanced_stats_keys,
6685 sizeof(ethtool_enhanced_stats_keys));
6686 stat_size += sizeof(ethtool_enhanced_stats_keys);
6689 memcpy(data + stat_size, ðtool_driver_stats_keys,
6690 sizeof(ethtool_driver_stats_keys));
6694 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6697 dev->features |= NETIF_F_IP_CSUM;
6699 dev->features &= ~NETIF_F_IP_CSUM;
6704 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6706 return (dev->features & NETIF_F_TSO) != 0;
6709 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6712 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6714 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6719 static int s2io_ethtool_set_flags(struct net_device *dev, u32 data)
6721 struct s2io_nic *sp = netdev_priv(dev);
6725 if (ethtool_invalid_flags(dev, data, ETH_FLAG_LRO))
6728 if (data & ETH_FLAG_LRO) {
6729 if (!(dev->features & NETIF_F_LRO)) {
6730 dev->features |= NETIF_F_LRO;
6733 } else if (dev->features & NETIF_F_LRO) {
6734 dev->features &= ~NETIF_F_LRO;
6738 if (changed && netif_running(dev)) {
6739 s2io_stop_all_tx_queue(sp);
6741 rc = s2io_card_up(sp);
6745 s2io_start_all_tx_queue(sp);
6751 static const struct ethtool_ops netdev_ethtool_ops = {
6752 .get_settings = s2io_ethtool_gset,
6753 .set_settings = s2io_ethtool_sset,
6754 .get_drvinfo = s2io_ethtool_gdrvinfo,
6755 .get_regs_len = s2io_ethtool_get_regs_len,
6756 .get_regs = s2io_ethtool_gregs,
6757 .get_link = ethtool_op_get_link,
6758 .get_eeprom_len = s2io_get_eeprom_len,
6759 .get_eeprom = s2io_ethtool_geeprom,
6760 .set_eeprom = s2io_ethtool_seeprom,
6761 .get_ringparam = s2io_ethtool_gringparam,
6762 .get_pauseparam = s2io_ethtool_getpause_data,
6763 .set_pauseparam = s2io_ethtool_setpause_data,
6764 .get_rx_csum = s2io_ethtool_get_rx_csum,
6765 .set_rx_csum = s2io_ethtool_set_rx_csum,
6766 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6767 .set_flags = s2io_ethtool_set_flags,
6768 .get_flags = ethtool_op_get_flags,
6769 .set_sg = ethtool_op_set_sg,
6770 .get_tso = s2io_ethtool_op_get_tso,
6771 .set_tso = s2io_ethtool_op_set_tso,
6772 .set_ufo = ethtool_op_set_ufo,
6773 .self_test = s2io_ethtool_test,
6774 .get_strings = s2io_ethtool_get_strings,
6775 .set_phys_id = s2io_ethtool_set_led,
6776 .get_ethtool_stats = s2io_get_ethtool_stats,
6777 .get_sset_count = s2io_get_sset_count,
6781 * s2io_ioctl - Entry point for the Ioctl
6782 * @dev : Device pointer.
6783 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6784 * a proprietary structure used to pass information to the driver.
6785 * @cmd : This is used to distinguish between the different commands that
6786 * can be passed to the IOCTL functions.
6788 * Currently there are no special functionality supported in IOCTL, hence
6789 * function always return EOPNOTSUPPORTED
6792 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6798 * s2io_change_mtu - entry point to change MTU size for the device.
6799 * @dev : device pointer.
6800 * @new_mtu : the new MTU size for the device.
6801 * Description: A driver entry point to change MTU size for the device.
6802 * Before changing the MTU the device must be stopped.
6804 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6808 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6810 struct s2io_nic *sp = netdev_priv(dev);
6813 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6814 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6819 if (netif_running(dev)) {
6820 s2io_stop_all_tx_queue(sp);
6822 ret = s2io_card_up(sp);
6824 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6828 s2io_wake_all_tx_queue(sp);
6829 } else { /* Device is down */
6830 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6831 u64 val64 = new_mtu;
6833 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6840 * s2io_set_link - Set the LInk status
6841 * @data: long pointer to device private structue
6842 * Description: Sets the link status for the adapter
6845 static void s2io_set_link(struct work_struct *work)
6847 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6849 struct net_device *dev = nic->dev;
6850 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6856 if (!netif_running(dev))
6859 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6860 /* The card is being reset, no point doing anything */
6864 subid = nic->pdev->subsystem_device;
6865 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6867 * Allow a small delay for the NICs self initiated
6868 * cleanup to complete.
6873 val64 = readq(&bar0->adapter_status);
6874 if (LINK_IS_UP(val64)) {
6875 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6876 if (verify_xena_quiescence(nic)) {
6877 val64 = readq(&bar0->adapter_control);
6878 val64 |= ADAPTER_CNTL_EN;
6879 writeq(val64, &bar0->adapter_control);
6880 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6881 nic->device_type, subid)) {
6882 val64 = readq(&bar0->gpio_control);
6883 val64 |= GPIO_CTRL_GPIO_0;
6884 writeq(val64, &bar0->gpio_control);
6885 val64 = readq(&bar0->gpio_control);
6887 val64 |= ADAPTER_LED_ON;
6888 writeq(val64, &bar0->adapter_control);
6890 nic->device_enabled_once = true;
6893 "%s: Error: device is not Quiescent\n",
6895 s2io_stop_all_tx_queue(nic);
6898 val64 = readq(&bar0->adapter_control);
6899 val64 |= ADAPTER_LED_ON;
6900 writeq(val64, &bar0->adapter_control);
6901 s2io_link(nic, LINK_UP);
6903 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6905 val64 = readq(&bar0->gpio_control);
6906 val64 &= ~GPIO_CTRL_GPIO_0;
6907 writeq(val64, &bar0->gpio_control);
6908 val64 = readq(&bar0->gpio_control);
6911 val64 = readq(&bar0->adapter_control);
6912 val64 = val64 & (~ADAPTER_LED_ON);
6913 writeq(val64, &bar0->adapter_control);
6914 s2io_link(nic, LINK_DOWN);
6916 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6922 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6924 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6925 u64 *temp2, int size)
6927 struct net_device *dev = sp->dev;
6928 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6930 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6931 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6934 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6936 * As Rx frame are not going to be processed,
6937 * using same mapped address for the Rxd
6940 rxdp1->Buffer0_ptr = *temp0;
6942 *skb = dev_alloc_skb(size);
6945 "%s: Out of memory to allocate %s\n",
6946 dev->name, "1 buf mode SKBs");
6947 stats->mem_alloc_fail_cnt++;
6950 stats->mem_allocated += (*skb)->truesize;
6951 /* storing the mapped addr in a temp variable
6952 * such it will be used for next rxd whose
6953 * Host Control is NULL
6955 rxdp1->Buffer0_ptr = *temp0 =
6956 pci_map_single(sp->pdev, (*skb)->data,
6957 size - NET_IP_ALIGN,
6958 PCI_DMA_FROMDEVICE);
6959 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6960 goto memalloc_failed;
6961 rxdp->Host_Control = (unsigned long) (*skb);
6963 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6964 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6965 /* Two buffer Mode */
6967 rxdp3->Buffer2_ptr = *temp2;
6968 rxdp3->Buffer0_ptr = *temp0;
6969 rxdp3->Buffer1_ptr = *temp1;
6971 *skb = dev_alloc_skb(size);
6974 "%s: Out of memory to allocate %s\n",
6977 stats->mem_alloc_fail_cnt++;
6980 stats->mem_allocated += (*skb)->truesize;
6981 rxdp3->Buffer2_ptr = *temp2 =
6982 pci_map_single(sp->pdev, (*skb)->data,
6984 PCI_DMA_FROMDEVICE);
6985 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6986 goto memalloc_failed;
6987 rxdp3->Buffer0_ptr = *temp0 =
6988 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6989 PCI_DMA_FROMDEVICE);
6990 if (pci_dma_mapping_error(sp->pdev,
6991 rxdp3->Buffer0_ptr)) {
6992 pci_unmap_single(sp->pdev,
6993 (dma_addr_t)rxdp3->Buffer2_ptr,
6995 PCI_DMA_FROMDEVICE);
6996 goto memalloc_failed;
6998 rxdp->Host_Control = (unsigned long) (*skb);
7000 /* Buffer-1 will be dummy buffer not used */
7001 rxdp3->Buffer1_ptr = *temp1 =
7002 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
7003 PCI_DMA_FROMDEVICE);
7004 if (pci_dma_mapping_error(sp->pdev,
7005 rxdp3->Buffer1_ptr)) {
7006 pci_unmap_single(sp->pdev,
7007 (dma_addr_t)rxdp3->Buffer0_ptr,
7008 BUF0_LEN, PCI_DMA_FROMDEVICE);
7009 pci_unmap_single(sp->pdev,
7010 (dma_addr_t)rxdp3->Buffer2_ptr,
7012 PCI_DMA_FROMDEVICE);
7013 goto memalloc_failed;
7020 stats->pci_map_fail_cnt++;
7021 stats->mem_freed += (*skb)->truesize;
7022 dev_kfree_skb(*skb);
7026 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7029 struct net_device *dev = sp->dev;
7030 if (sp->rxd_mode == RXD_MODE_1) {
7031 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
7032 } else if (sp->rxd_mode == RXD_MODE_3B) {
7033 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7034 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
7035 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
7039 static int rxd_owner_bit_reset(struct s2io_nic *sp)
7041 int i, j, k, blk_cnt = 0, size;
7042 struct config_param *config = &sp->config;
7043 struct mac_info *mac_control = &sp->mac_control;
7044 struct net_device *dev = sp->dev;
7045 struct RxD_t *rxdp = NULL;
7046 struct sk_buff *skb = NULL;
7047 struct buffAdd *ba = NULL;
7048 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7050 /* Calculate the size based on ring mode */
7051 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7052 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7053 if (sp->rxd_mode == RXD_MODE_1)
7054 size += NET_IP_ALIGN;
7055 else if (sp->rxd_mode == RXD_MODE_3B)
7056 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
7058 for (i = 0; i < config->rx_ring_num; i++) {
7059 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7060 struct ring_info *ring = &mac_control->rings[i];
7062 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
7064 for (j = 0; j < blk_cnt; j++) {
7065 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7066 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7067 if (sp->rxd_mode == RXD_MODE_3B)
7068 ba = &ring->ba[j][k];
7069 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7077 set_rxd_buffer_size(sp, rxdp, size);
7079 /* flip the Ownership bit to Hardware */
7080 rxdp->Control_1 |= RXD_OWN_XENA;
7088 static int s2io_add_isr(struct s2io_nic *sp)
7091 struct net_device *dev = sp->dev;
7094 if (sp->config.intr_type == MSI_X)
7095 ret = s2io_enable_msi_x(sp);
7097 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7098 sp->config.intr_type = INTA;
7102 * Store the values of the MSIX table in
7103 * the struct s2io_nic structure
7105 store_xmsi_data(sp);
7107 /* After proper initialization of H/W, register ISR */
7108 if (sp->config.intr_type == MSI_X) {
7109 int i, msix_rx_cnt = 0;
7111 for (i = 0; i < sp->num_entries; i++) {
7112 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7113 if (sp->s2io_entries[i].type ==
7115 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7117 err = request_irq(sp->entries[i].vector,
7118 s2io_msix_ring_handle,
7121 sp->s2io_entries[i].arg);
7122 } else if (sp->s2io_entries[i].type ==
7124 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7126 err = request_irq(sp->entries[i].vector,
7127 s2io_msix_fifo_handle,
7130 sp->s2io_entries[i].arg);
7133 /* if either data or addr is zero print it. */
7134 if (!(sp->msix_info[i].addr &&
7135 sp->msix_info[i].data)) {
7137 "%s @Addr:0x%llx Data:0x%llx\n",
7139 (unsigned long long)
7140 sp->msix_info[i].addr,
7141 (unsigned long long)
7142 ntohl(sp->msix_info[i].data));
7146 remove_msix_isr(sp);
7149 "%s:MSI-X-%d registration "
7150 "failed\n", dev->name, i);
7153 "%s: Defaulting to INTA\n",
7155 sp->config.intr_type = INTA;
7158 sp->s2io_entries[i].in_use =
7159 MSIX_REGISTERED_SUCCESS;
7163 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7165 "MSI-X-TX entries enabled through alarm vector\n");
7168 if (sp->config.intr_type == INTA) {
7169 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7172 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7180 static void s2io_rem_isr(struct s2io_nic *sp)
7182 if (sp->config.intr_type == MSI_X)
7183 remove_msix_isr(sp);
7185 remove_inta_isr(sp);
7188 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7191 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7192 register u64 val64 = 0;
7193 struct config_param *config;
7194 config = &sp->config;
7196 if (!is_s2io_card_up(sp))
7199 del_timer_sync(&sp->alarm_timer);
7200 /* If s2io_set_link task is executing, wait till it completes. */
7201 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7203 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7206 if (sp->config.napi) {
7208 if (config->intr_type == MSI_X) {
7209 for (; off < sp->config.rx_ring_num; off++)
7210 napi_disable(&sp->mac_control.rings[off].napi);
7213 napi_disable(&sp->napi);
7216 /* disable Tx and Rx traffic on the NIC */
7222 /* stop the tx queue, indicate link down */
7223 s2io_link(sp, LINK_DOWN);
7225 /* Check if the device is Quiescent and then Reset the NIC */
7227 /* As per the HW requirement we need to replenish the
7228 * receive buffer to avoid the ring bump. Since there is
7229 * no intention of processing the Rx frame at this pointwe are
7230 * just settting the ownership bit of rxd in Each Rx
7231 * ring to HW and set the appropriate buffer size
7232 * based on the ring mode
7234 rxd_owner_bit_reset(sp);
7236 val64 = readq(&bar0->adapter_status);
7237 if (verify_xena_quiescence(sp)) {
7238 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7245 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7246 "adapter status reads 0x%llx\n",
7247 (unsigned long long)val64);
7254 /* Free all Tx buffers */
7255 free_tx_buffers(sp);
7257 /* Free all Rx buffers */
7258 free_rx_buffers(sp);
7260 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7263 static void s2io_card_down(struct s2io_nic *sp)
7265 do_s2io_card_down(sp, 1);
7268 static int s2io_card_up(struct s2io_nic *sp)
7271 struct config_param *config;
7272 struct mac_info *mac_control;
7273 struct net_device *dev = (struct net_device *)sp->dev;
7276 /* Initialize the H/W I/O registers */
7279 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7287 * Initializing the Rx buffers. For now we are considering only 1
7288 * Rx ring and initializing buffers into 30 Rx blocks
7290 config = &sp->config;
7291 mac_control = &sp->mac_control;
7293 for (i = 0; i < config->rx_ring_num; i++) {
7294 struct ring_info *ring = &mac_control->rings[i];
7296 ring->mtu = dev->mtu;
7297 ring->lro = !!(dev->features & NETIF_F_LRO);
7298 ret = fill_rx_buffers(sp, ring, 1);
7300 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7303 free_rx_buffers(sp);
7306 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7307 ring->rx_bufs_left);
7310 /* Initialise napi */
7312 if (config->intr_type == MSI_X) {
7313 for (i = 0; i < sp->config.rx_ring_num; i++)
7314 napi_enable(&sp->mac_control.rings[i].napi);
7316 napi_enable(&sp->napi);
7320 /* Maintain the state prior to the open */
7321 if (sp->promisc_flg)
7322 sp->promisc_flg = 0;
7323 if (sp->m_cast_flg) {
7325 sp->all_multi_pos = 0;
7328 /* Setting its receive mode */
7329 s2io_set_multicast(dev);
7331 if (dev->features & NETIF_F_LRO) {
7332 /* Initialize max aggregatable pkts per session based on MTU */
7333 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7334 /* Check if we can use (if specified) user provided value */
7335 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7336 sp->lro_max_aggr_per_sess = lro_max_pkts;
7339 /* Enable Rx Traffic and interrupts on the NIC */
7340 if (start_nic(sp)) {
7341 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7343 free_rx_buffers(sp);
7347 /* Add interrupt service routine */
7348 if (s2io_add_isr(sp) != 0) {
7349 if (sp->config.intr_type == MSI_X)
7352 free_rx_buffers(sp);
7356 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7358 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7360 /* Enable select interrupts */
7361 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7362 if (sp->config.intr_type != INTA) {
7363 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7364 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7366 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7367 interruptible |= TX_PIC_INTR;
7368 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7375 * s2io_restart_nic - Resets the NIC.
7376 * @data : long pointer to the device private structure
7378 * This function is scheduled to be run by the s2io_tx_watchdog
7379 * function after 0.5 secs to reset the NIC. The idea is to reduce
7380 * the run time of the watch dog routine which is run holding a
7384 static void s2io_restart_nic(struct work_struct *work)
7386 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7387 struct net_device *dev = sp->dev;
7391 if (!netif_running(dev))
7395 if (s2io_card_up(sp)) {
7396 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7398 s2io_wake_all_tx_queue(sp);
7399 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7405 * s2io_tx_watchdog - Watchdog for transmit side.
7406 * @dev : Pointer to net device structure
7408 * This function is triggered if the Tx Queue is stopped
7409 * for a pre-defined amount of time when the Interface is still up.
7410 * If the Interface is jammed in such a situation, the hardware is
7411 * reset (by s2io_close) and restarted again (by s2io_open) to
7412 * overcome any problem that might have been caused in the hardware.
7417 static void s2io_tx_watchdog(struct net_device *dev)
7419 struct s2io_nic *sp = netdev_priv(dev);
7420 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7422 if (netif_carrier_ok(dev)) {
7423 swstats->watchdog_timer_cnt++;
7424 schedule_work(&sp->rst_timer_task);
7425 swstats->soft_reset_cnt++;
7430 * rx_osm_handler - To perform some OS related operations on SKB.
7431 * @sp: private member of the device structure,pointer to s2io_nic structure.
7432 * @skb : the socket buffer pointer.
7433 * @len : length of the packet
7434 * @cksum : FCS checksum of the frame.
7435 * @ring_no : the ring from which this RxD was extracted.
7437 * This function is called by the Rx interrupt serivce routine to perform
7438 * some OS related operations on the SKB before passing it to the upper
7439 * layers. It mainly checks if the checksum is OK, if so adds it to the
7440 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7441 * to the upper layer. If the checksum is wrong, it increments the Rx
7442 * packet error count, frees the SKB and returns error.
7444 * SUCCESS on success and -1 on failure.
7446 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7448 struct s2io_nic *sp = ring_data->nic;
7449 struct net_device *dev = (struct net_device *)ring_data->dev;
7450 struct sk_buff *skb = (struct sk_buff *)
7451 ((unsigned long)rxdp->Host_Control);
7452 int ring_no = ring_data->ring_no;
7453 u16 l3_csum, l4_csum;
7454 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7455 struct lro *uninitialized_var(lro);
7457 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7462 /* Check for parity error */
7464 swstats->parity_err_cnt++;
7466 err_mask = err >> 48;
7469 swstats->rx_parity_err_cnt++;
7473 swstats->rx_abort_cnt++;
7477 swstats->rx_parity_abort_cnt++;
7481 swstats->rx_rda_fail_cnt++;
7485 swstats->rx_unkn_prot_cnt++;
7489 swstats->rx_fcs_err_cnt++;
7493 swstats->rx_buf_size_err_cnt++;
7497 swstats->rx_rxd_corrupt_cnt++;
7501 swstats->rx_unkn_err_cnt++;
7505 * Drop the packet if bad transfer code. Exception being
7506 * 0x5, which could be due to unsupported IPv6 extension header.
7507 * In this case, we let stack handle the packet.
7508 * Note that in this case, since checksum will be incorrect,
7509 * stack will validate the same.
7511 if (err_mask != 0x5) {
7512 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7513 dev->name, err_mask);
7514 dev->stats.rx_crc_errors++;
7518 ring_data->rx_bufs_left -= 1;
7519 rxdp->Host_Control = 0;
7524 rxdp->Host_Control = 0;
7525 if (sp->rxd_mode == RXD_MODE_1) {
7526 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7529 } else if (sp->rxd_mode == RXD_MODE_3B) {
7530 int get_block = ring_data->rx_curr_get_info.block_index;
7531 int get_off = ring_data->rx_curr_get_info.offset;
7532 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7533 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7534 unsigned char *buff = skb_push(skb, buf0_len);
7536 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7537 memcpy(buff, ba->ba_0, buf0_len);
7538 skb_put(skb, buf2_len);
7541 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7542 ((!ring_data->lro) ||
7543 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7545 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7546 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7547 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7549 * NIC verifies if the Checksum of the received
7550 * frame is Ok or not and accordingly returns
7551 * a flag in the RxD.
7553 skb->ip_summed = CHECKSUM_UNNECESSARY;
7554 if (ring_data->lro) {
7559 ret = s2io_club_tcp_session(ring_data,
7564 case 3: /* Begin anew */
7567 case 1: /* Aggregate */
7568 lro_append_pkt(sp, lro, skb, tcp_len);
7570 case 4: /* Flush session */
7571 lro_append_pkt(sp, lro, skb, tcp_len);
7572 queue_rx_frame(lro->parent,
7574 clear_lro_session(lro);
7575 swstats->flush_max_pkts++;
7577 case 2: /* Flush both */
7578 lro->parent->data_len = lro->frags_len;
7579 swstats->sending_both++;
7580 queue_rx_frame(lro->parent,
7582 clear_lro_session(lro);
7584 case 0: /* sessions exceeded */
7585 case -1: /* non-TCP or not L2 aggregatable */
7587 * First pkt in session not
7588 * L3/L4 aggregatable
7593 "%s: Samadhana!!\n",
7600 * Packet with erroneous checksum, let the
7601 * upper layers deal with it.
7603 skb_checksum_none_assert(skb);
7606 skb_checksum_none_assert(skb);
7608 swstats->mem_freed += skb->truesize;
7610 skb_record_rx_queue(skb, ring_no);
7611 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7613 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7618 * s2io_link - stops/starts the Tx queue.
7619 * @sp : private member of the device structure, which is a pointer to the
7620 * s2io_nic structure.
7621 * @link : inidicates whether link is UP/DOWN.
7623 * This function stops/starts the Tx queue depending on whether the link
7624 * status of the NIC is is down or up. This is called by the Alarm
7625 * interrupt handler whenever a link change interrupt comes up.
7630 static void s2io_link(struct s2io_nic *sp, int link)
7632 struct net_device *dev = (struct net_device *)sp->dev;
7633 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7635 if (link != sp->last_link_state) {
7637 if (link == LINK_DOWN) {
7638 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7639 s2io_stop_all_tx_queue(sp);
7640 netif_carrier_off(dev);
7641 if (swstats->link_up_cnt)
7642 swstats->link_up_time =
7643 jiffies - sp->start_time;
7644 swstats->link_down_cnt++;
7646 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7647 if (swstats->link_down_cnt)
7648 swstats->link_down_time =
7649 jiffies - sp->start_time;
7650 swstats->link_up_cnt++;
7651 netif_carrier_on(dev);
7652 s2io_wake_all_tx_queue(sp);
7655 sp->last_link_state = link;
7656 sp->start_time = jiffies;
7660 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7661 * @sp : private member of the device structure, which is a pointer to the
7662 * s2io_nic structure.
7664 * This function initializes a few of the PCI and PCI-X configuration registers
7665 * with recommended values.
7670 static void s2io_init_pci(struct s2io_nic *sp)
7672 u16 pci_cmd = 0, pcix_cmd = 0;
7674 /* Enable Data Parity Error Recovery in PCI-X command register. */
7675 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7677 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7679 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7682 /* Set the PErr Response bit in PCI command register. */
7683 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7684 pci_write_config_word(sp->pdev, PCI_COMMAND,
7685 (pci_cmd | PCI_COMMAND_PARITY));
7686 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7689 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7694 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7695 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7696 "(%d) not supported\n", tx_fifo_num);
7698 if (tx_fifo_num < 1)
7701 tx_fifo_num = MAX_TX_FIFOS;
7703 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7707 *dev_multiq = multiq;
7709 if (tx_steering_type && (1 == tx_fifo_num)) {
7710 if (tx_steering_type != TX_DEFAULT_STEERING)
7712 "Tx steering is not supported with "
7713 "one fifo. Disabling Tx steering.\n");
7714 tx_steering_type = NO_STEERING;
7717 if ((tx_steering_type < NO_STEERING) ||
7718 (tx_steering_type > TX_DEFAULT_STEERING)) {
7720 "Requested transmit steering not supported\n");
7721 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7722 tx_steering_type = NO_STEERING;
7725 if (rx_ring_num > MAX_RX_RINGS) {
7727 "Requested number of rx rings not supported\n");
7728 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7730 rx_ring_num = MAX_RX_RINGS;
7733 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7734 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7735 "Defaulting to INTA\n");
7736 *dev_intr_type = INTA;
7739 if ((*dev_intr_type == MSI_X) &&
7740 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7741 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7742 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7743 "Defaulting to INTA\n");
7744 *dev_intr_type = INTA;
7747 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7748 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7749 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7753 for (i = 0; i < MAX_RX_RINGS; i++)
7754 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7755 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7756 "supported\nDefaulting to %d\n",
7757 MAX_RX_BLOCKS_PER_RING);
7758 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7765 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7766 * or Traffic class respectively.
7767 * @nic: device private variable
7768 * Description: The function configures the receive steering to
7769 * desired receive ring.
7770 * Return Value: SUCCESS on success and
7771 * '-1' on failure (endian settings incorrect).
7773 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7775 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7776 register u64 val64 = 0;
7778 if (ds_codepoint > 63)
7781 val64 = RTS_DS_MEM_DATA(ring);
7782 writeq(val64, &bar0->rts_ds_mem_data);
7784 val64 = RTS_DS_MEM_CTRL_WE |
7785 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7786 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7788 writeq(val64, &bar0->rts_ds_mem_ctrl);
7790 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7791 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7795 static const struct net_device_ops s2io_netdev_ops = {
7796 .ndo_open = s2io_open,
7797 .ndo_stop = s2io_close,
7798 .ndo_get_stats = s2io_get_stats,
7799 .ndo_start_xmit = s2io_xmit,
7800 .ndo_validate_addr = eth_validate_addr,
7801 .ndo_set_multicast_list = s2io_set_multicast,
7802 .ndo_do_ioctl = s2io_ioctl,
7803 .ndo_set_mac_address = s2io_set_mac_addr,
7804 .ndo_change_mtu = s2io_change_mtu,
7805 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7806 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7807 .ndo_tx_timeout = s2io_tx_watchdog,
7808 #ifdef CONFIG_NET_POLL_CONTROLLER
7809 .ndo_poll_controller = s2io_netpoll,
7814 * s2io_init_nic - Initialization of the adapter .
7815 * @pdev : structure containing the PCI related information of the device.
7816 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7818 * The function initializes an adapter identified by the pci_dec structure.
7819 * All OS related initialization including memory and device structure and
7820 * initlaization of the device private variable is done. Also the swapper
7821 * control register is initialized to enable read and write into the I/O
7822 * registers of the device.
7824 * returns 0 on success and negative on failure.
7827 static int __devinit
7828 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7830 struct s2io_nic *sp;
7831 struct net_device *dev;
7833 int dma_flag = false;
7834 u32 mac_up, mac_down;
7835 u64 val64 = 0, tmp64 = 0;
7836 struct XENA_dev_config __iomem *bar0 = NULL;
7838 struct config_param *config;
7839 struct mac_info *mac_control;
7841 u8 dev_intr_type = intr_type;
7844 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7848 ret = pci_enable_device(pdev);
7851 "%s: pci_enable_device failed\n", __func__);
7855 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7856 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7858 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7860 "Unable to obtain 64bit DMA "
7861 "for consistent allocations\n");
7862 pci_disable_device(pdev);
7865 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7866 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7868 pci_disable_device(pdev);
7871 ret = pci_request_regions(pdev, s2io_driver_name);
7873 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7875 pci_disable_device(pdev);
7879 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7881 dev = alloc_etherdev(sizeof(struct s2io_nic));
7883 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7884 pci_disable_device(pdev);
7885 pci_release_regions(pdev);
7889 pci_set_master(pdev);
7890 pci_set_drvdata(pdev, dev);
7891 SET_NETDEV_DEV(dev, &pdev->dev);
7893 /* Private member variable initialized to s2io NIC structure */
7894 sp = netdev_priv(dev);
7897 sp->high_dma_flag = dma_flag;
7898 sp->device_enabled_once = false;
7899 if (rx_ring_mode == 1)
7900 sp->rxd_mode = RXD_MODE_1;
7901 if (rx_ring_mode == 2)
7902 sp->rxd_mode = RXD_MODE_3B;
7904 sp->config.intr_type = dev_intr_type;
7906 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7907 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7908 sp->device_type = XFRAME_II_DEVICE;
7910 sp->device_type = XFRAME_I_DEVICE;
7913 /* Initialize some PCI/PCI-X fields of the NIC. */
7917 * Setting the device configuration parameters.
7918 * Most of these parameters can be specified by the user during
7919 * module insertion as they are module loadable parameters. If
7920 * these parameters are not not specified during load time, they
7921 * are initialized with default values.
7923 config = &sp->config;
7924 mac_control = &sp->mac_control;
7926 config->napi = napi;
7927 config->tx_steering_type = tx_steering_type;
7929 /* Tx side parameters. */
7930 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7931 config->tx_fifo_num = MAX_TX_FIFOS;
7933 config->tx_fifo_num = tx_fifo_num;
7935 /* Initialize the fifos used for tx steering */
7936 if (config->tx_fifo_num < 5) {
7937 if (config->tx_fifo_num == 1)
7938 sp->total_tcp_fifos = 1;
7940 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7941 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7942 sp->total_udp_fifos = 1;
7943 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7945 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7946 FIFO_OTHER_MAX_NUM);
7947 sp->udp_fifo_idx = sp->total_tcp_fifos;
7948 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7949 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7952 config->multiq = dev_multiq;
7953 for (i = 0; i < config->tx_fifo_num; i++) {
7954 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7956 tx_cfg->fifo_len = tx_fifo_len[i];
7957 tx_cfg->fifo_priority = i;
7960 /* mapping the QoS priority to the configured fifos */
7961 for (i = 0; i < MAX_TX_FIFOS; i++)
7962 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7964 /* map the hashing selector table to the configured fifos */
7965 for (i = 0; i < config->tx_fifo_num; i++)
7966 sp->fifo_selector[i] = fifo_selector[i];
7969 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7970 for (i = 0; i < config->tx_fifo_num; i++) {
7971 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7973 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7974 if (tx_cfg->fifo_len < 65) {
7975 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7979 /* + 2 because one Txd for skb->data and one Txd for UFO */
7980 config->max_txds = MAX_SKB_FRAGS + 2;
7982 /* Rx side parameters. */
7983 config->rx_ring_num = rx_ring_num;
7984 for (i = 0; i < config->rx_ring_num; i++) {
7985 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7986 struct ring_info *ring = &mac_control->rings[i];
7988 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7989 rx_cfg->ring_priority = i;
7990 ring->rx_bufs_left = 0;
7991 ring->rxd_mode = sp->rxd_mode;
7992 ring->rxd_count = rxd_count[sp->rxd_mode];
7993 ring->pdev = sp->pdev;
7994 ring->dev = sp->dev;
7997 for (i = 0; i < rx_ring_num; i++) {
7998 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
8000 rx_cfg->ring_org = RING_ORG_BUFF1;
8001 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
8004 /* Setting Mac Control parameters */
8005 mac_control->rmac_pause_time = rmac_pause_time;
8006 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
8007 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
8010 /* initialize the shared memory used by the NIC and the host */
8011 if (init_shared_mem(sp)) {
8012 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
8014 goto mem_alloc_failed;
8017 sp->bar0 = pci_ioremap_bar(pdev, 0);
8019 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
8022 goto bar0_remap_failed;
8025 sp->bar1 = pci_ioremap_bar(pdev, 2);
8027 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
8030 goto bar1_remap_failed;
8033 dev->irq = pdev->irq;
8034 dev->base_addr = (unsigned long)sp->bar0;
8036 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8037 for (j = 0; j < MAX_TX_FIFOS; j++) {
8038 mac_control->tx_FIFO_start[j] =
8039 (struct TxFIFO_element __iomem *)
8040 (sp->bar1 + (j * 0x00020000));
8043 /* Driver entry points */
8044 dev->netdev_ops = &s2io_netdev_ops;
8045 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
8046 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8047 dev->features |= NETIF_F_LRO;
8048 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8049 if (sp->high_dma_flag == true)
8050 dev->features |= NETIF_F_HIGHDMA;
8051 dev->features |= NETIF_F_TSO;
8052 dev->features |= NETIF_F_TSO6;
8053 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
8054 dev->features |= NETIF_F_UFO;
8055 dev->features |= NETIF_F_HW_CSUM;
8057 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
8058 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8059 INIT_WORK(&sp->set_link_task, s2io_set_link);
8061 pci_save_state(sp->pdev);
8063 /* Setting swapper control on the NIC, for proper reset operation */
8064 if (s2io_set_swapper(sp)) {
8065 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
8068 goto set_swap_failed;
8071 /* Verify if the Herc works on the slot its placed into */
8072 if (sp->device_type & XFRAME_II_DEVICE) {
8073 mode = s2io_verify_pci_mode(sp);
8075 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8078 goto set_swap_failed;
8082 if (sp->config.intr_type == MSI_X) {
8083 sp->num_entries = config->rx_ring_num + 1;
8084 ret = s2io_enable_msi_x(sp);
8087 ret = s2io_test_msi(sp);
8088 /* rollback MSI-X, will re-enable during add_isr() */
8089 remove_msix_isr(sp);
8094 "MSI-X requested but failed to enable\n");
8095 sp->config.intr_type = INTA;
8099 if (config->intr_type == MSI_X) {
8100 for (i = 0; i < config->rx_ring_num ; i++) {
8101 struct ring_info *ring = &mac_control->rings[i];
8103 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8106 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8109 /* Not needed for Herc */
8110 if (sp->device_type & XFRAME_I_DEVICE) {
8112 * Fix for all "FFs" MAC address problems observed on
8115 fix_mac_address(sp);
8120 * MAC address initialization.
8121 * For now only one mac address will be read and used.
8124 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8125 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8126 writeq(val64, &bar0->rmac_addr_cmd_mem);
8127 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8128 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8130 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8131 mac_down = (u32)tmp64;
8132 mac_up = (u32) (tmp64 >> 32);
8134 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8135 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8136 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8137 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8138 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8139 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8141 /* Set the factory defined MAC address initially */
8142 dev->addr_len = ETH_ALEN;
8143 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8144 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8146 /* initialize number of multicast & unicast MAC entries variables */
8147 if (sp->device_type == XFRAME_I_DEVICE) {
8148 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8149 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8150 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8151 } else if (sp->device_type == XFRAME_II_DEVICE) {
8152 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8153 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8154 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8157 /* store mac addresses from CAM to s2io_nic structure */
8158 do_s2io_store_unicast_mc(sp);
8160 /* Configure MSIX vector for number of rings configured plus one */
8161 if ((sp->device_type == XFRAME_II_DEVICE) &&
8162 (config->intr_type == MSI_X))
8163 sp->num_entries = config->rx_ring_num + 1;
8165 /* Store the values of the MSIX table in the s2io_nic structure */
8166 store_xmsi_data(sp);
8167 /* reset Nic and bring it to known state */
8171 * Initialize link state flags
8172 * and the card state parameter
8176 /* Initialize spinlocks */
8177 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8178 struct fifo_info *fifo = &mac_control->fifos[i];
8180 spin_lock_init(&fifo->tx_lock);
8184 * SXE-002: Configure link and activity LED to init state
8187 subid = sp->pdev->subsystem_device;
8188 if ((subid & 0xFF) >= 0x07) {
8189 val64 = readq(&bar0->gpio_control);
8190 val64 |= 0x0000800000000000ULL;
8191 writeq(val64, &bar0->gpio_control);
8192 val64 = 0x0411040400000000ULL;
8193 writeq(val64, (void __iomem *)bar0 + 0x2700);
8194 val64 = readq(&bar0->gpio_control);
8197 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8199 if (register_netdev(dev)) {
8200 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8202 goto register_failed;
8205 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8206 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8207 sp->product_name, pdev->revision);
8208 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8209 s2io_driver_version);
8210 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8211 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8212 if (sp->device_type & XFRAME_II_DEVICE) {
8213 mode = s2io_print_pci_mode(sp);
8216 unregister_netdev(dev);
8217 goto set_swap_failed;
8220 switch (sp->rxd_mode) {
8222 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8226 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8231 switch (sp->config.napi) {
8233 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8236 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8240 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8241 sp->config.tx_fifo_num);
8243 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8244 sp->config.rx_ring_num);
8246 switch (sp->config.intr_type) {
8248 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8251 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8254 if (sp->config.multiq) {
8255 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8256 struct fifo_info *fifo = &mac_control->fifos[i];
8258 fifo->multiq = config->multiq;
8260 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8263 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8266 switch (sp->config.tx_steering_type) {
8268 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8271 case TX_PRIORITY_STEERING:
8273 "%s: Priority steering enabled for transmit\n",
8276 case TX_DEFAULT_STEERING:
8278 "%s: Default steering enabled for transmit\n",
8282 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8286 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8288 /* Initialize device name */
8289 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8292 sp->vlan_strip_flag = 1;
8294 sp->vlan_strip_flag = 0;
8297 * Make Link state as off at this point, when the Link change
8298 * interrupt comes the state will be automatically changed to
8301 netif_carrier_off(dev);
8312 free_shared_mem(sp);
8313 pci_disable_device(pdev);
8314 pci_release_regions(pdev);
8315 pci_set_drvdata(pdev, NULL);
8322 * s2io_rem_nic - Free the PCI device
8323 * @pdev: structure containing the PCI related information of the device.
8324 * Description: This function is called by the Pci subsystem to release a
8325 * PCI device and free up all resource held up by the device. This could
8326 * be in response to a Hot plug event or when the driver is to be removed
8330 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8332 struct net_device *dev = pci_get_drvdata(pdev);
8333 struct s2io_nic *sp;
8336 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8340 sp = netdev_priv(dev);
8342 cancel_work_sync(&sp->rst_timer_task);
8343 cancel_work_sync(&sp->set_link_task);
8345 unregister_netdev(dev);
8347 free_shared_mem(sp);
8350 pci_release_regions(pdev);
8351 pci_set_drvdata(pdev, NULL);
8353 pci_disable_device(pdev);
8357 * s2io_starter - Entry point for the driver
8358 * Description: This function is the entry point for the driver. It verifies
8359 * the module loadable parameters and initializes PCI configuration space.
8362 static int __init s2io_starter(void)
8364 return pci_register_driver(&s2io_driver);
8368 * s2io_closer - Cleanup routine for the driver
8369 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8372 static __exit void s2io_closer(void)
8374 pci_unregister_driver(&s2io_driver);
8375 DBG_PRINT(INIT_DBG, "cleanup done\n");
8378 module_init(s2io_starter);
8379 module_exit(s2io_closer);
8381 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8382 struct tcphdr **tcp, struct RxD_t *rxdp,
8383 struct s2io_nic *sp)
8386 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8388 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8390 "%s: Non-TCP frames not supported for LRO\n",
8395 /* Checking for DIX type or DIX type with VLAN */
8396 if ((l2_type == 0) || (l2_type == 4)) {
8397 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8399 * If vlan stripping is disabled and the frame is VLAN tagged,
8400 * shift the offset by the VLAN header size bytes.
8402 if ((!sp->vlan_strip_flag) &&
8403 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8404 ip_off += HEADER_VLAN_SIZE;
8406 /* LLC, SNAP etc are considered non-mergeable */
8410 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8411 ip_len = (u8)((*ip)->ihl);
8413 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8418 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8421 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8422 if ((lro->iph->saddr != ip->saddr) ||
8423 (lro->iph->daddr != ip->daddr) ||
8424 (lro->tcph->source != tcp->source) ||
8425 (lro->tcph->dest != tcp->dest))
8430 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8432 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8435 static void initiate_new_session(struct lro *lro, u8 *l2h,
8436 struct iphdr *ip, struct tcphdr *tcp,
8437 u32 tcp_pyld_len, u16 vlan_tag)
8439 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8443 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8444 lro->tcp_ack = tcp->ack_seq;
8446 lro->total_len = ntohs(ip->tot_len);
8448 lro->vlan_tag = vlan_tag;
8450 * Check if we saw TCP timestamp.
8451 * Other consistency checks have already been done.
8453 if (tcp->doff == 8) {
8455 ptr = (__be32 *)(tcp+1);
8457 lro->cur_tsval = ntohl(*(ptr+1));
8458 lro->cur_tsecr = *(ptr+2);
8463 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8465 struct iphdr *ip = lro->iph;
8466 struct tcphdr *tcp = lro->tcph;
8468 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8470 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8472 /* Update L3 header */
8473 ip->tot_len = htons(lro->total_len);
8475 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8478 /* Update L4 header */
8479 tcp->ack_seq = lro->tcp_ack;
8480 tcp->window = lro->window;
8482 /* Update tsecr field if this session has timestamps enabled */
8484 __be32 *ptr = (__be32 *)(tcp + 1);
8485 *(ptr+2) = lro->cur_tsecr;
8488 /* Update counters required for calculation of
8489 * average no. of packets aggregated.
8491 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8492 swstats->num_aggregations++;
8495 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8496 struct tcphdr *tcp, u32 l4_pyld)
8498 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8499 lro->total_len += l4_pyld;
8500 lro->frags_len += l4_pyld;
8501 lro->tcp_next_seq += l4_pyld;
8504 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8505 lro->tcp_ack = tcp->ack_seq;
8506 lro->window = tcp->window;
8510 /* Update tsecr and tsval from this packet */
8511 ptr = (__be32 *)(tcp+1);
8512 lro->cur_tsval = ntohl(*(ptr+1));
8513 lro->cur_tsecr = *(ptr + 2);
8517 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8518 struct tcphdr *tcp, u32 tcp_pyld_len)
8522 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8524 if (!tcp_pyld_len) {
8525 /* Runt frame or a pure ack */
8529 if (ip->ihl != 5) /* IP has options */
8532 /* If we see CE codepoint in IP header, packet is not mergeable */
8533 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8536 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8537 if (tcp->urg || tcp->psh || tcp->rst ||
8538 tcp->syn || tcp->fin ||
8539 tcp->ece || tcp->cwr || !tcp->ack) {
8541 * Currently recognize only the ack control word and
8542 * any other control field being set would result in
8543 * flushing the LRO session
8549 * Allow only one TCP timestamp option. Don't aggregate if
8550 * any other options are detected.
8552 if (tcp->doff != 5 && tcp->doff != 8)
8555 if (tcp->doff == 8) {
8556 ptr = (u8 *)(tcp + 1);
8557 while (*ptr == TCPOPT_NOP)
8559 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8562 /* Ensure timestamp value increases monotonically */
8564 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8567 /* timestamp echo reply should be non-zero */
8568 if (*((__be32 *)(ptr+6)) == 0)
8575 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8576 u8 **tcp, u32 *tcp_len, struct lro **lro,
8577 struct RxD_t *rxdp, struct s2io_nic *sp)
8580 struct tcphdr *tcph;
8583 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8585 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8590 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8592 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8593 tcph = (struct tcphdr *)*tcp;
8594 *tcp_len = get_l4_pyld_length(ip, tcph);
8595 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8596 struct lro *l_lro = &ring_data->lro0_n[i];
8597 if (l_lro->in_use) {
8598 if (check_for_socket_match(l_lro, ip, tcph))
8600 /* Sock pair matched */
8603 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8604 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8605 "expected 0x%x, actual 0x%x\n",
8607 (*lro)->tcp_next_seq,
8610 swstats->outof_sequence_pkts++;
8615 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8617 ret = 1; /* Aggregate */
8619 ret = 2; /* Flush both */
8625 /* Before searching for available LRO objects,
8626 * check if the pkt is L3/L4 aggregatable. If not
8627 * don't create new LRO session. Just send this
8630 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8633 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8634 struct lro *l_lro = &ring_data->lro0_n[i];
8635 if (!(l_lro->in_use)) {
8637 ret = 3; /* Begin anew */
8643 if (ret == 0) { /* sessions exceeded */
8644 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8652 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8656 update_L3L4_header(sp, *lro);
8659 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8660 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8661 update_L3L4_header(sp, *lro);
8662 ret = 4; /* Flush the LRO */
8666 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8673 static void clear_lro_session(struct lro *lro)
8675 static u16 lro_struct_size = sizeof(struct lro);
8677 memset(lro, 0, lro_struct_size);
8680 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8682 struct net_device *dev = skb->dev;
8683 struct s2io_nic *sp = netdev_priv(dev);
8685 skb->protocol = eth_type_trans(skb, dev);
8686 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8687 /* Queueing the vlan frame to the upper layer */
8688 if (sp->config.napi)
8689 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8691 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8693 if (sp->config.napi)
8694 netif_receive_skb(skb);
8700 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8701 struct sk_buff *skb, u32 tcp_len)
8703 struct sk_buff *first = lro->parent;
8704 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8706 first->len += tcp_len;
8707 first->data_len = lro->frags_len;
8708 skb_pull(skb, (skb->len - tcp_len));
8709 if (skb_shinfo(first)->frag_list)
8710 lro->last_frag->next = skb;
8712 skb_shinfo(first)->frag_list = skb;
8713 first->truesize += skb->truesize;
8714 lro->last_frag = skb;
8715 swstats->clubbed_frms_cnt++;
8719 * s2io_io_error_detected - called when PCI error is detected
8720 * @pdev: Pointer to PCI device
8721 * @state: The current pci connection state
8723 * This function is called after a PCI bus error affecting
8724 * this device has been detected.
8726 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8727 pci_channel_state_t state)
8729 struct net_device *netdev = pci_get_drvdata(pdev);
8730 struct s2io_nic *sp = netdev_priv(netdev);
8732 netif_device_detach(netdev);
8734 if (state == pci_channel_io_perm_failure)
8735 return PCI_ERS_RESULT_DISCONNECT;
8737 if (netif_running(netdev)) {
8738 /* Bring down the card, while avoiding PCI I/O */
8739 do_s2io_card_down(sp, 0);
8741 pci_disable_device(pdev);
8743 return PCI_ERS_RESULT_NEED_RESET;
8747 * s2io_io_slot_reset - called after the pci bus has been reset.
8748 * @pdev: Pointer to PCI device
8750 * Restart the card from scratch, as if from a cold-boot.
8751 * At this point, the card has exprienced a hard reset,
8752 * followed by fixups by BIOS, and has its config space
8753 * set up identically to what it was at cold boot.
8755 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8757 struct net_device *netdev = pci_get_drvdata(pdev);
8758 struct s2io_nic *sp = netdev_priv(netdev);
8760 if (pci_enable_device(pdev)) {
8761 pr_err("Cannot re-enable PCI device after reset.\n");
8762 return PCI_ERS_RESULT_DISCONNECT;
8765 pci_set_master(pdev);
8768 return PCI_ERS_RESULT_RECOVERED;
8772 * s2io_io_resume - called when traffic can start flowing again.
8773 * @pdev: Pointer to PCI device
8775 * This callback is called when the error recovery driver tells
8776 * us that its OK to resume normal operation.
8778 static void s2io_io_resume(struct pci_dev *pdev)
8780 struct net_device *netdev = pci_get_drvdata(pdev);
8781 struct s2io_nic *sp = netdev_priv(netdev);
8783 if (netif_running(netdev)) {
8784 if (s2io_card_up(sp)) {
8785 pr_err("Can't bring device back up after reset.\n");
8789 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8791 pr_err("Can't restore mac addr after reset.\n");
8796 netif_device_attach(netdev);
8797 netif_tx_wake_all_queues(netdev);
projects / linux-2.6-block.git / blob