2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
97 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
98 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
99 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
100 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
101 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
102 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
103 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
104 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
105 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
106 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
107 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
108 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
109 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
110 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
111 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
112 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
113 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
114 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
115 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
116 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
117 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
118 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
119 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
120 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
121 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
166 static void rtl_hw_start_8169(struct net_device *);
167 static void rtl_hw_start_8168(struct net_device *);
168 static void rtl_hw_start_8101(struct net_device *);
170 static struct pci_device_id rtl8169_pci_tbl[] = {
171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
179 { PCI_VENDOR_ID_LINKSYS, 0x1032,
180 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
182 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
186 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188 static int rx_copybreak = 200;
195 MAC0 = 0, /* Ethernet hardware address. */
197 MAR0 = 8, /* Multicast filter. */
198 CounterAddrLow = 0x10,
199 CounterAddrHigh = 0x14,
200 TxDescStartAddrLow = 0x20,
201 TxDescStartAddrHigh = 0x24,
202 TxHDescStartAddrLow = 0x28,
203 TxHDescStartAddrHigh = 0x2c,
226 RxDescAddrLow = 0xe4,
227 RxDescAddrHigh = 0xe8,
230 FuncEventMask = 0xf4,
231 FuncPresetState = 0xf8,
232 FuncForceEvent = 0xfc,
235 enum rtl8110_registers {
241 enum rtl8168_8101_registers {
244 #define CSIAR_FLAG 0x80000000
245 #define CSIAR_WRITE_CMD 0x80000000
246 #define CSIAR_BYTE_ENABLE 0x0f
247 #define CSIAR_BYTE_ENABLE_SHIFT 12
248 #define CSIAR_ADDR_MASK 0x0fff
251 #define EPHYAR_FLAG 0x80000000
252 #define EPHYAR_WRITE_CMD 0x80000000
253 #define EPHYAR_REG_MASK 0x1f
254 #define EPHYAR_REG_SHIFT 16
255 #define EPHYAR_DATA_MASK 0xffff
257 #define FIX_NAK_1 (1 << 4)
258 #define FIX_NAK_2 (1 << 3)
261 enum rtl_register_content {
262 /* InterruptStatusBits */
266 TxDescUnavail = 0x0080,
288 /* TXPoll register p.5 */
289 HPQ = 0x80, /* Poll cmd on the high prio queue */
290 NPQ = 0x40, /* Poll cmd on the low prio queue */
291 FSWInt = 0x01, /* Forced software interrupt */
295 Cfg9346_Unlock = 0xc0,
300 AcceptBroadcast = 0x08,
301 AcceptMulticast = 0x04,
303 AcceptAllPhys = 0x01,
310 TxInterFrameGapShift = 24,
311 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
313 /* Config1 register p.24 */
316 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
317 Speed_down = (1 << 4),
321 PMEnable = (1 << 0), /* Power Management Enable */
323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz = 0x01,
325 PCI_Clock_33MHz = 0x00,
327 /* Config3 register p.25 */
328 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
330 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
332 /* Config5 register p.27 */
333 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
334 MWF = (1 << 5), /* Accept Multicast wakeup frame */
335 UWF = (1 << 4), /* Accept Unicast wakeup frame */
336 LanWake = (1 << 1), /* LanWake enable/disable */
337 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
340 TBIReset = 0x80000000,
341 TBILoopback = 0x40000000,
342 TBINwEnable = 0x20000000,
343 TBINwRestart = 0x10000000,
344 TBILinkOk = 0x02000000,
345 TBINwComplete = 0x01000000,
348 EnableBist = (1 << 15), // 8168 8101
349 Mac_dbgo_oe = (1 << 14), // 8168 8101
350 Normal_mode = (1 << 13), // unused
351 Force_half_dup = (1 << 12), // 8168 8101
352 Force_rxflow_en = (1 << 11), // 8168 8101
353 Force_txflow_en = (1 << 10), // 8168 8101
354 Cxpl_dbg_sel = (1 << 9), // 8168 8101
355 ASF = (1 << 8), // 8168 8101
356 PktCntrDisable = (1 << 7), // 8168 8101
357 Mac_dbgo_sel = 0x001c, // 8168
362 INTT_0 = 0x0000, // 8168
363 INTT_1 = 0x0001, // 8168
364 INTT_2 = 0x0002, // 8168
365 INTT_3 = 0x0003, // 8168
367 /* rtl8169_PHYstatus */
378 TBILinkOK = 0x02000000,
380 /* DumpCounterCommand */
384 enum desc_status_bit {
385 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
386 RingEnd = (1 << 30), /* End of descriptor ring */
387 FirstFrag = (1 << 29), /* First segment of a packet */
388 LastFrag = (1 << 28), /* Final segment of a packet */
391 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
392 MSSShift = 16, /* MSS value position */
393 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
394 IPCS = (1 << 18), /* Calculate IP checksum */
395 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
396 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
397 TxVlanTag = (1 << 17), /* Add VLAN tag */
400 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
401 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
403 #define RxProtoUDP (PID1)
404 #define RxProtoTCP (PID0)
405 #define RxProtoIP (PID1 | PID0)
406 #define RxProtoMask RxProtoIP
408 IPFail = (1 << 16), /* IP checksum failed */
409 UDPFail = (1 << 15), /* UDP/IP checksum failed */
410 TCPFail = (1 << 14), /* TCP/IP checksum failed */
411 RxVlanTag = (1 << 16), /* VLAN tag available */
414 #define RsvdMask 0x3fffc000
431 u8 __pad[sizeof(void *) - sizeof(u32)];
435 RTL_FEATURE_WOL = (1 << 0),
436 RTL_FEATURE_MSI = (1 << 1),
437 RTL_FEATURE_GMII = (1 << 2),
440 struct rtl8169_counters {
447 __le32 tx_one_collision;
448 __le32 tx_multi_collision;
456 struct rtl8169_private {
457 void __iomem *mmio_addr; /* memory map physical address */
458 struct pci_dev *pci_dev; /* Index of PCI device */
459 struct net_device *dev;
460 struct napi_struct napi;
461 spinlock_t lock; /* spin lock flag */
465 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
466 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
469 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
470 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
471 dma_addr_t TxPhyAddr;
472 dma_addr_t RxPhyAddr;
473 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
474 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
477 struct timer_list timer;
482 int phy_1000_ctrl_reg;
483 #ifdef CONFIG_R8169_VLAN
484 struct vlan_group *vlgrp;
486 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
487 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
488 void (*phy_reset_enable)(void __iomem *);
489 void (*hw_start)(struct net_device *);
490 unsigned int (*phy_reset_pending)(void __iomem *);
491 unsigned int (*link_ok)(void __iomem *);
492 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
494 struct delayed_work task;
497 struct mii_if_info mii;
498 struct rtl8169_counters counters;
501 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
502 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
503 module_param(rx_copybreak, int, 0);
504 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
505 module_param(use_dac, int, 0);
506 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
507 module_param_named(debug, debug.msg_enable, int, 0);
508 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
509 MODULE_LICENSE("GPL");
510 MODULE_VERSION(RTL8169_VERSION);
512 static int rtl8169_open(struct net_device *dev);
513 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
514 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
515 static int rtl8169_init_ring(struct net_device *dev);
516 static void rtl_hw_start(struct net_device *dev);
517 static int rtl8169_close(struct net_device *dev);
518 static void rtl_set_rx_mode(struct net_device *dev);
519 static void rtl8169_tx_timeout(struct net_device *dev);
520 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
521 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
522 void __iomem *, u32 budget);
523 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
524 static void rtl8169_down(struct net_device *dev);
525 static void rtl8169_rx_clear(struct rtl8169_private *tp);
526 static int rtl8169_poll(struct napi_struct *napi, int budget);
528 static const unsigned int rtl8169_rx_config =
529 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
531 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
535 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
537 for (i = 20; i > 0; i--) {
539 * Check if the RTL8169 has completed writing to the specified
542 if (!(RTL_R32(PHYAR) & 0x80000000))
548 static int mdio_read(void __iomem *ioaddr, int reg_addr)
552 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
554 for (i = 20; i > 0; i--) {
556 * Check if the RTL8169 has completed retrieving data from
557 * the specified MII register.
559 if (RTL_R32(PHYAR) & 0x80000000) {
560 value = RTL_R32(PHYAR) & 0xffff;
568 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
570 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
573 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
576 struct rtl8169_private *tp = netdev_priv(dev);
577 void __iomem *ioaddr = tp->mmio_addr;
579 mdio_write(ioaddr, location, val);
582 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
584 struct rtl8169_private *tp = netdev_priv(dev);
585 void __iomem *ioaddr = tp->mmio_addr;
587 return mdio_read(ioaddr, location);
590 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
594 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
595 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
597 for (i = 0; i < 100; i++) {
598 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
604 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
609 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
611 for (i = 0; i < 100; i++) {
612 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
613 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
622 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
626 RTL_W32(CSIDR, value);
627 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
628 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
630 for (i = 0; i < 100; i++) {
631 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
637 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
642 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
643 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
645 for (i = 0; i < 100; i++) {
646 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
647 value = RTL_R32(CSIDR);
656 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
658 RTL_W16(IntrMask, 0x0000);
660 RTL_W16(IntrStatus, 0xffff);
663 static void rtl8169_asic_down(void __iomem *ioaddr)
665 RTL_W8(ChipCmd, 0x00);
666 rtl8169_irq_mask_and_ack(ioaddr);
670 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
672 return RTL_R32(TBICSR) & TBIReset;
675 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
677 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
680 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
682 return RTL_R32(TBICSR) & TBILinkOk;
685 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
687 return RTL_R8(PHYstatus) & LinkStatus;
690 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
692 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
695 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
699 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
700 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
703 static void rtl8169_check_link_status(struct net_device *dev,
704 struct rtl8169_private *tp,
705 void __iomem *ioaddr)
709 spin_lock_irqsave(&tp->lock, flags);
710 if (tp->link_ok(ioaddr)) {
711 netif_carrier_on(dev);
712 if (netif_msg_ifup(tp))
713 printk(KERN_INFO PFX "%s: link up\n", dev->name);
715 if (netif_msg_ifdown(tp))
716 printk(KERN_INFO PFX "%s: link down\n", dev->name);
717 netif_carrier_off(dev);
719 spin_unlock_irqrestore(&tp->lock, flags);
722 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
724 struct rtl8169_private *tp = netdev_priv(dev);
725 void __iomem *ioaddr = tp->mmio_addr;
730 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
731 wol->supported = WAKE_ANY;
733 spin_lock_irq(&tp->lock);
735 options = RTL_R8(Config1);
736 if (!(options & PMEnable))
739 options = RTL_R8(Config3);
740 if (options & LinkUp)
741 wol->wolopts |= WAKE_PHY;
742 if (options & MagicPacket)
743 wol->wolopts |= WAKE_MAGIC;
745 options = RTL_R8(Config5);
747 wol->wolopts |= WAKE_UCAST;
749 wol->wolopts |= WAKE_BCAST;
751 wol->wolopts |= WAKE_MCAST;
754 spin_unlock_irq(&tp->lock);
757 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
759 struct rtl8169_private *tp = netdev_priv(dev);
760 void __iomem *ioaddr = tp->mmio_addr;
767 { WAKE_ANY, Config1, PMEnable },
768 { WAKE_PHY, Config3, LinkUp },
769 { WAKE_MAGIC, Config3, MagicPacket },
770 { WAKE_UCAST, Config5, UWF },
771 { WAKE_BCAST, Config5, BWF },
772 { WAKE_MCAST, Config5, MWF },
773 { WAKE_ANY, Config5, LanWake }
776 spin_lock_irq(&tp->lock);
778 RTL_W8(Cfg9346, Cfg9346_Unlock);
780 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
781 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
782 if (wol->wolopts & cfg[i].opt)
783 options |= cfg[i].mask;
784 RTL_W8(cfg[i].reg, options);
787 RTL_W8(Cfg9346, Cfg9346_Lock);
790 tp->features |= RTL_FEATURE_WOL;
792 tp->features &= ~RTL_FEATURE_WOL;
793 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
795 spin_unlock_irq(&tp->lock);
800 static void rtl8169_get_drvinfo(struct net_device *dev,
801 struct ethtool_drvinfo *info)
803 struct rtl8169_private *tp = netdev_priv(dev);
805 strcpy(info->driver, MODULENAME);
806 strcpy(info->version, RTL8169_VERSION);
807 strcpy(info->bus_info, pci_name(tp->pci_dev));
810 static int rtl8169_get_regs_len(struct net_device *dev)
812 return R8169_REGS_SIZE;
815 static int rtl8169_set_speed_tbi(struct net_device *dev,
816 u8 autoneg, u16 speed, u8 duplex)
818 struct rtl8169_private *tp = netdev_priv(dev);
819 void __iomem *ioaddr = tp->mmio_addr;
823 reg = RTL_R32(TBICSR);
824 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
825 (duplex == DUPLEX_FULL)) {
826 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
827 } else if (autoneg == AUTONEG_ENABLE)
828 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
830 if (netif_msg_link(tp)) {
831 printk(KERN_WARNING "%s: "
832 "incorrect speed setting refused in TBI mode\n",
841 static int rtl8169_set_speed_xmii(struct net_device *dev,
842 u8 autoneg, u16 speed, u8 duplex)
844 struct rtl8169_private *tp = netdev_priv(dev);
845 void __iomem *ioaddr = tp->mmio_addr;
848 if (autoneg == AUTONEG_ENABLE) {
851 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
852 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
853 ADVERTISE_100HALF | ADVERTISE_100FULL);
854 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
856 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
857 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
859 /* The 8100e/8101e/8102e do Fast Ethernet only. */
860 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
861 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
862 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
863 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
864 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
865 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
866 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
867 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
868 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
869 } else if (netif_msg_link(tp)) {
870 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
874 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
876 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
877 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
878 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
881 * Vendor specific (0x1f) and reserved (0x0e) MII
884 mdio_write(ioaddr, 0x1f, 0x0000);
885 mdio_write(ioaddr, 0x0e, 0x0000);
888 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
889 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
893 if (speed == SPEED_10)
895 else if (speed == SPEED_100)
896 bmcr = BMCR_SPEED100;
900 if (duplex == DUPLEX_FULL)
901 bmcr |= BMCR_FULLDPLX;
903 mdio_write(ioaddr, 0x1f, 0x0000);
906 tp->phy_1000_ctrl_reg = giga_ctrl;
908 mdio_write(ioaddr, MII_BMCR, bmcr);
910 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
911 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
912 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
913 mdio_write(ioaddr, 0x17, 0x2138);
914 mdio_write(ioaddr, 0x0e, 0x0260);
916 mdio_write(ioaddr, 0x17, 0x2108);
917 mdio_write(ioaddr, 0x0e, 0x0000);
924 static int rtl8169_set_speed(struct net_device *dev,
925 u8 autoneg, u16 speed, u8 duplex)
927 struct rtl8169_private *tp = netdev_priv(dev);
930 ret = tp->set_speed(dev, autoneg, speed, duplex);
932 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
933 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
938 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
940 struct rtl8169_private *tp = netdev_priv(dev);
944 spin_lock_irqsave(&tp->lock, flags);
945 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
946 spin_unlock_irqrestore(&tp->lock, flags);
951 static u32 rtl8169_get_rx_csum(struct net_device *dev)
953 struct rtl8169_private *tp = netdev_priv(dev);
955 return tp->cp_cmd & RxChkSum;
958 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
960 struct rtl8169_private *tp = netdev_priv(dev);
961 void __iomem *ioaddr = tp->mmio_addr;
964 spin_lock_irqsave(&tp->lock, flags);
967 tp->cp_cmd |= RxChkSum;
969 tp->cp_cmd &= ~RxChkSum;
971 RTL_W16(CPlusCmd, tp->cp_cmd);
974 spin_unlock_irqrestore(&tp->lock, flags);
979 #ifdef CONFIG_R8169_VLAN
981 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
984 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
985 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
988 static void rtl8169_vlan_rx_register(struct net_device *dev,
989 struct vlan_group *grp)
991 struct rtl8169_private *tp = netdev_priv(dev);
992 void __iomem *ioaddr = tp->mmio_addr;
995 spin_lock_irqsave(&tp->lock, flags);
998 tp->cp_cmd |= RxVlan;
1000 tp->cp_cmd &= ~RxVlan;
1001 RTL_W16(CPlusCmd, tp->cp_cmd);
1003 spin_unlock_irqrestore(&tp->lock, flags);
1006 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1007 struct sk_buff *skb)
1009 u32 opts2 = le32_to_cpu(desc->opts2);
1010 struct vlan_group *vlgrp = tp->vlgrp;
1013 if (vlgrp && (opts2 & RxVlanTag)) {
1014 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1022 #else /* !CONFIG_R8169_VLAN */
1024 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1025 struct sk_buff *skb)
1030 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1031 struct sk_buff *skb)
1038 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1040 struct rtl8169_private *tp = netdev_priv(dev);
1041 void __iomem *ioaddr = tp->mmio_addr;
1045 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1046 cmd->port = PORT_FIBRE;
1047 cmd->transceiver = XCVR_INTERNAL;
1049 status = RTL_R32(TBICSR);
1050 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1051 cmd->autoneg = !!(status & TBINwEnable);
1053 cmd->speed = SPEED_1000;
1054 cmd->duplex = DUPLEX_FULL; /* Always set */
1059 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1061 struct rtl8169_private *tp = netdev_priv(dev);
1063 return mii_ethtool_gset(&tp->mii, cmd);
1066 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1068 struct rtl8169_private *tp = netdev_priv(dev);
1069 unsigned long flags;
1072 spin_lock_irqsave(&tp->lock, flags);
1074 rc = tp->get_settings(dev, cmd);
1076 spin_unlock_irqrestore(&tp->lock, flags);
1080 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1083 struct rtl8169_private *tp = netdev_priv(dev);
1084 unsigned long flags;
1086 if (regs->len > R8169_REGS_SIZE)
1087 regs->len = R8169_REGS_SIZE;
1089 spin_lock_irqsave(&tp->lock, flags);
1090 memcpy_fromio(p, tp->mmio_addr, regs->len);
1091 spin_unlock_irqrestore(&tp->lock, flags);
1094 static u32 rtl8169_get_msglevel(struct net_device *dev)
1096 struct rtl8169_private *tp = netdev_priv(dev);
1098 return tp->msg_enable;
1101 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1103 struct rtl8169_private *tp = netdev_priv(dev);
1105 tp->msg_enable = value;
1108 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1115 "tx_single_collisions",
1116 "tx_multi_collisions",
1124 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1128 return ARRAY_SIZE(rtl8169_gstrings);
1134 static void rtl8169_update_counters(struct net_device *dev)
1136 struct rtl8169_private *tp = netdev_priv(dev);
1137 void __iomem *ioaddr = tp->mmio_addr;
1138 struct rtl8169_counters *counters;
1144 * Some chips are unable to dump tally counters when the receiver
1147 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1150 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1154 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1155 cmd = (u64)paddr & DMA_BIT_MASK(32);
1156 RTL_W32(CounterAddrLow, cmd);
1157 RTL_W32(CounterAddrLow, cmd | CounterDump);
1160 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1161 /* copy updated counters */
1162 memcpy(&tp->counters, counters, sizeof(*counters));
1168 RTL_W32(CounterAddrLow, 0);
1169 RTL_W32(CounterAddrHigh, 0);
1171 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1174 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1175 struct ethtool_stats *stats, u64 *data)
1177 struct rtl8169_private *tp = netdev_priv(dev);
1181 rtl8169_update_counters(dev);
1183 data[0] = le64_to_cpu(tp->counters.tx_packets);
1184 data[1] = le64_to_cpu(tp->counters.rx_packets);
1185 data[2] = le64_to_cpu(tp->counters.tx_errors);
1186 data[3] = le32_to_cpu(tp->counters.rx_errors);
1187 data[4] = le16_to_cpu(tp->counters.rx_missed);
1188 data[5] = le16_to_cpu(tp->counters.align_errors);
1189 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1190 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1191 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1192 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1193 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1194 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1195 data[12] = le16_to_cpu(tp->counters.tx_underun);
1198 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1202 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1207 static const struct ethtool_ops rtl8169_ethtool_ops = {
1208 .get_drvinfo = rtl8169_get_drvinfo,
1209 .get_regs_len = rtl8169_get_regs_len,
1210 .get_link = ethtool_op_get_link,
1211 .get_settings = rtl8169_get_settings,
1212 .set_settings = rtl8169_set_settings,
1213 .get_msglevel = rtl8169_get_msglevel,
1214 .set_msglevel = rtl8169_set_msglevel,
1215 .get_rx_csum = rtl8169_get_rx_csum,
1216 .set_rx_csum = rtl8169_set_rx_csum,
1217 .set_tx_csum = ethtool_op_set_tx_csum,
1218 .set_sg = ethtool_op_set_sg,
1219 .set_tso = ethtool_op_set_tso,
1220 .get_regs = rtl8169_get_regs,
1221 .get_wol = rtl8169_get_wol,
1222 .set_wol = rtl8169_set_wol,
1223 .get_strings = rtl8169_get_strings,
1224 .get_sset_count = rtl8169_get_sset_count,
1225 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1228 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1229 int bitnum, int bitval)
1233 val = mdio_read(ioaddr, reg);
1234 val = (bitval == 1) ?
1235 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1236 mdio_write(ioaddr, reg, val & 0xffff);
1239 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1240 void __iomem *ioaddr)
1243 * The driver currently handles the 8168Bf and the 8168Be identically
1244 * but they can be identified more specifically through the test below
1247 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1249 * Same thing for the 8101Eb and the 8101Ec:
1251 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1259 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1262 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1263 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1264 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1265 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1266 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1267 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1268 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1269 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1270 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1273 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1274 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1275 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1276 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1279 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1280 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1281 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1282 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1283 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1284 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1285 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1286 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1287 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1288 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1289 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1290 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1291 /* FIXME: where did these entries come from ? -- FR */
1292 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1293 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1296 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1297 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1298 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1299 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1300 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1301 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1303 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1307 reg = RTL_R32(TxConfig);
1308 while ((reg & p->mask) != p->val)
1310 tp->mac_version = p->mac_version;
1312 if (p->mask == 0x00000000) {
1313 struct pci_dev *pdev = tp->pci_dev;
1315 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1319 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1321 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1329 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1332 mdio_write(ioaddr, regs->reg, regs->val);
1337 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1340 u16 regs[5]; /* Beware of bit-sign propagation */
1341 } phy_magic[5] = { {
1342 { 0x0000, //w 4 15 12 0
1343 0x00a1, //w 3 15 0 00a1
1344 0x0008, //w 2 15 0 0008
1345 0x1020, //w 1 15 0 1020
1346 0x1000 } },{ //w 0 15 0 1000
1347 { 0x7000, //w 4 15 12 7
1348 0xff41, //w 3 15 0 ff41
1349 0xde60, //w 2 15 0 de60
1350 0x0140, //w 1 15 0 0140
1351 0x0077 } },{ //w 0 15 0 0077
1352 { 0xa000, //w 4 15 12 a
1353 0xdf01, //w 3 15 0 df01
1354 0xdf20, //w 2 15 0 df20
1355 0xff95, //w 1 15 0 ff95
1356 0xfa00 } },{ //w 0 15 0 fa00
1357 { 0xb000, //w 4 15 12 b
1358 0xff41, //w 3 15 0 ff41
1359 0xde20, //w 2 15 0 de20
1360 0x0140, //w 1 15 0 0140
1361 0x00bb } },{ //w 0 15 0 00bb
1362 { 0xf000, //w 4 15 12 f
1363 0xdf01, //w 3 15 0 df01
1364 0xdf20, //w 2 15 0 df20
1365 0xff95, //w 1 15 0 ff95
1366 0xbf00 } //w 0 15 0 bf00
1371 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1372 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1373 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1374 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1376 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1379 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1380 mdio_write(ioaddr, pos, val);
1382 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1383 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1384 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1386 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1389 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1391 struct phy_reg phy_reg_init[] = {
1397 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1400 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1402 struct phy_reg phy_reg_init[] = {
1407 mdio_write(ioaddr, 0x1f, 0x0001);
1408 mdio_patch(ioaddr, 0x16, 1 << 0);
1410 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1413 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1415 struct phy_reg phy_reg_init[] = {
1421 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1424 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1426 struct phy_reg phy_reg_init[] = {
1434 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1437 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1439 struct phy_reg phy_reg_init[] = {
1445 mdio_write(ioaddr, 0x1f, 0x0000);
1446 mdio_patch(ioaddr, 0x14, 1 << 5);
1447 mdio_patch(ioaddr, 0x0d, 1 << 5);
1449 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1452 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1454 struct phy_reg phy_reg_init[] = {
1474 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1476 mdio_patch(ioaddr, 0x14, 1 << 5);
1477 mdio_patch(ioaddr, 0x0d, 1 << 5);
1478 mdio_write(ioaddr, 0x1f, 0x0000);
1481 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1483 struct phy_reg phy_reg_init[] = {
1501 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1503 mdio_patch(ioaddr, 0x16, 1 << 0);
1504 mdio_patch(ioaddr, 0x14, 1 << 5);
1505 mdio_patch(ioaddr, 0x0d, 1 << 5);
1506 mdio_write(ioaddr, 0x1f, 0x0000);
1509 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1511 struct phy_reg phy_reg_init[] = {
1523 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1525 mdio_patch(ioaddr, 0x16, 1 << 0);
1526 mdio_patch(ioaddr, 0x14, 1 << 5);
1527 mdio_patch(ioaddr, 0x0d, 1 << 5);
1528 mdio_write(ioaddr, 0x1f, 0x0000);
1531 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1533 rtl8168c_3_hw_phy_config(ioaddr);
1536 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1538 struct phy_reg phy_reg_init_0[] = {
1564 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1566 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1567 struct phy_reg phy_reg_init_1[] = {
1599 rtl_phy_write(ioaddr, phy_reg_init_1,
1600 ARRAY_SIZE(phy_reg_init_1));
1603 mdio_write(ioaddr, 0x1f, 0x0000);
1606 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1608 struct phy_reg phy_reg_init[] = {
1615 mdio_write(ioaddr, 0x1f, 0x0000);
1616 mdio_patch(ioaddr, 0x11, 1 << 12);
1617 mdio_patch(ioaddr, 0x19, 1 << 13);
1619 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1622 static void rtl_hw_phy_config(struct net_device *dev)
1624 struct rtl8169_private *tp = netdev_priv(dev);
1625 void __iomem *ioaddr = tp->mmio_addr;
1627 rtl8169_print_mac_version(tp);
1629 switch (tp->mac_version) {
1630 case RTL_GIGA_MAC_VER_01:
1632 case RTL_GIGA_MAC_VER_02:
1633 case RTL_GIGA_MAC_VER_03:
1634 rtl8169s_hw_phy_config(ioaddr);
1636 case RTL_GIGA_MAC_VER_04:
1637 rtl8169sb_hw_phy_config(ioaddr);
1639 case RTL_GIGA_MAC_VER_07:
1640 case RTL_GIGA_MAC_VER_08:
1641 case RTL_GIGA_MAC_VER_09:
1642 rtl8102e_hw_phy_config(ioaddr);
1644 case RTL_GIGA_MAC_VER_11:
1645 rtl8168bb_hw_phy_config(ioaddr);
1647 case RTL_GIGA_MAC_VER_12:
1648 rtl8168bef_hw_phy_config(ioaddr);
1650 case RTL_GIGA_MAC_VER_17:
1651 rtl8168bef_hw_phy_config(ioaddr);
1653 case RTL_GIGA_MAC_VER_18:
1654 rtl8168cp_1_hw_phy_config(ioaddr);
1656 case RTL_GIGA_MAC_VER_19:
1657 rtl8168c_1_hw_phy_config(ioaddr);
1659 case RTL_GIGA_MAC_VER_20:
1660 rtl8168c_2_hw_phy_config(ioaddr);
1662 case RTL_GIGA_MAC_VER_21:
1663 rtl8168c_3_hw_phy_config(ioaddr);
1665 case RTL_GIGA_MAC_VER_22:
1666 rtl8168c_4_hw_phy_config(ioaddr);
1668 case RTL_GIGA_MAC_VER_23:
1669 case RTL_GIGA_MAC_VER_24:
1670 rtl8168cp_2_hw_phy_config(ioaddr);
1672 case RTL_GIGA_MAC_VER_25:
1673 rtl8168d_hw_phy_config(ioaddr);
1681 static void rtl8169_phy_timer(unsigned long __opaque)
1683 struct net_device *dev = (struct net_device *)__opaque;
1684 struct rtl8169_private *tp = netdev_priv(dev);
1685 struct timer_list *timer = &tp->timer;
1686 void __iomem *ioaddr = tp->mmio_addr;
1687 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1689 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1691 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1694 spin_lock_irq(&tp->lock);
1696 if (tp->phy_reset_pending(ioaddr)) {
1698 * A busy loop could burn quite a few cycles on nowadays CPU.
1699 * Let's delay the execution of the timer for a few ticks.
1705 if (tp->link_ok(ioaddr))
1708 if (netif_msg_link(tp))
1709 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1711 tp->phy_reset_enable(ioaddr);
1714 mod_timer(timer, jiffies + timeout);
1716 spin_unlock_irq(&tp->lock);
1719 static inline void rtl8169_delete_timer(struct net_device *dev)
1721 struct rtl8169_private *tp = netdev_priv(dev);
1722 struct timer_list *timer = &tp->timer;
1724 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1727 del_timer_sync(timer);
1730 static inline void rtl8169_request_timer(struct net_device *dev)
1732 struct rtl8169_private *tp = netdev_priv(dev);
1733 struct timer_list *timer = &tp->timer;
1735 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1738 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1741 #ifdef CONFIG_NET_POLL_CONTROLLER
1743 * Polling 'interrupt' - used by things like netconsole to send skbs
1744 * without having to re-enable interrupts. It's not called while
1745 * the interrupt routine is executing.
1747 static void rtl8169_netpoll(struct net_device *dev)
1749 struct rtl8169_private *tp = netdev_priv(dev);
1750 struct pci_dev *pdev = tp->pci_dev;
1752 disable_irq(pdev->irq);
1753 rtl8169_interrupt(pdev->irq, dev);
1754 enable_irq(pdev->irq);
1758 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1759 void __iomem *ioaddr)
1762 pci_release_regions(pdev);
1763 pci_disable_device(pdev);
1767 static void rtl8169_phy_reset(struct net_device *dev,
1768 struct rtl8169_private *tp)
1770 void __iomem *ioaddr = tp->mmio_addr;
1773 tp->phy_reset_enable(ioaddr);
1774 for (i = 0; i < 100; i++) {
1775 if (!tp->phy_reset_pending(ioaddr))
1779 if (netif_msg_link(tp))
1780 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1783 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1785 void __iomem *ioaddr = tp->mmio_addr;
1787 rtl_hw_phy_config(dev);
1789 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1790 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1794 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1796 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1797 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1799 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1800 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1802 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1803 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1806 rtl8169_phy_reset(dev, tp);
1809 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1810 * only 8101. Don't panic.
1812 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1814 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1815 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1818 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1820 void __iomem *ioaddr = tp->mmio_addr;
1824 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1825 high = addr[4] | (addr[5] << 8);
1827 spin_lock_irq(&tp->lock);
1829 RTL_W8(Cfg9346, Cfg9346_Unlock);
1831 RTL_W32(MAC4, high);
1832 RTL_W8(Cfg9346, Cfg9346_Lock);
1834 spin_unlock_irq(&tp->lock);
1837 static int rtl_set_mac_address(struct net_device *dev, void *p)
1839 struct rtl8169_private *tp = netdev_priv(dev);
1840 struct sockaddr *addr = p;
1842 if (!is_valid_ether_addr(addr->sa_data))
1843 return -EADDRNOTAVAIL;
1845 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1847 rtl_rar_set(tp, dev->dev_addr);
1852 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1854 struct rtl8169_private *tp = netdev_priv(dev);
1855 struct mii_ioctl_data *data = if_mii(ifr);
1857 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1860 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1864 data->phy_id = 32; /* Internal PHY */
1868 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1872 if (!capable(CAP_NET_ADMIN))
1874 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1880 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1885 static const struct rtl_cfg_info {
1886 void (*hw_start)(struct net_device *);
1887 unsigned int region;
1892 } rtl_cfg_infos [] = {
1894 .hw_start = rtl_hw_start_8169,
1897 .intr_event = SYSErr | LinkChg | RxOverflow |
1898 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1899 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1900 .features = RTL_FEATURE_GMII
1903 .hw_start = rtl_hw_start_8168,
1906 .intr_event = SYSErr | LinkChg | RxOverflow |
1907 TxErr | TxOK | RxOK | RxErr,
1908 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1909 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1912 .hw_start = rtl_hw_start_8101,
1915 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1916 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1917 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1918 .features = RTL_FEATURE_MSI
1922 /* Cfg9346_Unlock assumed. */
1923 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1924 const struct rtl_cfg_info *cfg)
1929 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1930 if (cfg->features & RTL_FEATURE_MSI) {
1931 if (pci_enable_msi(pdev)) {
1932 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1935 msi = RTL_FEATURE_MSI;
1938 RTL_W8(Config2, cfg2);
1942 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1944 if (tp->features & RTL_FEATURE_MSI) {
1945 pci_disable_msi(pdev);
1946 tp->features &= ~RTL_FEATURE_MSI;
1950 static const struct net_device_ops rtl8169_netdev_ops = {
1951 .ndo_open = rtl8169_open,
1952 .ndo_stop = rtl8169_close,
1953 .ndo_get_stats = rtl8169_get_stats,
1954 .ndo_start_xmit = rtl8169_start_xmit,
1955 .ndo_tx_timeout = rtl8169_tx_timeout,
1956 .ndo_validate_addr = eth_validate_addr,
1957 .ndo_change_mtu = rtl8169_change_mtu,
1958 .ndo_set_mac_address = rtl_set_mac_address,
1959 .ndo_do_ioctl = rtl8169_ioctl,
1960 .ndo_set_multicast_list = rtl_set_rx_mode,
1961 #ifdef CONFIG_R8169_VLAN
1962 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
1964 #ifdef CONFIG_NET_POLL_CONTROLLER
1965 .ndo_poll_controller = rtl8169_netpoll,
1970 static int __devinit
1971 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1973 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1974 const unsigned int region = cfg->region;
1975 struct rtl8169_private *tp;
1976 struct mii_if_info *mii;
1977 struct net_device *dev;
1978 void __iomem *ioaddr;
1982 if (netif_msg_drv(&debug)) {
1983 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1984 MODULENAME, RTL8169_VERSION);
1987 dev = alloc_etherdev(sizeof (*tp));
1989 if (netif_msg_drv(&debug))
1990 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1995 SET_NETDEV_DEV(dev, &pdev->dev);
1996 dev->netdev_ops = &rtl8169_netdev_ops;
1997 tp = netdev_priv(dev);
2000 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2004 mii->mdio_read = rtl_mdio_read;
2005 mii->mdio_write = rtl_mdio_write;
2006 mii->phy_id_mask = 0x1f;
2007 mii->reg_num_mask = 0x1f;
2008 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2010 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2011 rc = pci_enable_device(pdev);
2013 if (netif_msg_probe(tp))
2014 dev_err(&pdev->dev, "enable failure\n");
2015 goto err_out_free_dev_1;
2018 rc = pci_set_mwi(pdev);
2020 goto err_out_disable_2;
2022 /* make sure PCI base addr 1 is MMIO */
2023 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2024 if (netif_msg_probe(tp)) {
2026 "region #%d not an MMIO resource, aborting\n",
2033 /* check for weird/broken PCI region reporting */
2034 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2035 if (netif_msg_probe(tp)) {
2037 "Invalid PCI region size(s), aborting\n");
2043 rc = pci_request_regions(pdev, MODULENAME);
2045 if (netif_msg_probe(tp))
2046 dev_err(&pdev->dev, "could not request regions.\n");
2050 tp->cp_cmd = PCIMulRW | RxChkSum;
2052 if ((sizeof(dma_addr_t) > 4) &&
2053 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2054 tp->cp_cmd |= PCIDAC;
2055 dev->features |= NETIF_F_HIGHDMA;
2057 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2059 if (netif_msg_probe(tp)) {
2061 "DMA configuration failed.\n");
2063 goto err_out_free_res_4;
2067 pci_set_master(pdev);
2069 /* ioremap MMIO region */
2070 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2072 if (netif_msg_probe(tp))
2073 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2075 goto err_out_free_res_4;
2078 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2079 if (!tp->pcie_cap && netif_msg_probe(tp))
2080 dev_info(&pdev->dev, "no PCI Express capability\n");
2082 RTL_W16(IntrMask, 0x0000);
2084 /* Soft reset the chip. */
2085 RTL_W8(ChipCmd, CmdReset);
2087 /* Check that the chip has finished the reset. */
2088 for (i = 0; i < 100; i++) {
2089 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2091 msleep_interruptible(1);
2094 RTL_W16(IntrStatus, 0xffff);
2096 /* Identify chip attached to board */
2097 rtl8169_get_mac_version(tp, ioaddr);
2099 rtl8169_print_mac_version(tp);
2101 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2102 if (tp->mac_version == rtl_chip_info[i].mac_version)
2105 if (i == ARRAY_SIZE(rtl_chip_info)) {
2106 /* Unknown chip: assume array element #0, original RTL-8169 */
2107 if (netif_msg_probe(tp)) {
2108 dev_printk(KERN_DEBUG, &pdev->dev,
2109 "unknown chip version, assuming %s\n",
2110 rtl_chip_info[0].name);
2116 RTL_W8(Cfg9346, Cfg9346_Unlock);
2117 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2118 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2119 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2120 tp->features |= RTL_FEATURE_WOL;
2121 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2122 tp->features |= RTL_FEATURE_WOL;
2123 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2124 RTL_W8(Cfg9346, Cfg9346_Lock);
2126 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2127 (RTL_R8(PHYstatus) & TBI_Enable)) {
2128 tp->set_speed = rtl8169_set_speed_tbi;
2129 tp->get_settings = rtl8169_gset_tbi;
2130 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2131 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2132 tp->link_ok = rtl8169_tbi_link_ok;
2133 tp->do_ioctl = rtl_tbi_ioctl;
2135 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2137 tp->set_speed = rtl8169_set_speed_xmii;
2138 tp->get_settings = rtl8169_gset_xmii;
2139 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2140 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2141 tp->link_ok = rtl8169_xmii_link_ok;
2142 tp->do_ioctl = rtl_xmii_ioctl;
2145 spin_lock_init(&tp->lock);
2147 tp->mmio_addr = ioaddr;
2149 /* Get MAC address */
2150 for (i = 0; i < MAC_ADDR_LEN; i++)
2151 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2152 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2154 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2155 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2156 dev->irq = pdev->irq;
2157 dev->base_addr = (unsigned long) ioaddr;
2159 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2161 #ifdef CONFIG_R8169_VLAN
2162 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2165 tp->intr_mask = 0xffff;
2166 tp->align = cfg->align;
2167 tp->hw_start = cfg->hw_start;
2168 tp->intr_event = cfg->intr_event;
2169 tp->napi_event = cfg->napi_event;
2171 init_timer(&tp->timer);
2172 tp->timer.data = (unsigned long) dev;
2173 tp->timer.function = rtl8169_phy_timer;
2175 rc = register_netdev(dev);
2179 pci_set_drvdata(pdev, dev);
2181 if (netif_msg_probe(tp)) {
2182 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2184 printk(KERN_INFO "%s: %s at 0x%lx, "
2185 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2186 "XID %08x IRQ %d\n",
2188 rtl_chip_info[tp->chipset].name,
2190 dev->dev_addr[0], dev->dev_addr[1],
2191 dev->dev_addr[2], dev->dev_addr[3],
2192 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2195 rtl8169_init_phy(dev, tp);
2196 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2202 rtl_disable_msi(pdev, tp);
2205 pci_release_regions(pdev);
2207 pci_clear_mwi(pdev);
2209 pci_disable_device(pdev);
2215 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2217 struct net_device *dev = pci_get_drvdata(pdev);
2218 struct rtl8169_private *tp = netdev_priv(dev);
2220 flush_scheduled_work();
2222 unregister_netdev(dev);
2223 rtl_disable_msi(pdev, tp);
2224 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2225 pci_set_drvdata(pdev, NULL);
2228 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2229 struct net_device *dev)
2231 unsigned int mtu = dev->mtu;
2233 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2236 static int rtl8169_open(struct net_device *dev)
2238 struct rtl8169_private *tp = netdev_priv(dev);
2239 struct pci_dev *pdev = tp->pci_dev;
2240 int retval = -ENOMEM;
2243 rtl8169_set_rxbufsize(tp, dev);
2246 * Rx and Tx desscriptors needs 256 bytes alignment.
2247 * pci_alloc_consistent provides more.
2249 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2251 if (!tp->TxDescArray)
2254 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2256 if (!tp->RxDescArray)
2259 retval = rtl8169_init_ring(dev);
2263 INIT_DELAYED_WORK(&tp->task, NULL);
2267 retval = request_irq(dev->irq, rtl8169_interrupt,
2268 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2271 goto err_release_ring_2;
2273 napi_enable(&tp->napi);
2277 rtl8169_request_timer(dev);
2279 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2284 rtl8169_rx_clear(tp);
2286 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2289 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2294 static void rtl8169_hw_reset(void __iomem *ioaddr)
2296 /* Disable interrupts */
2297 rtl8169_irq_mask_and_ack(ioaddr);
2299 /* Reset the chipset */
2300 RTL_W8(ChipCmd, CmdReset);
2306 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2308 void __iomem *ioaddr = tp->mmio_addr;
2309 u32 cfg = rtl8169_rx_config;
2311 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2312 RTL_W32(RxConfig, cfg);
2314 /* Set DMA burst size and Interframe Gap Time */
2315 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2316 (InterFrameGap << TxInterFrameGapShift));
2319 static void rtl_hw_start(struct net_device *dev)
2321 struct rtl8169_private *tp = netdev_priv(dev);
2322 void __iomem *ioaddr = tp->mmio_addr;
2325 /* Soft reset the chip. */
2326 RTL_W8(ChipCmd, CmdReset);
2328 /* Check that the chip has finished the reset. */
2329 for (i = 0; i < 100; i++) {
2330 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2332 msleep_interruptible(1);
2337 netif_start_queue(dev);
2341 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2342 void __iomem *ioaddr)
2345 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2346 * register to be written before TxDescAddrLow to work.
2347 * Switching from MMIO to I/O access fixes the issue as well.
2349 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2350 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2351 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2352 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2355 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2359 cmd = RTL_R16(CPlusCmd);
2360 RTL_W16(CPlusCmd, cmd);
2364 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2366 /* Low hurts. Let's disable the filtering. */
2367 RTL_W16(RxMaxSize, 16383);
2370 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2377 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2378 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2379 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2380 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2385 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2386 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2387 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2388 RTL_W32(0x7c, p->val);
2394 static void rtl_hw_start_8169(struct net_device *dev)
2396 struct rtl8169_private *tp = netdev_priv(dev);
2397 void __iomem *ioaddr = tp->mmio_addr;
2398 struct pci_dev *pdev = tp->pci_dev;
2400 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2401 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2402 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2405 RTL_W8(Cfg9346, Cfg9346_Unlock);
2406 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2407 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2408 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2409 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2410 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2412 RTL_W8(EarlyTxThres, EarlyTxThld);
2414 rtl_set_rx_max_size(ioaddr);
2416 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2417 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2418 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2419 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2420 rtl_set_rx_tx_config_registers(tp);
2422 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2424 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2425 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2426 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2427 "Bit-3 and bit-14 MUST be 1\n");
2428 tp->cp_cmd |= (1 << 14);
2431 RTL_W16(CPlusCmd, tp->cp_cmd);
2433 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2436 * Undocumented corner. Supposedly:
2437 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2439 RTL_W16(IntrMitigate, 0x0000);
2441 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2443 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2444 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2445 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2446 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2447 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2448 rtl_set_rx_tx_config_registers(tp);
2451 RTL_W8(Cfg9346, Cfg9346_Lock);
2453 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2456 RTL_W32(RxMissed, 0);
2458 rtl_set_rx_mode(dev);
2460 /* no early-rx interrupts */
2461 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2463 /* Enable all known interrupts by setting the interrupt mask. */
2464 RTL_W16(IntrMask, tp->intr_event);
2467 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2469 struct net_device *dev = pci_get_drvdata(pdev);
2470 struct rtl8169_private *tp = netdev_priv(dev);
2471 int cap = tp->pcie_cap;
2476 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2477 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2478 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2482 static void rtl_csi_access_enable(void __iomem *ioaddr)
2486 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2487 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2491 unsigned int offset;
2496 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2501 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2502 rtl_ephy_write(ioaddr, e->offset, w);
2507 static void rtl_disable_clock_request(struct pci_dev *pdev)
2509 struct net_device *dev = pci_get_drvdata(pdev);
2510 struct rtl8169_private *tp = netdev_priv(dev);
2511 int cap = tp->pcie_cap;
2516 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2517 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2518 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2522 #define R8168_CPCMD_QUIRK_MASK (\
2533 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2535 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2537 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2539 rtl_tx_performance_tweak(pdev,
2540 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2543 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2545 rtl_hw_start_8168bb(ioaddr, pdev);
2547 RTL_W8(EarlyTxThres, EarlyTxThld);
2549 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2552 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2554 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2556 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2558 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2560 rtl_disable_clock_request(pdev);
2562 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2565 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2567 static struct ephy_info e_info_8168cp[] = {
2568 { 0x01, 0, 0x0001 },
2569 { 0x02, 0x0800, 0x1000 },
2570 { 0x03, 0, 0x0042 },
2571 { 0x06, 0x0080, 0x0000 },
2575 rtl_csi_access_enable(ioaddr);
2577 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2579 __rtl_hw_start_8168cp(ioaddr, pdev);
2582 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2584 rtl_csi_access_enable(ioaddr);
2586 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2588 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2590 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2593 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2595 rtl_csi_access_enable(ioaddr);
2597 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2600 RTL_W8(DBG_REG, 0x20);
2602 RTL_W8(EarlyTxThres, EarlyTxThld);
2604 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2606 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2609 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2611 static struct ephy_info e_info_8168c_1[] = {
2612 { 0x02, 0x0800, 0x1000 },
2613 { 0x03, 0, 0x0002 },
2614 { 0x06, 0x0080, 0x0000 }
2617 rtl_csi_access_enable(ioaddr);
2619 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2621 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2623 __rtl_hw_start_8168cp(ioaddr, pdev);
2626 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2628 static struct ephy_info e_info_8168c_2[] = {
2629 { 0x01, 0, 0x0001 },
2630 { 0x03, 0x0400, 0x0220 }
2633 rtl_csi_access_enable(ioaddr);
2635 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2637 __rtl_hw_start_8168cp(ioaddr, pdev);
2640 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2642 rtl_hw_start_8168c_2(ioaddr, pdev);
2645 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2647 rtl_csi_access_enable(ioaddr);
2649 __rtl_hw_start_8168cp(ioaddr, pdev);
2652 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2654 rtl_csi_access_enable(ioaddr);
2656 rtl_disable_clock_request(pdev);
2658 RTL_W8(EarlyTxThres, EarlyTxThld);
2660 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2662 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2665 static void rtl_hw_start_8168(struct net_device *dev)
2667 struct rtl8169_private *tp = netdev_priv(dev);
2668 void __iomem *ioaddr = tp->mmio_addr;
2669 struct pci_dev *pdev = tp->pci_dev;
2671 RTL_W8(Cfg9346, Cfg9346_Unlock);
2673 RTL_W8(EarlyTxThres, EarlyTxThld);
2675 rtl_set_rx_max_size(ioaddr);
2677 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2679 RTL_W16(CPlusCmd, tp->cp_cmd);
2681 RTL_W16(IntrMitigate, 0x5151);
2683 /* Work around for RxFIFO overflow. */
2684 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2685 tp->intr_event |= RxFIFOOver | PCSTimeout;
2686 tp->intr_event &= ~RxOverflow;
2689 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2691 rtl_set_rx_mode(dev);
2693 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2694 (InterFrameGap << TxInterFrameGapShift));
2698 switch (tp->mac_version) {
2699 case RTL_GIGA_MAC_VER_11:
2700 rtl_hw_start_8168bb(ioaddr, pdev);
2703 case RTL_GIGA_MAC_VER_12:
2704 case RTL_GIGA_MAC_VER_17:
2705 rtl_hw_start_8168bef(ioaddr, pdev);
2708 case RTL_GIGA_MAC_VER_18:
2709 rtl_hw_start_8168cp_1(ioaddr, pdev);
2712 case RTL_GIGA_MAC_VER_19:
2713 rtl_hw_start_8168c_1(ioaddr, pdev);
2716 case RTL_GIGA_MAC_VER_20:
2717 rtl_hw_start_8168c_2(ioaddr, pdev);
2720 case RTL_GIGA_MAC_VER_21:
2721 rtl_hw_start_8168c_3(ioaddr, pdev);
2724 case RTL_GIGA_MAC_VER_22:
2725 rtl_hw_start_8168c_4(ioaddr, pdev);
2728 case RTL_GIGA_MAC_VER_23:
2729 rtl_hw_start_8168cp_2(ioaddr, pdev);
2732 case RTL_GIGA_MAC_VER_24:
2733 rtl_hw_start_8168cp_3(ioaddr, pdev);
2736 case RTL_GIGA_MAC_VER_25:
2737 rtl_hw_start_8168d(ioaddr, pdev);
2741 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2742 dev->name, tp->mac_version);
2746 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2748 RTL_W8(Cfg9346, Cfg9346_Lock);
2750 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2752 RTL_W16(IntrMask, tp->intr_event);
2755 #define R810X_CPCMD_QUIRK_MASK (\
2767 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2769 static struct ephy_info e_info_8102e_1[] = {
2770 { 0x01, 0, 0x6e65 },
2771 { 0x02, 0, 0x091f },
2772 { 0x03, 0, 0xc2f9 },
2773 { 0x06, 0, 0xafb5 },
2774 { 0x07, 0, 0x0e00 },
2775 { 0x19, 0, 0xec80 },
2776 { 0x01, 0, 0x2e65 },
2781 rtl_csi_access_enable(ioaddr);
2783 RTL_W8(DBG_REG, FIX_NAK_1);
2785 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2788 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2789 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2791 cfg1 = RTL_R8(Config1);
2792 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2793 RTL_W8(Config1, cfg1 & ~LEDS0);
2795 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2797 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2800 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2802 rtl_csi_access_enable(ioaddr);
2804 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2806 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2807 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2809 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2812 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2814 rtl_hw_start_8102e_2(ioaddr, pdev);
2816 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2819 static void rtl_hw_start_8101(struct net_device *dev)
2821 struct rtl8169_private *tp = netdev_priv(dev);
2822 void __iomem *ioaddr = tp->mmio_addr;
2823 struct pci_dev *pdev = tp->pci_dev;
2825 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2826 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2827 int cap = tp->pcie_cap;
2830 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2831 PCI_EXP_DEVCTL_NOSNOOP_EN);
2835 switch (tp->mac_version) {
2836 case RTL_GIGA_MAC_VER_07:
2837 rtl_hw_start_8102e_1(ioaddr, pdev);
2840 case RTL_GIGA_MAC_VER_08:
2841 rtl_hw_start_8102e_3(ioaddr, pdev);
2844 case RTL_GIGA_MAC_VER_09:
2845 rtl_hw_start_8102e_2(ioaddr, pdev);
2849 RTL_W8(Cfg9346, Cfg9346_Unlock);
2851 RTL_W8(EarlyTxThres, EarlyTxThld);
2853 rtl_set_rx_max_size(ioaddr);
2855 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2857 RTL_W16(CPlusCmd, tp->cp_cmd);
2859 RTL_W16(IntrMitigate, 0x0000);
2861 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2863 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2864 rtl_set_rx_tx_config_registers(tp);
2866 RTL_W8(Cfg9346, Cfg9346_Lock);
2870 rtl_set_rx_mode(dev);
2872 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2874 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2876 RTL_W16(IntrMask, tp->intr_event);
2879 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2881 struct rtl8169_private *tp = netdev_priv(dev);
2884 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2889 if (!netif_running(dev))
2894 rtl8169_set_rxbufsize(tp, dev);
2896 ret = rtl8169_init_ring(dev);
2900 napi_enable(&tp->napi);
2904 rtl8169_request_timer(dev);
2910 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2912 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2913 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2916 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2917 struct sk_buff **sk_buff, struct RxDesc *desc)
2919 struct pci_dev *pdev = tp->pci_dev;
2921 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2922 PCI_DMA_FROMDEVICE);
2923 dev_kfree_skb(*sk_buff);
2925 rtl8169_make_unusable_by_asic(desc);
2928 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2930 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2932 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2935 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2938 desc->addr = cpu_to_le64(mapping);
2940 rtl8169_mark_to_asic(desc, rx_buf_sz);
2943 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2944 struct net_device *dev,
2945 struct RxDesc *desc, int rx_buf_sz,
2948 struct sk_buff *skb;
2952 pad = align ? align : NET_IP_ALIGN;
2954 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2958 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2960 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2961 PCI_DMA_FROMDEVICE);
2963 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2968 rtl8169_make_unusable_by_asic(desc);
2972 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2976 for (i = 0; i < NUM_RX_DESC; i++) {
2977 if (tp->Rx_skbuff[i]) {
2978 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2979 tp->RxDescArray + i);
2984 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2989 for (cur = start; end - cur != 0; cur++) {
2990 struct sk_buff *skb;
2991 unsigned int i = cur % NUM_RX_DESC;
2993 WARN_ON((s32)(end - cur) < 0);
2995 if (tp->Rx_skbuff[i])
2998 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2999 tp->RxDescArray + i,
3000 tp->rx_buf_sz, tp->align);
3004 tp->Rx_skbuff[i] = skb;
3009 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3011 desc->opts1 |= cpu_to_le32(RingEnd);
3014 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3016 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3019 static int rtl8169_init_ring(struct net_device *dev)
3021 struct rtl8169_private *tp = netdev_priv(dev);
3023 rtl8169_init_ring_indexes(tp);
3025 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3026 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3028 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3031 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3036 rtl8169_rx_clear(tp);
3040 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3041 struct TxDesc *desc)
3043 unsigned int len = tx_skb->len;
3045 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3052 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3056 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3057 unsigned int entry = i % NUM_TX_DESC;
3058 struct ring_info *tx_skb = tp->tx_skb + entry;
3059 unsigned int len = tx_skb->len;
3062 struct sk_buff *skb = tx_skb->skb;
3064 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3065 tp->TxDescArray + entry);
3070 tp->dev->stats.tx_dropped++;
3073 tp->cur_tx = tp->dirty_tx = 0;
3076 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3078 struct rtl8169_private *tp = netdev_priv(dev);
3080 PREPARE_DELAYED_WORK(&tp->task, task);
3081 schedule_delayed_work(&tp->task, 4);
3084 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3086 struct rtl8169_private *tp = netdev_priv(dev);
3087 void __iomem *ioaddr = tp->mmio_addr;
3089 synchronize_irq(dev->irq);
3091 /* Wait for any pending NAPI task to complete */
3092 napi_disable(&tp->napi);
3094 rtl8169_irq_mask_and_ack(ioaddr);
3096 tp->intr_mask = 0xffff;
3097 RTL_W16(IntrMask, tp->intr_event);
3098 napi_enable(&tp->napi);
3101 static void rtl8169_reinit_task(struct work_struct *work)
3103 struct rtl8169_private *tp =
3104 container_of(work, struct rtl8169_private, task.work);
3105 struct net_device *dev = tp->dev;
3110 if (!netif_running(dev))
3113 rtl8169_wait_for_quiescence(dev);
3116 ret = rtl8169_open(dev);
3117 if (unlikely(ret < 0)) {
3118 if (net_ratelimit() && netif_msg_drv(tp)) {
3119 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3120 " Rescheduling.\n", dev->name, ret);
3122 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3129 static void rtl8169_reset_task(struct work_struct *work)
3131 struct rtl8169_private *tp =
3132 container_of(work, struct rtl8169_private, task.work);
3133 struct net_device *dev = tp->dev;
3137 if (!netif_running(dev))
3140 rtl8169_wait_for_quiescence(dev);
3142 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3143 rtl8169_tx_clear(tp);
3145 if (tp->dirty_rx == tp->cur_rx) {
3146 rtl8169_init_ring_indexes(tp);
3148 netif_wake_queue(dev);
3149 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3151 if (net_ratelimit() && netif_msg_intr(tp)) {
3152 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3155 rtl8169_schedule_work(dev, rtl8169_reset_task);
3162 static void rtl8169_tx_timeout(struct net_device *dev)
3164 struct rtl8169_private *tp = netdev_priv(dev);
3166 rtl8169_hw_reset(tp->mmio_addr);
3168 /* Let's wait a bit while any (async) irq lands on */
3169 rtl8169_schedule_work(dev, rtl8169_reset_task);
3172 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3175 struct skb_shared_info *info = skb_shinfo(skb);
3176 unsigned int cur_frag, entry;
3177 struct TxDesc * uninitialized_var(txd);
3180 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3181 skb_frag_t *frag = info->frags + cur_frag;
3186 entry = (entry + 1) % NUM_TX_DESC;
3188 txd = tp->TxDescArray + entry;
3190 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3191 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3193 /* anti gcc 2.95.3 bugware (sic) */
3194 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3196 txd->opts1 = cpu_to_le32(status);
3197 txd->addr = cpu_to_le64(mapping);
3199 tp->tx_skb[entry].len = len;
3203 tp->tx_skb[entry].skb = skb;
3204 txd->opts1 |= cpu_to_le32(LastFrag);
3210 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3212 if (dev->features & NETIF_F_TSO) {
3213 u32 mss = skb_shinfo(skb)->gso_size;
3216 return LargeSend | ((mss & MSSMask) << MSSShift);
3218 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3219 const struct iphdr *ip = ip_hdr(skb);
3221 if (ip->protocol == IPPROTO_TCP)
3222 return IPCS | TCPCS;
3223 else if (ip->protocol == IPPROTO_UDP)
3224 return IPCS | UDPCS;
3225 WARN_ON(1); /* we need a WARN() */
3230 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3232 struct rtl8169_private *tp = netdev_priv(dev);
3233 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3234 struct TxDesc *txd = tp->TxDescArray + entry;
3235 void __iomem *ioaddr = tp->mmio_addr;
3239 int ret = NETDEV_TX_OK;
3241 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3242 if (netif_msg_drv(tp)) {
3244 "%s: BUG! Tx Ring full when queue awake!\n",
3250 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3253 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3255 frags = rtl8169_xmit_frags(tp, skb, opts1);
3257 len = skb_headlen(skb);
3261 opts1 |= FirstFrag | LastFrag;
3262 tp->tx_skb[entry].skb = skb;
3265 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3267 tp->tx_skb[entry].len = len;
3268 txd->addr = cpu_to_le64(mapping);
3269 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3273 /* anti gcc 2.95.3 bugware (sic) */
3274 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3275 txd->opts1 = cpu_to_le32(status);
3277 dev->trans_start = jiffies;
3279 tp->cur_tx += frags + 1;
3283 RTL_W8(TxPoll, NPQ); /* set polling bit */
3285 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3286 netif_stop_queue(dev);
3288 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3289 netif_wake_queue(dev);
3296 netif_stop_queue(dev);
3297 ret = NETDEV_TX_BUSY;
3298 dev->stats.tx_dropped++;
3302 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3304 struct rtl8169_private *tp = netdev_priv(dev);
3305 struct pci_dev *pdev = tp->pci_dev;
3306 void __iomem *ioaddr = tp->mmio_addr;
3307 u16 pci_status, pci_cmd;
3309 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3310 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3312 if (netif_msg_intr(tp)) {
3314 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3315 dev->name, pci_cmd, pci_status);
3319 * The recovery sequence below admits a very elaborated explanation:
3320 * - it seems to work;
3321 * - I did not see what else could be done;
3322 * - it makes iop3xx happy.
3324 * Feel free to adjust to your needs.
3326 if (pdev->broken_parity_status)
3327 pci_cmd &= ~PCI_COMMAND_PARITY;
3329 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3331 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3333 pci_write_config_word(pdev, PCI_STATUS,
3334 pci_status & (PCI_STATUS_DETECTED_PARITY |
3335 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3336 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3338 /* The infamous DAC f*ckup only happens at boot time */
3339 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3340 if (netif_msg_intr(tp))
3341 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3342 tp->cp_cmd &= ~PCIDAC;
3343 RTL_W16(CPlusCmd, tp->cp_cmd);
3344 dev->features &= ~NETIF_F_HIGHDMA;
3347 rtl8169_hw_reset(ioaddr);
3349 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3352 static void rtl8169_tx_interrupt(struct net_device *dev,
3353 struct rtl8169_private *tp,
3354 void __iomem *ioaddr)
3356 unsigned int dirty_tx, tx_left;
3358 dirty_tx = tp->dirty_tx;
3360 tx_left = tp->cur_tx - dirty_tx;
3362 while (tx_left > 0) {
3363 unsigned int entry = dirty_tx % NUM_TX_DESC;
3364 struct ring_info *tx_skb = tp->tx_skb + entry;
3365 u32 len = tx_skb->len;
3369 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3370 if (status & DescOwn)
3373 dev->stats.tx_bytes += len;
3374 dev->stats.tx_packets++;
3376 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3378 if (status & LastFrag) {
3379 dev_kfree_skb_irq(tx_skb->skb);
3386 if (tp->dirty_tx != dirty_tx) {
3387 tp->dirty_tx = dirty_tx;
3389 if (netif_queue_stopped(dev) &&
3390 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3391 netif_wake_queue(dev);
3394 * 8168 hack: TxPoll requests are lost when the Tx packets are
3395 * too close. Let's kick an extra TxPoll request when a burst
3396 * of start_xmit activity is detected (if it is not detected,
3397 * it is slow enough). -- FR
3400 if (tp->cur_tx != dirty_tx)
3401 RTL_W8(TxPoll, NPQ);
3405 static inline int rtl8169_fragmented_frame(u32 status)
3407 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3410 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3412 u32 opts1 = le32_to_cpu(desc->opts1);
3413 u32 status = opts1 & RxProtoMask;
3415 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3416 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3417 ((status == RxProtoIP) && !(opts1 & IPFail)))
3418 skb->ip_summed = CHECKSUM_UNNECESSARY;
3420 skb->ip_summed = CHECKSUM_NONE;
3423 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3424 struct rtl8169_private *tp, int pkt_size,
3427 struct sk_buff *skb;
3430 if (pkt_size >= rx_copybreak)
3433 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3437 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3438 PCI_DMA_FROMDEVICE);
3439 skb_reserve(skb, NET_IP_ALIGN);
3440 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3447 static int rtl8169_rx_interrupt(struct net_device *dev,
3448 struct rtl8169_private *tp,
3449 void __iomem *ioaddr, u32 budget)
3451 unsigned int cur_rx, rx_left;
3452 unsigned int delta, count;
3454 cur_rx = tp->cur_rx;
3455 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3456 rx_left = min(rx_left, budget);
3458 for (; rx_left > 0; rx_left--, cur_rx++) {
3459 unsigned int entry = cur_rx % NUM_RX_DESC;
3460 struct RxDesc *desc = tp->RxDescArray + entry;
3464 status = le32_to_cpu(desc->opts1);
3466 if (status & DescOwn)
3468 if (unlikely(status & RxRES)) {
3469 if (netif_msg_rx_err(tp)) {
3471 "%s: Rx ERROR. status = %08x\n",
3474 dev->stats.rx_errors++;
3475 if (status & (RxRWT | RxRUNT))
3476 dev->stats.rx_length_errors++;
3478 dev->stats.rx_crc_errors++;
3479 if (status & RxFOVF) {
3480 rtl8169_schedule_work(dev, rtl8169_reset_task);
3481 dev->stats.rx_fifo_errors++;
3483 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3485 struct sk_buff *skb = tp->Rx_skbuff[entry];
3486 dma_addr_t addr = le64_to_cpu(desc->addr);
3487 int pkt_size = (status & 0x00001FFF) - 4;
3488 struct pci_dev *pdev = tp->pci_dev;
3491 * The driver does not support incoming fragmented
3492 * frames. They are seen as a symptom of over-mtu
3495 if (unlikely(rtl8169_fragmented_frame(status))) {
3496 dev->stats.rx_dropped++;
3497 dev->stats.rx_length_errors++;
3498 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3502 rtl8169_rx_csum(skb, desc);
3504 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3505 pci_dma_sync_single_for_device(pdev, addr,
3506 pkt_size, PCI_DMA_FROMDEVICE);
3507 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3509 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3510 PCI_DMA_FROMDEVICE);
3511 tp->Rx_skbuff[entry] = NULL;
3514 skb_put(skb, pkt_size);
3515 skb->protocol = eth_type_trans(skb, dev);
3517 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3518 netif_receive_skb(skb);
3520 dev->stats.rx_bytes += pkt_size;
3521 dev->stats.rx_packets++;
3524 /* Work around for AMD plateform. */
3525 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3526 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3532 count = cur_rx - tp->cur_rx;
3533 tp->cur_rx = cur_rx;
3535 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3536 if (!delta && count && netif_msg_intr(tp))
3537 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3538 tp->dirty_rx += delta;
3541 * FIXME: until there is periodic timer to try and refill the ring,
3542 * a temporary shortage may definitely kill the Rx process.
3543 * - disable the asic to try and avoid an overflow and kick it again
3545 * - how do others driver handle this condition (Uh oh...).
3547 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3548 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3553 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3555 struct net_device *dev = dev_instance;
3556 struct rtl8169_private *tp = netdev_priv(dev);
3557 void __iomem *ioaddr = tp->mmio_addr;
3561 status = RTL_R16(IntrStatus);
3563 /* hotplug/major error/no more work/shared irq */
3564 if ((status == 0xffff) || !status)
3569 if (unlikely(!netif_running(dev))) {
3570 rtl8169_asic_down(ioaddr);
3574 status &= tp->intr_mask;
3576 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3578 if (!(status & tp->intr_event))
3581 /* Work around for rx fifo overflow */
3582 if (unlikely(status & RxFIFOOver) &&
3583 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3584 netif_stop_queue(dev);
3585 rtl8169_tx_timeout(dev);
3589 if (unlikely(status & SYSErr)) {
3590 rtl8169_pcierr_interrupt(dev);
3594 if (status & LinkChg)
3595 rtl8169_check_link_status(dev, tp, ioaddr);
3597 if (status & tp->napi_event) {
3598 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3599 tp->intr_mask = ~tp->napi_event;
3601 if (likely(napi_schedule_prep(&tp->napi)))
3602 __napi_schedule(&tp->napi);
3603 else if (netif_msg_intr(tp)) {
3604 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3609 return IRQ_RETVAL(handled);
3612 static int rtl8169_poll(struct napi_struct *napi, int budget)
3614 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3615 struct net_device *dev = tp->dev;
3616 void __iomem *ioaddr = tp->mmio_addr;
3619 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3620 rtl8169_tx_interrupt(dev, tp, ioaddr);
3622 if (work_done < budget) {
3623 napi_complete(napi);
3624 tp->intr_mask = 0xffff;
3626 * 20040426: the barrier is not strictly required but the
3627 * behavior of the irq handler could be less predictable
3628 * without it. Btw, the lack of flush for the posted pci
3629 * write is safe - FR
3632 RTL_W16(IntrMask, tp->intr_event);
3638 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3640 struct rtl8169_private *tp = netdev_priv(dev);
3642 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3645 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3646 RTL_W32(RxMissed, 0);
3649 static void rtl8169_down(struct net_device *dev)
3651 struct rtl8169_private *tp = netdev_priv(dev);
3652 void __iomem *ioaddr = tp->mmio_addr;
3653 unsigned int intrmask;
3655 rtl8169_delete_timer(dev);
3657 netif_stop_queue(dev);
3659 napi_disable(&tp->napi);
3662 spin_lock_irq(&tp->lock);
3664 rtl8169_asic_down(ioaddr);
3666 rtl8169_rx_missed(dev, ioaddr);
3668 spin_unlock_irq(&tp->lock);
3670 synchronize_irq(dev->irq);
3672 /* Give a racing hard_start_xmit a few cycles to complete. */
3673 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3676 * And now for the 50k$ question: are IRQ disabled or not ?
3678 * Two paths lead here:
3680 * -> netif_running() is available to sync the current code and the
3681 * IRQ handler. See rtl8169_interrupt for details.
3682 * 2) dev->change_mtu
3683 * -> rtl8169_poll can not be issued again and re-enable the
3684 * interruptions. Let's simply issue the IRQ down sequence again.
3686 * No loop if hotpluged or major error (0xffff).
3688 intrmask = RTL_R16(IntrMask);
3689 if (intrmask && (intrmask != 0xffff))
3692 rtl8169_tx_clear(tp);
3694 rtl8169_rx_clear(tp);
3697 static int rtl8169_close(struct net_device *dev)
3699 struct rtl8169_private *tp = netdev_priv(dev);
3700 struct pci_dev *pdev = tp->pci_dev;
3702 /* update counters before going down */
3703 rtl8169_update_counters(dev);
3707 free_irq(dev->irq, dev);
3709 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3711 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3713 tp->TxDescArray = NULL;
3714 tp->RxDescArray = NULL;
3719 static void rtl_set_rx_mode(struct net_device *dev)
3721 struct rtl8169_private *tp = netdev_priv(dev);
3722 void __iomem *ioaddr = tp->mmio_addr;
3723 unsigned long flags;
3724 u32 mc_filter[2]; /* Multicast hash filter */
3728 if (dev->flags & IFF_PROMISC) {
3729 /* Unconditionally log net taps. */
3730 if (netif_msg_link(tp)) {
3731 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3735 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3737 mc_filter[1] = mc_filter[0] = 0xffffffff;
3738 } else if ((dev->mc_count > multicast_filter_limit)
3739 || (dev->flags & IFF_ALLMULTI)) {
3740 /* Too many to filter perfectly -- accept all multicasts. */
3741 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3742 mc_filter[1] = mc_filter[0] = 0xffffffff;
3744 struct dev_mc_list *mclist;
3747 rx_mode = AcceptBroadcast | AcceptMyPhys;
3748 mc_filter[1] = mc_filter[0] = 0;
3749 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3750 i++, mclist = mclist->next) {
3751 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3752 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3753 rx_mode |= AcceptMulticast;
3757 spin_lock_irqsave(&tp->lock, flags);
3759 tmp = rtl8169_rx_config | rx_mode |
3760 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3762 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3763 u32 data = mc_filter[0];
3765 mc_filter[0] = swab32(mc_filter[1]);
3766 mc_filter[1] = swab32(data);
3769 RTL_W32(MAR0 + 0, mc_filter[0]);
3770 RTL_W32(MAR0 + 4, mc_filter[1]);
3772 RTL_W32(RxConfig, tmp);
3774 spin_unlock_irqrestore(&tp->lock, flags);
3778 * rtl8169_get_stats - Get rtl8169 read/write statistics
3779 * @dev: The Ethernet Device to get statistics for
3781 * Get TX/RX statistics for rtl8169
3783 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3785 struct rtl8169_private *tp = netdev_priv(dev);
3786 void __iomem *ioaddr = tp->mmio_addr;
3787 unsigned long flags;
3789 if (netif_running(dev)) {
3790 spin_lock_irqsave(&tp->lock, flags);
3791 rtl8169_rx_missed(dev, ioaddr);
3792 spin_unlock_irqrestore(&tp->lock, flags);
3798 static void rtl8169_net_suspend(struct net_device *dev)
3800 struct rtl8169_private *tp = netdev_priv(dev);
3801 void __iomem *ioaddr = tp->mmio_addr;
3803 if (!netif_running(dev))
3806 netif_device_detach(dev);
3807 netif_stop_queue(dev);
3809 spin_lock_irq(&tp->lock);
3811 rtl8169_asic_down(ioaddr);
3813 rtl8169_rx_missed(dev, ioaddr);
3815 spin_unlock_irq(&tp->lock);
3820 static int rtl8169_suspend(struct device *device)
3822 struct pci_dev *pdev = to_pci_dev(device);
3823 struct net_device *dev = pci_get_drvdata(pdev);
3825 rtl8169_net_suspend(dev);
3830 static int rtl8169_resume(struct device *device)
3832 struct pci_dev *pdev = to_pci_dev(device);
3833 struct net_device *dev = pci_get_drvdata(pdev);
3835 if (!netif_running(dev))
3838 netif_device_attach(dev);
3840 rtl8169_schedule_work(dev, rtl8169_reset_task);
3845 static struct dev_pm_ops rtl8169_pm_ops = {
3846 .suspend = rtl8169_suspend,
3847 .resume = rtl8169_resume,
3848 .freeze = rtl8169_suspend,
3849 .thaw = rtl8169_resume,
3850 .poweroff = rtl8169_suspend,
3851 .restore = rtl8169_resume,
3854 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
3856 #else /* !CONFIG_PM */
3858 #define RTL8169_PM_OPS NULL
3860 #endif /* !CONFIG_PM */
3862 static void rtl_shutdown(struct pci_dev *pdev)
3864 struct net_device *dev = pci_get_drvdata(pdev);
3866 rtl8169_net_suspend(dev);
3868 if (system_state == SYSTEM_POWER_OFF) {
3869 pci_wake_from_d3(pdev, true);
3870 pci_set_power_state(pdev, PCI_D3hot);
3874 static struct pci_driver rtl8169_pci_driver = {
3876 .id_table = rtl8169_pci_tbl,
3877 .probe = rtl8169_init_one,
3878 .remove = __devexit_p(rtl8169_remove_one),
3879 .shutdown = rtl_shutdown,
3880 .driver.pm = RTL8169_PM_OPS,
3883 static int __init rtl8169_init_module(void)
3885 return pci_register_driver(&rtl8169_pci_driver);
3888 static void __exit rtl8169_cleanup_module(void)
3890 pci_unregister_driver(&rtl8169_pci_driver);
3893 module_init(rtl8169_init_module);
3894 module_exit(rtl8169_cleanup_module);