drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* drivers/net/phy/realtek.c
   3  *
   4  * Driver for Realtek PHYs
   5  *
   6  * Author: Johnson Leung <r58129@freescale.com>
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  */
  10 #include <linux/bitops.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15
  16 #define RTL821x_PHYSR                           0x11
  17 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  18 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  19
  20 #define RTL821x_INER                            0x12
  21 #define RTL8211B_INER_INIT                      0x6400
  22 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  23 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  24
  25 #define RTL821x_INSR                            0x13
  26
  27 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  28 #define RTL821x_PAGE_SELECT                     0x1f
  29
  30 #define RTL8211F_PHYCR1                         0x18
  31 #define RTL8211F_PHYCR2                         0x19
  32 #define RTL8211F_INSR                           0x1d
  33
  34 #define RTL8211F_TX_DELAY                       BIT(8)
  35 #define RTL8211F_RX_DELAY                       BIT(3)
  36
  37 #define RTL8211F_ALDPS_PLL_OFF                  BIT(1)
  38 #define RTL8211F_ALDPS_ENABLE                   BIT(2)
  39 #define RTL8211F_ALDPS_XTAL_OFF                 BIT(12)
  40
  41 #define RTL8211E_CTRL_DELAY                     BIT(13)
  42 #define RTL8211E_TX_DELAY                       BIT(12)
  43 #define RTL8211E_RX_DELAY                       BIT(11)
  44
  45 #define RTL8211F_CLKOUT_EN                      BIT(0)
  46
  47 #define RTL8201F_ISR                            0x1e
  48 #define RTL8201F_ISR_ANERR                      BIT(15)
  49 #define RTL8201F_ISR_DUPLEX                     BIT(13)
  50 #define RTL8201F_ISR_LINK                       BIT(11)
  51 #define RTL8201F_ISR_MASK                       (RTL8201F_ISR_ANERR | \
  52                                                  RTL8201F_ISR_DUPLEX | \
  53                                                  RTL8201F_ISR_LINK)
  54 #define RTL8201F_IER                            0x13
  55
  56 #define RTL8366RB_POWER_SAVE                    0x15
  57 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  58
  59 #define RTL_SUPPORTS_5000FULL                   BIT(14)
  60 #define RTL_SUPPORTS_2500FULL                   BIT(13)
  61 #define RTL_SUPPORTS_10000FULL                  BIT(0)
  62 #define RTL_ADV_2500FULL                        BIT(7)
  63 #define RTL_LPADV_10000FULL                     BIT(11)
  64 #define RTL_LPADV_5000FULL                      BIT(6)
  65 #define RTL_LPADV_2500FULL                      BIT(5)
  66
  67 #define RTL9000A_GINMR                          0x14
  68 #define RTL9000A_GINMR_LINK_STATUS              BIT(4)
  69
  70 #define RTLGEN_SPEED_MASK                       0x0630
  71
  72 #define RTL_GENERIC_PHYID                       0x001cc800
  73 #define RTL_8211FVD_PHYID                       0x001cc878
  74
  75 MODULE_DESCRIPTION("Realtek PHY driver");
  76 MODULE_AUTHOR("Johnson Leung");
  77 MODULE_LICENSE("GPL");
  78
  79 struct rtl821x_priv {
  80         u16 phycr1;
  81         u16 phycr2;
  82         bool has_phycr2;
  83 };
  84
  85 static int rtl821x_read_page(struct phy_device *phydev)
  86 {
  87         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  88 }
  89
  90 static int rtl821x_write_page(struct phy_device *phydev, int page)
  91 {
  92         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  93 }
  94
  95 static int rtl821x_probe(struct phy_device *phydev)
  96 {
  97         struct device *dev = &phydev->mdio.dev;
  98         struct rtl821x_priv *priv;
  99         u32 phy_id = phydev->drv->phy_id;
 100         int ret;
 101
 102         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 103         if (!priv)
 104                 return -ENOMEM;
 105
 106         ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
 107         if (ret < 0)
 108                 return ret;
 109
 110         priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
 111         if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
 112                 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
 113
 114         priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
 115         if (priv->has_phycr2) {
 116                 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
 117                 if (ret < 0)
 118                         return ret;
 119
 120                 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
 121                 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
 122                         priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
 123         }
 124
 125         phydev->priv = priv;
 126
 127         return 0;
 128 }
 129
 130 static int rtl8201_ack_interrupt(struct phy_device *phydev)
 131 {
 132         int err;
 133
 134         err = phy_read(phydev, RTL8201F_ISR);
 135
 136         return (err < 0) ? err : 0;
 137 }
 138
 139 static int rtl821x_ack_interrupt(struct phy_device *phydev)
 140 {
 141         int err;
 142
 143         err = phy_read(phydev, RTL821x_INSR);
 144
 145         return (err < 0) ? err : 0;
 146 }
 147
 148 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
 149 {
 150         int err;
 151
 152         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 153
 154         return (err < 0) ? err : 0;
 155 }
 156
 157 static int rtl8201_config_intr(struct phy_device *phydev)
 158 {
 159         u16 val;
 160         int err;
 161
 162         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 163                 err = rtl8201_ack_interrupt(phydev);
 164                 if (err)
 165                         return err;
 166
 167                 val = BIT(13) | BIT(12) | BIT(11);
 168                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 169         } else {
 170                 val = 0;
 171                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 172                 if (err)
 173                         return err;
 174
 175                 err = rtl8201_ack_interrupt(phydev);
 176         }
 177
 178         return err;
 179 }
 180
 181 static int rtl8211b_config_intr(struct phy_device *phydev)
 182 {
 183         int err;
 184
 185         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 186                 err = rtl821x_ack_interrupt(phydev);
 187                 if (err)
 188                         return err;
 189
 190                 err = phy_write(phydev, RTL821x_INER,
 191                                 RTL8211B_INER_INIT);
 192         } else {
 193                 err = phy_write(phydev, RTL821x_INER, 0);
 194                 if (err)
 195                         return err;
 196
 197                 err = rtl821x_ack_interrupt(phydev);
 198         }
 199
 200         return err;
 201 }
 202
 203 static int rtl8211e_config_intr(struct phy_device *phydev)
 204 {
 205         int err;
 206
 207         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 208                 err = rtl821x_ack_interrupt(phydev);
 209                 if (err)
 210                         return err;
 211
 212                 err = phy_write(phydev, RTL821x_INER,
 213                                 RTL8211E_INER_LINK_STATUS);
 214         } else {
 215                 err = phy_write(phydev, RTL821x_INER, 0);
 216                 if (err)
 217                         return err;
 218
 219                 err = rtl821x_ack_interrupt(phydev);
 220         }
 221
 222         return err;
 223 }
 224
 225 static int rtl8211f_config_intr(struct phy_device *phydev)
 226 {
 227         u16 val;
 228         int err;
 229
 230         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 231                 err = rtl8211f_ack_interrupt(phydev);
 232                 if (err)
 233                         return err;
 234
 235                 val = RTL8211F_INER_LINK_STATUS;
 236                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 237         } else {
 238                 val = 0;
 239                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 240                 if (err)
 241                         return err;
 242
 243                 err = rtl8211f_ack_interrupt(phydev);
 244         }
 245
 246         return err;
 247 }
 248
 249 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
 250 {
 251         int irq_status;
 252
 253         irq_status = phy_read(phydev, RTL8201F_ISR);
 254         if (irq_status < 0) {
 255                 phy_error(phydev);
 256                 return IRQ_NONE;
 257         }
 258
 259         if (!(irq_status & RTL8201F_ISR_MASK))
 260                 return IRQ_NONE;
 261
 262         phy_trigger_machine(phydev);
 263
 264         return IRQ_HANDLED;
 265 }
 266
 267 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
 268 {
 269         int irq_status, irq_enabled;
 270
 271         irq_status = phy_read(phydev, RTL821x_INSR);
 272         if (irq_status < 0) {
 273                 phy_error(phydev);
 274                 return IRQ_NONE;
 275         }
 276
 277         irq_enabled = phy_read(phydev, RTL821x_INER);
 278         if (irq_enabled < 0) {
 279                 phy_error(phydev);
 280                 return IRQ_NONE;
 281         }
 282
 283         if (!(irq_status & irq_enabled))
 284                 return IRQ_NONE;
 285
 286         phy_trigger_machine(phydev);
 287
 288         return IRQ_HANDLED;
 289 }
 290
 291 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
 292 {
 293         int irq_status;
 294
 295         irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 296         if (irq_status < 0) {
 297                 phy_error(phydev);
 298                 return IRQ_NONE;
 299         }
 300
 301         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
 302                 return IRQ_NONE;
 303
 304         phy_trigger_machine(phydev);
 305
 306         return IRQ_HANDLED;
 307 }
 308
 309 static int rtl8211_config_aneg(struct phy_device *phydev)
 310 {
 311         int ret;
 312
 313         ret = genphy_config_aneg(phydev);
 314         if (ret < 0)
 315                 return ret;
 316
 317         /* Quirk was copied from vendor driver. Unfortunately it includes no
 318          * description of the magic numbers.
 319          */
 320         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 321                 phy_write(phydev, 0x17, 0x2138);
 322                 phy_write(phydev, 0x0e, 0x0260);
 323         } else {
 324                 phy_write(phydev, 0x17, 0x2108);
 325                 phy_write(phydev, 0x0e, 0x0000);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int rtl8211c_config_init(struct phy_device *phydev)
 332 {
 333         /* RTL8211C has an issue when operating in Gigabit slave mode */
 334         return phy_set_bits(phydev, MII_CTRL1000,
 335                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 336 }
 337
 338 static int rtl8211f_config_init(struct phy_device *phydev)
 339 {
 340         struct rtl821x_priv *priv = phydev->priv;
 341         struct device *dev = &phydev->mdio.dev;
 342         u16 val_txdly, val_rxdly;
 343         int ret;
 344
 345         ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
 346                                        RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
 347                                        priv->phycr1);
 348         if (ret < 0) {
 349                 dev_err(dev, "aldps mode  configuration failed: %pe\n",
 350                         ERR_PTR(ret));
 351                 return ret;
 352         }
 353
 354         switch (phydev->interface) {
 355         case PHY_INTERFACE_MODE_RGMII:
 356                 val_txdly = 0;
 357                 val_rxdly = 0;
 358                 break;
 359
 360         case PHY_INTERFACE_MODE_RGMII_RXID:
 361                 val_txdly = 0;
 362                 val_rxdly = RTL8211F_RX_DELAY;
 363                 break;
 364
 365         case PHY_INTERFACE_MODE_RGMII_TXID:
 366                 val_txdly = RTL8211F_TX_DELAY;
 367                 val_rxdly = 0;
 368                 break;
 369
 370         case PHY_INTERFACE_MODE_RGMII_ID:
 371                 val_txdly = RTL8211F_TX_DELAY;
 372                 val_rxdly = RTL8211F_RX_DELAY;
 373                 break;
 374
 375         default: /* the rest of the modes imply leaving delay as is. */
 376                 return 0;
 377         }
 378
 379         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 380                                        val_txdly);
 381         if (ret < 0) {
 382                 dev_err(dev, "Failed to update the TX delay register\n");
 383                 return ret;
 384         } else if (ret) {
 385                 dev_dbg(dev,
 386                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 387                         val_txdly ? "Enabling" : "Disabling");
 388         } else {
 389                 dev_dbg(dev,
 390                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 391                         val_txdly ? "enabled" : "disabled");
 392         }
 393
 394         ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
 395                                        val_rxdly);
 396         if (ret < 0) {
 397                 dev_err(dev, "Failed to update the RX delay register\n");
 398                 return ret;
 399         } else if (ret) {
 400                 dev_dbg(dev,
 401                         "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
 402                         val_rxdly ? "Enabling" : "Disabling");
 403         } else {
 404                 dev_dbg(dev,
 405                         "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
 406                         val_rxdly ? "enabled" : "disabled");
 407         }
 408
 409         if (priv->has_phycr2) {
 410                 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
 411                                        RTL8211F_CLKOUT_EN, priv->phycr2);
 412                 if (ret < 0) {
 413                         dev_err(dev, "clkout configuration failed: %pe\n",
 414                                 ERR_PTR(ret));
 415                         return ret;
 416                 }
 417         }
 418
 419         return genphy_soft_reset(phydev);
 420 }
 421
 422 static int rtl821x_resume(struct phy_device *phydev)
 423 {
 424         int ret;
 425
 426         ret = genphy_resume(phydev);
 427         if (ret < 0)
 428                 return ret;
 429
 430         msleep(20);
 431
 432         return 0;
 433 }
 434
 435 static int rtl8211e_config_init(struct phy_device *phydev)
 436 {
 437         int ret = 0, oldpage;
 438         u16 val;
 439
 440         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 441         switch (phydev->interface) {
 442         case PHY_INTERFACE_MODE_RGMII:
 443                 val = RTL8211E_CTRL_DELAY | 0;
 444                 break;
 445         case PHY_INTERFACE_MODE_RGMII_ID:
 446                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 447                 break;
 448         case PHY_INTERFACE_MODE_RGMII_RXID:
 449                 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
 450                 break;
 451         case PHY_INTERFACE_MODE_RGMII_TXID:
 452                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
 453                 break;
 454         default: /* the rest of the modes imply leaving delays as is. */
 455                 return 0;
 456         }
 457
 458         /* According to a sample driver there is a 0x1c config register on the
 459          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 460          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
 461          * The configuration register definition:
 462          * 14 = reserved
 463          * 13 = Force Tx RX Delay controlled by bit12 bit11,
 464          * 12 = RX Delay, 11 = TX Delay
 465          * 10:0 = Test && debug settings reserved by realtek
 466          */
 467         oldpage = phy_select_page(phydev, 0x7);
 468         if (oldpage < 0)
 469                 goto err_restore_page;
 470
 471         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 472         if (ret)
 473                 goto err_restore_page;
 474
 475         ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
 476                            | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 477                            val);
 478
 479 err_restore_page:
 480         return phy_restore_page(phydev, oldpage, ret);
 481 }
 482
 483 static int rtl8211b_suspend(struct phy_device *phydev)
 484 {
 485         phy_write(phydev, MII_MMD_DATA, BIT(9));
 486
 487         return genphy_suspend(phydev);
 488 }
 489
 490 static int rtl8211b_resume(struct phy_device *phydev)
 491 {
 492         phy_write(phydev, MII_MMD_DATA, 0);
 493
 494         return genphy_resume(phydev);
 495 }
 496
 497 static int rtl8366rb_config_init(struct phy_device *phydev)
 498 {
 499         int ret;
 500
 501         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 502                            RTL8366RB_POWER_SAVE_ON);
 503         if (ret) {
 504                 dev_err(&phydev->mdio.dev,
 505                         "error enabling power management\n");
 506         }
 507
 508         return ret;
 509 }
 510
 511 /* get actual speed to cover the downshift case */
 512 static int rtlgen_get_speed(struct phy_device *phydev)
 513 {
 514         int val;
 515
 516         if (!phydev->link)
 517                 return 0;
 518
 519         val = phy_read_paged(phydev, 0xa43, 0x12);
 520         if (val < 0)
 521                 return val;
 522
 523         switch (val & RTLGEN_SPEED_MASK) {
 524         case 0x0000:
 525                 phydev->speed = SPEED_10;
 526                 break;
 527         case 0x0010:
 528                 phydev->speed = SPEED_100;
 529                 break;
 530         case 0x0020:
 531                 phydev->speed = SPEED_1000;
 532                 break;
 533         case 0x0200:
 534                 phydev->speed = SPEED_10000;
 535                 break;
 536         case 0x0210:
 537                 phydev->speed = SPEED_2500;
 538                 break;
 539         case 0x0220:
 540                 phydev->speed = SPEED_5000;
 541                 break;
 542         default:
 543                 break;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int rtlgen_read_status(struct phy_device *phydev)
 550 {
 551         int ret;
 552
 553         ret = genphy_read_status(phydev);
 554         if (ret < 0)
 555                 return ret;
 556
 557         return rtlgen_get_speed(phydev);
 558 }
 559
 560 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 561 {
 562         int ret;
 563
 564         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 565                 rtl821x_write_page(phydev, 0xa5c);
 566                 ret = __phy_read(phydev, 0x12);
 567                 rtl821x_write_page(phydev, 0);
 568         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 569                 rtl821x_write_page(phydev, 0xa5d);
 570                 ret = __phy_read(phydev, 0x10);
 571                 rtl821x_write_page(phydev, 0);
 572         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 573                 rtl821x_write_page(phydev, 0xa5d);
 574                 ret = __phy_read(phydev, 0x11);
 575                 rtl821x_write_page(phydev, 0);
 576         } else {
 577                 ret = -EOPNOTSUPP;
 578         }
 579
 580         return ret;
 581 }
 582
 583 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 584                             u16 val)
 585 {
 586         int ret;
 587
 588         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 589                 rtl821x_write_page(phydev, 0xa5d);
 590                 ret = __phy_write(phydev, 0x10, val);
 591                 rtl821x_write_page(phydev, 0);
 592         } else {
 593                 ret = -EOPNOTSUPP;
 594         }
 595
 596         return ret;
 597 }
 598
 599 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 600 {
 601         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 602
 603         if (ret != -EOPNOTSUPP)
 604                 return ret;
 605
 606         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 607                 rtl821x_write_page(phydev, 0xa6e);
 608                 ret = __phy_read(phydev, 0x16);
 609                 rtl821x_write_page(phydev, 0);
 610         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 611                 rtl821x_write_page(phydev, 0xa6d);
 612                 ret = __phy_read(phydev, 0x12);
 613                 rtl821x_write_page(phydev, 0);
 614         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 615                 rtl821x_write_page(phydev, 0xa6d);
 616                 ret = __phy_read(phydev, 0x10);
 617                 rtl821x_write_page(phydev, 0);
 618         }
 619
 620         return ret;
 621 }
 622
 623 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 624                              u16 val)
 625 {
 626         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 627
 628         if (ret != -EOPNOTSUPP)
 629                 return ret;
 630
 631         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 632                 rtl821x_write_page(phydev, 0xa6d);
 633                 ret = __phy_write(phydev, 0x12, val);
 634                 rtl821x_write_page(phydev, 0);
 635         }
 636
 637         return ret;
 638 }
 639
 640 static int rtl822x_get_features(struct phy_device *phydev)
 641 {
 642         int val;
 643
 644         val = phy_read_paged(phydev, 0xa61, 0x13);
 645         if (val < 0)
 646                 return val;
 647
 648         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 649                          phydev->supported, val & RTL_SUPPORTS_2500FULL);
 650         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 651                          phydev->supported, val & RTL_SUPPORTS_5000FULL);
 652         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 653                          phydev->supported, val & RTL_SUPPORTS_10000FULL);
 654
 655         return genphy_read_abilities(phydev);
 656 }
 657
 658 static int rtl822x_config_aneg(struct phy_device *phydev)
 659 {
 660         int ret = 0;
 661
 662         if (phydev->autoneg == AUTONEG_ENABLE) {
 663                 u16 adv2500 = 0;
 664
 665                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 666                                       phydev->advertising))
 667                         adv2500 = RTL_ADV_2500FULL;
 668
 669                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 670                                                RTL_ADV_2500FULL, adv2500);
 671                 if (ret < 0)
 672                         return ret;
 673         }
 674
 675         return __genphy_config_aneg(phydev, ret);
 676 }
 677
 678 static int rtl822x_read_status(struct phy_device *phydev)
 679 {
 680         int ret;
 681
 682         if (phydev->autoneg == AUTONEG_ENABLE) {
 683                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 684
 685                 if (lpadv < 0)
 686                         return lpadv;
 687
 688                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 689                         phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
 690                 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 691                         phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
 692                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 693                         phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
 694         }
 695
 696         ret = genphy_read_status(phydev);
 697         if (ret < 0)
 698                 return ret;
 699
 700         return rtlgen_get_speed(phydev);
 701 }
 702
 703 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 704 {
 705         int val;
 706
 707         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
 708         val = phy_read(phydev, 0x13);
 709         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
 710
 711         return val >= 0 && val & RTL_SUPPORTS_2500FULL;
 712 }
 713
 714 static int rtlgen_match_phy_device(struct phy_device *phydev)
 715 {
 716         return phydev->phy_id == RTL_GENERIC_PHYID &&
 717                !rtlgen_supports_2_5gbps(phydev);
 718 }
 719
 720 static int rtl8226_match_phy_device(struct phy_device *phydev)
 721 {
 722         return phydev->phy_id == RTL_GENERIC_PHYID &&
 723                rtlgen_supports_2_5gbps(phydev);
 724 }
 725
 726 static int rtlgen_resume(struct phy_device *phydev)
 727 {
 728         int ret = genphy_resume(phydev);
 729
 730         /* Internal PHY's from RTL8168h up may not be instantly ready */
 731         msleep(20);
 732
 733         return ret;
 734 }
 735
 736 static int rtl9000a_config_init(struct phy_device *phydev)
 737 {
 738         phydev->autoneg = AUTONEG_DISABLE;
 739         phydev->speed = SPEED_100;
 740         phydev->duplex = DUPLEX_FULL;
 741
 742         return 0;
 743 }
 744
 745 static int rtl9000a_config_aneg(struct phy_device *phydev)
 746 {
 747         int ret;
 748         u16 ctl = 0;
 749
 750         switch (phydev->master_slave_set) {
 751         case MASTER_SLAVE_CFG_MASTER_FORCE:
 752                 ctl |= CTL1000_AS_MASTER;
 753                 break;
 754         case MASTER_SLAVE_CFG_SLAVE_FORCE:
 755                 break;
 756         case MASTER_SLAVE_CFG_UNKNOWN:
 757         case MASTER_SLAVE_CFG_UNSUPPORTED:
 758                 return 0;
 759         default:
 760                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
 761                 return -EOPNOTSUPP;
 762         }
 763
 764         ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
 765         if (ret == 1)
 766                 ret = genphy_soft_reset(phydev);
 767
 768         return ret;
 769 }
 770
 771 static int rtl9000a_read_status(struct phy_device *phydev)
 772 {
 773         int ret;
 774
 775         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
 776         phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
 777
 778         ret = genphy_update_link(phydev);
 779         if (ret)
 780                 return ret;
 781
 782         ret = phy_read(phydev, MII_CTRL1000);
 783         if (ret < 0)
 784                 return ret;
 785         if (ret & CTL1000_AS_MASTER)
 786                 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
 787         else
 788                 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
 789
 790         ret = phy_read(phydev, MII_STAT1000);
 791         if (ret < 0)
 792                 return ret;
 793         if (ret & LPA_1000MSRES)
 794                 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
 795         else
 796                 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
 797
 798         return 0;
 799 }
 800
 801 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
 802 {
 803         int err;
 804
 805         err = phy_read(phydev, RTL8211F_INSR);
 806
 807         return (err < 0) ? err : 0;
 808 }
 809
 810 static int rtl9000a_config_intr(struct phy_device *phydev)
 811 {
 812         u16 val;
 813         int err;
 814
 815         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 816                 err = rtl9000a_ack_interrupt(phydev);
 817                 if (err)
 818                         return err;
 819
 820                 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
 821                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
 822         } else {
 823                 val = ~0;
 824                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
 825                 if (err)
 826                         return err;
 827
 828                 err = rtl9000a_ack_interrupt(phydev);
 829         }
 830
 831         return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
 832 }
 833
 834 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
 835 {
 836         int irq_status;
 837
 838         irq_status = phy_read(phydev, RTL8211F_INSR);
 839         if (irq_status < 0) {
 840                 phy_error(phydev);
 841                 return IRQ_NONE;
 842         }
 843
 844         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
 845                 return IRQ_NONE;
 846
 847         phy_trigger_machine(phydev);
 848
 849         return IRQ_HANDLED;
 850 }
 851
 852 static struct phy_driver realtek_drvs[] = {
 853         {
 854                 PHY_ID_MATCH_EXACT(0x00008201),
 855                 .name           = "RTL8201CP Ethernet",
 856                 .read_page      = rtl821x_read_page,
 857                 .write_page     = rtl821x_write_page,
 858         }, {
 859                 PHY_ID_MATCH_EXACT(0x001cc816),
 860                 .name           = "RTL8201F Fast Ethernet",
 861                 .config_intr    = &rtl8201_config_intr,
 862                 .handle_interrupt = rtl8201_handle_interrupt,
 863                 .suspend        = genphy_suspend,
 864                 .resume         = genphy_resume,
 865                 .read_page      = rtl821x_read_page,
 866                 .write_page     = rtl821x_write_page,
 867         }, {
 868                 PHY_ID_MATCH_MODEL(0x001cc880),
 869                 .name           = "RTL8208 Fast Ethernet",
 870                 .read_mmd       = genphy_read_mmd_unsupported,
 871                 .write_mmd      = genphy_write_mmd_unsupported,
 872                 .suspend        = genphy_suspend,
 873                 .resume         = genphy_resume,
 874                 .read_page      = rtl821x_read_page,
 875                 .write_page     = rtl821x_write_page,
 876         }, {
 877                 PHY_ID_MATCH_EXACT(0x001cc910),
 878                 .name           = "RTL8211 Gigabit Ethernet",
 879                 .config_aneg    = rtl8211_config_aneg,
 880                 .read_mmd       = &genphy_read_mmd_unsupported,
 881                 .write_mmd      = &genphy_write_mmd_unsupported,
 882                 .read_page      = rtl821x_read_page,
 883                 .write_page     = rtl821x_write_page,
 884         }, {
 885                 PHY_ID_MATCH_EXACT(0x001cc912),
 886                 .name           = "RTL8211B Gigabit Ethernet",
 887                 .config_intr    = &rtl8211b_config_intr,
 888                 .handle_interrupt = rtl821x_handle_interrupt,
 889                 .read_mmd       = &genphy_read_mmd_unsupported,
 890                 .write_mmd      = &genphy_write_mmd_unsupported,
 891                 .suspend        = rtl8211b_suspend,
 892                 .resume         = rtl8211b_resume,
 893                 .read_page      = rtl821x_read_page,
 894                 .write_page     = rtl821x_write_page,
 895         }, {
 896                 PHY_ID_MATCH_EXACT(0x001cc913),
 897                 .name           = "RTL8211C Gigabit Ethernet",
 898                 .config_init    = rtl8211c_config_init,
 899                 .read_mmd       = &genphy_read_mmd_unsupported,
 900                 .write_mmd      = &genphy_write_mmd_unsupported,
 901                 .read_page      = rtl821x_read_page,
 902                 .write_page     = rtl821x_write_page,
 903         }, {
 904                 PHY_ID_MATCH_EXACT(0x001cc914),
 905                 .name           = "RTL8211DN Gigabit Ethernet",
 906                 .config_intr    = rtl8211e_config_intr,
 907                 .handle_interrupt = rtl821x_handle_interrupt,
 908                 .suspend        = genphy_suspend,
 909                 .resume         = genphy_resume,
 910                 .read_page      = rtl821x_read_page,
 911                 .write_page     = rtl821x_write_page,
 912         }, {
 913                 PHY_ID_MATCH_EXACT(0x001cc915),
 914                 .name           = "RTL8211E Gigabit Ethernet",
 915                 .config_init    = &rtl8211e_config_init,
 916                 .config_intr    = &rtl8211e_config_intr,
 917                 .handle_interrupt = rtl821x_handle_interrupt,
 918                 .suspend        = genphy_suspend,
 919                 .resume         = genphy_resume,
 920                 .read_page      = rtl821x_read_page,
 921                 .write_page     = rtl821x_write_page,
 922         }, {
 923                 PHY_ID_MATCH_EXACT(0x001cc916),
 924                 .name           = "RTL8211F Gigabit Ethernet",
 925                 .probe          = rtl821x_probe,
 926                 .config_init    = &rtl8211f_config_init,
 927                 .read_status    = rtlgen_read_status,
 928                 .config_intr    = &rtl8211f_config_intr,
 929                 .handle_interrupt = rtl8211f_handle_interrupt,
 930                 .suspend        = genphy_suspend,
 931                 .resume         = rtl821x_resume,
 932                 .read_page      = rtl821x_read_page,
 933                 .write_page     = rtl821x_write_page,
 934         }, {
 935                 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
 936                 .name           = "RTL8211F-VD Gigabit Ethernet",
 937                 .probe          = rtl821x_probe,
 938                 .config_init    = &rtl8211f_config_init,
 939                 .read_status    = rtlgen_read_status,
 940                 .config_intr    = &rtl8211f_config_intr,
 941                 .handle_interrupt = rtl8211f_handle_interrupt,
 942                 .suspend        = genphy_suspend,
 943                 .resume         = rtl821x_resume,
 944                 .read_page      = rtl821x_read_page,
 945                 .write_page     = rtl821x_write_page,
 946         }, {
 947                 .name           = "Generic FE-GE Realtek PHY",
 948                 .match_phy_device = rtlgen_match_phy_device,
 949                 .read_status    = rtlgen_read_status,
 950                 .suspend        = genphy_suspend,
 951                 .resume         = rtlgen_resume,
 952                 .read_page      = rtl821x_read_page,
 953                 .write_page     = rtl821x_write_page,
 954                 .read_mmd       = rtlgen_read_mmd,
 955                 .write_mmd      = rtlgen_write_mmd,
 956         }, {
 957                 .name           = "RTL8226 2.5Gbps PHY",
 958                 .match_phy_device = rtl8226_match_phy_device,
 959                 .get_features   = rtl822x_get_features,
 960                 .config_aneg    = rtl822x_config_aneg,
 961                 .read_status    = rtl822x_read_status,
 962                 .suspend        = genphy_suspend,
 963                 .resume         = rtlgen_resume,
 964                 .read_page      = rtl821x_read_page,
 965                 .write_page     = rtl821x_write_page,
 966                 .read_mmd       = rtl822x_read_mmd,
 967                 .write_mmd      = rtl822x_write_mmd,
 968         }, {
 969                 PHY_ID_MATCH_EXACT(0x001cc840),
 970                 .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
 971                 .get_features   = rtl822x_get_features,
 972                 .config_aneg    = rtl822x_config_aneg,
 973                 .read_status    = rtl822x_read_status,
 974                 .suspend        = genphy_suspend,
 975                 .resume         = rtlgen_resume,
 976                 .read_page      = rtl821x_read_page,
 977                 .write_page     = rtl821x_write_page,
 978                 .read_mmd       = rtl822x_read_mmd,
 979                 .write_mmd      = rtl822x_write_mmd,
 980         }, {
 981                 PHY_ID_MATCH_EXACT(0x001cc838),
 982                 .name           = "RTL8226-CG 2.5Gbps PHY",
 983                 .get_features   = rtl822x_get_features,
 984                 .config_aneg    = rtl822x_config_aneg,
 985                 .read_status    = rtl822x_read_status,
 986                 .suspend        = genphy_suspend,
 987                 .resume         = rtlgen_resume,
 988                 .read_page      = rtl821x_read_page,
 989                 .write_page     = rtl821x_write_page,
 990         }, {
 991                 PHY_ID_MATCH_EXACT(0x001cc848),
 992                 .name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
 993                 .get_features   = rtl822x_get_features,
 994                 .config_aneg    = rtl822x_config_aneg,
 995                 .read_status    = rtl822x_read_status,
 996                 .suspend        = genphy_suspend,
 997                 .resume         = rtlgen_resume,
 998                 .read_page      = rtl821x_read_page,
 999                 .write_page     = rtl821x_write_page,
1000         }, {
1001                 PHY_ID_MATCH_EXACT(0x001cc849),
1002                 .name           = "RTL8221B-VB-CG 2.5Gbps PHY",
1003                 .get_features   = rtl822x_get_features,
1004                 .config_aneg    = rtl822x_config_aneg,
1005                 .read_status    = rtl822x_read_status,
1006                 .suspend        = genphy_suspend,
1007                 .resume         = rtlgen_resume,
1008                 .read_page      = rtl821x_read_page,
1009                 .write_page     = rtl821x_write_page,
1010         }, {
1011                 PHY_ID_MATCH_EXACT(0x001cc84a),
1012                 .name           = "RTL8221B-VM-CG 2.5Gbps PHY",
1013                 .get_features   = rtl822x_get_features,
1014                 .config_aneg    = rtl822x_config_aneg,
1015                 .read_status    = rtl822x_read_status,
1016                 .suspend        = genphy_suspend,
1017                 .resume         = rtlgen_resume,
1018                 .read_page      = rtl821x_read_page,
1019                 .write_page     = rtl821x_write_page,
1020         }, {
1021                 PHY_ID_MATCH_EXACT(0x001cc961),
1022                 .name           = "RTL8366RB Gigabit Ethernet",
1023                 .config_init    = &rtl8366rb_config_init,
1024                 /* These interrupts are handled by the irq controller
1025                  * embedded inside the RTL8366RB, they get unmasked when the
1026                  * irq is requested and ACKed by reading the status register,
1027                  * which is done by the irqchip code.
1028                  */
1029                 .config_intr    = genphy_no_config_intr,
1030                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1031                 .suspend        = genphy_suspend,
1032                 .resume         = genphy_resume,
1033         }, {
1034                 PHY_ID_MATCH_EXACT(0x001ccb00),
1035                 .name           = "RTL9000AA_RTL9000AN Ethernet",
1036                 .features       = PHY_BASIC_T1_FEATURES,
1037                 .config_init    = rtl9000a_config_init,
1038                 .config_aneg    = rtl9000a_config_aneg,
1039                 .read_status    = rtl9000a_read_status,
1040                 .config_intr    = rtl9000a_config_intr,
1041                 .handle_interrupt = rtl9000a_handle_interrupt,
1042                 .suspend        = genphy_suspend,
1043                 .resume         = genphy_resume,
1044                 .read_page      = rtl821x_read_page,
1045                 .write_page     = rtl821x_write_page,
1046         }, {
1047                 PHY_ID_MATCH_EXACT(0x001cc942),
1048                 .name           = "RTL8365MB-VC Gigabit Ethernet",
1049                 /* Interrupt handling analogous to RTL8366RB */
1050                 .config_intr    = genphy_no_config_intr,
1051                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1052                 .suspend        = genphy_suspend,
1053                 .resume         = genphy_resume,
1054         },
1055 };
1056
1057 module_phy_driver(realtek_drvs);
1058
1059 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1060         { PHY_ID_MATCH_VENDOR(0x001cc800) },
1061         { }
1062 };
1063
1064 MODULE_DEVICE_TABLE(mdio, realtek_tbl);