drivers/net/phy/phy-c45.c

   1 /*
   2  * Clause 45 PHY support
   3  */
   4 #include <linux/ethtool.h>
   5 #include <linux/export.h>
   6 #include <linux/mdio.h>
   7 #include <linux/mii.h>
   8 #include <linux/phy.h>
   9
  10 /**
  11  * genphy_c45_setup_forced - configures a forced speed
  12  * @phydev: target phy_device struct
  13  */
  14 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
  15 {
  16         int ctrl1, ctrl2, ret;
  17
  18         /* Half duplex is not supported */
  19         if (phydev->duplex != DUPLEX_FULL)
  20                 return -EINVAL;
  21
  22         ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
  23         if (ctrl1 < 0)
  24                 return ctrl1;
  25
  26         ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
  27         if (ctrl2 < 0)
  28                 return ctrl2;
  29
  30         ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
  31         /*
  32          * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0.  See 45.2.1.6.1
  33          * in 802.3-2012 and 802.3-2015.
  34          */
  35         ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
  36
  37         switch (phydev->speed) {
  38         case SPEED_10:
  39                 ctrl2 |= MDIO_PMA_CTRL2_10BT;
  40                 break;
  41         case SPEED_100:
  42                 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
  43                 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
  44                 break;
  45         case SPEED_1000:
  46                 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
  47                 /* Assume 1000base-T */
  48                 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
  49                 break;
  50         case SPEED_2500:
  51                 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
  52                 /* Assume 2.5Gbase-T */
  53                 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
  54                 break;
  55         case SPEED_5000:
  56                 ctrl1 |= MDIO_CTRL1_SPEED5G;
  57                 /* Assume 5Gbase-T */
  58                 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
  59                 break;
  60         case SPEED_10000:
  61                 ctrl1 |= MDIO_CTRL1_SPEED10G;
  62                 /* Assume 10Gbase-T */
  63                 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
  64                 break;
  65         default:
  66                 return -EINVAL;
  67         }
  68
  69         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
  70         if (ret < 0)
  71                 return ret;
  72
  73         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
  74         if (ret < 0)
  75                 return ret;
  76
  77         return genphy_c45_an_disable_aneg(phydev);
  78 }
  79 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
  80
  81 /**
  82  * genphy_c45_an_config_aneg - configure advertisement registers
  83  * @phydev: target phy_device struct
  84  *
  85  * Configure advertisement registers based on modes set in phydev->advertising
  86  *
  87  * Returns negative errno code on failure, 0 if advertisement didn't change,
  88  * or 1 if advertised modes changed.
  89  */
  90 int genphy_c45_an_config_aneg(struct phy_device *phydev)
  91 {
  92         int changed, ret;
  93         u32 adv;
  94
  95         linkmode_and(phydev->advertising, phydev->advertising,
  96                      phydev->supported);
  97
  98         changed = genphy_config_eee_advert(phydev);
  99
 100         adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
 101
 102         ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
 103                              ADVERTISE_ALL | ADVERTISE_100BASE4 |
 104                              ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
 105                              adv);
 106         if (ret < 0)
 107                 return ret;
 108         if (ret > 0)
 109                 changed = 1;
 110
 111         adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 112
 113         ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
 114                              MDIO_AN_10GBT_CTRL_ADV10G |
 115                              MDIO_AN_10GBT_CTRL_ADV5G |
 116                              MDIO_AN_10GBT_CTRL_ADV2_5G,
 117                              adv);
 118         if (ret < 0)
 119                 return ret;
 120         if (ret > 0)
 121                 changed = 1;
 122
 123         return changed;
 124 }
 125 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
 126
 127 /**
 128  * genphy_c45_an_disable_aneg - disable auto-negotiation
 129  * @phydev: target phy_device struct
 130  *
 131  * Disable auto-negotiation in the Clause 45 PHY. The link parameters
 132  * parameters are controlled through the PMA/PMD MMD registers.
 133  *
 134  * Returns zero on success, negative errno code on failure.
 135  */
 136 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
 137 {
 138
 139         return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
 140                                   MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 141 }
 142 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
 143
 144 /**
 145  * genphy_c45_restart_aneg - Enable and restart auto-negotiation
 146  * @phydev: target phy_device struct
 147  *
 148  * This assumes that the auto-negotiation MMD is present.
 149  *
 150  * Enable and restart auto-negotiation.
 151  */
 152 int genphy_c45_restart_aneg(struct phy_device *phydev)
 153 {
 154         return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
 155                                 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 156 }
 157 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
 158
 159 /**
 160  * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
 161  * @phydev: target phy_device struct
 162  * @restart: whether aneg restart is requested
 163  *
 164  * This assumes that the auto-negotiation MMD is present.
 165  *
 166  * Check, and restart auto-negotiation if needed.
 167  */
 168 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
 169 {
 170         int ret = 0;
 171
 172         if (!restart) {
 173                 /* Configure and restart aneg if it wasn't set before */
 174                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
 175                 if (ret < 0)
 176                         return ret;
 177
 178                 if (!(ret & MDIO_AN_CTRL1_ENABLE))
 179                         restart = true;
 180         }
 181
 182         if (restart)
 183                 ret = genphy_c45_restart_aneg(phydev);
 184
 185         return ret;
 186 }
 187 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
 188
 189 /**
 190  * genphy_c45_aneg_done - return auto-negotiation complete status
 191  * @phydev: target phy_device struct
 192  *
 193  * This assumes that the auto-negotiation MMD is present.
 194  *
 195  * Reads the status register from the auto-negotiation MMD, returning:
 196  * - positive if auto-negotiation is complete
 197  * - negative errno code on error
 198  * - zero otherwise
 199  */
 200 int genphy_c45_aneg_done(struct phy_device *phydev)
 201 {
 202         int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 203
 204         return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
 205 }
 206 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
 207
 208 /**
 209  * genphy_c45_read_link - read the overall link status from the MMDs
 210  * @phydev: target phy_device struct
 211  *
 212  * Read the link status from the specified MMDs, and if they all indicate
 213  * that the link is up, set phydev->link to 1.  If an error is encountered,
 214  * a negative errno will be returned, otherwise zero.
 215  */
 216 int genphy_c45_read_link(struct phy_device *phydev)
 217 {
 218         u32 mmd_mask = MDIO_DEVS_PMAPMD;
 219         int val, devad;
 220         bool link = true;
 221
 222         while (mmd_mask && link) {
 223                 devad = __ffs(mmd_mask);
 224                 mmd_mask &= ~BIT(devad);
 225
 226                 /* The link state is latched low so that momentary link
 227                  * drops can be detected. Do not double-read the status
 228                  * in polling mode to detect such short link drops.
 229                  */
 230                 if (!phy_polling_mode(phydev)) {
 231                         val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 232                         if (val < 0)
 233                                 return val;
 234                         else if (val & MDIO_STAT1_LSTATUS)
 235                                 continue;
 236                 }
 237
 238                 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 239                 if (val < 0)
 240                         return val;
 241
 242                 if (!(val & MDIO_STAT1_LSTATUS))
 243                         link = false;
 244         }
 245
 246         phydev->link = link;
 247
 248         return 0;
 249 }
 250 EXPORT_SYMBOL_GPL(genphy_c45_read_link);
 251
 252 /**
 253  * genphy_c45_read_lpa - read the link partner advertisement and pause
 254  * @phydev: target phy_device struct
 255  *
 256  * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
 257  * filling in the link partner advertisement, pause and asym_pause members
 258  * in @phydev.  This assumes that the auto-negotiation MMD is present, and
 259  * the backplane bit (7.48.0) is clear.  Clause 45 PHY drivers are expected
 260  * to fill in the remainder of the link partner advert from vendor registers.
 261  */
 262 int genphy_c45_read_lpa(struct phy_device *phydev)
 263 {
 264         int val;
 265
 266         /* Read the link partner's base page advertisement */
 267         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
 268         if (val < 0)
 269                 return val;
 270
 271         mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 272         phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
 273         phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
 274
 275         /* Read the link partner's 10G advertisement */
 276         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
 277         if (val < 0)
 278                 return val;
 279
 280         mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 281
 282         return 0;
 283 }
 284 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
 285
 286 /**
 287  * genphy_c45_read_pma - read link speed etc from PMA
 288  * @phydev: target phy_device struct
 289  */
 290 int genphy_c45_read_pma(struct phy_device *phydev)
 291 {
 292         int val;
 293
 294         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
 295         if (val < 0)
 296                 return val;
 297
 298         switch (val & MDIO_CTRL1_SPEEDSEL) {
 299         case 0:
 300                 phydev->speed = SPEED_10;
 301                 break;
 302         case MDIO_PMA_CTRL1_SPEED100:
 303                 phydev->speed = SPEED_100;
 304                 break;
 305         case MDIO_PMA_CTRL1_SPEED1000:
 306                 phydev->speed = SPEED_1000;
 307                 break;
 308         case MDIO_CTRL1_SPEED2_5G:
 309                 phydev->speed = SPEED_2500;
 310                 break;
 311         case MDIO_CTRL1_SPEED5G:
 312                 phydev->speed = SPEED_5000;
 313                 break;
 314         case MDIO_CTRL1_SPEED10G:
 315                 phydev->speed = SPEED_10000;
 316                 break;
 317         default:
 318                 phydev->speed = SPEED_UNKNOWN;
 319                 break;
 320         }
 321
 322         phydev->duplex = DUPLEX_FULL;
 323
 324         return 0;
 325 }
 326 EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
 327
 328 /**
 329  * genphy_c45_read_mdix - read mdix status from PMA
 330  * @phydev: target phy_device struct
 331  */
 332 int genphy_c45_read_mdix(struct phy_device *phydev)
 333 {
 334         int val;
 335
 336         if (phydev->speed == SPEED_10000) {
 337                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 338                                    MDIO_PMA_10GBT_SWAPPOL);
 339                 if (val < 0)
 340                         return val;
 341
 342                 switch (val) {
 343                 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
 344                         phydev->mdix = ETH_TP_MDI;
 345                         break;
 346
 347                 case 0:
 348                         phydev->mdix = ETH_TP_MDI_X;
 349                         break;
 350
 351                 default:
 352                         phydev->mdix = ETH_TP_MDI_INVALID;
 353                         break;
 354                 }
 355         }
 356
 357         return 0;
 358 }
 359 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
 360
 361 /**
 362  * genphy_c45_pma_read_abilities - read supported link modes from PMA
 363  * @phydev: target phy_device struct
 364  *
 365  * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
 366  * 1.8.9 is set, the list of supported modes is build using the values in the
 367  * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
 368  * modes. If bit 1.11.14 is set, then the list is also extended with the modes
 369  * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
 370  * 5GBASET are supported.
 371  */
 372 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
 373 {
 374         int val;
 375
 376         linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
 377         if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
 378                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 379                 if (val < 0)
 380                         return val;
 381
 382                 if (val & MDIO_AN_STAT1_ABLE)
 383                         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 384                                          phydev->supported);
 385         }
 386
 387         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
 388         if (val < 0)
 389                 return val;
 390
 391         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 392                          phydev->supported,
 393                          val & MDIO_PMA_STAT2_10GBSR);
 394
 395         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 396                          phydev->supported,
 397                          val & MDIO_PMA_STAT2_10GBLR);
 398
 399         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
 400                          phydev->supported,
 401                          val & MDIO_PMA_STAT2_10GBER);
 402
 403         if (val & MDIO_PMA_STAT2_EXTABLE) {
 404                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
 405                 if (val < 0)
 406                         return val;
 407
 408                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 409                                  phydev->supported,
 410                                  val & MDIO_PMA_EXTABLE_10GBLRM);
 411                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 412                                  phydev->supported,
 413                                  val & MDIO_PMA_EXTABLE_10GBT);
 414                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 415                                  phydev->supported,
 416                                  val & MDIO_PMA_EXTABLE_10GBKX4);
 417                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 418                                  phydev->supported,
 419                                  val & MDIO_PMA_EXTABLE_10GBKR);
 420                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 421                                  phydev->supported,
 422                                  val & MDIO_PMA_EXTABLE_1000BT);
 423                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 424                                  phydev->supported,
 425                                  val & MDIO_PMA_EXTABLE_1000BKX);
 426
 427                 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 428                                  phydev->supported,
 429                                  val & MDIO_PMA_EXTABLE_100BTX);
 430                 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
 431                                  phydev->supported,
 432                                  val & MDIO_PMA_EXTABLE_100BTX);
 433
 434                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 435                                  phydev->supported,
 436                                  val & MDIO_PMA_EXTABLE_10BT);
 437                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
 438                                  phydev->supported,
 439                                  val & MDIO_PMA_EXTABLE_10BT);
 440
 441                 if (val & MDIO_PMA_EXTABLE_NBT) {
 442                         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 443                                            MDIO_PMA_NG_EXTABLE);
 444                         if (val < 0)
 445                                 return val;
 446
 447                         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 448                                          phydev->supported,
 449                                          val & MDIO_PMA_NG_EXTABLE_2_5GBT);
 450
 451                         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 452                                          phydev->supported,
 453                                          val & MDIO_PMA_NG_EXTABLE_5GBT);
 454                 }
 455         }
 456
 457         return 0;
 458 }
 459 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
 460
 461 /**
 462  * genphy_c45_read_status - read PHY status
 463  * @phydev: target phy_device struct
 464  *
 465  * Reads status from PHY and sets phy_device members accordingly.
 466  */
 467 int genphy_c45_read_status(struct phy_device *phydev)
 468 {
 469         int ret;
 470
 471         ret = genphy_c45_read_link(phydev);
 472         if (ret)
 473                 return ret;
 474
 475         phydev->speed = SPEED_UNKNOWN;
 476         phydev->duplex = DUPLEX_UNKNOWN;
 477         phydev->pause = 0;
 478         phydev->asym_pause = 0;
 479
 480         if (phydev->autoneg == AUTONEG_ENABLE) {
 481                 ret = genphy_c45_read_lpa(phydev);
 482                 if (ret)
 483                         return ret;
 484
 485                 phy_resolve_aneg_linkmode(phydev);
 486         } else {
 487                 ret = genphy_c45_read_pma(phydev);
 488         }
 489
 490         return ret;
 491 }
 492 EXPORT_SYMBOL_GPL(genphy_c45_read_status);
 493
 494 /* The gen10g_* functions are the old Clause 45 stub */
 495
 496 int gen10g_config_aneg(struct phy_device *phydev)
 497 {
 498         return 0;
 499 }
 500 EXPORT_SYMBOL_GPL(gen10g_config_aneg);
 501
 502 int gen10g_read_status(struct phy_device *phydev)
 503 {
 504         /* For now just lie and say it's 10G all the time */
 505         phydev->speed = SPEED_10000;
 506         phydev->duplex = DUPLEX_FULL;
 507
 508         return genphy_c45_read_link(phydev);
 509 }
 510 EXPORT_SYMBOL_GPL(gen10g_read_status);
 511
 512 int gen10g_no_soft_reset(struct phy_device *phydev)
 513 {
 514         /* Do nothing for now */
 515         return 0;
 516 }
 517 EXPORT_SYMBOL_GPL(gen10g_no_soft_reset);
 518
 519 int gen10g_config_init(struct phy_device *phydev)
 520 {
 521         /* Temporarily just say we support everything */
 522         linkmode_zero(phydev->supported);
 523
 524         linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 525                          phydev->supported);
 526         linkmode_copy(phydev->advertising, phydev->supported);
 527
 528         return 0;
 529 }
 530 EXPORT_SYMBOL_GPL(gen10g_config_init);
 531
 532 struct phy_driver genphy_10g_driver = {
 533         .phy_id         = 0xffffffff,
 534         .phy_id_mask    = 0xffffffff,
 535         .name           = "Generic 10G PHY",
 536         .soft_reset     = gen10g_no_soft_reset,
 537         .config_init    = gen10g_config_init,
 538         .features       = PHY_10GBIT_FEATURES,
 539         .config_aneg    = gen10g_config_aneg,
 540         .read_status    = gen10g_read_status,
 541 };