drivers/net/phy/mxl-gpy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2021 Maxlinear Corporation
   3  * Copyright (C) 2020 Intel Corporation
   4  *
   5  * Drivers for Maxlinear Ethernet GPY
   6  *
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/hwmon.h>
  12 #include <linux/phy.h>
  13 #include <linux/polynomial.h>
  14 #include <linux/netdevice.h>
  15
  16 /* PHY ID */
  17 #define PHY_ID_GPYx15B_MASK     0xFFFFFFFC
  18 #define PHY_ID_GPY21xB_MASK     0xFFFFFFF9
  19 #define PHY_ID_GPY2xx           0x67C9DC00
  20 #define PHY_ID_GPY115B          0x67C9DF00
  21 #define PHY_ID_GPY115C          0x67C9DF10
  22 #define PHY_ID_GPY211B          0x67C9DE08
  23 #define PHY_ID_GPY211C          0x67C9DE10
  24 #define PHY_ID_GPY212B          0x67C9DE09
  25 #define PHY_ID_GPY212C          0x67C9DE20
  26 #define PHY_ID_GPY215B          0x67C9DF04
  27 #define PHY_ID_GPY215C          0x67C9DF20
  28 #define PHY_ID_GPY241B          0x67C9DE40
  29 #define PHY_ID_GPY241BM         0x67C9DE80
  30 #define PHY_ID_GPY245B          0x67C9DEC0
  31
  32 #define PHY_MIISTAT             0x18    /* MII state */
  33 #define PHY_IMASK               0x19    /* interrupt mask */
  34 #define PHY_ISTAT               0x1A    /* interrupt status */
  35 #define PHY_FWV                 0x1E    /* firmware version */
  36
  37 #define PHY_MIISTAT_SPD_MASK    GENMASK(2, 0)
  38 #define PHY_MIISTAT_DPX         BIT(3)
  39 #define PHY_MIISTAT_LS          BIT(10)
  40
  41 #define PHY_MIISTAT_SPD_10      0
  42 #define PHY_MIISTAT_SPD_100     1
  43 #define PHY_MIISTAT_SPD_1000    2
  44 #define PHY_MIISTAT_SPD_2500    4
  45
  46 #define PHY_IMASK_WOL           BIT(15) /* Wake-on-LAN */
  47 #define PHY_IMASK_ANC           BIT(10) /* Auto-Neg complete */
  48 #define PHY_IMASK_ADSC          BIT(5)  /* Link auto-downspeed detect */
  49 #define PHY_IMASK_DXMC          BIT(2)  /* Duplex mode change */
  50 #define PHY_IMASK_LSPC          BIT(1)  /* Link speed change */
  51 #define PHY_IMASK_LSTC          BIT(0)  /* Link state change */
  52 #define PHY_IMASK_MASK          (PHY_IMASK_LSTC | \
  53                                  PHY_IMASK_LSPC | \
  54                                  PHY_IMASK_DXMC | \
  55                                  PHY_IMASK_ADSC | \
  56                                  PHY_IMASK_ANC)
  57
  58 #define PHY_FWV_REL_MASK        BIT(15)
  59 #define PHY_FWV_TYPE_MASK       GENMASK(11, 8)
  60 #define PHY_FWV_MINOR_MASK      GENMASK(7, 0)
  61
  62 /* SGMII */
  63 #define VSPEC1_SGMII_CTRL       0x08
  64 #define VSPEC1_SGMII_CTRL_ANEN  BIT(12)         /* Aneg enable */
  65 #define VSPEC1_SGMII_CTRL_ANRS  BIT(9)          /* Restart Aneg */
  66 #define VSPEC1_SGMII_ANEN_ANRS  (VSPEC1_SGMII_CTRL_ANEN | \
  67                                  VSPEC1_SGMII_CTRL_ANRS)
  68
  69 /* Temperature sensor */
  70 #define VPSPEC1_TEMP_STA        0x0E
  71 #define VPSPEC1_TEMP_STA_DATA   GENMASK(9, 0)
  72
  73 /* WoL */
  74 #define VPSPEC2_WOL_CTL         0x0E06
  75 #define VPSPEC2_WOL_AD01        0x0E08
  76 #define VPSPEC2_WOL_AD23        0x0E09
  77 #define VPSPEC2_WOL_AD45        0x0E0A
  78 #define WOL_EN                  BIT(0)
  79
  80 struct gpy_priv {
  81         u8 fw_type;
  82         u8 fw_minor;
  83 };
  84
  85 static const struct {
  86         int type;
  87         int minor;
  88 } ver_need_sgmii_reaneg[] = {
  89         {7, 0x6D},
  90         {8, 0x6D},
  91         {9, 0x73},
  92 };
  93
  94 #if IS_ENABLED(CONFIG_HWMON)
  95 /* The original translation formulae of the temperature (in degrees of Celsius)
  96  * are as follows:
  97  *
  98  *   T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
  99  *       3.0762e-1*(N^1) + -5.2156e1
 100  *
 101  * where [-52.156, 137.961]C and N = [0, 1023].
 102  *
 103  * They must be accordingly altered to be suitable for the integer arithmetics.
 104  * The technique is called 'factor redistribution', which just makes sure the
 105  * multiplications and divisions are made so to have a result of the operations
 106  * within the integer numbers limit. In addition we need to translate the
 107  * formulae to accept millidegrees of Celsius. Here what it looks like after
 108  * the alterations:
 109  *
 110  *   T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
 111  *       307620e-3*(N^1) + -52156
 112  *
 113  * where T = [-52156, 137961]mC and N = [0, 1023].
 114  */
 115 static const struct polynomial poly_N_to_temp = {
 116         .terms = {
 117                 {4,  -25761, 1000, 1},
 118                 {3,   97332, 1000, 1},
 119                 {2, -191650, 1000, 1},
 120                 {1,  307620, 1000, 1},
 121                 {0,  -52156,    1, 1}
 122         }
 123 };
 124
 125 static int gpy_hwmon_read(struct device *dev,
 126                           enum hwmon_sensor_types type,
 127                           u32 attr, int channel, long *value)
 128 {
 129         struct phy_device *phydev = dev_get_drvdata(dev);
 130         int ret;
 131
 132         ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VPSPEC1_TEMP_STA);
 133         if (ret < 0)
 134                 return ret;
 135         if (!ret)
 136                 return -ENODATA;
 137
 138         *value = polynomial_calc(&poly_N_to_temp,
 139                                  FIELD_GET(VPSPEC1_TEMP_STA_DATA, ret));
 140
 141         return 0;
 142 }
 143
 144 static umode_t gpy_hwmon_is_visible(const void *data,
 145                                     enum hwmon_sensor_types type,
 146                                     u32 attr, int channel)
 147 {
 148         return 0444;
 149 }
 150
 151 static const struct hwmon_channel_info *gpy_hwmon_info[] = {
 152         HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
 153         NULL
 154 };
 155
 156 static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
 157         .is_visible     = gpy_hwmon_is_visible,
 158         .read           = gpy_hwmon_read,
 159 };
 160
 161 static const struct hwmon_chip_info gpy_hwmon_chip_info = {
 162         .ops            = &gpy_hwmon_hwmon_ops,
 163         .info           = gpy_hwmon_info,
 164 };
 165
 166 static int gpy_hwmon_register(struct phy_device *phydev)
 167 {
 168         struct device *dev = &phydev->mdio.dev;
 169         struct device *hwmon_dev;
 170         char *hwmon_name;
 171
 172         hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
 173         if (IS_ERR(hwmon_name))
 174                 return PTR_ERR(hwmon_name);
 175
 176         hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
 177                                                          phydev,
 178                                                          &gpy_hwmon_chip_info,
 179                                                          NULL);
 180
 181         return PTR_ERR_OR_ZERO(hwmon_dev);
 182 }
 183 #else
 184 static int gpy_hwmon_register(struct phy_device *phydev)
 185 {
 186         return 0;
 187 }
 188 #endif
 189
 190 static int gpy_config_init(struct phy_device *phydev)
 191 {
 192         int ret;
 193
 194         /* Mask all interrupts */
 195         ret = phy_write(phydev, PHY_IMASK, 0);
 196         if (ret)
 197                 return ret;
 198
 199         /* Clear all pending interrupts */
 200         ret = phy_read(phydev, PHY_ISTAT);
 201         return ret < 0 ? ret : 0;
 202 }
 203
 204 static int gpy_probe(struct phy_device *phydev)
 205 {
 206         struct device *dev = &phydev->mdio.dev;
 207         struct gpy_priv *priv;
 208         int fw_version;
 209         int ret;
 210
 211         if (!phydev->is_c45) {
 212                 ret = phy_get_c45_ids(phydev);
 213                 if (ret < 0)
 214                         return ret;
 215         }
 216
 217         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 218         if (!priv)
 219                 return -ENOMEM;
 220         phydev->priv = priv;
 221
 222         fw_version = phy_read(phydev, PHY_FWV);
 223         if (fw_version < 0)
 224                 return fw_version;
 225         priv->fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_version);
 226         priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
 227
 228         ret = gpy_hwmon_register(phydev);
 229         if (ret)
 230                 return ret;
 231
 232         /* Show GPY PHY FW version in dmesg */
 233         phydev_info(phydev, "Firmware Version: 0x%04X (%s)\n", fw_version,
 234                     (fw_version & PHY_FWV_REL_MASK) ? "release" : "test");
 235
 236         return 0;
 237 }
 238
 239 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
 240 {
 241         struct gpy_priv *priv = phydev->priv;
 242         size_t i;
 243
 244         for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
 245                 if (priv->fw_type != ver_need_sgmii_reaneg[i].type)
 246                         continue;
 247                 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
 248                         return true;
 249                 break;
 250         }
 251
 252         return false;
 253 }
 254
 255 static bool gpy_2500basex_chk(struct phy_device *phydev)
 256 {
 257         int ret;
 258
 259         ret = phy_read(phydev, PHY_MIISTAT);
 260         if (ret < 0) {
 261                 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
 262                            ret);
 263                 return false;
 264         }
 265
 266         if (!(ret & PHY_MIISTAT_LS) ||
 267             FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
 268                 return false;
 269
 270         phydev->speed = SPEED_2500;
 271         phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 272         phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
 273                        VSPEC1_SGMII_CTRL_ANEN, 0);
 274         return true;
 275 }
 276
 277 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
 278 {
 279         int ret;
 280
 281         ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
 282         if (ret < 0) {
 283                 phydev_err(phydev, "Error: MMD register access failed: %d\n",
 284                            ret);
 285                 return true;
 286         }
 287
 288         return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
 289 }
 290
 291 static int gpy_config_aneg(struct phy_device *phydev)
 292 {
 293         bool changed = false;
 294         u32 adv;
 295         int ret;
 296
 297         if (phydev->autoneg == AUTONEG_DISABLE) {
 298                 /* Configure half duplex with genphy_setup_forced,
 299                  * because genphy_c45_pma_setup_forced does not support.
 300                  */
 301                 return phydev->duplex != DUPLEX_FULL
 302                         ? genphy_setup_forced(phydev)
 303                         : genphy_c45_pma_setup_forced(phydev);
 304         }
 305
 306         ret = genphy_c45_an_config_aneg(phydev);
 307         if (ret < 0)
 308                 return ret;
 309         if (ret > 0)
 310                 changed = true;
 311
 312         adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
 313         ret = phy_modify_changed(phydev, MII_CTRL1000,
 314                                  ADVERTISE_1000FULL | ADVERTISE_1000HALF,
 315                                  adv);
 316         if (ret < 0)
 317                 return ret;
 318         if (ret > 0)
 319                 changed = true;
 320
 321         ret = genphy_c45_check_and_restart_aneg(phydev, changed);
 322         if (ret < 0)
 323                 return ret;
 324
 325         if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
 326             phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
 327                 return 0;
 328
 329         /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
 330          * disabled.
 331          */
 332         if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
 333             !gpy_sgmii_aneg_en(phydev))
 334                 return 0;
 335
 336         /* There is a design constraint in GPY2xx device where SGMII AN is
 337          * only triggered when there is change of speed. If, PHY link
 338          * partner`s speed is still same even after PHY TPI is down and up
 339          * again, SGMII AN is not triggered and hence no new in-band message
 340          * from GPY to MAC side SGMII.
 341          * This could cause an issue during power up, when PHY is up prior to
 342          * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
 343          * wouldn`t receive new in-band message from GPY with correct link
 344          * status, speed and duplex info.
 345          *
 346          * 1) If PHY is already up and TPI link status is still down (such as
 347          *    hard reboot), TPI link status is polled for 4 seconds before
 348          *    retriggerring SGMII AN.
 349          * 2) If PHY is already up and TPI link status is also up (such as soft
 350          *    reboot), polling of TPI link status is not needed and SGMII AN is
 351          *    immediately retriggered.
 352          * 3) Other conditions such as PHY is down, speed change etc, skip
 353          *    retriggering SGMII AN. Note: in case of speed change, GPY FW will
 354          *    initiate SGMII AN.
 355          */
 356
 357         if (phydev->state != PHY_UP)
 358                 return 0;
 359
 360         ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
 361                                     20000, 4000000, false);
 362         if (ret == -ETIMEDOUT)
 363                 return 0;
 364         else if (ret < 0)
 365                 return ret;
 366
 367         /* Trigger SGMII AN. */
 368         return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
 369                               VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
 370 }
 371
 372 static void gpy_update_interface(struct phy_device *phydev)
 373 {
 374         int ret;
 375
 376         /* Interface mode is fixed for USXGMII and integrated PHY */
 377         if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
 378             phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
 379                 return;
 380
 381         /* Automatically switch SERDES interface between SGMII and 2500-BaseX
 382          * according to speed. Disable ANEG in 2500-BaseX mode.
 383          */
 384         switch (phydev->speed) {
 385         case SPEED_2500:
 386                 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 387                 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
 388                                      VSPEC1_SGMII_CTRL_ANEN, 0);
 389                 if (ret < 0)
 390                         phydev_err(phydev,
 391                                    "Error: Disable of SGMII ANEG failed: %d\n",
 392                                    ret);
 393                 break;
 394         case SPEED_1000:
 395         case SPEED_100:
 396         case SPEED_10:
 397                 phydev->interface = PHY_INTERFACE_MODE_SGMII;
 398                 if (gpy_sgmii_aneg_en(phydev))
 399                         break;
 400                 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
 401                  * if ANEG is disabled (in 2500-BaseX mode).
 402                  */
 403                 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
 404                                      VSPEC1_SGMII_ANEN_ANRS,
 405                                      VSPEC1_SGMII_ANEN_ANRS);
 406                 if (ret < 0)
 407                         phydev_err(phydev,
 408                                    "Error: Enable of SGMII ANEG failed: %d\n",
 409                                    ret);
 410                 break;
 411         }
 412
 413         if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000)
 414                 genphy_read_master_slave(phydev);
 415 }
 416
 417 static int gpy_read_status(struct phy_device *phydev)
 418 {
 419         int ret;
 420
 421         ret = genphy_update_link(phydev);
 422         if (ret)
 423                 return ret;
 424
 425         phydev->speed = SPEED_UNKNOWN;
 426         phydev->duplex = DUPLEX_UNKNOWN;
 427         phydev->pause = 0;
 428         phydev->asym_pause = 0;
 429
 430         if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
 431                 ret = genphy_c45_read_lpa(phydev);
 432                 if (ret < 0)
 433                         return ret;
 434
 435                 /* Read the link partner's 1G advertisement */
 436                 ret = phy_read(phydev, MII_STAT1000);
 437                 if (ret < 0)
 438                         return ret;
 439                 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
 440         } else if (phydev->autoneg == AUTONEG_DISABLE) {
 441                 linkmode_zero(phydev->lp_advertising);
 442         }
 443
 444         ret = phy_read(phydev, PHY_MIISTAT);
 445         if (ret < 0)
 446                 return ret;
 447
 448         phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
 449         phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
 450         switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
 451         case PHY_MIISTAT_SPD_10:
 452                 phydev->speed = SPEED_10;
 453                 break;
 454         case PHY_MIISTAT_SPD_100:
 455                 phydev->speed = SPEED_100;
 456                 break;
 457         case PHY_MIISTAT_SPD_1000:
 458                 phydev->speed = SPEED_1000;
 459                 break;
 460         case PHY_MIISTAT_SPD_2500:
 461                 phydev->speed = SPEED_2500;
 462                 break;
 463         }
 464
 465         if (phydev->link)
 466                 gpy_update_interface(phydev);
 467
 468         return 0;
 469 }
 470
 471 static int gpy_config_intr(struct phy_device *phydev)
 472 {
 473         u16 mask = 0;
 474
 475         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 476                 mask = PHY_IMASK_MASK;
 477
 478         return phy_write(phydev, PHY_IMASK, mask);
 479 }
 480
 481 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
 482 {
 483         int reg;
 484
 485         reg = phy_read(phydev, PHY_ISTAT);
 486         if (reg < 0) {
 487                 phy_error(phydev);
 488                 return IRQ_NONE;
 489         }
 490
 491         if (!(reg & PHY_IMASK_MASK))
 492                 return IRQ_NONE;
 493
 494         phy_trigger_machine(phydev);
 495
 496         return IRQ_HANDLED;
 497 }
 498
 499 static int gpy_set_wol(struct phy_device *phydev,
 500                        struct ethtool_wolinfo *wol)
 501 {
 502         struct net_device *attach_dev = phydev->attached_dev;
 503         int ret;
 504
 505         if (wol->wolopts & WAKE_MAGIC) {
 506                 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
 507                  * VPSPEC2_WOL_AD45 = Byte0:Byte1
 508                  * VPSPEC2_WOL_AD23 = Byte2:Byte3
 509                  * VPSPEC2_WOL_AD01 = Byte4:Byte5
 510                  */
 511                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
 512                                        VPSPEC2_WOL_AD45,
 513                                        ((attach_dev->dev_addr[0] << 8) |
 514                                        attach_dev->dev_addr[1]));
 515                 if (ret < 0)
 516                         return ret;
 517
 518                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
 519                                        VPSPEC2_WOL_AD23,
 520                                        ((attach_dev->dev_addr[2] << 8) |
 521                                        attach_dev->dev_addr[3]));
 522                 if (ret < 0)
 523                         return ret;
 524
 525                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
 526                                        VPSPEC2_WOL_AD01,
 527                                        ((attach_dev->dev_addr[4] << 8) |
 528                                        attach_dev->dev_addr[5]));
 529                 if (ret < 0)
 530                         return ret;
 531
 532                 /* Enable the WOL interrupt */
 533                 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
 534                 if (ret < 0)
 535                         return ret;
 536
 537                 /* Enable magic packet matching */
 538                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
 539                                        VPSPEC2_WOL_CTL,
 540                                        WOL_EN);
 541                 if (ret < 0)
 542                         return ret;
 543
 544                 /* Clear the interrupt status register.
 545                  * Only WoL is enabled so clear all.
 546                  */
 547                 ret = phy_read(phydev, PHY_ISTAT);
 548                 if (ret < 0)
 549                         return ret;
 550         } else {
 551                 /* Disable magic packet matching */
 552                 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
 553                                          VPSPEC2_WOL_CTL,
 554                                          WOL_EN);
 555                 if (ret < 0)
 556                         return ret;
 557         }
 558
 559         if (wol->wolopts & WAKE_PHY) {
 560                 /* Enable the link state change interrupt */
 561                 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
 562                 if (ret < 0)
 563                         return ret;
 564
 565                 /* Clear the interrupt status register */
 566                 ret = phy_read(phydev, PHY_ISTAT);
 567                 if (ret < 0)
 568                         return ret;
 569
 570                 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
 571                         phy_trigger_machine(phydev);
 572
 573                 return 0;
 574         }
 575
 576         /* Disable the link state change interrupt */
 577         return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
 578 }
 579
 580 static void gpy_get_wol(struct phy_device *phydev,
 581                         struct ethtool_wolinfo *wol)
 582 {
 583         int ret;
 584
 585         wol->supported = WAKE_MAGIC | WAKE_PHY;
 586         wol->wolopts = 0;
 587
 588         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
 589         if (ret & WOL_EN)
 590                 wol->wolopts |= WAKE_MAGIC;
 591
 592         ret = phy_read(phydev, PHY_IMASK);
 593         if (ret & PHY_IMASK_LSTC)
 594                 wol->wolopts |= WAKE_PHY;
 595 }
 596
 597 static int gpy_loopback(struct phy_device *phydev, bool enable)
 598 {
 599         int ret;
 600
 601         ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
 602                          enable ? BMCR_LOOPBACK : 0);
 603         if (!ret) {
 604                 /* It takes some time for PHY device to switch
 605                  * into/out-of loopback mode.
 606                  */
 607                 msleep(100);
 608         }
 609
 610         return ret;
 611 }
 612
 613 static int gpy115_loopback(struct phy_device *phydev, bool enable)
 614 {
 615         struct gpy_priv *priv = phydev->priv;
 616
 617         if (enable)
 618                 return gpy_loopback(phydev, enable);
 619
 620         if (priv->fw_minor > 0x76)
 621                 return gpy_loopback(phydev, 0);
 622
 623         return genphy_soft_reset(phydev);
 624 }
 625
 626 static struct phy_driver gpy_drivers[] = {
 627         {
 628                 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
 629                 .name           = "Maxlinear Ethernet GPY2xx",
 630                 .get_features   = genphy_c45_pma_read_abilities,
 631                 .config_init    = gpy_config_init,
 632                 .probe          = gpy_probe,
 633                 .suspend        = genphy_suspend,
 634                 .resume         = genphy_resume,
 635                 .config_aneg    = gpy_config_aneg,
 636                 .aneg_done      = genphy_c45_aneg_done,
 637                 .read_status    = gpy_read_status,
 638                 .config_intr    = gpy_config_intr,
 639                 .handle_interrupt = gpy_handle_interrupt,
 640                 .set_wol        = gpy_set_wol,
 641                 .get_wol        = gpy_get_wol,
 642                 .set_loopback   = gpy_loopback,
 643         },
 644         {
 645                 .phy_id         = PHY_ID_GPY115B,
 646                 .phy_id_mask    = PHY_ID_GPYx15B_MASK,
 647                 .name           = "Maxlinear Ethernet GPY115B",
 648                 .get_features   = genphy_c45_pma_read_abilities,
 649                 .config_init    = gpy_config_init,
 650                 .probe          = gpy_probe,
 651                 .suspend        = genphy_suspend,
 652                 .resume         = genphy_resume,
 653                 .config_aneg    = gpy_config_aneg,
 654                 .aneg_done      = genphy_c45_aneg_done,
 655                 .read_status    = gpy_read_status,
 656                 .config_intr    = gpy_config_intr,
 657                 .handle_interrupt = gpy_handle_interrupt,
 658                 .set_wol        = gpy_set_wol,
 659                 .get_wol        = gpy_get_wol,
 660                 .set_loopback   = gpy115_loopback,
 661         },
 662         {
 663                 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
 664                 .name           = "Maxlinear Ethernet GPY115C",
 665                 .get_features   = genphy_c45_pma_read_abilities,
 666                 .config_init    = gpy_config_init,
 667                 .probe          = gpy_probe,
 668                 .suspend        = genphy_suspend,
 669                 .resume         = genphy_resume,
 670                 .config_aneg    = gpy_config_aneg,
 671                 .aneg_done      = genphy_c45_aneg_done,
 672                 .read_status    = gpy_read_status,
 673                 .config_intr    = gpy_config_intr,
 674                 .handle_interrupt = gpy_handle_interrupt,
 675                 .set_wol        = gpy_set_wol,
 676                 .get_wol        = gpy_get_wol,
 677                 .set_loopback   = gpy115_loopback,
 678         },
 679         {
 680                 .phy_id         = PHY_ID_GPY211B,
 681                 .phy_id_mask    = PHY_ID_GPY21xB_MASK,
 682                 .name           = "Maxlinear Ethernet GPY211B",
 683                 .get_features   = genphy_c45_pma_read_abilities,
 684                 .config_init    = gpy_config_init,
 685                 .probe          = gpy_probe,
 686                 .suspend        = genphy_suspend,
 687                 .resume         = genphy_resume,
 688                 .config_aneg    = gpy_config_aneg,
 689                 .aneg_done      = genphy_c45_aneg_done,
 690                 .read_status    = gpy_read_status,
 691                 .config_intr    = gpy_config_intr,
 692                 .handle_interrupt = gpy_handle_interrupt,
 693                 .set_wol        = gpy_set_wol,
 694                 .get_wol        = gpy_get_wol,
 695                 .set_loopback   = gpy_loopback,
 696         },
 697         {
 698                 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
 699                 .name           = "Maxlinear Ethernet GPY211C",
 700                 .get_features   = genphy_c45_pma_read_abilities,
 701                 .config_init    = gpy_config_init,
 702                 .probe          = gpy_probe,
 703                 .suspend        = genphy_suspend,
 704                 .resume         = genphy_resume,
 705                 .config_aneg    = gpy_config_aneg,
 706                 .aneg_done      = genphy_c45_aneg_done,
 707                 .read_status    = gpy_read_status,
 708                 .config_intr    = gpy_config_intr,
 709                 .handle_interrupt = gpy_handle_interrupt,
 710                 .set_wol        = gpy_set_wol,
 711                 .get_wol        = gpy_get_wol,
 712                 .set_loopback   = gpy_loopback,
 713         },
 714         {
 715                 .phy_id         = PHY_ID_GPY212B,
 716                 .phy_id_mask    = PHY_ID_GPY21xB_MASK,
 717                 .name           = "Maxlinear Ethernet GPY212B",
 718                 .get_features   = genphy_c45_pma_read_abilities,
 719                 .config_init    = gpy_config_init,
 720                 .probe          = gpy_probe,
 721                 .suspend        = genphy_suspend,
 722                 .resume         = genphy_resume,
 723                 .config_aneg    = gpy_config_aneg,
 724                 .aneg_done      = genphy_c45_aneg_done,
 725                 .read_status    = gpy_read_status,
 726                 .config_intr    = gpy_config_intr,
 727                 .handle_interrupt = gpy_handle_interrupt,
 728                 .set_wol        = gpy_set_wol,
 729                 .get_wol        = gpy_get_wol,
 730                 .set_loopback   = gpy_loopback,
 731         },
 732         {
 733                 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
 734                 .name           = "Maxlinear Ethernet GPY212C",
 735                 .get_features   = genphy_c45_pma_read_abilities,
 736                 .config_init    = gpy_config_init,
 737                 .probe          = gpy_probe,
 738                 .suspend        = genphy_suspend,
 739                 .resume         = genphy_resume,
 740                 .config_aneg    = gpy_config_aneg,
 741                 .aneg_done      = genphy_c45_aneg_done,
 742                 .read_status    = gpy_read_status,
 743                 .config_intr    = gpy_config_intr,
 744                 .handle_interrupt = gpy_handle_interrupt,
 745                 .set_wol        = gpy_set_wol,
 746                 .get_wol        = gpy_get_wol,
 747                 .set_loopback   = gpy_loopback,
 748         },
 749         {
 750                 .phy_id         = PHY_ID_GPY215B,
 751                 .phy_id_mask    = PHY_ID_GPYx15B_MASK,
 752                 .name           = "Maxlinear Ethernet GPY215B",
 753                 .get_features   = genphy_c45_pma_read_abilities,
 754                 .config_init    = gpy_config_init,
 755                 .probe          = gpy_probe,
 756                 .suspend        = genphy_suspend,
 757                 .resume         = genphy_resume,
 758                 .config_aneg    = gpy_config_aneg,
 759                 .aneg_done      = genphy_c45_aneg_done,
 760                 .read_status    = gpy_read_status,
 761                 .config_intr    = gpy_config_intr,
 762                 .handle_interrupt = gpy_handle_interrupt,
 763                 .set_wol        = gpy_set_wol,
 764                 .get_wol        = gpy_get_wol,
 765                 .set_loopback   = gpy_loopback,
 766         },
 767         {
 768                 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
 769                 .name           = "Maxlinear Ethernet GPY215C",
 770                 .get_features   = genphy_c45_pma_read_abilities,
 771                 .config_init    = gpy_config_init,
 772                 .probe          = gpy_probe,
 773                 .suspend        = genphy_suspend,
 774                 .resume         = genphy_resume,
 775                 .config_aneg    = gpy_config_aneg,
 776                 .aneg_done      = genphy_c45_aneg_done,
 777                 .read_status    = gpy_read_status,
 778                 .config_intr    = gpy_config_intr,
 779                 .handle_interrupt = gpy_handle_interrupt,
 780                 .set_wol        = gpy_set_wol,
 781                 .get_wol        = gpy_get_wol,
 782                 .set_loopback   = gpy_loopback,
 783         },
 784         {
 785                 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
 786                 .name           = "Maxlinear Ethernet GPY241B",
 787                 .get_features   = genphy_c45_pma_read_abilities,
 788                 .config_init    = gpy_config_init,
 789                 .probe          = gpy_probe,
 790                 .suspend        = genphy_suspend,
 791                 .resume         = genphy_resume,
 792                 .config_aneg    = gpy_config_aneg,
 793                 .aneg_done      = genphy_c45_aneg_done,
 794                 .read_status    = gpy_read_status,
 795                 .config_intr    = gpy_config_intr,
 796                 .handle_interrupt = gpy_handle_interrupt,
 797                 .set_wol        = gpy_set_wol,
 798                 .get_wol        = gpy_get_wol,
 799                 .set_loopback   = gpy_loopback,
 800         },
 801         {
 802                 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
 803                 .name           = "Maxlinear Ethernet GPY241BM",
 804                 .get_features   = genphy_c45_pma_read_abilities,
 805                 .config_init    = gpy_config_init,
 806                 .probe          = gpy_probe,
 807                 .suspend        = genphy_suspend,
 808                 .resume         = genphy_resume,
 809                 .config_aneg    = gpy_config_aneg,
 810                 .aneg_done      = genphy_c45_aneg_done,
 811                 .read_status    = gpy_read_status,
 812                 .config_intr    = gpy_config_intr,
 813                 .handle_interrupt = gpy_handle_interrupt,
 814                 .set_wol        = gpy_set_wol,
 815                 .get_wol        = gpy_get_wol,
 816                 .set_loopback   = gpy_loopback,
 817         },
 818         {
 819                 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
 820                 .name           = "Maxlinear Ethernet GPY245B",
 821                 .get_features   = genphy_c45_pma_read_abilities,
 822                 .config_init    = gpy_config_init,
 823                 .probe          = gpy_probe,
 824                 .suspend        = genphy_suspend,
 825                 .resume         = genphy_resume,
 826                 .config_aneg    = gpy_config_aneg,
 827                 .aneg_done      = genphy_c45_aneg_done,
 828                 .read_status    = gpy_read_status,
 829                 .config_intr    = gpy_config_intr,
 830                 .handle_interrupt = gpy_handle_interrupt,
 831                 .set_wol        = gpy_set_wol,
 832                 .get_wol        = gpy_get_wol,
 833                 .set_loopback   = gpy_loopback,
 834         },
 835 };
 836 module_phy_driver(gpy_drivers);
 837
 838 static struct mdio_device_id __maybe_unused gpy_tbl[] = {
 839         {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
 840         {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
 841         {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
 842         {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
 843         {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
 844         {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
 845         {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
 846         {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
 847         {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
 848         {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
 849         {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
 850         {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
 851         { }
 852 };
 853 MODULE_DEVICE_TABLE(mdio, gpy_tbl);
 854
 855 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
 856 MODULE_AUTHOR("Xu Liang");
 857 MODULE_LICENSE("GPL");