1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for Microsemi VSC85xx PHYs
5 * Author: Nagaraju Lakkaraju
6 * License: Dual MIT/GPL
7 * Copyright (c) 2016 Microsemi Corporation
10 #include <linux/firmware.h>
11 #include <linux/jiffies.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mdio.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
18 #include <linux/netdevice.h>
19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
21 enum rgmii_rx_clock_delay {
22 RGMII_RX_CLK_DELAY_0_2_NS = 0,
23 RGMII_RX_CLK_DELAY_0_8_NS = 1,
24 RGMII_RX_CLK_DELAY_1_1_NS = 2,
25 RGMII_RX_CLK_DELAY_1_7_NS = 3,
26 RGMII_RX_CLK_DELAY_2_0_NS = 4,
27 RGMII_RX_CLK_DELAY_2_3_NS = 5,
28 RGMII_RX_CLK_DELAY_2_6_NS = 6,
29 RGMII_RX_CLK_DELAY_3_4_NS = 7
32 /* Microsemi VSC85xx PHY registers */
33 /* IEEE 802. Std Registers */
34 #define MSCC_PHY_BYPASS_CONTROL 18
35 #define DISABLE_HP_AUTO_MDIX_MASK 0x0080
36 #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
37 #define DISABLE_POLARITY_CORR_MASK 0x0010
38 #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
40 #define MSCC_PHY_EXT_CNTL_STATUS 22
41 #define SMI_BROADCAST_WR_EN 0x0001
43 #define MSCC_PHY_ERR_RX_CNT 19
44 #define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20
45 #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21
46 #define ERR_CNT_MASK GENMASK(7, 0)
48 #define MSCC_PHY_EXT_PHY_CNTL_1 23
49 #define MAC_IF_SELECTION_MASK 0x1800
50 #define MAC_IF_SELECTION_GMII 0
51 #define MAC_IF_SELECTION_RMII 1
52 #define MAC_IF_SELECTION_RGMII 2
53 #define MAC_IF_SELECTION_POS 11
54 #define VSC8584_MAC_IF_SELECTION_MASK 0x1000
55 #define VSC8584_MAC_IF_SELECTION_SGMII 0
56 #define VSC8584_MAC_IF_SELECTION_1000BASEX 1
57 #define VSC8584_MAC_IF_SELECTION_POS 12
58 #define FAR_END_LOOPBACK_MODE_MASK 0x0008
59 #define MEDIA_OP_MODE_MASK 0x0700
60 #define MEDIA_OP_MODE_COPPER 0
61 #define MEDIA_OP_MODE_SERDES 1
62 #define MEDIA_OP_MODE_1000BASEX 2
63 #define MEDIA_OP_MODE_100BASEFX 3
64 #define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
65 #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
66 #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
67 #define MEDIA_OP_MODE_POS 8
69 #define MSCC_PHY_EXT_PHY_CNTL_2 24
71 #define MII_VSC85XX_INT_MASK 25
72 #define MII_VSC85XX_INT_MASK_MASK 0xa000
73 #define MII_VSC85XX_INT_MASK_WOL 0x0040
74 #define MII_VSC85XX_INT_STATUS 26
76 #define MSCC_PHY_WOL_MAC_CONTROL 27
77 #define EDGE_RATE_CNTL_POS 5
78 #define EDGE_RATE_CNTL_MASK 0x00E0
80 #define MSCC_PHY_DEV_AUX_CNTL 28
81 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
83 #define MSCC_PHY_LED_MODE_SEL 29
84 #define LED_MODE_SEL_POS(x) ((x) * 4)
85 #define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
86 #define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
88 #define MSCC_EXT_PAGE_CSR_CNTL_17 17
89 #define MSCC_EXT_PAGE_CSR_CNTL_18 18
91 #define MSCC_EXT_PAGE_CSR_CNTL_19 19
92 #define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x)
93 #define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12)
94 #define MSCC_PHY_CSR_CNTL_19_READ BIT(14)
95 #define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)
97 #define MSCC_EXT_PAGE_CSR_CNTL_20 20
98 #define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x)
100 #define PHY_MCB_TARGET 0x07
101 #define PHY_MCB_S6G_WRITE BIT(31)
102 #define PHY_MCB_S6G_READ BIT(30)
104 #define PHY_S6G_PLL5G_CFG0 0x06
105 #define PHY_S6G_LCPLL_CFG 0x11
106 #define PHY_S6G_PLL_CFG 0x2b
107 #define PHY_S6G_COMMON_CFG 0x2c
108 #define PHY_S6G_GPC_CFG 0x2e
109 #define PHY_S6G_MISC_CFG 0x3b
110 #define PHY_MCB_S6G_CFG 0x3f
111 #define PHY_S6G_DFT_CFG2 0x3e
112 #define PHY_S6G_PLL_STATUS 0x31
113 #define PHY_S6G_IB_STATUS0 0x2f
115 #define PHY_S6G_SYS_RST_POS 31
116 #define PHY_S6G_ENA_LANE_POS 18
117 #define PHY_S6G_ENA_LOOP_POS 8
118 #define PHY_S6G_QRATE_POS 6
119 #define PHY_S6G_IF_MODE_POS 4
120 #define PHY_S6G_PLL_ENA_OFFS_POS 21
121 #define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8
122 #define PHY_S6G_PLL_FSM_ENA_POS 7
124 #define MSCC_EXT_PAGE_ACCESS 31
125 #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
126 #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
127 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
128 #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
129 #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
130 #define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4
131 /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
132 * in the same package.
134 #define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
135 #define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
136 #define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
138 /* Extended Page 1 Registers */
139 #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18
140 #define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
142 #define MSCC_PHY_EXT_MODE_CNTL 19
143 #define FORCE_MDI_CROSSOVER_MASK 0x000C
144 #define FORCE_MDI_CROSSOVER_MDIX 0x000C
145 #define FORCE_MDI_CROSSOVER_MDI 0x0008
147 #define MSCC_PHY_ACTIPHY_CNTL 20
148 #define PHY_ADDR_REVERSED 0x0200
149 #define DOWNSHIFT_CNTL_MASK 0x001C
150 #define DOWNSHIFT_EN 0x0010
151 #define DOWNSHIFT_CNTL_POS 2
153 #define MSCC_PHY_EXT_PHY_CNTL_4 23
154 #define PHY_CNTL_4_ADDR_POS 11
156 #define MSCC_PHY_VERIPHY_CNTL_2 25
158 #define MSCC_PHY_VERIPHY_CNTL_3 26
160 /* Extended Page 2 Registers */
161 #define MSCC_PHY_CU_PMD_TX_CNTL 16
163 #define MSCC_PHY_RGMII_CNTL 20
164 #define RGMII_RX_CLK_DELAY_MASK 0x0070
165 #define RGMII_RX_CLK_DELAY_POS 4
167 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
168 #define MSCC_PHY_WOL_MID_MAC_ADDR 22
169 #define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
170 #define MSCC_PHY_WOL_LOWER_PASSWD 24
171 #define MSCC_PHY_WOL_MID_PASSWD 25
172 #define MSCC_PHY_WOL_UPPER_PASSWD 26
174 #define MSCC_PHY_WOL_MAC_CONTROL 27
175 #define SECURE_ON_ENABLE 0x8000
176 #define SECURE_ON_PASSWD_LEN_4 0x4000
178 /* Extended Page 3 Registers */
179 #define MSCC_PHY_SERDES_TX_VALID_CNT 21
180 #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
181 #define MSCC_PHY_SERDES_RX_VALID_CNT 28
182 #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29
184 /* Extended page GPIO Registers */
185 #define MSCC_DW8051_CNTL_STATUS 0
186 #define MICRO_NSOFT_RESET 0x8000
187 #define RUN_FROM_INT_ROM 0x4000
188 #define AUTOINC_ADDR 0x2000
189 #define PATCH_RAM_CLK 0x1000
190 #define MICRO_PATCH_EN 0x0080
191 #define DW8051_CLK_EN 0x0010
192 #define MICRO_CLK_EN 0x0008
193 #define MICRO_CLK_DIVIDE(x) ((x) >> 1)
194 #define MSCC_DW8051_VLD_MASK 0xf1ff
196 /* x Address in range 1-4 */
197 #define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
198 #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
199 #define MSCC_INT_MEM_ADDR 11
201 #define MSCC_INT_MEM_CNTL 12
202 #define READ_SFR 0x6000
203 #define READ_PRAM 0x4000
204 #define READ_ROM 0x2000
205 #define READ_RAM 0x0000
206 #define INT_MEM_WRITE_EN 0x1000
207 #define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
208 #define INT_MEM_DATA_M 0x00ff
209 #define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
211 #define MSCC_PHY_PROC_CMD 18
212 #define PROC_CMD_NCOMPLETED 0x8000
213 #define PROC_CMD_FAILED 0x4000
214 #define PROC_CMD_SGMII_PORT(x) ((x) << 8)
215 #define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
216 #define PROC_CMD_QSGMII_PORT 0x0c00
217 #define PROC_CMD_RST_CONF_PORT 0x0080
218 #define PROC_CMD_RECONF_PORT 0x0000
219 #define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
220 #define PROC_CMD_WRITE 0x0040
221 #define PROC_CMD_READ 0x0000
222 #define PROC_CMD_FIBER_DISABLE 0x0020
223 #define PROC_CMD_FIBER_100BASE_FX 0x0010
224 #define PROC_CMD_FIBER_1000BASE_X 0x0000
225 #define PROC_CMD_SGMII_MAC 0x0030
226 #define PROC_CMD_QSGMII_MAC 0x0020
227 #define PROC_CMD_NO_MAC_CONF 0x0000
228 #define PROC_CMD_1588_DEFAULT_INIT 0x0010
229 #define PROC_CMD_NOP 0x000f
230 #define PROC_CMD_PHY_INIT 0x000a
231 #define PROC_CMD_CRC16 0x0008
232 #define PROC_CMD_FIBER_MEDIA_CONF 0x0001
233 #define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
234 #define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
236 #define MSCC_PHY_MAC_CFG_FASTLINK 19
237 #define MAC_CFG_MASK 0xc000
238 #define MAC_CFG_SGMII 0x0000
239 #define MAC_CFG_QSGMII 0x4000
241 /* Test page Registers */
242 #define MSCC_PHY_TEST_PAGE_5 5
243 #define MSCC_PHY_TEST_PAGE_8 8
244 #define MSCC_PHY_TEST_PAGE_9 9
245 #define MSCC_PHY_TEST_PAGE_20 20
246 #define MSCC_PHY_TEST_PAGE_24 24
248 /* Token ring page Registers */
249 #define MSCC_PHY_TR_CNTL 16
250 #define TR_WRITE 0x8000
251 #define TR_ADDR(x) (0x7fff & (x))
252 #define MSCC_PHY_TR_LSB 17
253 #define MSCC_PHY_TR_MSB 18
255 /* Microsemi PHY ID's
256 * Code assumes lowest nibble is 0
258 #define PHY_ID_VSC8504 0x000704c0
259 #define PHY_ID_VSC8514 0x00070670
260 #define PHY_ID_VSC8530 0x00070560
261 #define PHY_ID_VSC8531 0x00070570
262 #define PHY_ID_VSC8540 0x00070760
263 #define PHY_ID_VSC8541 0x00070770
264 #define PHY_ID_VSC8552 0x000704e0
265 #define PHY_ID_VSC856X 0x000707e0
266 #define PHY_ID_VSC8572 0x000704d0
267 #define PHY_ID_VSC8574 0x000704a0
268 #define PHY_ID_VSC8575 0x000707d0
269 #define PHY_ID_VSC8582 0x000707b0
270 #define PHY_ID_VSC8584 0x000707c0
272 #define MSCC_VDDMAC_1500 1500
273 #define MSCC_VDDMAC_1800 1800
274 #define MSCC_VDDMAC_2500 2500
275 #define MSCC_VDDMAC_3300 3300
277 #define DOWNSHIFT_COUNT_MAX 5
281 #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
282 BIT(VSC8531_LINK_1000_ACTIVITY) | \
283 BIT(VSC8531_LINK_100_ACTIVITY) | \
284 BIT(VSC8531_LINK_10_ACTIVITY) | \
285 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
286 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
287 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
288 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
289 BIT(VSC8531_DUPLEX_COLLISION) | \
290 BIT(VSC8531_COLLISION) | \
291 BIT(VSC8531_ACTIVITY) | \
292 BIT(VSC8584_100FX_1000X_ACTIVITY) | \
293 BIT(VSC8531_AUTONEG_FAULT) | \
294 BIT(VSC8531_SERIAL_MODE) | \
295 BIT(VSC8531_FORCE_LED_OFF) | \
296 BIT(VSC8531_FORCE_LED_ON))
298 #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
299 BIT(VSC8531_LINK_1000_ACTIVITY) | \
300 BIT(VSC8531_LINK_100_ACTIVITY) | \
301 BIT(VSC8531_LINK_10_ACTIVITY) | \
302 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
303 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
304 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
305 BIT(VSC8531_DUPLEX_COLLISION) | \
306 BIT(VSC8531_COLLISION) | \
307 BIT(VSC8531_ACTIVITY) | \
308 BIT(VSC8531_AUTONEG_FAULT) | \
309 BIT(VSC8531_SERIAL_MODE) | \
310 BIT(VSC8531_FORCE_LED_OFF) | \
311 BIT(VSC8531_FORCE_LED_ON))
313 #define MSCC_VSC8584_REVB_INT8051_FW "mscc_vsc8584_revb_int8051_fb48.bin"
314 #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
315 #define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
317 #define MSCC_VSC8574_REVB_INT8051_FW "mscc_vsc8574_revb_int8051_29e8.bin"
318 #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
319 #define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
321 #define VSC8584_REVB 0x0001
322 #define MSCC_DEV_REV_MASK GENMASK(3, 0)
329 struct vsc85xx_hw_stat {
336 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
338 .string = "phy_receive_errors",
339 .reg = MSCC_PHY_ERR_RX_CNT,
340 .page = MSCC_PHY_PAGE_STANDARD,
341 .mask = ERR_CNT_MASK,
343 .string = "phy_false_carrier",
344 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
345 .page = MSCC_PHY_PAGE_STANDARD,
346 .mask = ERR_CNT_MASK,
348 .string = "phy_cu_media_link_disconnect",
349 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
350 .page = MSCC_PHY_PAGE_STANDARD,
351 .mask = ERR_CNT_MASK,
353 .string = "phy_cu_media_crc_good_count",
354 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
355 .page = MSCC_PHY_PAGE_EXTENDED,
356 .mask = VALID_CRC_CNT_CRC_MASK,
358 .string = "phy_cu_media_crc_error_count",
359 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
360 .page = MSCC_PHY_PAGE_EXTENDED,
361 .mask = ERR_CNT_MASK,
365 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
367 .string = "phy_receive_errors",
368 .reg = MSCC_PHY_ERR_RX_CNT,
369 .page = MSCC_PHY_PAGE_STANDARD,
370 .mask = ERR_CNT_MASK,
372 .string = "phy_false_carrier",
373 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
374 .page = MSCC_PHY_PAGE_STANDARD,
375 .mask = ERR_CNT_MASK,
377 .string = "phy_cu_media_link_disconnect",
378 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
379 .page = MSCC_PHY_PAGE_STANDARD,
380 .mask = ERR_CNT_MASK,
382 .string = "phy_cu_media_crc_good_count",
383 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
384 .page = MSCC_PHY_PAGE_EXTENDED,
385 .mask = VALID_CRC_CNT_CRC_MASK,
387 .string = "phy_cu_media_crc_error_count",
388 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
389 .page = MSCC_PHY_PAGE_EXTENDED,
390 .mask = ERR_CNT_MASK,
392 .string = "phy_serdes_tx_good_pkt_count",
393 .reg = MSCC_PHY_SERDES_TX_VALID_CNT,
394 .page = MSCC_PHY_PAGE_EXTENDED_3,
395 .mask = VALID_CRC_CNT_CRC_MASK,
397 .string = "phy_serdes_tx_bad_crc_count",
398 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
399 .page = MSCC_PHY_PAGE_EXTENDED_3,
400 .mask = ERR_CNT_MASK,
402 .string = "phy_serdes_rx_good_pkt_count",
403 .reg = MSCC_PHY_SERDES_RX_VALID_CNT,
404 .page = MSCC_PHY_PAGE_EXTENDED_3,
405 .mask = VALID_CRC_CNT_CRC_MASK,
407 .string = "phy_serdes_rx_bad_crc_count",
408 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
409 .page = MSCC_PHY_PAGE_EXTENDED_3,
410 .mask = ERR_CNT_MASK,
414 struct vsc8531_private {
417 u32 leds_mode[MAX_LEDS];
419 const struct vsc85xx_hw_stat *hw_stats;
423 /* For multiple port PHYs; the MDIO address of the base PHY in the
426 unsigned int base_addr;
429 #ifdef CONFIG_OF_MDIO
430 struct vsc8531_edge_rate_table {
435 static const struct vsc8531_edge_rate_table edge_table[] = {
436 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
437 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
438 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
439 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
441 #endif /* CONFIG_OF_MDIO */
443 static int vsc85xx_phy_read_page(struct phy_device *phydev)
445 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
448 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
450 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
453 static int vsc85xx_get_sset_count(struct phy_device *phydev)
455 struct vsc8531_private *priv = phydev->priv;
463 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
465 struct vsc8531_private *priv = phydev->priv;
471 for (i = 0; i < priv->nstats; i++)
472 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
476 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
478 struct vsc8531_private *priv = phydev->priv;
481 val = phy_read_paged(phydev, priv->hw_stats[i].page,
482 priv->hw_stats[i].reg);
486 val = val & priv->hw_stats[i].mask;
487 priv->stats[i] += val;
489 return priv->stats[i];
492 static void vsc85xx_get_stats(struct phy_device *phydev,
493 struct ethtool_stats *stats, u64 *data)
495 struct vsc8531_private *priv = phydev->priv;
501 for (i = 0; i < priv->nstats; i++)
502 data[i] = vsc85xx_get_stat(phydev, i);
505 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
512 mutex_lock(&phydev->lock);
513 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
514 reg_val &= ~LED_MODE_SEL_MASK(led_num);
515 reg_val |= LED_MODE_SEL(led_num, (u16)mode);
516 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
517 mutex_unlock(&phydev->lock);
522 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
526 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
527 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
528 *mdix = ETH_TP_MDI_X;
535 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
540 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
541 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
542 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
543 DISABLE_POLARITY_CORR_MASK |
544 DISABLE_HP_AUTO_MDIX_MASK);
546 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
547 DISABLE_POLARITY_CORR_MASK |
548 DISABLE_HP_AUTO_MDIX_MASK);
550 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
556 if (mdix == ETH_TP_MDI)
557 reg_val = FORCE_MDI_CROSSOVER_MDI;
558 else if (mdix == ETH_TP_MDI_X)
559 reg_val = FORCE_MDI_CROSSOVER_MDIX;
561 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
562 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
567 return genphy_restart_aneg(phydev);
570 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
574 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
575 MSCC_PHY_ACTIPHY_CNTL);
579 reg_val &= DOWNSHIFT_CNTL_MASK;
580 if (!(reg_val & DOWNSHIFT_EN))
581 *count = DOWNSHIFT_DEV_DISABLE;
583 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
588 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
590 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
591 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
592 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
593 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
594 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
597 /* Downshift count is either 2,3,4 or 5 */
598 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
601 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
602 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
606 static int vsc85xx_wol_set(struct phy_device *phydev,
607 struct ethtool_wolinfo *wol)
612 u16 pwd[3] = {0, 0, 0};
613 struct ethtool_wolinfo *wol_conf = wol;
614 u8 *mac_addr = phydev->attached_dev->dev_addr;
616 mutex_lock(&phydev->lock);
617 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
619 rc = phy_restore_page(phydev, rc, rc);
623 if (wol->wolopts & WAKE_MAGIC) {
624 /* Store the device address for the magic packet */
625 for (i = 0; i < ARRAY_SIZE(pwd); i++)
626 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
628 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
629 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
630 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
632 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
633 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
634 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
637 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
638 for (i = 0; i < ARRAY_SIZE(pwd); i++)
639 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
640 wol_conf->sopass[5 - i * 2];
641 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
642 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
643 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
645 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
646 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
647 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
650 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
651 if (wol_conf->wolopts & WAKE_MAGICSECURE)
652 reg_val |= SECURE_ON_ENABLE;
654 reg_val &= ~SECURE_ON_ENABLE;
655 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
657 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
661 if (wol->wolopts & WAKE_MAGIC) {
662 /* Enable the WOL interrupt */
663 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
664 reg_val |= MII_VSC85XX_INT_MASK_WOL;
665 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
669 /* Disable the WOL interrupt */
670 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
671 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
672 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
676 /* Clear WOL iterrupt status */
677 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
680 mutex_unlock(&phydev->lock);
685 static void vsc85xx_wol_get(struct phy_device *phydev,
686 struct ethtool_wolinfo *wol)
691 u16 pwd[3] = {0, 0, 0};
692 struct ethtool_wolinfo *wol_conf = wol;
694 mutex_lock(&phydev->lock);
695 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
699 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
700 if (reg_val & SECURE_ON_ENABLE)
701 wol_conf->wolopts |= WAKE_MAGICSECURE;
702 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
703 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
704 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
705 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
706 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
707 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
708 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
714 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
715 mutex_unlock(&phydev->lock);
718 #ifdef CONFIG_OF_MDIO
719 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
723 struct device *dev = &phydev->mdio.dev;
724 struct device_node *of_node = dev->of_node;
725 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
730 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
731 vdd = MSCC_VDDMAC_3300;
733 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
736 for (i = 0; i < ARRAY_SIZE(edge_table); i++)
737 if (edge_table[i].vddmac == vdd)
738 for (j = 0; j < sd_array_size; j++)
739 if (edge_table[i].slowdown[j] == sd)
740 return (sd_array_size - j - 1);
745 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
749 struct vsc8531_private *priv = phydev->priv;
750 struct device *dev = &phydev->mdio.dev;
751 struct device_node *of_node = dev->of_node;
758 led_mode = default_mode;
759 err = of_property_read_u32(of_node, led, &led_mode);
760 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
761 phydev_err(phydev, "DT %s invalid\n", led);
769 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
774 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
780 #endif /* CONFIG_OF_MDIO */
782 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
785 struct vsc8531_private *priv = phydev->priv;
786 char led_dt_prop[28];
789 for (i = 0; i < priv->nleds; i++) {
790 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
794 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
798 priv->leds_mode[i] = ret;
804 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
808 mutex_lock(&phydev->lock);
809 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
810 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
811 edge_rate << EDGE_RATE_CNTL_POS);
812 mutex_unlock(&phydev->lock);
817 static int vsc85xx_mac_if_set(struct phy_device *phydev,
818 phy_interface_t interface)
823 mutex_lock(&phydev->lock);
824 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
825 reg_val &= ~(MAC_IF_SELECTION_MASK);
827 case PHY_INTERFACE_MODE_RGMII:
828 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
830 case PHY_INTERFACE_MODE_RMII:
831 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
833 case PHY_INTERFACE_MODE_MII:
834 case PHY_INTERFACE_MODE_GMII:
835 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
841 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
845 rc = genphy_soft_reset(phydev);
848 mutex_unlock(&phydev->lock);
853 static int vsc85xx_default_config(struct phy_device *phydev)
858 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
859 mutex_lock(&phydev->lock);
861 reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
863 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
864 MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
867 mutex_unlock(&phydev->lock);
872 static int vsc85xx_get_tunable(struct phy_device *phydev,
873 struct ethtool_tunable *tuna, void *data)
876 case ETHTOOL_PHY_DOWNSHIFT:
877 return vsc85xx_downshift_get(phydev, (u8 *)data);
883 static int vsc85xx_set_tunable(struct phy_device *phydev,
884 struct ethtool_tunable *tuna,
888 case ETHTOOL_PHY_DOWNSHIFT:
889 return vsc85xx_downshift_set(phydev, *(u8 *)data);
895 /* mdiobus lock should be locked when using this function */
896 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
898 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
899 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
900 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
903 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
906 static const struct reg_val init_seq[] = {
907 {0x0f90, 0x00688980},
908 {0x0696, 0x00000003},
909 {0x07fa, 0x0050100f},
910 {0x1686, 0x00000004},
915 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
916 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
917 SMI_BROADCAST_WR_EN);
920 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
921 MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
924 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
925 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
928 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
929 MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000);
933 mutex_lock(&phydev->lock);
934 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
938 for (i = 0; i < ARRAY_SIZE(init_seq); i++)
939 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
942 oldpage = phy_restore_page(phydev, oldpage, oldpage);
943 mutex_unlock(&phydev->lock);
948 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
950 static const struct reg_val init_eee[] = {
951 {0x0f82, 0x0012b00a},
952 {0x1686, 0x00000004},
953 {0x168c, 0x00d2c46f},
954 {0x17a2, 0x00000620},
955 {0x16a0, 0x00eeffdd},
956 {0x16a6, 0x00071448},
957 {0x16a4, 0x0013132f},
958 {0x16a8, 0x00000000},
959 {0x0ffc, 0x00c0a028},
960 {0x0fe8, 0x0091b06c},
961 {0x0fea, 0x00041600},
962 {0x0f80, 0x00000af4},
963 {0x0fec, 0x00901809},
964 {0x0fee, 0x0000a6a1},
965 {0x0ffe, 0x00b01007},
966 {0x16b0, 0x00eeff00},
967 {0x16b2, 0x00007000},
968 {0x16b4, 0x00000814},
973 mutex_lock(&phydev->lock);
974 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
978 for (i = 0; i < ARRAY_SIZE(init_eee); i++)
979 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
982 oldpage = phy_restore_page(phydev, oldpage, oldpage);
983 mutex_unlock(&phydev->lock);
988 /* phydev->bus->mdio_lock should be locked when using this function */
989 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
991 struct vsc8531_private *priv = phydev->priv;
993 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
994 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
998 return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val);
1001 /* phydev->bus->mdio_lock should be locked when using this function */
1002 static int phy_base_read(struct phy_device *phydev, u32 regnum)
1004 struct vsc8531_private *priv = phydev->priv;
1006 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
1007 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
1011 return __mdiobus_read(phydev->mdio.bus, priv->base_addr, regnum);
1014 /* bus->mdio_lock should be locked when using this function */
1015 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
1017 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
1018 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
1019 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
1022 /* bus->mdio_lock should be locked when using this function */
1023 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
1025 unsigned long deadline;
1028 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1029 MSCC_PHY_PAGE_EXTENDED_GPIO);
1031 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
1033 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1035 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
1036 } while (time_before(jiffies, deadline) &&
1037 (reg_val & PROC_CMD_NCOMPLETED) &&
1038 !(reg_val & PROC_CMD_FAILED));
1040 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1042 if (reg_val & PROC_CMD_FAILED)
1045 if (reg_val & PROC_CMD_NCOMPLETED)
1051 /* bus->mdio_lock should be locked when using this function */
1052 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
1055 u32 enable, release;
1057 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1058 MSCC_PHY_PAGE_EXTENDED_GPIO);
1060 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
1061 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
1065 enable |= MICRO_PATCH_EN;
1066 release |= MICRO_PATCH_EN;
1068 /* Clear all patches */
1069 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
1072 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
1073 * override and addr. auto-incr; operate at 125 MHz
1075 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
1076 /* Release 8051 Micro SW reset */
1077 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
1079 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1084 /* bus->mdio_lock should be locked when using this function */
1085 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
1090 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
1094 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1095 MSCC_PHY_PAGE_EXTENDED_GPIO);
1097 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1098 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
1099 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1101 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
1102 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
1104 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1105 reg |= EN_PATCH_RAM_TRAP_ADDR(4);
1106 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1108 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
1110 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1111 reg &= ~MICRO_NSOFT_RESET;
1112 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
1114 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
1115 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
1118 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1119 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
1120 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1122 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1127 /* bus->mdio_lock should be locked when using this function */
1128 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
1133 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1135 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
1136 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
1138 /* Start Micro command */
1139 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
1143 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1145 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
1148 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1153 /* bus->mdio_lock should be locked when using this function */
1154 static int vsc8584_patch_fw(struct phy_device *phydev,
1155 const struct firmware *fw)
1159 ret = vsc8584_micro_assert_reset(phydev);
1161 dev_err(&phydev->mdio.dev,
1162 "%s: failed to assert reset of micro\n", __func__);
1166 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1167 MSCC_PHY_PAGE_EXTENDED_GPIO);
1169 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
1170 * Disable the 8051 Micro clock
1172 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
1173 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
1174 MICRO_CLK_DIVIDE(2));
1175 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
1177 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
1179 for (i = 0; i < fw->size; i++)
1180 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
1181 INT_MEM_WRITE_EN | fw->data[i]);
1183 /* Clear internal memory access */
1184 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
1186 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1191 /* bus->mdio_lock should be locked when using this function */
1192 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1197 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1198 MSCC_PHY_PAGE_EXTENDED_GPIO);
1200 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1201 if (reg != 0x3eb7) {
1206 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1207 if (reg != 0x4012) {
1212 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1213 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1218 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1219 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
1220 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1227 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1232 /* bus->mdio_lock should be locked when using this function */
1233 static int vsc8574_config_pre_init(struct phy_device *phydev)
1235 static const struct reg_val pre_init1[] = {
1236 {0x0fae, 0x000401bd},
1237 {0x0fac, 0x000f000f},
1238 {0x17a0, 0x00a0f147},
1239 {0x0fe4, 0x00052f54},
1240 {0x1792, 0x0027303d},
1241 {0x07fe, 0x00000704},
1242 {0x0fe0, 0x00060150},
1243 {0x0f82, 0x0012b00a},
1244 {0x0f80, 0x00000d74},
1245 {0x02e0, 0x00000012},
1246 {0x03a2, 0x00050208},
1247 {0x03b2, 0x00009186},
1248 {0x0fb0, 0x000e3700},
1249 {0x1688, 0x00049f81},
1250 {0x0fd2, 0x0000ffff},
1251 {0x168a, 0x00039fa2},
1252 {0x1690, 0x0020640b},
1253 {0x0258, 0x00002220},
1254 {0x025a, 0x00002a20},
1255 {0x025c, 0x00003060},
1256 {0x025e, 0x00003fa0},
1257 {0x03a6, 0x0000e0f0},
1258 {0x0f92, 0x00001489},
1259 {0x16a2, 0x00007000},
1260 {0x16a6, 0x00071448},
1261 {0x16a0, 0x00eeffdd},
1262 {0x0fe8, 0x0091b06c},
1263 {0x0fea, 0x00041600},
1264 {0x16b0, 0x00eeff00},
1265 {0x16b2, 0x00007000},
1266 {0x16b4, 0x00000814},
1267 {0x0f90, 0x00688980},
1268 {0x03a4, 0x0000d8f0},
1269 {0x0fc0, 0x00000400},
1270 {0x07fa, 0x0050100f},
1271 {0x0796, 0x00000003},
1272 {0x07f8, 0x00c3ff98},
1273 {0x0fa4, 0x0018292a},
1274 {0x168c, 0x00d2c46f},
1275 {0x17a2, 0x00000620},
1276 {0x16a4, 0x0013132f},
1277 {0x16a8, 0x00000000},
1278 {0x0ffc, 0x00c0a028},
1279 {0x0fec, 0x00901c09},
1280 {0x0fee, 0x0004a6a1},
1281 {0x0ffe, 0x00b01807},
1283 static const struct reg_val pre_init2[] = {
1284 {0x0486, 0x0008a518},
1285 {0x0488, 0x006dc696},
1286 {0x048a, 0x00000912},
1287 {0x048e, 0x00000db6},
1288 {0x049c, 0x00596596},
1289 {0x049e, 0x00000514},
1290 {0x04a2, 0x00410280},
1291 {0x04a4, 0x00000000},
1292 {0x04a6, 0x00000000},
1293 {0x04a8, 0x00000000},
1294 {0x04aa, 0x00000000},
1295 {0x04ae, 0x007df7dd},
1296 {0x04b0, 0x006d95d4},
1297 {0x04b2, 0x00492410},
1299 struct device *dev = &phydev->mdio.dev;
1300 const struct firmware *fw;
1306 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1308 /* all writes below are broadcasted to all PHYs in the same package */
1309 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1310 reg |= SMI_BROADCAST_WR_EN;
1311 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1313 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1315 /* The below register writes are tweaking analog and electrical
1316 * configuration that were determined through characterization by PHY
1317 * engineers. These don't mean anything more than "these are the best
1320 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1322 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1324 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1325 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1326 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1327 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1329 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1331 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1333 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1335 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1336 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1338 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1340 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1342 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1344 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1345 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1347 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1349 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1351 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1353 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1355 /* end of write broadcasting */
1356 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1357 reg &= ~SMI_BROADCAST_WR_EN;
1358 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1360 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1362 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1363 MSCC_VSC8574_REVB_INT8051_FW, ret);
1367 /* Add one byte to size for the one added by the patch_fw function */
1368 ret = vsc8584_get_fw_crc(phydev,
1369 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1370 fw->size + 1, &crc);
1374 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1375 serdes_init = vsc8574_is_serdes_init(phydev);
1378 ret = vsc8584_micro_assert_reset(phydev);
1381 "%s: failed to assert reset of micro\n",
1387 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1389 serdes_init = false;
1391 if (vsc8584_patch_fw(phydev, fw))
1393 "failed to patch FW, expect non-optimal device\n");
1397 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1398 MSCC_PHY_PAGE_EXTENDED_GPIO);
1400 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1401 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1402 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1403 EN_PATCH_RAM_TRAP_ADDR(1));
1405 vsc8584_micro_deassert_reset(phydev, false);
1407 /* Add one byte to size for the one added by the patch_fw
1410 ret = vsc8584_get_fw_crc(phydev,
1411 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1412 fw->size + 1, &crc);
1416 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1418 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1421 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1422 MSCC_PHY_PAGE_EXTENDED_GPIO);
1424 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1428 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1430 release_firmware(fw);
1435 /* bus->mdio_lock should be locked when using this function */
1436 static int vsc8584_config_pre_init(struct phy_device *phydev)
1438 static const struct reg_val pre_init1[] = {
1439 {0x07fa, 0x0050100f},
1440 {0x1688, 0x00049f81},
1441 {0x0f90, 0x00688980},
1442 {0x03a4, 0x0000d8f0},
1443 {0x0fc0, 0x00000400},
1444 {0x0f82, 0x0012b002},
1445 {0x1686, 0x00000004},
1446 {0x168c, 0x00d2c46f},
1447 {0x17a2, 0x00000620},
1448 {0x16a0, 0x00eeffdd},
1449 {0x16a6, 0x00071448},
1450 {0x16a4, 0x0013132f},
1451 {0x16a8, 0x00000000},
1452 {0x0ffc, 0x00c0a028},
1453 {0x0fe8, 0x0091b06c},
1454 {0x0fea, 0x00041600},
1455 {0x0f80, 0x00fffaff},
1456 {0x0fec, 0x00901809},
1457 {0x0ffe, 0x00b01007},
1458 {0x16b0, 0x00eeff00},
1459 {0x16b2, 0x00007000},
1460 {0x16b4, 0x00000814},
1462 static const struct reg_val pre_init2[] = {
1463 {0x0486, 0x0008a518},
1464 {0x0488, 0x006dc696},
1465 {0x048a, 0x00000912},
1467 const struct firmware *fw;
1468 struct device *dev = &phydev->mdio.dev;
1473 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1475 /* all writes below are broadcasted to all PHYs in the same package */
1476 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1477 reg |= SMI_BROADCAST_WR_EN;
1478 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1480 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1482 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1483 reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1484 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1486 /* The below register writes are tweaking analog and electrical
1487 * configuration that were determined through characterization by PHY
1488 * engineers. These don't mean anything more than "these are the best
1491 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1493 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1495 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1497 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1499 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1501 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1503 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1505 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1507 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1510 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1512 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1514 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1515 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1517 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1519 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1521 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1523 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1524 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1526 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1528 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1530 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1532 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1534 /* end of write broadcasting */
1535 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1536 reg &= ~SMI_BROADCAST_WR_EN;
1537 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1539 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1541 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1542 MSCC_VSC8584_REVB_INT8051_FW, ret);
1546 /* Add one byte to size for the one added by the patch_fw function */
1547 ret = vsc8584_get_fw_crc(phydev,
1548 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1549 fw->size + 1, &crc);
1553 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1554 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1555 if (vsc8584_patch_fw(phydev, fw))
1557 "failed to patch FW, expect non-optimal device\n");
1560 vsc8584_micro_deassert_reset(phydev, false);
1562 /* Add one byte to size for the one added by the patch_fw function */
1563 ret = vsc8584_get_fw_crc(phydev,
1564 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1565 fw->size + 1, &crc);
1569 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1571 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1573 ret = vsc8584_micro_assert_reset(phydev);
1577 vsc8584_micro_deassert_reset(phydev, true);
1580 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1582 release_firmware(fw);
1587 /* Check if one PHY has already done the init of the parts common to all PHYs
1588 * in the Quad PHY package.
1590 static bool vsc8584_is_pkg_init(struct phy_device *phydev, bool reversed)
1592 struct mdio_device **map = phydev->mdio.bus->mdio_map;
1593 struct vsc8531_private *vsc8531;
1594 struct phy_device *phy;
1597 /* VSC8584 is a Quad PHY */
1598 for (i = 0; i < 4; i++) {
1599 vsc8531 = phydev->priv;
1602 addr = vsc8531->base_addr - i;
1604 addr = vsc8531->base_addr + i;
1609 phy = container_of(map[addr], struct phy_device, mdio);
1611 if ((phy->phy_id & phydev->drv->phy_id_mask) !=
1612 (phydev->drv->phy_id & phydev->drv->phy_id_mask))
1615 vsc8531 = phy->priv;
1617 if (vsc8531 && vsc8531->pkg_init)
1624 static int vsc8584_config_init(struct phy_device *phydev)
1626 struct vsc8531_private *vsc8531 = phydev->priv;
1630 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1632 mutex_lock(&phydev->mdio.bus->mdio_lock);
1634 __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
1635 MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1636 addr = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
1637 MSCC_PHY_EXT_PHY_CNTL_4);
1638 addr >>= PHY_CNTL_4_ADDR_POS;
1640 val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
1641 MSCC_PHY_ACTIPHY_CNTL);
1642 if (val & PHY_ADDR_REVERSED)
1643 vsc8531->base_addr = phydev->mdio.addr + addr;
1645 vsc8531->base_addr = phydev->mdio.addr - addr;
1647 /* Some parts of the init sequence are identical for every PHY in the
1648 * package. Some parts are modifying the GPIO register bank which is a
1649 * set of registers that are affecting all PHYs, a few resetting the
1650 * microprocessor common to all PHYs. The CRC check responsible of the
1651 * checking the firmware within the 8051 microprocessor can only be
1652 * accessed via the PHY whose internal address in the package is 0.
1653 * All PHYs' interrupts mask register has to be zeroed before enabling
1654 * any PHY's interrupt in this register.
1655 * For all these reasons, we need to do the init sequence once and only
1656 * once whatever is the first PHY in the package that is initialized and
1657 * do the correct init sequence for all PHYs that are package-critical
1658 * in this pre-init function.
1660 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) {
1661 /* The following switch statement assumes that the lowest
1662 * nibble of the phy_id_mask is always 0. This works because
1663 * the lowest nibble of the PHY_ID's below are also 0.
1665 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1667 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1668 case PHY_ID_VSC8504:
1669 case PHY_ID_VSC8552:
1670 case PHY_ID_VSC8572:
1671 case PHY_ID_VSC8574:
1672 ret = vsc8574_config_pre_init(phydev);
1674 case PHY_ID_VSC856X:
1675 case PHY_ID_VSC8575:
1676 case PHY_ID_VSC8582:
1677 case PHY_ID_VSC8584:
1678 ret = vsc8584_config_pre_init(phydev);
1689 vsc8531->pkg_init = true;
1691 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1692 MSCC_PHY_PAGE_EXTENDED_GPIO);
1694 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1695 val &= ~MAC_CFG_MASK;
1696 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1697 val |= MAC_CFG_QSGMII;
1699 val |= MAC_CFG_SGMII;
1701 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1705 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1706 PROC_CMD_READ_MOD_WRITE_PORT;
1707 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1708 val |= PROC_CMD_QSGMII_MAC;
1710 val |= PROC_CMD_SGMII_MAC;
1712 ret = vsc8584_cmd(phydev, val);
1716 usleep_range(10000, 20000);
1718 /* Disable SerDes for 100Base-FX */
1719 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1720 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
1721 PROC_CMD_READ_MOD_WRITE_PORT |
1722 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1726 /* Disable SerDes for 1000Base-X */
1727 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1728 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
1729 PROC_CMD_READ_MOD_WRITE_PORT |
1730 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1734 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1736 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1738 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1739 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1740 val |= MEDIA_OP_MODE_COPPER | (VSC8584_MAC_IF_SELECTION_SGMII <<
1741 VSC8584_MAC_IF_SELECTION_POS);
1742 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1744 ret = genphy_soft_reset(phydev);
1748 for (i = 0; i < vsc8531->nleds; i++) {
1749 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1757 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1761 static int vsc85xx_config_init(struct phy_device *phydev)
1764 struct vsc8531_private *vsc8531 = phydev->priv;
1766 rc = vsc85xx_default_config(phydev);
1770 rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1774 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1778 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1779 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1780 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1781 rc = vsc8531_pre_init_seq_set(phydev);
1786 rc = vsc85xx_eee_init_seq_set(phydev);
1790 for (i = 0; i < vsc8531->nleds; i++) {
1791 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1799 static int vsc8584_did_interrupt(struct phy_device *phydev)
1803 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1804 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1806 return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1809 static int vsc8514_config_pre_init(struct phy_device *phydev)
1811 /* These are the settings to override the silicon default
1812 * values to handle hardware performance of PHY. They
1813 * are set at Power-On state and remain until PHY Reset.
1815 static const struct reg_val pre_init1[] = {
1816 {0x0f90, 0x00688980},
1817 {0x0786, 0x00000003},
1818 {0x07fa, 0x0050100f},
1819 {0x0f82, 0x0012b002},
1820 {0x1686, 0x00000004},
1821 {0x168c, 0x00d2c46f},
1822 {0x17a2, 0x00000620},
1823 {0x16a0, 0x00eeffdd},
1824 {0x16a6, 0x00071448},
1825 {0x16a4, 0x0013132f},
1826 {0x16a8, 0x00000000},
1827 {0x0ffc, 0x00c0a028},
1828 {0x0fe8, 0x0091b06c},
1829 {0x0fea, 0x00041600},
1830 {0x0f80, 0x00fffaff},
1831 {0x0fec, 0x00901809},
1832 {0x0ffe, 0x00b01007},
1833 {0x16b0, 0x00eeff00},
1834 {0x16b2, 0x00007000},
1835 {0x16b4, 0x00000814},
1840 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1842 /* all writes below are broadcasted to all PHYs in the same package */
1843 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1844 reg |= SMI_BROADCAST_WR_EN;
1845 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1847 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1849 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1851 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1853 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1855 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1856 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1858 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1860 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1862 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1864 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1866 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1867 reg &= ~SMI_BROADCAST_WR_EN;
1868 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1873 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev,
1874 u32 target, u32 reg)
1876 unsigned long deadline;
1877 u32 val, val_l, val_h;
1879 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1881 /* CSR registers are grouped under different Target IDs.
1882 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1883 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1884 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1885 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1888 /* Setup the Target ID */
1889 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1890 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1892 /* Trigger CSR Action - Read into the CSR's */
1893 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1894 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
1895 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1896 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1898 /* Wait for register access*/
1899 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1901 usleep_range(500, 1000);
1902 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1903 } while (time_before(jiffies, deadline) &&
1904 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1906 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1909 /* Read the Least Significant Word (LSW) (17) */
1910 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
1912 /* Read the Most Significant Word (MSW) (18) */
1913 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
1915 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1916 MSCC_PHY_PAGE_STANDARD);
1918 return (val_h << 16) | val_l;
1921 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev,
1922 u32 target, u32 reg, u32 val)
1924 unsigned long deadline;
1926 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1928 /* CSR registers are grouped under different Target IDs.
1929 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1930 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1931 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1932 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1935 /* Setup the Target ID */
1936 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1937 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1939 /* Write the Least Significant Word (LSW) (17) */
1940 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
1942 /* Write the Most Significant Word (MSW) (18) */
1943 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
1945 /* Trigger CSR Action - Write into the CSR's */
1946 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1947 MSCC_PHY_CSR_CNTL_19_CMD |
1948 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1949 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1951 /* Wait for register access */
1952 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1954 usleep_range(500, 1000);
1955 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1956 } while (time_before(jiffies, deadline) &&
1957 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1959 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1962 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1963 MSCC_PHY_PAGE_STANDARD);
1968 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1971 unsigned long deadline;
1975 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg,
1980 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1982 usleep_range(500, 1000);
1983 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg);
1985 if (val == 0xffffffff)
1988 } while (time_before(jiffies, deadline) && (val & op));
1996 /* Trigger a read to the spcified MCB */
1997 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1999 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
2002 /* Trigger a write to the spcified MCB */
2003 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
2005 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
2008 static int vsc8514_config_init(struct phy_device *phydev)
2010 struct vsc8531_private *vsc8531 = phydev->priv;
2011 unsigned long deadline;
2016 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
2018 mutex_lock(&phydev->mdio.bus->mdio_lock);
2020 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
2022 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
2023 addr >>= PHY_CNTL_4_ADDR_POS;
2025 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
2027 if (val & PHY_ADDR_REVERSED)
2028 vsc8531->base_addr = phydev->mdio.addr + addr;
2030 vsc8531->base_addr = phydev->mdio.addr - addr;
2032 /* Some parts of the init sequence are identical for every PHY in the
2033 * package. Some parts are modifying the GPIO register bank which is a
2034 * set of registers that are affecting all PHYs, a few resetting the
2035 * microprocessor common to all PHYs.
2036 * All PHYs' interrupts mask register has to be zeroed before enabling
2037 * any PHY's interrupt in this register.
2038 * For all these reasons, we need to do the init sequence once and only
2039 * once whatever is the first PHY in the package that is initialized and
2040 * do the correct init sequence for all PHYs that are package-critical
2041 * in this pre-init function.
2043 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0))
2044 vsc8514_config_pre_init(phydev);
2046 vsc8531->pkg_init = true;
2048 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
2049 MSCC_PHY_PAGE_EXTENDED_GPIO);
2051 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
2053 val &= ~MAC_CFG_MASK;
2054 val |= MAC_CFG_QSGMII;
2055 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
2060 ret = vsc8584_cmd(phydev,
2061 PROC_CMD_MCB_ACCESS_MAC_CONF |
2062 PROC_CMD_RST_CONF_PORT |
2063 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
2068 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
2070 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
2072 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
2073 PHY_S6G_PLL5G_CFG0, 0x7036f145);
2077 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
2079 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
2081 (3 << PHY_S6G_PLL_ENA_OFFS_POS) |
2082 (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS)
2083 | (0 << PHY_S6G_PLL_FSM_ENA_POS));
2088 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
2090 (0 << PHY_S6G_SYS_RST_POS) |
2091 (0 << PHY_S6G_ENA_LANE_POS) |
2092 (0 << PHY_S6G_ENA_LOOP_POS) |
2093 (0 << PHY_S6G_QRATE_POS) |
2094 (3 << PHY_S6G_IF_MODE_POS));
2099 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
2100 PHY_S6G_MISC_CFG, 1);
2105 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
2106 PHY_S6G_GPC_CFG, 768);
2110 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
2112 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
2114 usleep_range(500, 1000);
2115 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
2116 0); /* read 6G MCB into CSRs */
2117 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
2118 PHY_S6G_PLL_STATUS);
2119 if (reg == 0xffffffff) {
2120 mutex_unlock(&phydev->mdio.bus->mdio_lock);
2124 } while (time_before(jiffies, deadline) && (reg & BIT(12)));
2126 if (reg & BIT(12)) {
2127 mutex_unlock(&phydev->mdio.bus->mdio_lock);
2132 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
2133 PHY_S6G_MISC_CFG, 0);
2137 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
2139 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
2141 usleep_range(500, 1000);
2142 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
2143 0); /* read 6G MCB into CSRs */
2144 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
2145 PHY_S6G_IB_STATUS0);
2146 if (reg == 0xffffffff) {
2147 mutex_unlock(&phydev->mdio.bus->mdio_lock);
2151 } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
2153 if (!(reg & BIT(8))) {
2154 mutex_unlock(&phydev->mdio.bus->mdio_lock);
2158 mutex_unlock(&phydev->mdio.bus->mdio_lock);
2160 ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
2165 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2166 MEDIA_OP_MODE_COPPER);
2171 ret = genphy_soft_reset(phydev);
2176 for (i = 0; i < vsc8531->nleds; i++) {
2177 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2185 mutex_unlock(&phydev->mdio.bus->mdio_lock);
2189 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2193 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2194 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2196 return (rc < 0) ? rc : 0;
2199 static int vsc85xx_config_intr(struct phy_device *phydev)
2203 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2204 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2205 MII_VSC85XX_INT_MASK_MASK);
2207 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2210 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2216 static int vsc85xx_config_aneg(struct phy_device *phydev)
2220 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2224 return genphy_config_aneg(phydev);
2227 static int vsc85xx_read_status(struct phy_device *phydev)
2231 rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2235 return genphy_read_status(phydev);
2238 static int vsc8514_probe(struct phy_device *phydev)
2240 struct vsc8531_private *vsc8531;
2241 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2242 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2243 VSC8531_DUPLEX_COLLISION};
2245 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2249 phydev->priv = vsc8531;
2252 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2253 vsc8531->hw_stats = vsc85xx_hw_stats;
2254 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2255 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2256 sizeof(u64), GFP_KERNEL);
2257 if (!vsc8531->stats)
2260 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2263 static int vsc8574_probe(struct phy_device *phydev)
2265 struct vsc8531_private *vsc8531;
2266 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2267 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2268 VSC8531_DUPLEX_COLLISION};
2270 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2274 phydev->priv = vsc8531;
2277 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2278 vsc8531->hw_stats = vsc8584_hw_stats;
2279 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2280 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2281 sizeof(u64), GFP_KERNEL);
2282 if (!vsc8531->stats)
2285 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2288 static int vsc8584_probe(struct phy_device *phydev)
2290 struct vsc8531_private *vsc8531;
2291 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2292 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2293 VSC8531_DUPLEX_COLLISION};
2295 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2296 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2300 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2304 phydev->priv = vsc8531;
2307 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2308 vsc8531->hw_stats = vsc8584_hw_stats;
2309 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2310 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2311 sizeof(u64), GFP_KERNEL);
2312 if (!vsc8531->stats)
2315 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2318 static int vsc85xx_probe(struct phy_device *phydev)
2320 struct vsc8531_private *vsc8531;
2322 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2323 VSC8531_LINK_100_ACTIVITY};
2325 rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2329 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2333 phydev->priv = vsc8531;
2335 vsc8531->rate_magic = rate_magic;
2337 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2338 vsc8531->hw_stats = vsc85xx_hw_stats;
2339 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2340 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2341 sizeof(u64), GFP_KERNEL);
2342 if (!vsc8531->stats)
2345 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2348 /* Microsemi VSC85xx PHYs */
2349 static struct phy_driver vsc85xx_driver[] = {
2351 .phy_id = PHY_ID_VSC8504,
2352 .name = "Microsemi GE VSC8504 SyncE",
2353 .phy_id_mask = 0xfffffff0,
2354 /* PHY_GBIT_FEATURES */
2355 .soft_reset = &genphy_soft_reset,
2356 .config_init = &vsc8584_config_init,
2357 .config_aneg = &vsc85xx_config_aneg,
2358 .aneg_done = &genphy_aneg_done,
2359 .read_status = &vsc85xx_read_status,
2360 .ack_interrupt = &vsc85xx_ack_interrupt,
2361 .config_intr = &vsc85xx_config_intr,
2362 .did_interrupt = &vsc8584_did_interrupt,
2363 .suspend = &genphy_suspend,
2364 .resume = &genphy_resume,
2365 .probe = &vsc8574_probe,
2366 .set_wol = &vsc85xx_wol_set,
2367 .get_wol = &vsc85xx_wol_get,
2368 .get_tunable = &vsc85xx_get_tunable,
2369 .set_tunable = &vsc85xx_set_tunable,
2370 .read_page = &vsc85xx_phy_read_page,
2371 .write_page = &vsc85xx_phy_write_page,
2372 .get_sset_count = &vsc85xx_get_sset_count,
2373 .get_strings = &vsc85xx_get_strings,
2374 .get_stats = &vsc85xx_get_stats,
2377 .phy_id = PHY_ID_VSC8514,
2378 .name = "Microsemi GE VSC8514 SyncE",
2379 .phy_id_mask = 0xfffffff0,
2380 .soft_reset = &genphy_soft_reset,
2381 .config_init = &vsc8514_config_init,
2382 .config_aneg = &vsc85xx_config_aneg,
2383 .read_status = &vsc85xx_read_status,
2384 .ack_interrupt = &vsc85xx_ack_interrupt,
2385 .config_intr = &vsc85xx_config_intr,
2386 .suspend = &genphy_suspend,
2387 .resume = &genphy_resume,
2388 .probe = &vsc8514_probe,
2389 .set_wol = &vsc85xx_wol_set,
2390 .get_wol = &vsc85xx_wol_get,
2391 .get_tunable = &vsc85xx_get_tunable,
2392 .set_tunable = &vsc85xx_set_tunable,
2393 .read_page = &vsc85xx_phy_read_page,
2394 .write_page = &vsc85xx_phy_write_page,
2395 .get_sset_count = &vsc85xx_get_sset_count,
2396 .get_strings = &vsc85xx_get_strings,
2397 .get_stats = &vsc85xx_get_stats,
2400 .phy_id = PHY_ID_VSC8530,
2401 .name = "Microsemi FE VSC8530",
2402 .phy_id_mask = 0xfffffff0,
2403 /* PHY_BASIC_FEATURES */
2404 .soft_reset = &genphy_soft_reset,
2405 .config_init = &vsc85xx_config_init,
2406 .config_aneg = &vsc85xx_config_aneg,
2407 .aneg_done = &genphy_aneg_done,
2408 .read_status = &vsc85xx_read_status,
2409 .ack_interrupt = &vsc85xx_ack_interrupt,
2410 .config_intr = &vsc85xx_config_intr,
2411 .suspend = &genphy_suspend,
2412 .resume = &genphy_resume,
2413 .probe = &vsc85xx_probe,
2414 .set_wol = &vsc85xx_wol_set,
2415 .get_wol = &vsc85xx_wol_get,
2416 .get_tunable = &vsc85xx_get_tunable,
2417 .set_tunable = &vsc85xx_set_tunable,
2418 .read_page = &vsc85xx_phy_read_page,
2419 .write_page = &vsc85xx_phy_write_page,
2420 .get_sset_count = &vsc85xx_get_sset_count,
2421 .get_strings = &vsc85xx_get_strings,
2422 .get_stats = &vsc85xx_get_stats,
2425 .phy_id = PHY_ID_VSC8531,
2426 .name = "Microsemi VSC8531",
2427 .phy_id_mask = 0xfffffff0,
2428 /* PHY_GBIT_FEATURES */
2429 .soft_reset = &genphy_soft_reset,
2430 .config_init = &vsc85xx_config_init,
2431 .config_aneg = &vsc85xx_config_aneg,
2432 .aneg_done = &genphy_aneg_done,
2433 .read_status = &vsc85xx_read_status,
2434 .ack_interrupt = &vsc85xx_ack_interrupt,
2435 .config_intr = &vsc85xx_config_intr,
2436 .suspend = &genphy_suspend,
2437 .resume = &genphy_resume,
2438 .probe = &vsc85xx_probe,
2439 .set_wol = &vsc85xx_wol_set,
2440 .get_wol = &vsc85xx_wol_get,
2441 .get_tunable = &vsc85xx_get_tunable,
2442 .set_tunable = &vsc85xx_set_tunable,
2443 .read_page = &vsc85xx_phy_read_page,
2444 .write_page = &vsc85xx_phy_write_page,
2445 .get_sset_count = &vsc85xx_get_sset_count,
2446 .get_strings = &vsc85xx_get_strings,
2447 .get_stats = &vsc85xx_get_stats,
2450 .phy_id = PHY_ID_VSC8540,
2451 .name = "Microsemi FE VSC8540 SyncE",
2452 .phy_id_mask = 0xfffffff0,
2453 /* PHY_BASIC_FEATURES */
2454 .soft_reset = &genphy_soft_reset,
2455 .config_init = &vsc85xx_config_init,
2456 .config_aneg = &vsc85xx_config_aneg,
2457 .aneg_done = &genphy_aneg_done,
2458 .read_status = &vsc85xx_read_status,
2459 .ack_interrupt = &vsc85xx_ack_interrupt,
2460 .config_intr = &vsc85xx_config_intr,
2461 .suspend = &genphy_suspend,
2462 .resume = &genphy_resume,
2463 .probe = &vsc85xx_probe,
2464 .set_wol = &vsc85xx_wol_set,
2465 .get_wol = &vsc85xx_wol_get,
2466 .get_tunable = &vsc85xx_get_tunable,
2467 .set_tunable = &vsc85xx_set_tunable,
2468 .read_page = &vsc85xx_phy_read_page,
2469 .write_page = &vsc85xx_phy_write_page,
2470 .get_sset_count = &vsc85xx_get_sset_count,
2471 .get_strings = &vsc85xx_get_strings,
2472 .get_stats = &vsc85xx_get_stats,
2475 .phy_id = PHY_ID_VSC8541,
2476 .name = "Microsemi VSC8541 SyncE",
2477 .phy_id_mask = 0xfffffff0,
2478 /* PHY_GBIT_FEATURES */
2479 .soft_reset = &genphy_soft_reset,
2480 .config_init = &vsc85xx_config_init,
2481 .config_aneg = &vsc85xx_config_aneg,
2482 .aneg_done = &genphy_aneg_done,
2483 .read_status = &vsc85xx_read_status,
2484 .ack_interrupt = &vsc85xx_ack_interrupt,
2485 .config_intr = &vsc85xx_config_intr,
2486 .suspend = &genphy_suspend,
2487 .resume = &genphy_resume,
2488 .probe = &vsc85xx_probe,
2489 .set_wol = &vsc85xx_wol_set,
2490 .get_wol = &vsc85xx_wol_get,
2491 .get_tunable = &vsc85xx_get_tunable,
2492 .set_tunable = &vsc85xx_set_tunable,
2493 .read_page = &vsc85xx_phy_read_page,
2494 .write_page = &vsc85xx_phy_write_page,
2495 .get_sset_count = &vsc85xx_get_sset_count,
2496 .get_strings = &vsc85xx_get_strings,
2497 .get_stats = &vsc85xx_get_stats,
2500 .phy_id = PHY_ID_VSC8552,
2501 .name = "Microsemi GE VSC8552 SyncE",
2502 .phy_id_mask = 0xfffffff0,
2503 /* PHY_GBIT_FEATURES */
2504 .soft_reset = &genphy_soft_reset,
2505 .config_init = &vsc8584_config_init,
2506 .config_aneg = &vsc85xx_config_aneg,
2507 .aneg_done = &genphy_aneg_done,
2508 .read_status = &vsc85xx_read_status,
2509 .ack_interrupt = &vsc85xx_ack_interrupt,
2510 .config_intr = &vsc85xx_config_intr,
2511 .did_interrupt = &vsc8584_did_interrupt,
2512 .suspend = &genphy_suspend,
2513 .resume = &genphy_resume,
2514 .probe = &vsc8574_probe,
2515 .set_wol = &vsc85xx_wol_set,
2516 .get_wol = &vsc85xx_wol_get,
2517 .get_tunable = &vsc85xx_get_tunable,
2518 .set_tunable = &vsc85xx_set_tunable,
2519 .read_page = &vsc85xx_phy_read_page,
2520 .write_page = &vsc85xx_phy_write_page,
2521 .get_sset_count = &vsc85xx_get_sset_count,
2522 .get_strings = &vsc85xx_get_strings,
2523 .get_stats = &vsc85xx_get_stats,
2526 .phy_id = PHY_ID_VSC856X,
2527 .name = "Microsemi GE VSC856X SyncE",
2528 .phy_id_mask = 0xfffffff0,
2529 /* PHY_GBIT_FEATURES */
2530 .soft_reset = &genphy_soft_reset,
2531 .config_init = &vsc8584_config_init,
2532 .config_aneg = &vsc85xx_config_aneg,
2533 .aneg_done = &genphy_aneg_done,
2534 .read_status = &vsc85xx_read_status,
2535 .ack_interrupt = &vsc85xx_ack_interrupt,
2536 .config_intr = &vsc85xx_config_intr,
2537 .did_interrupt = &vsc8584_did_interrupt,
2538 .suspend = &genphy_suspend,
2539 .resume = &genphy_resume,
2540 .probe = &vsc8584_probe,
2541 .get_tunable = &vsc85xx_get_tunable,
2542 .set_tunable = &vsc85xx_set_tunable,
2543 .read_page = &vsc85xx_phy_read_page,
2544 .write_page = &vsc85xx_phy_write_page,
2545 .get_sset_count = &vsc85xx_get_sset_count,
2546 .get_strings = &vsc85xx_get_strings,
2547 .get_stats = &vsc85xx_get_stats,
2550 .phy_id = PHY_ID_VSC8572,
2551 .name = "Microsemi GE VSC8572 SyncE",
2552 .phy_id_mask = 0xfffffff0,
2553 /* PHY_GBIT_FEATURES */
2554 .soft_reset = &genphy_soft_reset,
2555 .config_init = &vsc8584_config_init,
2556 .config_aneg = &vsc85xx_config_aneg,
2557 .aneg_done = &genphy_aneg_done,
2558 .read_status = &vsc85xx_read_status,
2559 .ack_interrupt = &vsc85xx_ack_interrupt,
2560 .config_intr = &vsc85xx_config_intr,
2561 .did_interrupt = &vsc8584_did_interrupt,
2562 .suspend = &genphy_suspend,
2563 .resume = &genphy_resume,
2564 .probe = &vsc8574_probe,
2565 .set_wol = &vsc85xx_wol_set,
2566 .get_wol = &vsc85xx_wol_get,
2567 .get_tunable = &vsc85xx_get_tunable,
2568 .set_tunable = &vsc85xx_set_tunable,
2569 .read_page = &vsc85xx_phy_read_page,
2570 .write_page = &vsc85xx_phy_write_page,
2571 .get_sset_count = &vsc85xx_get_sset_count,
2572 .get_strings = &vsc85xx_get_strings,
2573 .get_stats = &vsc85xx_get_stats,
2576 .phy_id = PHY_ID_VSC8574,
2577 .name = "Microsemi GE VSC8574 SyncE",
2578 .phy_id_mask = 0xfffffff0,
2579 /* PHY_GBIT_FEATURES */
2580 .soft_reset = &genphy_soft_reset,
2581 .config_init = &vsc8584_config_init,
2582 .config_aneg = &vsc85xx_config_aneg,
2583 .aneg_done = &genphy_aneg_done,
2584 .read_status = &vsc85xx_read_status,
2585 .ack_interrupt = &vsc85xx_ack_interrupt,
2586 .config_intr = &vsc85xx_config_intr,
2587 .did_interrupt = &vsc8584_did_interrupt,
2588 .suspend = &genphy_suspend,
2589 .resume = &genphy_resume,
2590 .probe = &vsc8574_probe,
2591 .set_wol = &vsc85xx_wol_set,
2592 .get_wol = &vsc85xx_wol_get,
2593 .get_tunable = &vsc85xx_get_tunable,
2594 .set_tunable = &vsc85xx_set_tunable,
2595 .read_page = &vsc85xx_phy_read_page,
2596 .write_page = &vsc85xx_phy_write_page,
2597 .get_sset_count = &vsc85xx_get_sset_count,
2598 .get_strings = &vsc85xx_get_strings,
2599 .get_stats = &vsc85xx_get_stats,
2602 .phy_id = PHY_ID_VSC8575,
2603 .name = "Microsemi GE VSC8575 SyncE",
2604 .phy_id_mask = 0xfffffff0,
2605 /* PHY_GBIT_FEATURES */
2606 .soft_reset = &genphy_soft_reset,
2607 .config_init = &vsc8584_config_init,
2608 .config_aneg = &vsc85xx_config_aneg,
2609 .aneg_done = &genphy_aneg_done,
2610 .read_status = &vsc85xx_read_status,
2611 .ack_interrupt = &vsc85xx_ack_interrupt,
2612 .config_intr = &vsc85xx_config_intr,
2613 .did_interrupt = &vsc8584_did_interrupt,
2614 .suspend = &genphy_suspend,
2615 .resume = &genphy_resume,
2616 .probe = &vsc8584_probe,
2617 .get_tunable = &vsc85xx_get_tunable,
2618 .set_tunable = &vsc85xx_set_tunable,
2619 .read_page = &vsc85xx_phy_read_page,
2620 .write_page = &vsc85xx_phy_write_page,
2621 .get_sset_count = &vsc85xx_get_sset_count,
2622 .get_strings = &vsc85xx_get_strings,
2623 .get_stats = &vsc85xx_get_stats,
2626 .phy_id = PHY_ID_VSC8582,
2627 .name = "Microsemi GE VSC8582 SyncE",
2628 .phy_id_mask = 0xfffffff0,
2629 /* PHY_GBIT_FEATURES */
2630 .soft_reset = &genphy_soft_reset,
2631 .config_init = &vsc8584_config_init,
2632 .config_aneg = &vsc85xx_config_aneg,
2633 .aneg_done = &genphy_aneg_done,
2634 .read_status = &vsc85xx_read_status,
2635 .ack_interrupt = &vsc85xx_ack_interrupt,
2636 .config_intr = &vsc85xx_config_intr,
2637 .did_interrupt = &vsc8584_did_interrupt,
2638 .suspend = &genphy_suspend,
2639 .resume = &genphy_resume,
2640 .probe = &vsc8584_probe,
2641 .get_tunable = &vsc85xx_get_tunable,
2642 .set_tunable = &vsc85xx_set_tunable,
2643 .read_page = &vsc85xx_phy_read_page,
2644 .write_page = &vsc85xx_phy_write_page,
2645 .get_sset_count = &vsc85xx_get_sset_count,
2646 .get_strings = &vsc85xx_get_strings,
2647 .get_stats = &vsc85xx_get_stats,
2650 .phy_id = PHY_ID_VSC8584,
2651 .name = "Microsemi GE VSC8584 SyncE",
2652 .phy_id_mask = 0xfffffff0,
2653 /* PHY_GBIT_FEATURES */
2654 .soft_reset = &genphy_soft_reset,
2655 .config_init = &vsc8584_config_init,
2656 .config_aneg = &vsc85xx_config_aneg,
2657 .aneg_done = &genphy_aneg_done,
2658 .read_status = &vsc85xx_read_status,
2659 .ack_interrupt = &vsc85xx_ack_interrupt,
2660 .config_intr = &vsc85xx_config_intr,
2661 .did_interrupt = &vsc8584_did_interrupt,
2662 .suspend = &genphy_suspend,
2663 .resume = &genphy_resume,
2664 .probe = &vsc8584_probe,
2665 .get_tunable = &vsc85xx_get_tunable,
2666 .set_tunable = &vsc85xx_set_tunable,
2667 .read_page = &vsc85xx_phy_read_page,
2668 .write_page = &vsc85xx_phy_write_page,
2669 .get_sset_count = &vsc85xx_get_sset_count,
2670 .get_strings = &vsc85xx_get_strings,
2671 .get_stats = &vsc85xx_get_stats,
2676 module_phy_driver(vsc85xx_driver);
2678 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2679 { PHY_ID_VSC8504, 0xfffffff0, },
2680 { PHY_ID_VSC8514, 0xfffffff0, },
2681 { PHY_ID_VSC8530, 0xfffffff0, },
2682 { PHY_ID_VSC8531, 0xfffffff0, },
2683 { PHY_ID_VSC8540, 0xfffffff0, },
2684 { PHY_ID_VSC8541, 0xfffffff0, },
2685 { PHY_ID_VSC8552, 0xfffffff0, },
2686 { PHY_ID_VSC856X, 0xfffffff0, },
2687 { PHY_ID_VSC8572, 0xfffffff0, },
2688 { PHY_ID_VSC8574, 0xfffffff0, },
2689 { PHY_ID_VSC8575, 0xfffffff0, },
2690 { PHY_ID_VSC8582, 0xfffffff0, },
2691 { PHY_ID_VSC8584, 0xfffffff0, },
2695 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2697 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2698 MODULE_AUTHOR("Nagaraju Lakkaraju");
2699 MODULE_LICENSE("Dual MIT/GPL");