drivers/net/phy/mscc/mscc_main.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs
   4  *
   5  * Author: Nagaraju Lakkaraju
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2016 Microsemi Corporation
   8  */
   9
  10 #include <linux/firmware.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/mdio.h>
  15 #include <linux/mii.h>
  16 #include <linux/phy.h>
  17 #include <linux/of.h>
  18 #include <linux/netdevice.h>
  19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  20
  21 #include "mscc.h"
  22
  23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
  24         {
  25                 .string = "phy_receive_errors",
  26                 .reg    = MSCC_PHY_ERR_RX_CNT,
  27                 .page   = MSCC_PHY_PAGE_STANDARD,
  28                 .mask   = ERR_CNT_MASK,
  29         }, {
  30                 .string = "phy_false_carrier",
  31                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
  32                 .page   = MSCC_PHY_PAGE_STANDARD,
  33                 .mask   = ERR_CNT_MASK,
  34         }, {
  35                 .string = "phy_cu_media_link_disconnect",
  36                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
  37                 .page   = MSCC_PHY_PAGE_STANDARD,
  38                 .mask   = ERR_CNT_MASK,
  39         }, {
  40                 .string = "phy_cu_media_crc_good_count",
  41                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
  42                 .page   = MSCC_PHY_PAGE_EXTENDED,
  43                 .mask   = VALID_CRC_CNT_CRC_MASK,
  44         }, {
  45                 .string = "phy_cu_media_crc_error_count",
  46                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
  47                 .page   = MSCC_PHY_PAGE_EXTENDED,
  48                 .mask   = ERR_CNT_MASK,
  49         },
  50 };
  51
  52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
  53         {
  54                 .string = "phy_receive_errors",
  55                 .reg    = MSCC_PHY_ERR_RX_CNT,
  56                 .page   = MSCC_PHY_PAGE_STANDARD,
  57                 .mask   = ERR_CNT_MASK,
  58         }, {
  59                 .string = "phy_false_carrier",
  60                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
  61                 .page   = MSCC_PHY_PAGE_STANDARD,
  62                 .mask   = ERR_CNT_MASK,
  63         }, {
  64                 .string = "phy_cu_media_link_disconnect",
  65                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
  66                 .page   = MSCC_PHY_PAGE_STANDARD,
  67                 .mask   = ERR_CNT_MASK,
  68         }, {
  69                 .string = "phy_cu_media_crc_good_count",
  70                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
  71                 .page   = MSCC_PHY_PAGE_EXTENDED,
  72                 .mask   = VALID_CRC_CNT_CRC_MASK,
  73         }, {
  74                 .string = "phy_cu_media_crc_error_count",
  75                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
  76                 .page   = MSCC_PHY_PAGE_EXTENDED,
  77                 .mask   = ERR_CNT_MASK,
  78         }, {
  79                 .string = "phy_serdes_tx_good_pkt_count",
  80                 .reg    = MSCC_PHY_SERDES_TX_VALID_CNT,
  81                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  82                 .mask   = VALID_CRC_CNT_CRC_MASK,
  83         }, {
  84                 .string = "phy_serdes_tx_bad_crc_count",
  85                 .reg    = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
  86                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  87                 .mask   = ERR_CNT_MASK,
  88         }, {
  89                 .string = "phy_serdes_rx_good_pkt_count",
  90                 .reg    = MSCC_PHY_SERDES_RX_VALID_CNT,
  91                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  92                 .mask   = VALID_CRC_CNT_CRC_MASK,
  93         }, {
  94                 .string = "phy_serdes_rx_bad_crc_count",
  95                 .reg    = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
  96                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  97                 .mask   = ERR_CNT_MASK,
  98         },
  99 };
 100
 101 #if IS_ENABLED(CONFIG_OF_MDIO)
 102 static const struct vsc8531_edge_rate_table edge_table[] = {
 103         {MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
 104         {MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
 105         {MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
 106         {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
 107 };
 108 #endif
 109
 110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
 111 {
 112         return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
 113 }
 114
 115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
 116 {
 117         return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
 118 }
 119
 120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
 121 {
 122         struct vsc8531_private *priv = phydev->priv;
 123
 124         if (!priv)
 125                 return 0;
 126
 127         return priv->nstats;
 128 }
 129
 130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
 131 {
 132         struct vsc8531_private *priv = phydev->priv;
 133         int i;
 134
 135         if (!priv)
 136                 return;
 137
 138         for (i = 0; i < priv->nstats; i++)
 139                 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
 140                         ETH_GSTRING_LEN);
 141 }
 142
 143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
 144 {
 145         struct vsc8531_private *priv = phydev->priv;
 146         int val;
 147
 148         val = phy_read_paged(phydev, priv->hw_stats[i].page,
 149                              priv->hw_stats[i].reg);
 150         if (val < 0)
 151                 return U64_MAX;
 152
 153         val = val & priv->hw_stats[i].mask;
 154         priv->stats[i] += val;
 155
 156         return priv->stats[i];
 157 }
 158
 159 static void vsc85xx_get_stats(struct phy_device *phydev,
 160                               struct ethtool_stats *stats, u64 *data)
 161 {
 162         struct vsc8531_private *priv = phydev->priv;
 163         int i;
 164
 165         if (!priv)
 166                 return;
 167
 168         for (i = 0; i < priv->nstats; i++)
 169                 data[i] = vsc85xx_get_stat(phydev, i);
 170 }
 171
 172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
 173                                 u8 led_num,
 174                                 u8 mode)
 175 {
 176         int rc;
 177         u16 reg_val;
 178
 179         mutex_lock(&phydev->lock);
 180         reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
 181         reg_val &= ~LED_MODE_SEL_MASK(led_num);
 182         reg_val |= LED_MODE_SEL(led_num, (u16)mode);
 183         rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
 184         mutex_unlock(&phydev->lock);
 185
 186         return rc;
 187 }
 188
 189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 190 {
 191         u16 reg_val;
 192
 193         reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
 194         if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
 195                 *mdix = ETH_TP_MDI_X;
 196         else
 197                 *mdix = ETH_TP_MDI;
 198
 199         return 0;
 200 }
 201
 202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
 203 {
 204         int rc;
 205         u16 reg_val;
 206
 207         reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
 208         if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
 209                 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
 210                             DISABLE_POLARITY_CORR_MASK  |
 211                             DISABLE_HP_AUTO_MDIX_MASK);
 212         } else {
 213                 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
 214                              DISABLE_POLARITY_CORR_MASK  |
 215                              DISABLE_HP_AUTO_MDIX_MASK);
 216         }
 217         rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
 218         if (rc)
 219                 return rc;
 220
 221         reg_val = 0;
 222
 223         if (mdix == ETH_TP_MDI)
 224                 reg_val = FORCE_MDI_CROSSOVER_MDI;
 225         else if (mdix == ETH_TP_MDI_X)
 226                 reg_val = FORCE_MDI_CROSSOVER_MDIX;
 227
 228         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 229                               MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
 230                               reg_val);
 231         if (rc < 0)
 232                 return rc;
 233
 234         return genphy_restart_aneg(phydev);
 235 }
 236
 237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
 238 {
 239         int reg_val;
 240
 241         reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 242                                  MSCC_PHY_ACTIPHY_CNTL);
 243         if (reg_val < 0)
 244                 return reg_val;
 245
 246         reg_val &= DOWNSHIFT_CNTL_MASK;
 247         if (!(reg_val & DOWNSHIFT_EN))
 248                 *count = DOWNSHIFT_DEV_DISABLE;
 249         else
 250                 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
 251
 252         return 0;
 253 }
 254
 255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
 256 {
 257         if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
 258                 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
 259                 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 260         } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
 261                 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
 262                 return -ERANGE;
 263         } else if (count) {
 264                 /* Downshift count is either 2,3,4 or 5 */
 265                 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 266         }
 267
 268         return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 269                                 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
 270                                 count);
 271 }
 272
 273 static int vsc85xx_wol_set(struct phy_device *phydev,
 274                            struct ethtool_wolinfo *wol)
 275 {
 276         int rc;
 277         u16 reg_val;
 278         u8  i;
 279         u16 pwd[3] = {0, 0, 0};
 280         struct ethtool_wolinfo *wol_conf = wol;
 281         u8 *mac_addr = phydev->attached_dev->dev_addr;
 282
 283         mutex_lock(&phydev->lock);
 284         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 285         if (rc < 0) {
 286                 rc = phy_restore_page(phydev, rc, rc);
 287                 goto out_unlock;
 288         }
 289
 290         if (wol->wolopts & WAKE_MAGIC) {
 291                 /* Store the device address for the magic packet */
 292                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 293                         pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
 294                                  mac_addr[5 - i * 2];
 295                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
 296                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
 297                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
 298         } else {
 299                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
 300                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
 301                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
 302         }
 303
 304         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 305                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 306                         pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
 307                                  wol_conf->sopass[5 - i * 2];
 308                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
 309                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
 310                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
 311         } else {
 312                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
 313                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
 314                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
 315         }
 316
 317         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 318         if (wol_conf->wolopts & WAKE_MAGICSECURE)
 319                 reg_val |= SECURE_ON_ENABLE;
 320         else
 321                 reg_val &= ~SECURE_ON_ENABLE;
 322         __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
 323
 324         rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 325         if (rc < 0)
 326                 goto out_unlock;
 327
 328         if (wol->wolopts & WAKE_MAGIC) {
 329                 /* Enable the WOL interrupt */
 330                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 331                 reg_val |= MII_VSC85XX_INT_MASK_WOL;
 332                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 333                 if (rc)
 334                         goto out_unlock;
 335         } else {
 336                 /* Disable the WOL interrupt */
 337                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 338                 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
 339                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 340                 if (rc)
 341                         goto out_unlock;
 342         }
 343         /* Clear WOL iterrupt status */
 344         reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 345
 346 out_unlock:
 347         mutex_unlock(&phydev->lock);
 348
 349         return rc;
 350 }
 351
 352 static void vsc85xx_wol_get(struct phy_device *phydev,
 353                             struct ethtool_wolinfo *wol)
 354 {
 355         int rc;
 356         u16 reg_val;
 357         u8  i;
 358         u16 pwd[3] = {0, 0, 0};
 359         struct ethtool_wolinfo *wol_conf = wol;
 360
 361         mutex_lock(&phydev->lock);
 362         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 363         if (rc < 0)
 364                 goto out_unlock;
 365
 366         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 367         if (reg_val & SECURE_ON_ENABLE)
 368                 wol_conf->wolopts |= WAKE_MAGICSECURE;
 369         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 370                 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
 371                 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
 372                 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
 373                 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
 374                         wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
 375                         wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
 376                                                             >> 8;
 377                 }
 378         }
 379
 380 out_unlock:
 381         phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 382         mutex_unlock(&phydev->lock);
 383 }
 384
 385 #if IS_ENABLED(CONFIG_OF_MDIO)
 386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 387 {
 388         u32 vdd, sd;
 389         int i, j;
 390         struct device *dev = &phydev->mdio.dev;
 391         struct device_node *of_node = dev->of_node;
 392         u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
 393
 394         if (!of_node)
 395                 return -ENODEV;
 396
 397         if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
 398                 vdd = MSCC_VDDMAC_3300;
 399
 400         if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
 401                 sd = 0;
 402
 403         for (i = 0; i < ARRAY_SIZE(edge_table); i++)
 404                 if (edge_table[i].vddmac == vdd)
 405                         for (j = 0; j < sd_array_size; j++)
 406                                 if (edge_table[i].slowdown[j] == sd)
 407                                         return (sd_array_size - j - 1);
 408
 409         return -EINVAL;
 410 }
 411
 412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 413                                    char *led,
 414                                    u32 default_mode)
 415 {
 416         struct vsc8531_private *priv = phydev->priv;
 417         struct device *dev = &phydev->mdio.dev;
 418         struct device_node *of_node = dev->of_node;
 419         u32 led_mode;
 420         int err;
 421
 422         if (!of_node)
 423                 return -ENODEV;
 424
 425         led_mode = default_mode;
 426         err = of_property_read_u32(of_node, led, &led_mode);
 427         if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
 428                 phydev_err(phydev, "DT %s invalid\n", led);
 429                 return -EINVAL;
 430         }
 431
 432         return led_mode;
 433 }
 434
 435 #else
 436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 437 {
 438         return 0;
 439 }
 440
 441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 442                                    char *led,
 443                                    u8 default_mode)
 444 {
 445         return default_mode;
 446 }
 447 #endif /* CONFIG_OF_MDIO */
 448
 449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
 450                                     u32 *default_mode)
 451 {
 452         struct vsc8531_private *priv = phydev->priv;
 453         char led_dt_prop[28];
 454         int i, ret;
 455
 456         for (i = 0; i < priv->nleds; i++) {
 457                 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
 458                 if (ret < 0)
 459                         return ret;
 460
 461                 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
 462                                               default_mode[i]);
 463                 if (ret < 0)
 464                         return ret;
 465                 priv->leds_mode[i] = ret;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
 472 {
 473         int rc;
 474
 475         mutex_lock(&phydev->lock);
 476         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 477                               MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
 478                               edge_rate << EDGE_RATE_CNTL_POS);
 479         mutex_unlock(&phydev->lock);
 480
 481         return rc;
 482 }
 483
 484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
 485                               phy_interface_t interface)
 486 {
 487         int rc;
 488         u16 reg_val;
 489
 490         mutex_lock(&phydev->lock);
 491         reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
 492         reg_val &= ~(MAC_IF_SELECTION_MASK);
 493         switch (interface) {
 494         case PHY_INTERFACE_MODE_RGMII_TXID:
 495         case PHY_INTERFACE_MODE_RGMII_RXID:
 496         case PHY_INTERFACE_MODE_RGMII_ID:
 497         case PHY_INTERFACE_MODE_RGMII:
 498                 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
 499                 break;
 500         case PHY_INTERFACE_MODE_RMII:
 501                 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
 502                 break;
 503         case PHY_INTERFACE_MODE_MII:
 504         case PHY_INTERFACE_MODE_GMII:
 505                 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
 506                 break;
 507         default:
 508                 rc = -EINVAL;
 509                 goto out_unlock;
 510         }
 511         rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
 512         if (rc)
 513                 goto out_unlock;
 514
 515         rc = genphy_soft_reset(phydev);
 516
 517 out_unlock:
 518         mutex_unlock(&phydev->lock);
 519
 520         return rc;
 521 }
 522
 523 /* Set the RGMII RX and TX clock skews individually, according to the PHY
 524  * interface type, to:
 525  *  * 0.2 ns (their default, and lowest, hardware value) if delays should
 526  *    not be enabled
 527  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
 528  *    clock transitions at 1000 Mbps) if delays should be enabled
 529  */
 530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
 531                                    u16 rgmii_rx_delay_mask,
 532                                    u16 rgmii_tx_delay_mask)
 533 {
 534         u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
 535         u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
 536         u16 reg_val = 0;
 537         int rc;
 538
 539         mutex_lock(&phydev->lock);
 540
 541         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 542             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 543                 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
 544         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 545             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 546                 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
 547
 548         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 549                               rgmii_cntl,
 550                               rgmii_rx_delay_mask | rgmii_tx_delay_mask,
 551                               reg_val);
 552
 553         mutex_unlock(&phydev->lock);
 554
 555         return rc;
 556 }
 557
 558 static int vsc85xx_default_config(struct phy_device *phydev)
 559 {
 560         int rc;
 561
 562         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 563
 564         if (phy_interface_mode_is_rgmii(phydev->interface)) {
 565                 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL,
 566                                              VSC8502_RGMII_RX_DELAY_MASK,
 567                                              VSC8502_RGMII_TX_DELAY_MASK);
 568                 if (rc)
 569                         return rc;
 570         }
 571
 572         return 0;
 573 }
 574
 575 static int vsc85xx_get_tunable(struct phy_device *phydev,
 576                                struct ethtool_tunable *tuna, void *data)
 577 {
 578         switch (tuna->id) {
 579         case ETHTOOL_PHY_DOWNSHIFT:
 580                 return vsc85xx_downshift_get(phydev, (u8 *)data);
 581         default:
 582                 return -EINVAL;
 583         }
 584 }
 585
 586 static int vsc85xx_set_tunable(struct phy_device *phydev,
 587                                struct ethtool_tunable *tuna,
 588                                const void *data)
 589 {
 590         switch (tuna->id) {
 591         case ETHTOOL_PHY_DOWNSHIFT:
 592                 return vsc85xx_downshift_set(phydev, *(u8 *)data);
 593         default:
 594                 return -EINVAL;
 595         }
 596 }
 597
 598 /* mdiobus lock should be locked when using this function */
 599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
 600 {
 601         __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 602         __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 603         __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 604 }
 605
 606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
 607 {
 608         int rc;
 609         static const struct reg_val init_seq[] = {
 610                 {0x0f90, 0x00688980},
 611                 {0x0696, 0x00000003},
 612                 {0x07fa, 0x0050100f},
 613                 {0x1686, 0x00000004},
 614         };
 615         unsigned int i;
 616         int oldpage;
 617
 618         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
 619                               MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
 620                               SMI_BROADCAST_WR_EN);
 621         if (rc < 0)
 622                 return rc;
 623         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 624                               MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
 625         if (rc < 0)
 626                 return rc;
 627         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 628                               MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
 629         if (rc < 0)
 630                 return rc;
 631         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 632                               MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
 633         if (rc < 0)
 634                 return rc;
 635
 636         mutex_lock(&phydev->lock);
 637         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 638         if (oldpage < 0)
 639                 goto out_unlock;
 640
 641         for (i = 0; i < ARRAY_SIZE(init_seq); i++)
 642                 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
 643
 644 out_unlock:
 645         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 646         mutex_unlock(&phydev->lock);
 647
 648         return oldpage;
 649 }
 650
 651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
 652 {
 653         static const struct reg_val init_eee[] = {
 654                 {0x0f82, 0x0012b00a},
 655                 {0x1686, 0x00000004},
 656                 {0x168c, 0x00d2c46f},
 657                 {0x17a2, 0x00000620},
 658                 {0x16a0, 0x00eeffdd},
 659                 {0x16a6, 0x00071448},
 660                 {0x16a4, 0x0013132f},
 661                 {0x16a8, 0x00000000},
 662                 {0x0ffc, 0x00c0a028},
 663                 {0x0fe8, 0x0091b06c},
 664                 {0x0fea, 0x00041600},
 665                 {0x0f80, 0x00000af4},
 666                 {0x0fec, 0x00901809},
 667                 {0x0fee, 0x0000a6a1},
 668                 {0x0ffe, 0x00b01007},
 669                 {0x16b0, 0x00eeff00},
 670                 {0x16b2, 0x00007000},
 671                 {0x16b4, 0x00000814},
 672         };
 673         unsigned int i;
 674         int oldpage;
 675
 676         mutex_lock(&phydev->lock);
 677         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 678         if (oldpage < 0)
 679                 goto out_unlock;
 680
 681         for (i = 0; i < ARRAY_SIZE(init_eee); i++)
 682                 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
 683
 684 out_unlock:
 685         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 686         mutex_unlock(&phydev->lock);
 687
 688         return oldpage;
 689 }
 690
 691 /* phydev->bus->mdio_lock should be locked when using this function */
 692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
 693 {
 694         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 695                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 696                 dump_stack();
 697         }
 698
 699         return __phy_package_write(phydev, regnum, val);
 700 }
 701
 702 /* phydev->bus->mdio_lock should be locked when using this function */
 703 static int phy_base_read(struct phy_device *phydev, u32 regnum)
 704 {
 705         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 706                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 707                 dump_stack();
 708         }
 709
 710         return __phy_package_read(phydev, regnum);
 711 }
 712
 713 /* bus->mdio_lock should be locked when using this function */
 714 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
 715 {
 716         phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 717         phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 718         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 719 }
 720
 721 /* bus->mdio_lock should be locked when using this function */
 722 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
 723 {
 724         unsigned long deadline;
 725         u16 reg_val;
 726
 727         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 728                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 729
 730         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
 731
 732         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
 733         do {
 734                 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
 735         } while (time_before(jiffies, deadline) &&
 736                  (reg_val & PROC_CMD_NCOMPLETED) &&
 737                  !(reg_val & PROC_CMD_FAILED));
 738
 739         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 740
 741         if (reg_val & PROC_CMD_FAILED)
 742                 return -EIO;
 743
 744         if (reg_val & PROC_CMD_NCOMPLETED)
 745                 return -ETIMEDOUT;
 746
 747         return 0;
 748 }
 749
 750 /* bus->mdio_lock should be locked when using this function */
 751 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
 752                                         bool patch_en)
 753 {
 754         u32 enable, release;
 755
 756         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 757                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 758
 759         enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
 760         release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
 761                 MICRO_CLK_EN;
 762
 763         if (patch_en) {
 764                 enable |= MICRO_PATCH_EN;
 765                 release |= MICRO_PATCH_EN;
 766
 767                 /* Clear all patches */
 768                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 769         }
 770
 771         /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
 772          * override and addr. auto-incr; operate at 125 MHz
 773          */
 774         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
 775         /* Release 8051 Micro SW reset */
 776         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
 777
 778         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 779
 780         return 0;
 781 }
 782
 783 /* bus->mdio_lock should be locked when using this function */
 784 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
 785 {
 786         int ret;
 787         u16 reg;
 788
 789         ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
 790         if (ret)
 791                 return ret;
 792
 793         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 794                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 795
 796         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 797         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
 798         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 799
 800         phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
 801         phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
 802
 803         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 804         reg |= EN_PATCH_RAM_TRAP_ADDR(4);
 805         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 806
 807         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
 808
 809         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
 810         reg &= ~MICRO_NSOFT_RESET;
 811         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
 812
 813         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
 814                        PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
 815                        PROC_CMD_READ);
 816
 817         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 818         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
 819         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 820
 821         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 822
 823         return 0;
 824 }
 825
 826 /* bus->mdio_lock should be locked when using this function */
 827 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
 828                               u16 *crc)
 829 {
 830         int ret;
 831
 832         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 833
 834         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
 835         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
 836
 837         /* Start Micro command */
 838         ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
 839         if (ret)
 840                 goto out;
 841
 842         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 843
 844         *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
 845
 846 out:
 847         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 848
 849         return ret;
 850 }
 851
 852 /* bus->mdio_lock should be locked when using this function */
 853 static int vsc8584_patch_fw(struct phy_device *phydev,
 854                             const struct firmware *fw)
 855 {
 856         int i, ret;
 857
 858         ret = vsc8584_micro_assert_reset(phydev);
 859         if (ret) {
 860                 dev_err(&phydev->mdio.dev,
 861                         "%s: failed to assert reset of micro\n", __func__);
 862                 return ret;
 863         }
 864
 865         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 866                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 867
 868         /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
 869          * Disable the 8051 Micro clock
 870          */
 871         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
 872                        AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
 873                        MICRO_CLK_DIVIDE(2));
 874         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
 875                        INT_MEM_DATA(2));
 876         phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
 877
 878         for (i = 0; i < fw->size; i++)
 879                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
 880                                INT_MEM_WRITE_EN | fw->data[i]);
 881
 882         /* Clear internal memory access */
 883         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 884
 885         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 886
 887         return 0;
 888 }
 889
 890 /* bus->mdio_lock should be locked when using this function */
 891 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
 892 {
 893         u16 reg;
 894         bool ret;
 895
 896         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 897                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 898
 899         reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
 900         if (reg != 0x3eb7) {
 901                 ret = false;
 902                 goto out;
 903         }
 904
 905         reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
 906         if (reg != 0x4012) {
 907                 ret = false;
 908                 goto out;
 909         }
 910
 911         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 912         if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
 913                 ret = false;
 914                 goto out;
 915         }
 916
 917         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
 918         if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM |  DW8051_CLK_EN |
 919              MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
 920                 ret = false;
 921                 goto out;
 922         }
 923
 924         ret = true;
 925 out:
 926         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 927
 928         return ret;
 929 }
 930
 931 /* bus->mdio_lock should be locked when using this function */
 932 static int vsc8574_config_pre_init(struct phy_device *phydev)
 933 {
 934         static const struct reg_val pre_init1[] = {
 935                 {0x0fae, 0x000401bd},
 936                 {0x0fac, 0x000f000f},
 937                 {0x17a0, 0x00a0f147},
 938                 {0x0fe4, 0x00052f54},
 939                 {0x1792, 0x0027303d},
 940                 {0x07fe, 0x00000704},
 941                 {0x0fe0, 0x00060150},
 942                 {0x0f82, 0x0012b00a},
 943                 {0x0f80, 0x00000d74},
 944                 {0x02e0, 0x00000012},
 945                 {0x03a2, 0x00050208},
 946                 {0x03b2, 0x00009186},
 947                 {0x0fb0, 0x000e3700},
 948                 {0x1688, 0x00049f81},
 949                 {0x0fd2, 0x0000ffff},
 950                 {0x168a, 0x00039fa2},
 951                 {0x1690, 0x0020640b},
 952                 {0x0258, 0x00002220},
 953                 {0x025a, 0x00002a20},
 954                 {0x025c, 0x00003060},
 955                 {0x025e, 0x00003fa0},
 956                 {0x03a6, 0x0000e0f0},
 957                 {0x0f92, 0x00001489},
 958                 {0x16a2, 0x00007000},
 959                 {0x16a6, 0x00071448},
 960                 {0x16a0, 0x00eeffdd},
 961                 {0x0fe8, 0x0091b06c},
 962                 {0x0fea, 0x00041600},
 963                 {0x16b0, 0x00eeff00},
 964                 {0x16b2, 0x00007000},
 965                 {0x16b4, 0x00000814},
 966                 {0x0f90, 0x00688980},
 967                 {0x03a4, 0x0000d8f0},
 968                 {0x0fc0, 0x00000400},
 969                 {0x07fa, 0x0050100f},
 970                 {0x0796, 0x00000003},
 971                 {0x07f8, 0x00c3ff98},
 972                 {0x0fa4, 0x0018292a},
 973                 {0x168c, 0x00d2c46f},
 974                 {0x17a2, 0x00000620},
 975                 {0x16a4, 0x0013132f},
 976                 {0x16a8, 0x00000000},
 977                 {0x0ffc, 0x00c0a028},
 978                 {0x0fec, 0x00901c09},
 979                 {0x0fee, 0x0004a6a1},
 980                 {0x0ffe, 0x00b01807},
 981         };
 982         static const struct reg_val pre_init2[] = {
 983                 {0x0486, 0x0008a518},
 984                 {0x0488, 0x006dc696},
 985                 {0x048a, 0x00000912},
 986                 {0x048e, 0x00000db6},
 987                 {0x049c, 0x00596596},
 988                 {0x049e, 0x00000514},
 989                 {0x04a2, 0x00410280},
 990                 {0x04a4, 0x00000000},
 991                 {0x04a6, 0x00000000},
 992                 {0x04a8, 0x00000000},
 993                 {0x04aa, 0x00000000},
 994                 {0x04ae, 0x007df7dd},
 995                 {0x04b0, 0x006d95d4},
 996                 {0x04b2, 0x00492410},
 997         };
 998         struct device *dev = &phydev->mdio.dev;
 999         const struct firmware *fw;
1000         unsigned int i;
1001         u16 crc, reg;
1002         bool serdes_init;
1003         int ret;
1004
1005         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1006
1007         /* all writes below are broadcasted to all PHYs in the same package */
1008         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1009         reg |= SMI_BROADCAST_WR_EN;
1010         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1011
1012         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1013
1014         /* The below register writes are tweaking analog and electrical
1015          * configuration that were determined through characterization by PHY
1016          * engineers. These don't mean anything more than "these are the best
1017          * values".
1018          */
1019         phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1020
1021         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1022
1023         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1024         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1025         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1026         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1027
1028         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1029         reg |= TR_CLK_DISABLE;
1030         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1031
1032         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1033
1034         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1035                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1036
1037         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1038
1039         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1040
1041         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1042
1043         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1044                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1045
1046         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1047
1048         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1049         reg &= ~TR_CLK_DISABLE;
1050         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1051
1052         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1053
1054         /* end of write broadcasting */
1055         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1056         reg &= ~SMI_BROADCAST_WR_EN;
1057         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1058
1059         ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1060         if (ret) {
1061                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1062                         MSCC_VSC8574_REVB_INT8051_FW, ret);
1063                 return ret;
1064         }
1065
1066         /* Add one byte to size for the one added by the patch_fw function */
1067         ret = vsc8584_get_fw_crc(phydev,
1068                                  MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1069                                  fw->size + 1, &crc);
1070         if (ret)
1071                 goto out;
1072
1073         if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1074                 serdes_init = vsc8574_is_serdes_init(phydev);
1075
1076                 if (!serdes_init) {
1077                         ret = vsc8584_micro_assert_reset(phydev);
1078                         if (ret) {
1079                                 dev_err(dev,
1080                                         "%s: failed to assert reset of micro\n",
1081                                         __func__);
1082                                 goto out;
1083                         }
1084                 }
1085         } else {
1086                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1087
1088                 serdes_init = false;
1089
1090                 if (vsc8584_patch_fw(phydev, fw))
1091                         dev_warn(dev,
1092                                  "failed to patch FW, expect non-optimal device\n");
1093         }
1094
1095         if (!serdes_init) {
1096                 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1097                                MSCC_PHY_PAGE_EXTENDED_GPIO);
1098
1099                 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1100                 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1101                 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1102                                EN_PATCH_RAM_TRAP_ADDR(1));
1103
1104                 vsc8584_micro_deassert_reset(phydev, false);
1105
1106                 /* Add one byte to size for the one added by the patch_fw
1107                  * function
1108                  */
1109                 ret = vsc8584_get_fw_crc(phydev,
1110                                          MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1111                                          fw->size + 1, &crc);
1112                 if (ret)
1113                         goto out;
1114
1115                 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1116                         dev_warn(dev,
1117                                  "FW CRC after patching is not the expected one, expect non-optimal device\n");
1118         }
1119
1120         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1121                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1122
1123         ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1124                           PROC_CMD_PHY_INIT);
1125
1126 out:
1127         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1128
1129         release_firmware(fw);
1130
1131         return ret;
1132 }
1133
1134 /* bus->mdio_lock should be locked when using this function */
1135 static int vsc8584_config_pre_init(struct phy_device *phydev)
1136 {
1137         static const struct reg_val pre_init1[] = {
1138                 {0x07fa, 0x0050100f},
1139                 {0x1688, 0x00049f81},
1140                 {0x0f90, 0x00688980},
1141                 {0x03a4, 0x0000d8f0},
1142                 {0x0fc0, 0x00000400},
1143                 {0x0f82, 0x0012b002},
1144                 {0x1686, 0x00000004},
1145                 {0x168c, 0x00d2c46f},
1146                 {0x17a2, 0x00000620},
1147                 {0x16a0, 0x00eeffdd},
1148                 {0x16a6, 0x00071448},
1149                 {0x16a4, 0x0013132f},
1150                 {0x16a8, 0x00000000},
1151                 {0x0ffc, 0x00c0a028},
1152                 {0x0fe8, 0x0091b06c},
1153                 {0x0fea, 0x00041600},
1154                 {0x0f80, 0x00fffaff},
1155                 {0x0fec, 0x00901809},
1156                 {0x0ffe, 0x00b01007},
1157                 {0x16b0, 0x00eeff00},
1158                 {0x16b2, 0x00007000},
1159                 {0x16b4, 0x00000814},
1160         };
1161         static const struct reg_val pre_init2[] = {
1162                 {0x0486, 0x0008a518},
1163                 {0x0488, 0x006dc696},
1164                 {0x048a, 0x00000912},
1165         };
1166         const struct firmware *fw;
1167         struct device *dev = &phydev->mdio.dev;
1168         unsigned int i;
1169         u16 crc, reg;
1170         int ret;
1171
1172         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1173
1174         /* all writes below are broadcasted to all PHYs in the same package */
1175         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1176         reg |= SMI_BROADCAST_WR_EN;
1177         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1178
1179         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1180
1181         reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);
1182         reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1183         phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1184
1185         /* The below register writes are tweaking analog and electrical
1186          * configuration that were determined through characterization by PHY
1187          * engineers. These don't mean anything more than "these are the best
1188          * values".
1189          */
1190         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1191
1192         phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1193
1194         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1195
1196         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1197
1198         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1199         reg |= TR_CLK_DISABLE;
1200         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1201
1202         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1203
1204         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1205
1206         reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1207         reg &= ~0x007f;
1208         reg |= 0x0019;
1209         phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1210
1211         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1212
1213         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1214                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1215
1216         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1217
1218         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1219
1220         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1221
1222         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1223                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1224
1225         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1226
1227         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1228         reg &= ~TR_CLK_DISABLE;
1229         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1230
1231         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1232
1233         /* end of write broadcasting */
1234         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1235         reg &= ~SMI_BROADCAST_WR_EN;
1236         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1237
1238         ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1239         if (ret) {
1240                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1241                         MSCC_VSC8584_REVB_INT8051_FW, ret);
1242                 return ret;
1243         }
1244
1245         /* Add one byte to size for the one added by the patch_fw function */
1246         ret = vsc8584_get_fw_crc(phydev,
1247                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1248                                  fw->size + 1, &crc);
1249         if (ret)
1250                 goto out;
1251
1252         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1253                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1254                 if (vsc8584_patch_fw(phydev, fw))
1255                         dev_warn(dev,
1256                                  "failed to patch FW, expect non-optimal device\n");
1257         }
1258
1259         vsc8584_micro_deassert_reset(phydev, false);
1260
1261         /* Add one byte to size for the one added by the patch_fw function */
1262         ret = vsc8584_get_fw_crc(phydev,
1263                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1264                                  fw->size + 1, &crc);
1265         if (ret)
1266                 goto out;
1267
1268         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1269                 dev_warn(dev,
1270                          "FW CRC after patching is not the expected one, expect non-optimal device\n");
1271
1272         ret = vsc8584_micro_assert_reset(phydev);
1273         if (ret)
1274                 goto out;
1275
1276         vsc8584_micro_deassert_reset(phydev, true);
1277
1278 out:
1279         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1280
1281         release_firmware(fw);
1282
1283         return ret;
1284 }
1285
1286 static void vsc8584_get_base_addr(struct phy_device *phydev)
1287 {
1288         struct vsc8531_private *vsc8531 = phydev->priv;
1289         u16 val, addr;
1290
1291         phy_lock_mdio_bus(phydev);
1292         __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1293
1294         addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1295         addr >>= PHY_CNTL_4_ADDR_POS;
1296
1297         val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1298
1299         __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1300         phy_unlock_mdio_bus(phydev);
1301
1302         /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1303          * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1304          * the base PHY for timestamping operations.
1305          */
1306         vsc8531->ts_base_addr = phydev->mdio.addr;
1307         vsc8531->ts_base_phy = addr;
1308
1309         if (val & PHY_ADDR_REVERSED) {
1310                 vsc8531->base_addr = phydev->mdio.addr + addr;
1311                 if (addr > 1) {
1312                         vsc8531->ts_base_addr += 2;
1313                         vsc8531->ts_base_phy += 2;
1314                 }
1315         } else {
1316                 vsc8531->base_addr = phydev->mdio.addr - addr;
1317                 if (addr > 1) {
1318                         vsc8531->ts_base_addr -= 2;
1319                         vsc8531->ts_base_phy -= 2;
1320                 }
1321         }
1322
1323         vsc8531->addr = addr;
1324 }
1325
1326 static int vsc8584_config_init(struct phy_device *phydev)
1327 {
1328         struct vsc8531_private *vsc8531 = phydev->priv;
1329         int ret, i;
1330         u16 val;
1331
1332         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1333
1334         phy_lock_mdio_bus(phydev);
1335
1336         /* Some parts of the init sequence are identical for every PHY in the
1337          * package. Some parts are modifying the GPIO register bank which is a
1338          * set of registers that are affecting all PHYs, a few resetting the
1339          * microprocessor common to all PHYs. The CRC check responsible of the
1340          * checking the firmware within the 8051 microprocessor can only be
1341          * accessed via the PHY whose internal address in the package is 0.
1342          * All PHYs' interrupts mask register has to be zeroed before enabling
1343          * any PHY's interrupt in this register.
1344          * For all these reasons, we need to do the init sequence once and only
1345          * once whatever is the first PHY in the package that is initialized and
1346          * do the correct init sequence for all PHYs that are package-critical
1347          * in this pre-init function.
1348          */
1349         if (phy_package_init_once(phydev)) {
1350                 /* The following switch statement assumes that the lowest
1351                  * nibble of the phy_id_mask is always 0. This works because
1352                  * the lowest nibble of the PHY_ID's below are also 0.
1353                  */
1354                 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1355
1356                 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1357                 case PHY_ID_VSC8504:
1358                 case PHY_ID_VSC8552:
1359                 case PHY_ID_VSC8572:
1360                 case PHY_ID_VSC8574:
1361                         ret = vsc8574_config_pre_init(phydev);
1362                         break;
1363                 case PHY_ID_VSC856X:
1364                 case PHY_ID_VSC8575:
1365                 case PHY_ID_VSC8582:
1366                 case PHY_ID_VSC8584:
1367                         ret = vsc8584_config_pre_init(phydev);
1368                         break;
1369                 default:
1370                         ret = -EINVAL;
1371                         break;
1372                 }
1373
1374                 if (ret)
1375                         goto err;
1376         }
1377
1378         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1379                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1380
1381         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1382         val &= ~MAC_CFG_MASK;
1383         if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1384                 val |= MAC_CFG_QSGMII;
1385         } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1386                 val |= MAC_CFG_SGMII;
1387         } else if (phy_interface_is_rgmii(phydev)) {
1388                 val |= MAC_CFG_RGMII;
1389         } else {
1390                 ret = -EINVAL;
1391                 goto err;
1392         }
1393
1394         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1395         if (ret)
1396                 goto err;
1397
1398         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1399                              MSCC_PHY_PAGE_STANDARD);
1400         if (ret)
1401                 goto err;
1402
1403         if (!phy_interface_is_rgmii(phydev)) {
1404                 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1405                         PROC_CMD_READ_MOD_WRITE_PORT;
1406                 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1407                         val |= PROC_CMD_QSGMII_MAC;
1408                 else
1409                         val |= PROC_CMD_SGMII_MAC;
1410
1411                 ret = vsc8584_cmd(phydev, val);
1412                 if (ret)
1413                         goto err;
1414
1415                 usleep_range(10000, 20000);
1416         }
1417
1418         /* Disable SerDes for 100Base-FX */
1419         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1420                           PROC_CMD_FIBER_PORT(vsc8531->addr) |
1421                           PROC_CMD_FIBER_DISABLE |
1422                           PROC_CMD_READ_MOD_WRITE_PORT |
1423                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1424         if (ret)
1425                 goto err;
1426
1427         /* Disable SerDes for 1000Base-X */
1428         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1429                           PROC_CMD_FIBER_PORT(vsc8531->addr) |
1430                           PROC_CMD_FIBER_DISABLE |
1431                           PROC_CMD_READ_MOD_WRITE_PORT |
1432                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1433         if (ret)
1434                 goto err;
1435
1436         phy_unlock_mdio_bus(phydev);
1437
1438         ret = vsc8584_macsec_init(phydev);
1439         if (ret)
1440                 return ret;
1441
1442         ret = vsc8584_ptp_init(phydev);
1443         if (ret)
1444                 return ret;
1445
1446         val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1447         val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1448         val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1449                (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1450         ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1451         if (ret)
1452                 return ret;
1453
1454         if (phy_interface_is_rgmii(phydev)) {
1455                 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL,
1456                                               VSC8572_RGMII_RX_DELAY_MASK,
1457                                               VSC8572_RGMII_TX_DELAY_MASK);
1458                 if (ret)
1459                         return ret;
1460         }
1461
1462         ret = genphy_soft_reset(phydev);
1463         if (ret)
1464                 return ret;
1465
1466         for (i = 0; i < vsc8531->nleds; i++) {
1467                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1468                 if (ret)
1469                         return ret;
1470         }
1471
1472         return 0;
1473
1474 err:
1475         phy_unlock_mdio_bus(phydev);
1476         return ret;
1477 }
1478
1479 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1480 {
1481         irqreturn_t ret;
1482         int irq_status;
1483
1484         irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1485         if (irq_status < 0)
1486                 return IRQ_NONE;
1487
1488         /* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1489          * irq_status would be 0.
1490          */
1491         ret = vsc8584_handle_ts_interrupt(phydev);
1492         if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1493                 return ret;
1494
1495         if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1496                 vsc8584_handle_macsec_interrupt(phydev);
1497
1498         if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1499                 phy_mac_interrupt(phydev);
1500
1501         return IRQ_HANDLED;
1502 }
1503
1504 static int vsc85xx_config_init(struct phy_device *phydev)
1505 {
1506         int rc, i, phy_id;
1507         struct vsc8531_private *vsc8531 = phydev->priv;
1508
1509         rc = vsc85xx_default_config(phydev);
1510         if (rc)
1511                 return rc;
1512
1513         rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1514         if (rc)
1515                 return rc;
1516
1517         rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1518         if (rc)
1519                 return rc;
1520
1521         phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1522         if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1523             PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1524                 rc = vsc8531_pre_init_seq_set(phydev);
1525                 if (rc)
1526                         return rc;
1527         }
1528
1529         rc = vsc85xx_eee_init_seq_set(phydev);
1530         if (rc)
1531                 return rc;
1532
1533         for (i = 0; i < vsc8531->nleds; i++) {
1534                 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1535                 if (rc)
1536                         return rc;
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int vsc8584_did_interrupt(struct phy_device *phydev)
1543 {
1544         int rc = 0;
1545
1546         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1547                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1548
1549         return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1550 }
1551
1552 static int vsc8514_config_pre_init(struct phy_device *phydev)
1553 {
1554         /* These are the settings to override the silicon default
1555          * values to handle hardware performance of PHY. They
1556          * are set at Power-On state and remain until PHY Reset.
1557          */
1558         static const struct reg_val pre_init1[] = {
1559                 {0x0f90, 0x00688980},
1560                 {0x0786, 0x00000003},
1561                 {0x07fa, 0x0050100f},
1562                 {0x0f82, 0x0012b002},
1563                 {0x1686, 0x00000004},
1564                 {0x168c, 0x00d2c46f},
1565                 {0x17a2, 0x00000620},
1566                 {0x16a0, 0x00eeffdd},
1567                 {0x16a6, 0x00071448},
1568                 {0x16a4, 0x0013132f},
1569                 {0x16a8, 0x00000000},
1570                 {0x0ffc, 0x00c0a028},
1571                 {0x0fe8, 0x0091b06c},
1572                 {0x0fea, 0x00041600},
1573                 {0x0f80, 0x00fffaff},
1574                 {0x0fec, 0x00901809},
1575                 {0x0ffe, 0x00b01007},
1576                 {0x16b0, 0x00eeff00},
1577                 {0x16b2, 0x00007000},
1578                 {0x16b4, 0x00000814},
1579         };
1580         unsigned int i;
1581         u16 reg;
1582
1583         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1584
1585         /* all writes below are broadcasted to all PHYs in the same package */
1586         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1587         reg |= SMI_BROADCAST_WR_EN;
1588         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1589
1590         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1591
1592         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1593         reg |= BIT(15);
1594         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1595
1596         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1597
1598         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1599                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1600
1601         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1602
1603         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1604         reg &= ~BIT(15);
1605         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1606
1607         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1608
1609         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1610         reg &= ~SMI_BROADCAST_WR_EN;
1611         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1612
1613         return 0;
1614 }
1615
1616 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev,
1617                                      u32 target, u32 reg)
1618 {
1619         unsigned long deadline;
1620         u32 val, val_l, val_h;
1621
1622         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1623
1624         /* CSR registers are grouped under different Target IDs.
1625          * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1626          * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1627          * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1628          * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1629          */
1630
1631         /* Setup the Target ID */
1632         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1633                        MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1634
1635         /* Trigger CSR Action - Read into the CSR's */
1636         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1637                        MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
1638                        MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1639                        MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1640
1641         /* Wait for register access*/
1642         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1643         do {
1644                 usleep_range(500, 1000);
1645                 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1646         } while (time_before(jiffies, deadline) &&
1647                 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1648
1649         if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1650                 return 0xffffffff;
1651
1652         /* Read the Least Significant Word (LSW) (17) */
1653         val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
1654
1655         /* Read the Most Significant Word (MSW) (18) */
1656         val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
1657
1658         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1659                        MSCC_PHY_PAGE_STANDARD);
1660
1661         return (val_h << 16) | val_l;
1662 }
1663
1664 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev,
1665                                       u32 target, u32 reg, u32 val)
1666 {
1667         unsigned long deadline;
1668
1669         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1670
1671         /* CSR registers are grouped under different Target IDs.
1672          * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1673          * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1674          * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1675          * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1676          */
1677
1678         /* Setup the Target ID */
1679         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1680                        MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1681
1682         /* Write the Least Significant Word (LSW) (17) */
1683         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
1684
1685         /* Write the Most Significant Word (MSW) (18) */
1686         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
1687
1688         /* Trigger CSR Action - Write into the CSR's */
1689         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1690                        MSCC_PHY_CSR_CNTL_19_CMD |
1691                        MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1692                        MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1693
1694         /* Wait for register access */
1695         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1696         do {
1697                 usleep_range(500, 1000);
1698                 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1699         } while (time_before(jiffies, deadline) &&
1700                  !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1701
1702         if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1703                 return -ETIMEDOUT;
1704
1705         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1706                        MSCC_PHY_PAGE_STANDARD);
1707
1708         return 0;
1709 }
1710
1711 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1712                                u32 op)
1713 {
1714         unsigned long deadline;
1715         u32 val;
1716         int ret;
1717
1718         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg,
1719                                          op | (1 << mcb));
1720         if (ret)
1721                 return -EINVAL;
1722
1723         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1724         do {
1725                 usleep_range(500, 1000);
1726                 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg);
1727
1728                 if (val == 0xffffffff)
1729                         return -EIO;
1730
1731         } while (time_before(jiffies, deadline) && (val & op));
1732
1733         if (val & op)
1734                 return -ETIMEDOUT;
1735
1736         return 0;
1737 }
1738
1739 /* Trigger a read to the spcified MCB */
1740 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1741 {
1742         return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1743 }
1744
1745 /* Trigger a write to the spcified MCB */
1746 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1747 {
1748         return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1749 }
1750
1751 static int vsc8514_config_init(struct phy_device *phydev)
1752 {
1753         struct vsc8531_private *vsc8531 = phydev->priv;
1754         unsigned long deadline;
1755         int ret, i;
1756         u16 val;
1757         u32 reg;
1758
1759         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1760
1761         phy_lock_mdio_bus(phydev);
1762
1763         /* Some parts of the init sequence are identical for every PHY in the
1764          * package. Some parts are modifying the GPIO register bank which is a
1765          * set of registers that are affecting all PHYs, a few resetting the
1766          * microprocessor common to all PHYs.
1767          * All PHYs' interrupts mask register has to be zeroed before enabling
1768          * any PHY's interrupt in this register.
1769          * For all these reasons, we need to do the init sequence once and only
1770          * once whatever is the first PHY in the package that is initialized and
1771          * do the correct init sequence for all PHYs that are package-critical
1772          * in this pre-init function.
1773          */
1774         if (phy_package_init_once(phydev))
1775                 vsc8514_config_pre_init(phydev);
1776
1777         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1778                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1779
1780         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1781
1782         val &= ~MAC_CFG_MASK;
1783         val |= MAC_CFG_QSGMII;
1784         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1785         if (ret)
1786                 goto err;
1787
1788         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1789                              MSCC_PHY_PAGE_STANDARD);
1790         if (ret)
1791                 goto err;
1792
1793         ret = vsc8584_cmd(phydev,
1794                           PROC_CMD_MCB_ACCESS_MAC_CONF |
1795                           PROC_CMD_RST_CONF_PORT |
1796                           PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1797         if (ret)
1798                 goto err;
1799
1800         /* 6g mcb */
1801         phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1802         /* lcpll mcb */
1803         phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1804         /* pll5gcfg0 */
1805         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1806                                          PHY_S6G_PLL5G_CFG0, 0x7036f145);
1807         if (ret)
1808                 goto err;
1809
1810         phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1811         /* pllcfg */
1812         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1813                                          PHY_S6G_PLL_CFG,
1814                                          (3 << PHY_S6G_PLL_ENA_OFFS_POS) |
1815                                          (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS)
1816                                          | (0 << PHY_S6G_PLL_FSM_ENA_POS));
1817         if (ret)
1818                 goto err;
1819
1820         /* commoncfg */
1821         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1822                                          PHY_S6G_COMMON_CFG,
1823                                          (0 << PHY_S6G_SYS_RST_POS) |
1824                                          (0 << PHY_S6G_ENA_LANE_POS) |
1825                                          (0 << PHY_S6G_ENA_LOOP_POS) |
1826                                          (0 << PHY_S6G_QRATE_POS) |
1827                                          (3 << PHY_S6G_IF_MODE_POS));
1828         if (ret)
1829                 goto err;
1830
1831         /* misccfg */
1832         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1833                                          PHY_S6G_MISC_CFG, 1);
1834         if (ret)
1835                 goto err;
1836
1837         /* gpcfg */
1838         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1839                                          PHY_S6G_GPC_CFG, 768);
1840         if (ret)
1841                 goto err;
1842
1843         phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
1844
1845         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1846         do {
1847                 usleep_range(500, 1000);
1848                 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1849                                    0); /* read 6G MCB into CSRs */
1850                 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
1851                                                 PHY_S6G_PLL_STATUS);
1852                 if (reg == 0xffffffff) {
1853                         phy_unlock_mdio_bus(phydev);
1854                         return -EIO;
1855                 }
1856
1857         } while (time_before(jiffies, deadline) && (reg & BIT(12)));
1858
1859         if (reg & BIT(12)) {
1860                 phy_unlock_mdio_bus(phydev);
1861                 return -ETIMEDOUT;
1862         }
1863
1864         /* misccfg */
1865         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1866                                          PHY_S6G_MISC_CFG, 0);
1867         if (ret)
1868                 goto err;
1869
1870         phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1871
1872         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1873         do {
1874                 usleep_range(500, 1000);
1875                 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1876                                    0); /* read 6G MCB into CSRs */
1877                 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
1878                                                 PHY_S6G_IB_STATUS0);
1879                 if (reg == 0xffffffff) {
1880                         phy_unlock_mdio_bus(phydev);
1881                         return -EIO;
1882                 }
1883
1884         } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
1885
1886         if (!(reg & BIT(8))) {
1887                 phy_unlock_mdio_bus(phydev);
1888                 return -ETIMEDOUT;
1889         }
1890
1891         phy_unlock_mdio_bus(phydev);
1892
1893         ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
1894                          MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
1895
1896         if (ret)
1897                 return ret;
1898
1899         ret = genphy_soft_reset(phydev);
1900
1901         if (ret)
1902                 return ret;
1903
1904         for (i = 0; i < vsc8531->nleds; i++) {
1905                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1906                 if (ret)
1907                         return ret;
1908         }
1909
1910         return ret;
1911
1912 err:
1913         phy_unlock_mdio_bus(phydev);
1914         return ret;
1915 }
1916
1917 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
1918 {
1919         int rc = 0;
1920
1921         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1922                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1923
1924         return (rc < 0) ? rc : 0;
1925 }
1926
1927 static int vsc85xx_config_intr(struct phy_device *phydev)
1928 {
1929         int rc;
1930
1931         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1932                 vsc8584_config_macsec_intr(phydev);
1933                 vsc8584_config_ts_intr(phydev);
1934
1935                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
1936                                MII_VSC85XX_INT_MASK_MASK);
1937         } else {
1938                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
1939                 if (rc < 0)
1940                         return rc;
1941                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1942         }
1943
1944         return rc;
1945 }
1946
1947 static int vsc85xx_config_aneg(struct phy_device *phydev)
1948 {
1949         int rc;
1950
1951         rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
1952         if (rc < 0)
1953                 return rc;
1954
1955         return genphy_config_aneg(phydev);
1956 }
1957
1958 static int vsc85xx_read_status(struct phy_device *phydev)
1959 {
1960         int rc;
1961
1962         rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
1963         if (rc < 0)
1964                 return rc;
1965
1966         return genphy_read_status(phydev);
1967 }
1968
1969 static int vsc8514_probe(struct phy_device *phydev)
1970 {
1971         struct vsc8531_private *vsc8531;
1972         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1973            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1974            VSC8531_DUPLEX_COLLISION};
1975
1976         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1977         if (!vsc8531)
1978                 return -ENOMEM;
1979
1980         phydev->priv = vsc8531;
1981
1982         vsc8584_get_base_addr(phydev);
1983         devm_phy_package_join(&phydev->mdio.dev, phydev,
1984                               vsc8531->base_addr, 0);
1985
1986         vsc8531->nleds = 4;
1987         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
1988         vsc8531->hw_stats = vsc85xx_hw_stats;
1989         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
1990         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
1991                                       sizeof(u64), GFP_KERNEL);
1992         if (!vsc8531->stats)
1993                 return -ENOMEM;
1994
1995         return vsc85xx_dt_led_modes_get(phydev, default_mode);
1996 }
1997
1998 static int vsc8574_probe(struct phy_device *phydev)
1999 {
2000         struct vsc8531_private *vsc8531;
2001         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2002            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2003            VSC8531_DUPLEX_COLLISION};
2004
2005         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2006         if (!vsc8531)
2007                 return -ENOMEM;
2008
2009         phydev->priv = vsc8531;
2010
2011         vsc8584_get_base_addr(phydev);
2012         devm_phy_package_join(&phydev->mdio.dev, phydev,
2013                               vsc8531->base_addr, 0);
2014
2015         vsc8531->nleds = 4;
2016         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2017         vsc8531->hw_stats = vsc8584_hw_stats;
2018         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2019         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2020                                       sizeof(u64), GFP_KERNEL);
2021         if (!vsc8531->stats)
2022                 return -ENOMEM;
2023
2024         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2025 }
2026
2027 static int vsc8584_probe(struct phy_device *phydev)
2028 {
2029         struct vsc8531_private *vsc8531;
2030         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2031            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2032            VSC8531_DUPLEX_COLLISION};
2033         int ret;
2034
2035         if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2036                 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2037                 return -ENOTSUPP;
2038         }
2039
2040         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2041         if (!vsc8531)
2042                 return -ENOMEM;
2043
2044         phydev->priv = vsc8531;
2045
2046         vsc8584_get_base_addr(phydev);
2047         devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2048                               sizeof(struct vsc85xx_shared_private));
2049
2050         vsc8531->nleds = 4;
2051         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2052         vsc8531->hw_stats = vsc8584_hw_stats;
2053         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2054         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2055                                       sizeof(u64), GFP_KERNEL);
2056         if (!vsc8531->stats)
2057                 return -ENOMEM;
2058
2059         if (phy_package_probe_once(phydev)) {
2060                 ret = vsc8584_ptp_probe_once(phydev);
2061                 if (ret)
2062                         return ret;
2063         }
2064
2065         ret = vsc8584_ptp_probe(phydev);
2066         if (ret)
2067                 return ret;
2068
2069         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2070 }
2071
2072 static int vsc85xx_probe(struct phy_device *phydev)
2073 {
2074         struct vsc8531_private *vsc8531;
2075         int rate_magic;
2076         u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2077            VSC8531_LINK_100_ACTIVITY};
2078
2079         rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2080         if (rate_magic < 0)
2081                 return rate_magic;
2082
2083         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2084         if (!vsc8531)
2085                 return -ENOMEM;
2086
2087         phydev->priv = vsc8531;
2088
2089         vsc8531->rate_magic = rate_magic;
2090         vsc8531->nleds = 2;
2091         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2092         vsc8531->hw_stats = vsc85xx_hw_stats;
2093         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2094         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2095                                       sizeof(u64), GFP_KERNEL);
2096         if (!vsc8531->stats)
2097                 return -ENOMEM;
2098
2099         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2100 }
2101
2102 /* Microsemi VSC85xx PHYs */
2103 static struct phy_driver vsc85xx_driver[] = {
2104 {
2105         .phy_id         = PHY_ID_VSC8502,
2106         .name           = "Microsemi GE VSC8502 SyncE",
2107         .phy_id_mask    = 0xfffffff0,
2108         /* PHY_BASIC_FEATURES */
2109         .soft_reset     = &genphy_soft_reset,
2110         .config_init    = &vsc85xx_config_init,
2111         .config_aneg    = &vsc85xx_config_aneg,
2112         .read_status    = &vsc85xx_read_status,
2113         .ack_interrupt  = &vsc85xx_ack_interrupt,
2114         .config_intr    = &vsc85xx_config_intr,
2115         .suspend        = &genphy_suspend,
2116         .resume         = &genphy_resume,
2117         .probe          = &vsc85xx_probe,
2118         .set_wol        = &vsc85xx_wol_set,
2119         .get_wol        = &vsc85xx_wol_get,
2120         .get_tunable    = &vsc85xx_get_tunable,
2121         .set_tunable    = &vsc85xx_set_tunable,
2122         .read_page      = &vsc85xx_phy_read_page,
2123         .write_page     = &vsc85xx_phy_write_page,
2124         .get_sset_count = &vsc85xx_get_sset_count,
2125         .get_strings    = &vsc85xx_get_strings,
2126         .get_stats      = &vsc85xx_get_stats,
2127 },
2128 {
2129         .phy_id         = PHY_ID_VSC8504,
2130         .name           = "Microsemi GE VSC8504 SyncE",
2131         .phy_id_mask    = 0xfffffff0,
2132         /* PHY_GBIT_FEATURES */
2133         .soft_reset     = &genphy_soft_reset,
2134         .config_init    = &vsc8584_config_init,
2135         .config_aneg    = &vsc85xx_config_aneg,
2136         .aneg_done      = &genphy_aneg_done,
2137         .read_status    = &vsc85xx_read_status,
2138         .ack_interrupt  = &vsc85xx_ack_interrupt,
2139         .config_intr    = &vsc85xx_config_intr,
2140         .did_interrupt  = &vsc8584_did_interrupt,
2141         .suspend        = &genphy_suspend,
2142         .resume         = &genphy_resume,
2143         .probe          = &vsc8574_probe,
2144         .set_wol        = &vsc85xx_wol_set,
2145         .get_wol        = &vsc85xx_wol_get,
2146         .get_tunable    = &vsc85xx_get_tunable,
2147         .set_tunable    = &vsc85xx_set_tunable,
2148         .read_page      = &vsc85xx_phy_read_page,
2149         .write_page     = &vsc85xx_phy_write_page,
2150         .get_sset_count = &vsc85xx_get_sset_count,
2151         .get_strings    = &vsc85xx_get_strings,
2152         .get_stats      = &vsc85xx_get_stats,
2153 },
2154 {
2155         .phy_id         = PHY_ID_VSC8514,
2156         .name           = "Microsemi GE VSC8514 SyncE",
2157         .phy_id_mask    = 0xfffffff0,
2158         .soft_reset     = &genphy_soft_reset,
2159         .config_init    = &vsc8514_config_init,
2160         .config_aneg    = &vsc85xx_config_aneg,
2161         .read_status    = &vsc85xx_read_status,
2162         .ack_interrupt  = &vsc85xx_ack_interrupt,
2163         .config_intr    = &vsc85xx_config_intr,
2164         .suspend        = &genphy_suspend,
2165         .resume         = &genphy_resume,
2166         .probe          = &vsc8514_probe,
2167         .set_wol        = &vsc85xx_wol_set,
2168         .get_wol        = &vsc85xx_wol_get,
2169         .get_tunable    = &vsc85xx_get_tunable,
2170         .set_tunable    = &vsc85xx_set_tunable,
2171         .read_page      = &vsc85xx_phy_read_page,
2172         .write_page     = &vsc85xx_phy_write_page,
2173         .get_sset_count = &vsc85xx_get_sset_count,
2174         .get_strings    = &vsc85xx_get_strings,
2175         .get_stats      = &vsc85xx_get_stats,
2176 },
2177 {
2178         .phy_id         = PHY_ID_VSC8530,
2179         .name           = "Microsemi FE VSC8530",
2180         .phy_id_mask    = 0xfffffff0,
2181         /* PHY_BASIC_FEATURES */
2182         .soft_reset     = &genphy_soft_reset,
2183         .config_init    = &vsc85xx_config_init,
2184         .config_aneg    = &vsc85xx_config_aneg,
2185         .read_status    = &vsc85xx_read_status,
2186         .ack_interrupt  = &vsc85xx_ack_interrupt,
2187         .config_intr    = &vsc85xx_config_intr,
2188         .suspend        = &genphy_suspend,
2189         .resume         = &genphy_resume,
2190         .probe          = &vsc85xx_probe,
2191         .set_wol        = &vsc85xx_wol_set,
2192         .get_wol        = &vsc85xx_wol_get,
2193         .get_tunable    = &vsc85xx_get_tunable,
2194         .set_tunable    = &vsc85xx_set_tunable,
2195         .read_page      = &vsc85xx_phy_read_page,
2196         .write_page     = &vsc85xx_phy_write_page,
2197         .get_sset_count = &vsc85xx_get_sset_count,
2198         .get_strings    = &vsc85xx_get_strings,
2199         .get_stats      = &vsc85xx_get_stats,
2200 },
2201 {
2202         .phy_id         = PHY_ID_VSC8531,
2203         .name           = "Microsemi VSC8531",
2204         .phy_id_mask    = 0xfffffff0,
2205         /* PHY_GBIT_FEATURES */
2206         .soft_reset     = &genphy_soft_reset,
2207         .config_init    = &vsc85xx_config_init,
2208         .config_aneg    = &vsc85xx_config_aneg,
2209         .read_status    = &vsc85xx_read_status,
2210         .ack_interrupt  = &vsc85xx_ack_interrupt,
2211         .config_intr    = &vsc85xx_config_intr,
2212         .suspend        = &genphy_suspend,
2213         .resume         = &genphy_resume,
2214         .probe          = &vsc85xx_probe,
2215         .set_wol        = &vsc85xx_wol_set,
2216         .get_wol        = &vsc85xx_wol_get,
2217         .get_tunable    = &vsc85xx_get_tunable,
2218         .set_tunable    = &vsc85xx_set_tunable,
2219         .read_page      = &vsc85xx_phy_read_page,
2220         .write_page     = &vsc85xx_phy_write_page,
2221         .get_sset_count = &vsc85xx_get_sset_count,
2222         .get_strings    = &vsc85xx_get_strings,
2223         .get_stats      = &vsc85xx_get_stats,
2224 },
2225 {
2226         .phy_id         = PHY_ID_VSC8540,
2227         .name           = "Microsemi FE VSC8540 SyncE",
2228         .phy_id_mask    = 0xfffffff0,
2229         /* PHY_BASIC_FEATURES */
2230         .soft_reset     = &genphy_soft_reset,
2231         .config_init    = &vsc85xx_config_init,
2232         .config_aneg    = &vsc85xx_config_aneg,
2233         .read_status    = &vsc85xx_read_status,
2234         .ack_interrupt  = &vsc85xx_ack_interrupt,
2235         .config_intr    = &vsc85xx_config_intr,
2236         .suspend        = &genphy_suspend,
2237         .resume         = &genphy_resume,
2238         .probe          = &vsc85xx_probe,
2239         .set_wol        = &vsc85xx_wol_set,
2240         .get_wol        = &vsc85xx_wol_get,
2241         .get_tunable    = &vsc85xx_get_tunable,
2242         .set_tunable    = &vsc85xx_set_tunable,
2243         .read_page      = &vsc85xx_phy_read_page,
2244         .write_page     = &vsc85xx_phy_write_page,
2245         .get_sset_count = &vsc85xx_get_sset_count,
2246         .get_strings    = &vsc85xx_get_strings,
2247         .get_stats      = &vsc85xx_get_stats,
2248 },
2249 {
2250         .phy_id         = PHY_ID_VSC8541,
2251         .name           = "Microsemi VSC8541 SyncE",
2252         .phy_id_mask    = 0xfffffff0,
2253         /* PHY_GBIT_FEATURES */
2254         .soft_reset     = &genphy_soft_reset,
2255         .config_init    = &vsc85xx_config_init,
2256         .config_aneg    = &vsc85xx_config_aneg,
2257         .read_status    = &vsc85xx_read_status,
2258         .ack_interrupt  = &vsc85xx_ack_interrupt,
2259         .config_intr    = &vsc85xx_config_intr,
2260         .suspend        = &genphy_suspend,
2261         .resume         = &genphy_resume,
2262         .probe          = &vsc85xx_probe,
2263         .set_wol        = &vsc85xx_wol_set,
2264         .get_wol        = &vsc85xx_wol_get,
2265         .get_tunable    = &vsc85xx_get_tunable,
2266         .set_tunable    = &vsc85xx_set_tunable,
2267         .read_page      = &vsc85xx_phy_read_page,
2268         .write_page     = &vsc85xx_phy_write_page,
2269         .get_sset_count = &vsc85xx_get_sset_count,
2270         .get_strings    = &vsc85xx_get_strings,
2271         .get_stats      = &vsc85xx_get_stats,
2272 },
2273 {
2274         .phy_id         = PHY_ID_VSC8552,
2275         .name           = "Microsemi GE VSC8552 SyncE",
2276         .phy_id_mask    = 0xfffffff0,
2277         /* PHY_GBIT_FEATURES */
2278         .soft_reset     = &genphy_soft_reset,
2279         .config_init    = &vsc8584_config_init,
2280         .config_aneg    = &vsc85xx_config_aneg,
2281         .read_status    = &vsc85xx_read_status,
2282         .ack_interrupt  = &vsc85xx_ack_interrupt,
2283         .config_intr    = &vsc85xx_config_intr,
2284         .did_interrupt  = &vsc8584_did_interrupt,
2285         .suspend        = &genphy_suspend,
2286         .resume         = &genphy_resume,
2287         .probe          = &vsc8574_probe,
2288         .set_wol        = &vsc85xx_wol_set,
2289         .get_wol        = &vsc85xx_wol_get,
2290         .get_tunable    = &vsc85xx_get_tunable,
2291         .set_tunable    = &vsc85xx_set_tunable,
2292         .read_page      = &vsc85xx_phy_read_page,
2293         .write_page     = &vsc85xx_phy_write_page,
2294         .get_sset_count = &vsc85xx_get_sset_count,
2295         .get_strings    = &vsc85xx_get_strings,
2296         .get_stats      = &vsc85xx_get_stats,
2297 },
2298 {
2299         .phy_id         = PHY_ID_VSC856X,
2300         .name           = "Microsemi GE VSC856X SyncE",
2301         .phy_id_mask    = 0xfffffff0,
2302         /* PHY_GBIT_FEATURES */
2303         .soft_reset     = &genphy_soft_reset,
2304         .config_init    = &vsc8584_config_init,
2305         .config_aneg    = &vsc85xx_config_aneg,
2306         .read_status    = &vsc85xx_read_status,
2307         .ack_interrupt  = &vsc85xx_ack_interrupt,
2308         .config_intr    = &vsc85xx_config_intr,
2309         .did_interrupt  = &vsc8584_did_interrupt,
2310         .suspend        = &genphy_suspend,
2311         .resume         = &genphy_resume,
2312         .probe          = &vsc8584_probe,
2313         .get_tunable    = &vsc85xx_get_tunable,
2314         .set_tunable    = &vsc85xx_set_tunable,
2315         .read_page      = &vsc85xx_phy_read_page,
2316         .write_page     = &vsc85xx_phy_write_page,
2317         .get_sset_count = &vsc85xx_get_sset_count,
2318         .get_strings    = &vsc85xx_get_strings,
2319         .get_stats      = &vsc85xx_get_stats,
2320 },
2321 {
2322         .phy_id         = PHY_ID_VSC8572,
2323         .name           = "Microsemi GE VSC8572 SyncE",
2324         .phy_id_mask    = 0xfffffff0,
2325         /* PHY_GBIT_FEATURES */
2326         .soft_reset     = &genphy_soft_reset,
2327         .config_init    = &vsc8584_config_init,
2328         .config_aneg    = &vsc85xx_config_aneg,
2329         .aneg_done      = &genphy_aneg_done,
2330         .read_status    = &vsc85xx_read_status,
2331         .handle_interrupt = &vsc8584_handle_interrupt,
2332         .ack_interrupt  = &vsc85xx_ack_interrupt,
2333         .config_intr    = &vsc85xx_config_intr,
2334         .did_interrupt  = &vsc8584_did_interrupt,
2335         .suspend        = &genphy_suspend,
2336         .resume         = &genphy_resume,
2337         .probe          = &vsc8574_probe,
2338         .set_wol        = &vsc85xx_wol_set,
2339         .get_wol        = &vsc85xx_wol_get,
2340         .get_tunable    = &vsc85xx_get_tunable,
2341         .set_tunable    = &vsc85xx_set_tunable,
2342         .read_page      = &vsc85xx_phy_read_page,
2343         .write_page     = &vsc85xx_phy_write_page,
2344         .get_sset_count = &vsc85xx_get_sset_count,
2345         .get_strings    = &vsc85xx_get_strings,
2346         .get_stats      = &vsc85xx_get_stats,
2347 },
2348 {
2349         .phy_id         = PHY_ID_VSC8574,
2350         .name           = "Microsemi GE VSC8574 SyncE",
2351         .phy_id_mask    = 0xfffffff0,
2352         /* PHY_GBIT_FEATURES */
2353         .soft_reset     = &genphy_soft_reset,
2354         .config_init    = &vsc8584_config_init,
2355         .config_aneg    = &vsc85xx_config_aneg,
2356         .aneg_done      = &genphy_aneg_done,
2357         .read_status    = &vsc85xx_read_status,
2358         .ack_interrupt  = &vsc85xx_ack_interrupt,
2359         .config_intr    = &vsc85xx_config_intr,
2360         .did_interrupt  = &vsc8584_did_interrupt,
2361         .suspend        = &genphy_suspend,
2362         .resume         = &genphy_resume,
2363         .probe          = &vsc8574_probe,
2364         .set_wol        = &vsc85xx_wol_set,
2365         .get_wol        = &vsc85xx_wol_get,
2366         .get_tunable    = &vsc85xx_get_tunable,
2367         .set_tunable    = &vsc85xx_set_tunable,
2368         .read_page      = &vsc85xx_phy_read_page,
2369         .write_page     = &vsc85xx_phy_write_page,
2370         .get_sset_count = &vsc85xx_get_sset_count,
2371         .get_strings    = &vsc85xx_get_strings,
2372         .get_stats      = &vsc85xx_get_stats,
2373 },
2374 {
2375         .phy_id         = PHY_ID_VSC8575,
2376         .name           = "Microsemi GE VSC8575 SyncE",
2377         .phy_id_mask    = 0xfffffff0,
2378         /* PHY_GBIT_FEATURES */
2379         .soft_reset     = &genphy_soft_reset,
2380         .config_init    = &vsc8584_config_init,
2381         .config_aneg    = &vsc85xx_config_aneg,
2382         .aneg_done      = &genphy_aneg_done,
2383         .read_status    = &vsc85xx_read_status,
2384         .handle_interrupt = &vsc8584_handle_interrupt,
2385         .ack_interrupt  = &vsc85xx_ack_interrupt,
2386         .config_intr    = &vsc85xx_config_intr,
2387         .did_interrupt  = &vsc8584_did_interrupt,
2388         .suspend        = &genphy_suspend,
2389         .resume         = &genphy_resume,
2390         .probe          = &vsc8584_probe,
2391         .get_tunable    = &vsc85xx_get_tunable,
2392         .set_tunable    = &vsc85xx_set_tunable,
2393         .read_page      = &vsc85xx_phy_read_page,
2394         .write_page     = &vsc85xx_phy_write_page,
2395         .get_sset_count = &vsc85xx_get_sset_count,
2396         .get_strings    = &vsc85xx_get_strings,
2397         .get_stats      = &vsc85xx_get_stats,
2398 },
2399 {
2400         .phy_id         = PHY_ID_VSC8582,
2401         .name           = "Microsemi GE VSC8582 SyncE",
2402         .phy_id_mask    = 0xfffffff0,
2403         /* PHY_GBIT_FEATURES */
2404         .soft_reset     = &genphy_soft_reset,
2405         .config_init    = &vsc8584_config_init,
2406         .config_aneg    = &vsc85xx_config_aneg,
2407         .aneg_done      = &genphy_aneg_done,
2408         .read_status    = &vsc85xx_read_status,
2409         .handle_interrupt = &vsc8584_handle_interrupt,
2410         .ack_interrupt  = &vsc85xx_ack_interrupt,
2411         .config_intr    = &vsc85xx_config_intr,
2412         .did_interrupt  = &vsc8584_did_interrupt,
2413         .suspend        = &genphy_suspend,
2414         .resume         = &genphy_resume,
2415         .probe          = &vsc8584_probe,
2416         .get_tunable    = &vsc85xx_get_tunable,
2417         .set_tunable    = &vsc85xx_set_tunable,
2418         .read_page      = &vsc85xx_phy_read_page,
2419         .write_page     = &vsc85xx_phy_write_page,
2420         .get_sset_count = &vsc85xx_get_sset_count,
2421         .get_strings    = &vsc85xx_get_strings,
2422         .get_stats      = &vsc85xx_get_stats,
2423 },
2424 {
2425         .phy_id         = PHY_ID_VSC8584,
2426         .name           = "Microsemi GE VSC8584 SyncE",
2427         .phy_id_mask    = 0xfffffff0,
2428         /* PHY_GBIT_FEATURES */
2429         .soft_reset     = &genphy_soft_reset,
2430         .config_init    = &vsc8584_config_init,
2431         .config_aneg    = &vsc85xx_config_aneg,
2432         .aneg_done      = &genphy_aneg_done,
2433         .read_status    = &vsc85xx_read_status,
2434         .handle_interrupt = &vsc8584_handle_interrupt,
2435         .ack_interrupt  = &vsc85xx_ack_interrupt,
2436         .config_intr    = &vsc85xx_config_intr,
2437         .did_interrupt  = &vsc8584_did_interrupt,
2438         .suspend        = &genphy_suspend,
2439         .resume         = &genphy_resume,
2440         .probe          = &vsc8584_probe,
2441         .get_tunable    = &vsc85xx_get_tunable,
2442         .set_tunable    = &vsc85xx_set_tunable,
2443         .read_page      = &vsc85xx_phy_read_page,
2444         .write_page     = &vsc85xx_phy_write_page,
2445         .get_sset_count = &vsc85xx_get_sset_count,
2446         .get_strings    = &vsc85xx_get_strings,
2447         .get_stats      = &vsc85xx_get_stats,
2448         .link_change_notify = &vsc85xx_link_change_notify,
2449 }
2450
2451 };
2452
2453 module_phy_driver(vsc85xx_driver);
2454
2455 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2456         { PHY_ID_VSC8504, 0xfffffff0, },
2457         { PHY_ID_VSC8514, 0xfffffff0, },
2458         { PHY_ID_VSC8530, 0xfffffff0, },
2459         { PHY_ID_VSC8531, 0xfffffff0, },
2460         { PHY_ID_VSC8540, 0xfffffff0, },
2461         { PHY_ID_VSC8541, 0xfffffff0, },
2462         { PHY_ID_VSC8552, 0xfffffff0, },
2463         { PHY_ID_VSC856X, 0xfffffff0, },
2464         { PHY_ID_VSC8572, 0xfffffff0, },
2465         { PHY_ID_VSC8574, 0xfffffff0, },
2466         { PHY_ID_VSC8575, 0xfffffff0, },
2467         { PHY_ID_VSC8582, 0xfffffff0, },
2468         { PHY_ID_VSC8584, 0xfffffff0, },
2469         { }
2470 };
2471
2472 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2473
2474 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2475 MODULE_AUTHOR("Nagaraju Lakkaraju");
2476 MODULE_LICENSE("Dual MIT/GPL");