2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
32 /* Operation Mode Strap Override */
33 #define MII_KSZPHY_OMSO 0x16
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
76 struct kszphy_hw_stat {
82 static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
89 u16 interrupt_level_mask;
90 bool has_broadcast_disable;
91 bool has_nand_tree_disable;
92 bool has_rmii_ref_clk_sel;
96 const struct kszphy_type *type;
98 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
103 static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
105 .has_broadcast_disable = true,
106 .has_nand_tree_disable = true,
107 .has_rmii_ref_clk_sel = true,
110 static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
114 static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
116 .has_nand_tree_disable = true,
119 static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
121 .has_broadcast_disable = true,
122 .has_nand_tree_disable = true,
123 .has_rmii_ref_clk_sel = true,
126 static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
130 static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
134 static int kszphy_extended_write(struct phy_device *phydev,
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
141 static int kszphy_extended_read(struct phy_device *phydev,
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
148 static int kszphy_ack_interrupt(struct phy_device *phydev)
150 /* bit[7..0] int status, which is a read and clear register. */
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
155 return (rc < 0) ? rc : 0;
158 static int kszphy_config_intr(struct phy_device *phydev)
160 const struct kszphy_type *type = phydev->drv->driver_data;
164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
206 case MII_KSZPHY_CTRL_1:
209 case MII_KSZPHY_CTRL_2:
216 temp = phy_read(phydev, reg);
222 temp &= ~(3 << shift);
223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
227 phydev_err(phydev, "failed to set led mode\n");
232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
235 static int kszphy_broadcast_disable(struct phy_device *phydev)
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
246 phydev_err(phydev, "failed to disable broadcast address\n");
251 static int kszphy_nand_tree_disable(struct phy_device *phydev)
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
266 phydev_err(phydev, "failed to disable NAND tree mode\n");
271 static int kszphy_config_init(struct phy_device *phydev)
273 struct kszphy_priv *priv = phydev->priv;
274 const struct kszphy_type *type;
282 if (type->has_broadcast_disable)
283 kszphy_broadcast_disable(phydev);
285 if (type->has_nand_tree_disable)
286 kszphy_nand_tree_disable(phydev);
288 if (priv->rmii_ref_clk_sel) {
289 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
292 "failed to set rmii reference clock\n");
297 if (priv->led_mode >= 0)
298 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
300 if (phy_interrupt_is_valid(phydev)) {
301 int ctl = phy_read(phydev, MII_BMCR);
306 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
314 static int ksz9021_load_values_from_of(struct phy_device *phydev,
315 const struct device_node *of_node,
317 const char *field1, const char *field2,
318 const char *field3, const char *field4)
327 if (!of_property_read_u32(of_node, field1, &val1))
330 if (!of_property_read_u32(of_node, field2, &val2))
333 if (!of_property_read_u32(of_node, field3, &val3))
336 if (!of_property_read_u32(of_node, field4, &val4))
343 newval = kszphy_extended_read(phydev, reg);
348 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
351 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
354 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
357 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
359 return kszphy_extended_write(phydev, reg, newval);
362 static int ksz9021_config_init(struct phy_device *phydev)
364 const struct device *dev = &phydev->mdio.dev;
365 const struct device_node *of_node = dev->of_node;
366 const struct device *dev_walker;
368 /* The Micrel driver has a deprecated option to place phy OF
369 * properties in the MAC node. Walk up the tree of devices to
370 * find a device with an OF node.
372 dev_walker = &phydev->mdio.dev;
374 of_node = dev_walker->of_node;
375 dev_walker = dev_walker->parent;
377 } while (!of_node && dev_walker);
380 ksz9021_load_values_from_of(phydev, of_node,
381 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
382 "txen-skew-ps", "txc-skew-ps",
383 "rxdv-skew-ps", "rxc-skew-ps");
384 ksz9021_load_values_from_of(phydev, of_node,
385 MII_KSZPHY_RX_DATA_PAD_SKEW,
386 "rxd0-skew-ps", "rxd1-skew-ps",
387 "rxd2-skew-ps", "rxd3-skew-ps");
388 ksz9021_load_values_from_of(phydev, of_node,
389 MII_KSZPHY_TX_DATA_PAD_SKEW,
390 "txd0-skew-ps", "txd1-skew-ps",
391 "txd2-skew-ps", "txd3-skew-ps");
396 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
397 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
399 #define KSZ9031_PS_TO_REG 60
401 /* Extended registers */
402 /* MMD Address 0x0 */
403 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
404 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
406 /* MMD Address 0x2 */
407 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
408 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
409 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
410 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
412 static int ksz9031_extended_write(struct phy_device *phydev,
413 u8 mode, u32 dev_addr, u32 regnum, u16 val)
415 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
416 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
417 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
418 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
421 static int ksz9031_extended_read(struct phy_device *phydev,
422 u8 mode, u32 dev_addr, u32 regnum)
424 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
425 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
426 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
427 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
430 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
431 const struct device_node *of_node,
432 u16 reg, size_t field_sz,
433 const char *field[], u8 numfields)
435 int val[4] = {-1, -2, -3, -4};
442 for (i = 0; i < numfields; i++)
443 if (!of_property_read_u32(of_node, field[i], val + i))
449 if (matches < numfields)
450 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
454 maxval = (field_sz == 4) ? 0xf : 0x1f;
455 for (i = 0; i < numfields; i++)
456 if (val[i] != -(i + 1)) {
458 mask ^= maxval << (field_sz * i);
459 newval = (newval & mask) |
460 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
464 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
467 static int ksz9031_center_flp_timing(struct phy_device *phydev)
471 /* Center KSZ9031RNX FLP timing at 16ms. */
472 result = ksz9031_extended_write(phydev, OP_DATA, 0,
473 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
474 result = ksz9031_extended_write(phydev, OP_DATA, 0,
475 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
480 return genphy_restart_aneg(phydev);
483 static int ksz9031_config_init(struct phy_device *phydev)
485 const struct device *dev = &phydev->mdio.dev;
486 const struct device_node *of_node = dev->of_node;
487 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
488 static const char *rx_data_skews[4] = {
489 "rxd0-skew-ps", "rxd1-skew-ps",
490 "rxd2-skew-ps", "rxd3-skew-ps"
492 static const char *tx_data_skews[4] = {
493 "txd0-skew-ps", "txd1-skew-ps",
494 "txd2-skew-ps", "txd3-skew-ps"
496 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
497 const struct device *dev_walker;
499 /* The Micrel driver has a deprecated option to place phy OF
500 * properties in the MAC node. Walk up the tree of devices to
501 * find a device with an OF node.
503 dev_walker = &phydev->mdio.dev;
505 of_node = dev_walker->of_node;
506 dev_walker = dev_walker->parent;
507 } while (!of_node && dev_walker);
510 ksz9031_of_load_skew_values(phydev, of_node,
511 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
514 ksz9031_of_load_skew_values(phydev, of_node,
515 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
518 ksz9031_of_load_skew_values(phydev, of_node,
519 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
522 ksz9031_of_load_skew_values(phydev, of_node,
523 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
527 return ksz9031_center_flp_timing(phydev);
530 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
531 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
532 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
533 static int ksz8873mll_read_status(struct phy_device *phydev)
538 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
540 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
542 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
543 phydev->duplex = DUPLEX_HALF;
545 phydev->duplex = DUPLEX_FULL;
547 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
548 phydev->speed = SPEED_10;
550 phydev->speed = SPEED_100;
553 phydev->pause = phydev->asym_pause = 0;
558 static int ksz9031_read_status(struct phy_device *phydev)
563 err = genphy_read_status(phydev);
567 /* Make sure the PHY is not broken. Read idle error count,
568 * and reset the PHY if it is maxed out.
570 regval = phy_read(phydev, MII_STAT1000);
571 if ((regval & 0xFF) == 0xFF) {
579 static int ksz8873mll_config_aneg(struct phy_device *phydev)
584 /* This routine returns -1 as an indication to the caller that the
585 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
586 * MMD extended PHY registers.
589 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
595 /* This routine does nothing since the Micrel ksz9021 does not support
596 * standard IEEE MMD extended PHY registers.
599 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
604 static int kszphy_get_sset_count(struct phy_device *phydev)
606 return ARRAY_SIZE(kszphy_hw_stats);
609 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
613 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
614 memcpy(data + i * ETH_GSTRING_LEN,
615 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
620 #define UINT64_MAX (u64)(~((u64)0))
622 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
624 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
625 struct kszphy_priv *priv = phydev->priv;
628 val = phy_read(phydev, stat.reg);
632 val = val & ((1 << stat.bits) - 1);
633 priv->stats[i] += val;
634 val = priv->stats[i];
640 static void kszphy_get_stats(struct phy_device *phydev,
641 struct ethtool_stats *stats, u64 *data)
645 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
646 data[i] = kszphy_get_stat(phydev, i);
649 static int kszphy_resume(struct phy_device *phydev)
653 mutex_lock(&phydev->lock);
655 value = phy_read(phydev, MII_BMCR);
656 phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
658 kszphy_config_intr(phydev);
659 mutex_unlock(&phydev->lock);
664 static int kszphy_probe(struct phy_device *phydev)
666 const struct kszphy_type *type = phydev->drv->driver_data;
667 const struct device_node *np = phydev->mdio.dev.of_node;
668 struct kszphy_priv *priv;
672 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
680 if (type->led_mode_reg) {
681 ret = of_property_read_u32(np, "micrel,led-mode",
686 if (priv->led_mode > 3) {
687 phydev_err(phydev, "invalid led mode: 0x%02x\n",
695 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
696 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
697 if (!IS_ERR_OR_NULL(clk)) {
698 unsigned long rate = clk_get_rate(clk);
699 bool rmii_ref_clk_sel_25_mhz;
701 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
702 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
703 "micrel,rmii-reference-clock-select-25-mhz");
705 if (rate > 24500000 && rate < 25500000) {
706 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
707 } else if (rate > 49500000 && rate < 50500000) {
708 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
710 phydev_err(phydev, "Clock rate out of range: %ld\n",
716 /* Support legacy board-file configuration */
717 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
718 priv->rmii_ref_clk_sel = true;
719 priv->rmii_ref_clk_sel_val = true;
725 static struct phy_driver ksphy_driver[] = {
727 .phy_id = PHY_ID_KS8737,
728 .phy_id_mask = 0x00fffff0,
729 .name = "Micrel KS8737",
730 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
731 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
732 .driver_data = &ks8737_type,
733 .config_init = kszphy_config_init,
734 .config_aneg = genphy_config_aneg,
735 .read_status = genphy_read_status,
736 .ack_interrupt = kszphy_ack_interrupt,
737 .config_intr = kszphy_config_intr,
738 .get_sset_count = kszphy_get_sset_count,
739 .get_strings = kszphy_get_strings,
740 .get_stats = kszphy_get_stats,
741 .suspend = genphy_suspend,
742 .resume = genphy_resume,
744 .phy_id = PHY_ID_KSZ8021,
745 .phy_id_mask = 0x00ffffff,
746 .name = "Micrel KSZ8021 or KSZ8031",
747 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
748 SUPPORTED_Asym_Pause),
749 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
750 .driver_data = &ksz8021_type,
751 .probe = kszphy_probe,
752 .config_init = kszphy_config_init,
753 .config_aneg = genphy_config_aneg,
754 .read_status = genphy_read_status,
755 .ack_interrupt = kszphy_ack_interrupt,
756 .config_intr = kszphy_config_intr,
757 .get_sset_count = kszphy_get_sset_count,
758 .get_strings = kszphy_get_strings,
759 .get_stats = kszphy_get_stats,
760 .suspend = genphy_suspend,
761 .resume = genphy_resume,
763 .phy_id = PHY_ID_KSZ8031,
764 .phy_id_mask = 0x00ffffff,
765 .name = "Micrel KSZ8031",
766 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
767 SUPPORTED_Asym_Pause),
768 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
769 .driver_data = &ksz8021_type,
770 .probe = kszphy_probe,
771 .config_init = kszphy_config_init,
772 .config_aneg = genphy_config_aneg,
773 .read_status = genphy_read_status,
774 .ack_interrupt = kszphy_ack_interrupt,
775 .config_intr = kszphy_config_intr,
776 .get_sset_count = kszphy_get_sset_count,
777 .get_strings = kszphy_get_strings,
778 .get_stats = kszphy_get_stats,
779 .suspend = genphy_suspend,
780 .resume = genphy_resume,
782 .phy_id = PHY_ID_KSZ8041,
783 .phy_id_mask = 0x00fffff0,
784 .name = "Micrel KSZ8041",
785 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
786 | SUPPORTED_Asym_Pause),
787 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
788 .driver_data = &ksz8041_type,
789 .probe = kszphy_probe,
790 .config_init = kszphy_config_init,
791 .config_aneg = genphy_config_aneg,
792 .read_status = genphy_read_status,
793 .ack_interrupt = kszphy_ack_interrupt,
794 .config_intr = kszphy_config_intr,
795 .get_sset_count = kszphy_get_sset_count,
796 .get_strings = kszphy_get_strings,
797 .get_stats = kszphy_get_stats,
798 .suspend = genphy_suspend,
799 .resume = genphy_resume,
801 .phy_id = PHY_ID_KSZ8041RNLI,
802 .phy_id_mask = 0x00fffff0,
803 .name = "Micrel KSZ8041RNLI",
804 .features = PHY_BASIC_FEATURES |
805 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
806 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
807 .driver_data = &ksz8041_type,
808 .probe = kszphy_probe,
809 .config_init = kszphy_config_init,
810 .config_aneg = genphy_config_aneg,
811 .read_status = genphy_read_status,
812 .ack_interrupt = kszphy_ack_interrupt,
813 .config_intr = kszphy_config_intr,
814 .get_sset_count = kszphy_get_sset_count,
815 .get_strings = kszphy_get_strings,
816 .get_stats = kszphy_get_stats,
817 .suspend = genphy_suspend,
818 .resume = genphy_resume,
820 .phy_id = PHY_ID_KSZ8051,
821 .phy_id_mask = 0x00fffff0,
822 .name = "Micrel KSZ8051",
823 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
824 | SUPPORTED_Asym_Pause),
825 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
826 .driver_data = &ksz8051_type,
827 .probe = kszphy_probe,
828 .config_init = kszphy_config_init,
829 .config_aneg = genphy_config_aneg,
830 .read_status = genphy_read_status,
831 .ack_interrupt = kszphy_ack_interrupt,
832 .config_intr = kszphy_config_intr,
833 .get_sset_count = kszphy_get_sset_count,
834 .get_strings = kszphy_get_strings,
835 .get_stats = kszphy_get_stats,
836 .suspend = genphy_suspend,
837 .resume = genphy_resume,
839 .phy_id = PHY_ID_KSZ8001,
840 .name = "Micrel KSZ8001 or KS8721",
841 .phy_id_mask = 0x00ffffff,
842 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
843 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
844 .driver_data = &ksz8041_type,
845 .probe = kszphy_probe,
846 .config_init = kszphy_config_init,
847 .config_aneg = genphy_config_aneg,
848 .read_status = genphy_read_status,
849 .ack_interrupt = kszphy_ack_interrupt,
850 .config_intr = kszphy_config_intr,
851 .get_sset_count = kszphy_get_sset_count,
852 .get_strings = kszphy_get_strings,
853 .get_stats = kszphy_get_stats,
854 .suspend = genphy_suspend,
855 .resume = genphy_resume,
857 .phy_id = PHY_ID_KSZ8081,
858 .name = "Micrel KSZ8081 or KSZ8091",
859 .phy_id_mask = 0x00fffff0,
860 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
861 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
862 .driver_data = &ksz8081_type,
863 .probe = kszphy_probe,
864 .config_init = kszphy_config_init,
865 .config_aneg = genphy_config_aneg,
866 .read_status = genphy_read_status,
867 .ack_interrupt = kszphy_ack_interrupt,
868 .config_intr = kszphy_config_intr,
869 .get_sset_count = kszphy_get_sset_count,
870 .get_strings = kszphy_get_strings,
871 .get_stats = kszphy_get_stats,
872 .suspend = genphy_suspend,
873 .resume = kszphy_resume,
875 .phy_id = PHY_ID_KSZ8061,
876 .name = "Micrel KSZ8061",
877 .phy_id_mask = 0x00fffff0,
878 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
879 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
880 .config_init = kszphy_config_init,
881 .config_aneg = genphy_config_aneg,
882 .read_status = genphy_read_status,
883 .ack_interrupt = kszphy_ack_interrupt,
884 .config_intr = kszphy_config_intr,
885 .get_sset_count = kszphy_get_sset_count,
886 .get_strings = kszphy_get_strings,
887 .get_stats = kszphy_get_stats,
888 .suspend = genphy_suspend,
889 .resume = genphy_resume,
891 .phy_id = PHY_ID_KSZ9021,
892 .phy_id_mask = 0x000ffffe,
893 .name = "Micrel KSZ9021 Gigabit PHY",
894 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
895 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
896 .driver_data = &ksz9021_type,
897 .config_init = ksz9021_config_init,
898 .config_aneg = genphy_config_aneg,
899 .read_status = genphy_read_status,
900 .ack_interrupt = kszphy_ack_interrupt,
901 .config_intr = kszphy_config_intr,
902 .get_sset_count = kszphy_get_sset_count,
903 .get_strings = kszphy_get_strings,
904 .get_stats = kszphy_get_stats,
905 .suspend = genphy_suspend,
906 .resume = genphy_resume,
907 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
908 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
910 .phy_id = PHY_ID_KSZ9031,
911 .phy_id_mask = 0x00fffff0,
912 .name = "Micrel KSZ9031 Gigabit PHY",
913 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
914 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
915 .driver_data = &ksz9021_type,
916 .config_init = ksz9031_config_init,
917 .config_aneg = genphy_config_aneg,
918 .read_status = ksz9031_read_status,
919 .ack_interrupt = kszphy_ack_interrupt,
920 .config_intr = kszphy_config_intr,
921 .get_sset_count = kszphy_get_sset_count,
922 .get_strings = kszphy_get_strings,
923 .get_stats = kszphy_get_stats,
924 .suspend = genphy_suspend,
925 .resume = genphy_resume,
927 .phy_id = PHY_ID_KSZ8873MLL,
928 .phy_id_mask = 0x00fffff0,
929 .name = "Micrel KSZ8873MLL Switch",
930 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
931 .flags = PHY_HAS_MAGICANEG,
932 .config_init = kszphy_config_init,
933 .config_aneg = ksz8873mll_config_aneg,
934 .read_status = ksz8873mll_read_status,
935 .get_sset_count = kszphy_get_sset_count,
936 .get_strings = kszphy_get_strings,
937 .get_stats = kszphy_get_stats,
938 .suspend = genphy_suspend,
939 .resume = genphy_resume,
941 .phy_id = PHY_ID_KSZ886X,
942 .phy_id_mask = 0x00fffff0,
943 .name = "Micrel KSZ886X Switch",
944 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
945 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
946 .config_init = kszphy_config_init,
947 .config_aneg = genphy_config_aneg,
948 .read_status = genphy_read_status,
949 .get_sset_count = kszphy_get_sset_count,
950 .get_strings = kszphy_get_strings,
951 .get_stats = kszphy_get_stats,
952 .suspend = genphy_suspend,
953 .resume = genphy_resume,
956 module_phy_driver(ksphy_driver);
958 MODULE_DESCRIPTION("Micrel PHY driver");
959 MODULE_AUTHOR("David J. Choi");
960 MODULE_LICENSE("GPL");
962 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
963 { PHY_ID_KSZ9021, 0x000ffffe },
964 { PHY_ID_KSZ9031, 0x00fffff0 },
965 { PHY_ID_KSZ8001, 0x00ffffff },
966 { PHY_ID_KS8737, 0x00fffff0 },
967 { PHY_ID_KSZ8021, 0x00ffffff },
968 { PHY_ID_KSZ8031, 0x00ffffff },
969 { PHY_ID_KSZ8041, 0x00fffff0 },
970 { PHY_ID_KSZ8051, 0x00fffff0 },
971 { PHY_ID_KSZ8061, 0x00fffff0 },
972 { PHY_ID_KSZ8081, 0x00fffff0 },
973 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
974 { PHY_ID_KSZ886X, 0x00fffff0 },
978 MODULE_DEVICE_TABLE(mdio, micrel_tbl);