1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson GXL Internal PHY Driver
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
7 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/phy.h>
14 #include <linux/netdevice.h>
15 #include <linux/bitfield.h>
18 #define TSTCNTL_READ BIT(15)
19 #define TSTCNTL_WRITE BIT(14)
20 #define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)
21 #define TSTCNTL_TEST_MODE BIT(10)
22 #define TSTCNTL_READ_ADDRESS GENMASK(9, 5)
23 #define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
26 #define INTSRC_FLAG 29
27 #define INTSRC_ANEG_PR BIT(1)
28 #define INTSRC_PARALLEL_FAULT BIT(2)
29 #define INTSRC_ANEG_LP_ACK BIT(3)
30 #define INTSRC_LINK_DOWN BIT(4)
31 #define INTSRC_REMOTE_FAULT BIT(5)
32 #define INTSRC_ANEG_COMPLETE BIT(6)
33 #define INTSRC_ENERGY_DETECT BIT(7)
34 #define INTSRC_MASK 30
36 #define INT_SOURCES (INTSRC_LINK_DOWN | INTSRC_ANEG_COMPLETE | \
39 #define BANK_ANALOG_DSP 0
44 #define LPI_STATUS 0xc
45 #define LPI_STATUS_RSV12 BIT(12)
48 #define FR_PLL_CONTROL 0x1b
49 #define FR_PLL_DIV0 0x1c
50 #define FR_PLL_DIV1 0x1d
52 static int meson_gxl_open_banks(struct phy_device *phydev)
56 /* Enable Analog and DSP register Bank access by
57 * toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register
59 ret = phy_write(phydev, TSTCNTL, 0);
62 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
65 ret = phy_write(phydev, TSTCNTL, 0);
68 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
71 static void meson_gxl_close_banks(struct phy_device *phydev)
73 phy_write(phydev, TSTCNTL, 0);
76 static int meson_gxl_read_reg(struct phy_device *phydev,
77 unsigned int bank, unsigned int reg)
81 ret = meson_gxl_open_banks(phydev);
85 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ |
86 FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
88 FIELD_PREP(TSTCNTL_READ_ADDRESS, reg));
92 ret = phy_read(phydev, TSTREAD1);
94 /* Close the bank access on our way out */
95 meson_gxl_close_banks(phydev);
99 static int meson_gxl_write_reg(struct phy_device *phydev,
100 unsigned int bank, unsigned int reg,
105 ret = meson_gxl_open_banks(phydev);
109 ret = phy_write(phydev, TSTWRITE, value);
113 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE |
114 FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
116 FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg));
119 /* Close the bank access on our way out */
120 meson_gxl_close_banks(phydev);
124 static int meson_gxl_config_init(struct phy_device *phydev)
128 /* Enable fractional PLL */
129 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5);
133 /* Program fraction FR_PLL_DIV1 */
134 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a);
138 /* Program fraction FR_PLL_DIV1 */
139 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa);
146 /* This function is provided to cope with the possible failures of this phy
147 * during aneg process. When aneg fails, the PHY reports that aneg is done
148 * but the value found in MII_LPA is wrong:
149 * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
150 * the link partner (LP) supports aneg but the LP never acked our base
151 * code word, it is likely that we never sent it to begin with.
152 * - Late failures: MII_LPA is filled with a value which seems to make sense
153 * but it actually is not what the LP is advertising. It seems that we
154 * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
155 * If this particular bit is not set when aneg is reported being done,
156 * it means MII_LPA is likely to be wrong.
158 * In both case, forcing a restart of the aneg process solve the problem.
159 * When this failure happens, the first retry is usually successful but,
160 * in some cases, it may take up to 6 retries to get a decent result
162 static int meson_gxl_read_status(struct phy_device *phydev)
164 int ret, wol, lpa, exp;
166 if (phydev->autoneg == AUTONEG_ENABLE) {
167 ret = genphy_aneg_done(phydev);
171 goto read_status_continue;
173 /* Aneg is done, let's check everything is fine */
174 wol = meson_gxl_read_reg(phydev, BANK_WOL, LPI_STATUS);
178 lpa = phy_read(phydev, MII_LPA);
182 exp = phy_read(phydev, MII_EXPANSION);
186 if (!(wol & LPI_STATUS_RSV12) ||
187 ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
188 /* Looks like aneg failed after all */
189 phydev_dbg(phydev, "LPA corruption - aneg restart\n");
190 return genphy_restart_aneg(phydev);
194 read_status_continue:
195 return genphy_read_status(phydev);
198 static int meson_gxl_ack_interrupt(struct phy_device *phydev)
200 int ret = phy_read(phydev, INTSRC_FLAG);
202 return ret < 0 ? ret : 0;
205 static int meson_gxl_config_intr(struct phy_device *phydev)
209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
210 /* Ack any pending IRQ */
211 ret = meson_gxl_ack_interrupt(phydev);
215 ret = phy_write(phydev, INTSRC_MASK, INT_SOURCES);
217 ret = phy_write(phydev, INTSRC_MASK, 0);
219 /* Ack any pending IRQ */
220 ret = meson_gxl_ack_interrupt(phydev);
226 static irqreturn_t meson_gxl_handle_interrupt(struct phy_device *phydev)
230 irq_status = phy_read(phydev, INTSRC_FLAG);
231 if (irq_status < 0) {
236 irq_status &= INT_SOURCES;
241 /* Aneg-complete interrupt is used for link-up detection */
242 if (phydev->autoneg == AUTONEG_ENABLE &&
243 irq_status == INTSRC_ENERGY_DETECT)
246 phy_trigger_machine(phydev);
251 static struct phy_driver meson_gxl_phy[] = {
253 PHY_ID_MATCH_EXACT(0x01814400),
254 .name = "Meson GXL Internal PHY",
255 /* PHY_BASIC_FEATURES */
256 .flags = PHY_IS_INTERNAL,
257 .soft_reset = genphy_soft_reset,
258 .config_init = meson_gxl_config_init,
259 .read_status = meson_gxl_read_status,
260 .config_intr = meson_gxl_config_intr,
261 .handle_interrupt = meson_gxl_handle_interrupt,
262 .suspend = genphy_suspend,
263 .resume = genphy_resume,
265 PHY_ID_MATCH_EXACT(0x01803301),
266 .name = "Meson G12A Internal PHY",
267 /* PHY_BASIC_FEATURES */
268 .flags = PHY_IS_INTERNAL,
269 .soft_reset = genphy_soft_reset,
270 .config_intr = meson_gxl_config_intr,
271 .handle_interrupt = meson_gxl_handle_interrupt,
272 .suspend = genphy_suspend,
273 .resume = genphy_resume,
277 static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
278 { PHY_ID_MATCH_VENDOR(0x01814400) },
279 { PHY_ID_MATCH_VENDOR(0x01803301) },
283 module_phy_driver(meson_gxl_phy);
285 MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
287 MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
288 MODULE_AUTHOR("Baoqi wang");
289 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
290 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
291 MODULE_LICENSE("GPL");