1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
16 * With XAUI, observation shows:
18 * XAUI PHYXS -- <appropriate PCS as above>
20 * and no switching of the host interface mode occurs.
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
25 #include <linux/bitfield.h>
26 #include <linux/ctype.h>
27 #include <linux/delay.h>
28 #include <linux/hwmon.h>
29 #include <linux/marvell_phy.h>
30 #include <linux/phy.h>
31 #include <linux/sfp.h>
32 #include <linux/netdevice.h>
34 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
35 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
37 #define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
40 MV_PMA_FW_VER0 = 0xc011,
41 MV_PMA_FW_VER1 = 0xc012,
42 MV_PMA_21X0_PORT_CTRL = 0xc04a,
43 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
44 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
46 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
47 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
48 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
49 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
50 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
52 MV_PMA_BOOT_FATAL = BIT(0),
54 MV_PCS_BASE_T = 0x0000,
55 MV_PCS_BASE_R = 0x1000,
56 MV_PCS_1000BASEX = 0x2000,
58 MV_PCS_CSCR1 = 0x8000,
59 MV_PCS_CSCR1_ED_MASK = 0x0300,
60 MV_PCS_CSCR1_ED_OFF = 0x0000,
61 MV_PCS_CSCR1_ED_RX = 0x0200,
62 MV_PCS_CSCR1_ED_NLP = 0x0300,
63 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
64 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
65 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
66 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
69 MV_PCS_DSC1_ENABLE = BIT(9),
70 MV_PCS_DSC1_10GBT = 0x01c0,
71 MV_PCS_DSC1_1GBR = 0x0038,
72 MV_PCS_DSC1_100BTX = 0x0007,
74 MV_PCS_DSC2_2P5G = 0xf000,
75 MV_PCS_DSC2_5G = 0x0f00,
77 MV_PCS_CSSR1 = 0x8008,
78 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
79 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
80 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
81 MV_PCS_CSSR1_SPD1_100 = 0x4000,
82 MV_PCS_CSSR1_SPD1_10 = 0x0000,
83 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
84 MV_PCS_CSSR1_RESOLVED = BIT(11),
85 MV_PCS_CSSR1_MDIX = BIT(6),
86 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
87 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
88 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
89 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
91 /* Temperature read register (88E2110 only) */
94 /* Number of ports on the device */
95 MV_PCS_PORT_INFO = 0xd00d,
96 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
97 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
99 /* SerDes reinitialization 88E21X0 */
100 MV_AN_21X0_SERDES_CTRL2 = 0x800f,
101 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
102 MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
105 * registers appear to set themselves to the 0x800X when AN is
106 * restarted, but status registers appear readable from either.
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
111 /* Vendor2 MMD registers */
112 MV_V2_PORT_CTRL = 0xf001,
113 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
114 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
115 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
116 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
117 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
118 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
119 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
120 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
121 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
122 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
123 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
124 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
125 MV_V2_PORT_INTR_STS = 0xf040,
126 MV_V2_PORT_INTR_MASK = 0xf043,
127 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
128 MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
129 MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
130 MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
131 /* Wake on LAN registers */
132 MV_V2_WOL_CTRL = 0xf06e,
133 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
134 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
135 /* Temperature control/read registers (88X3310 only) */
136 MV_V2_TEMP_CTRL = 0xf08a,
137 MV_V2_TEMP_CTRL_MASK = 0xc000,
138 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
139 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
141 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
145 bool (*has_downshift)(struct phy_device *phydev);
146 void (*init_supported_interfaces)(unsigned long *mask);
147 int (*get_mactype)(struct phy_device *phydev);
148 int (*set_mactype)(struct phy_device *phydev, int mactype);
149 int (*select_mactype)(unsigned long *interfaces);
150 int (*init_interface)(struct phy_device *phydev, int mactype);
153 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
158 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
163 phy_interface_t const_interface;
165 struct device *hwmon_dev;
169 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
171 return phydev->drv->driver_data;
175 static umode_t mv3310_hwmon_is_visible(const void *data,
176 enum hwmon_sensor_types type,
177 u32 attr, int channel)
179 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
181 if (type == hwmon_temp && attr == hwmon_temp_input)
186 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
188 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
191 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
193 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
196 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
197 u32 attr, int channel, long *value)
199 struct phy_device *phydev = dev_get_drvdata(dev);
200 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
203 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
204 *value = MSEC_PER_SEC;
208 if (type == hwmon_temp && attr == hwmon_temp_input) {
209 temp = chip->hwmon_read_temp_reg(phydev);
213 *value = ((temp & 0xff) - 75) * 1000;
221 static const struct hwmon_ops mv3310_hwmon_ops = {
222 .is_visible = mv3310_hwmon_is_visible,
223 .read = mv3310_hwmon_read,
226 static u32 mv3310_hwmon_chip_config[] = {
227 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
231 static const struct hwmon_channel_info mv3310_hwmon_chip = {
233 .config = mv3310_hwmon_chip_config,
236 static u32 mv3310_hwmon_temp_config[] = {
241 static const struct hwmon_channel_info mv3310_hwmon_temp = {
243 .config = mv3310_hwmon_temp_config,
246 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
252 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
253 .ops = &mv3310_hwmon_ops,
254 .info = mv3310_hwmon_info,
257 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
262 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
270 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
272 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
273 MV_V2_TEMP_CTRL_MASK, val);
276 static int mv3310_hwmon_probe(struct phy_device *phydev)
278 struct device *dev = &phydev->mdio.dev;
279 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
282 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
283 if (!priv->hwmon_name)
286 for (i = j = 0; priv->hwmon_name[i]; i++) {
287 if (isalnum(priv->hwmon_name[i])) {
289 priv->hwmon_name[j] = priv->hwmon_name[i];
293 priv->hwmon_name[j] = '\0';
295 ret = mv3310_hwmon_config(phydev, true);
299 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
300 priv->hwmon_name, phydev,
301 &mv3310_hwmon_chip_info, NULL);
303 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
306 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
311 static int mv3310_hwmon_probe(struct phy_device *phydev)
317 static int mv3310_power_down(struct phy_device *phydev)
319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
320 MV_V2_PORT_CTRL_PWRDOWN);
323 static int mv3310_power_up(struct phy_device *phydev)
325 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
329 MV_V2_PORT_CTRL_PWRDOWN);
331 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
332 priv->firmware_ver < 0x00030000)
335 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
336 MV_V2_33X0_PORT_CTRL_SWRST);
339 static int mv3310_reset(struct phy_device *phydev, u32 unit)
343 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
344 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
348 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
349 unit + MDIO_CTRL1, val,
350 !(val & MDIO_CTRL1_RESET),
354 static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
356 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
359 if (!priv->has_downshift)
362 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
366 if (val & MV_PCS_DSC1_ENABLE)
367 /* assume that all fields are the same */
368 *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val);
370 *ds = DOWNSHIFT_DEV_DISABLE;
375 static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
377 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
381 if (!priv->has_downshift)
384 if (ds == DOWNSHIFT_DEV_DISABLE)
385 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
388 /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should
389 * set the default settings for the PHY. However, it is used for
390 * "ethtool --set-phy-tunable ethN downshift on". The intention is
391 * to enable downshift at a default number of retries. The default
392 * settings for 88x3310 are for two retries with downshift disabled.
393 * So let's use two retries with downshift enabled.
395 if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
402 val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
403 val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
404 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
405 MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
409 val = MV_PCS_DSC1_ENABLE;
410 val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
411 val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
412 val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
414 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
415 MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
416 MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
419 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
423 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
427 switch (val & MV_PCS_CSCR1_ED_MASK) {
428 case MV_PCS_CSCR1_ED_NLP:
431 case MV_PCS_CSCR1_ED_RX:
432 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
435 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
441 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
448 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
449 val = MV_PCS_CSCR1_ED_NLP;
452 case ETHTOOL_PHY_EDPD_NO_TX:
453 val = MV_PCS_CSCR1_ED_RX;
456 case ETHTOOL_PHY_EDPD_DISABLE:
457 val = MV_PCS_CSCR1_ED_OFF;
464 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
465 MV_PCS_CSCR1_ED_MASK, val);
467 err = mv3310_reset(phydev, MV_PCS_BASE_T);
472 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
474 struct phy_device *phydev = upstream;
475 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
476 DECLARE_PHY_INTERFACE_MASK(interfaces);
477 phy_interface_t iface;
479 sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
480 iface = sfp_select_interface(phydev->sfp_bus, support);
482 if (iface != PHY_INTERFACE_MODE_10GBASER) {
483 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
489 static const struct sfp_upstream_ops mv3310_sfp_ops = {
490 .attach = phy_sfp_attach,
491 .detach = phy_sfp_detach,
492 .module_insert = mv3310_sfp_insert,
495 static int mv3310_probe(struct phy_device *phydev)
497 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
498 struct mv3310_priv *priv;
499 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
502 if (!phydev->is_c45 ||
503 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
506 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
510 if (ret & MV_PMA_BOOT_FATAL) {
511 dev_warn(&phydev->mdio.dev,
512 "PHY failed to boot firmware, status=%04x\n", ret);
516 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
520 dev_set_drvdata(&phydev->mdio.dev, priv);
522 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
526 priv->firmware_ver = ret << 16;
528 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
532 priv->firmware_ver |= ret;
534 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
535 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
536 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
538 if (chip->has_downshift)
539 priv->has_downshift = chip->has_downshift(phydev);
541 /* Powering down the port when not in use saves about 600mW */
542 ret = mv3310_power_down(phydev);
546 ret = mv3310_hwmon_probe(phydev);
550 chip->init_supported_interfaces(priv->supported_interfaces);
552 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
555 static void mv3310_remove(struct phy_device *phydev)
557 mv3310_hwmon_config(phydev, false);
560 static int mv3310_suspend(struct phy_device *phydev)
562 return mv3310_power_down(phydev);
565 static int mv3310_resume(struct phy_device *phydev)
569 ret = mv3310_power_up(phydev);
573 return mv3310_hwmon_config(phydev, true);
576 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
577 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
578 * support 2.5GBASET and 5GBASET. For these models, we can still read their
579 * 2.5G/5G extended abilities register (1.21). We detect these models based on
580 * the PMA device identifier, with a mask matching models known to have this
583 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
585 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
588 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
589 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
590 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
593 static int mv2110_get_mactype(struct phy_device *phydev)
597 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
601 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
604 static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
608 mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
609 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
610 MV_PMA_21X0_PORT_CTRL_SWRST |
611 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
612 MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
616 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
617 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
618 MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
622 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
623 MV_AN_21X0_SERDES_CTRL2, val,
625 MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
630 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
631 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
634 static int mv2110_select_mactype(unsigned long *interfaces)
636 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
637 return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
638 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
639 !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
640 return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
641 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
642 return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
647 static int mv3310_get_mactype(struct phy_device *phydev)
651 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
655 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
658 static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
662 mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
663 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
664 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
669 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
670 MV_V2_33X0_PORT_CTRL_SWRST);
673 static int mv3310_select_mactype(unsigned long *interfaces)
675 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
676 return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
677 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
678 test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
679 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
680 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
681 test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
682 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
683 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
684 test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
685 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
686 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
687 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
688 else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
689 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
690 else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
691 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
692 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces))
693 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
698 static int mv2110_init_interface(struct phy_device *phydev, int mactype)
700 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
702 priv->rate_match = false;
704 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
705 priv->rate_match = true;
707 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
708 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
709 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
710 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
711 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
712 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
713 priv->const_interface = PHY_INTERFACE_MODE_NA;
720 static int mv3310_init_interface(struct phy_device *phydev, int mactype)
722 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
724 priv->rate_match = false;
726 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
727 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
728 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
729 priv->rate_match = true;
731 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
732 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
733 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
734 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
735 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
736 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
737 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
738 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
739 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
740 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
741 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
742 priv->const_interface = PHY_INTERFACE_MODE_XAUI;
749 static int mv3340_init_interface(struct phy_device *phydev, int mactype)
751 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
754 priv->rate_match = false;
756 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
757 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
759 err = mv3310_init_interface(phydev, mactype);
764 static int mv3310_config_init(struct phy_device *phydev)
766 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
767 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
770 /* Check that the PHY interface type is compatible */
771 if (!test_bit(phydev->interface, priv->supported_interfaces))
774 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
776 /* Power up so reset works */
777 err = mv3310_power_up(phydev);
781 /* If host provided host supported interface modes, try to select the
784 if (!phy_interface_empty(phydev->host_interfaces)) {
785 mactype = chip->select_mactype(phydev->host_interfaces);
787 phydev_info(phydev, "Changing MACTYPE to %i\n",
789 err = chip->set_mactype(phydev, mactype);
795 mactype = chip->get_mactype(phydev);
799 err = chip->init_interface(phydev, mactype);
801 phydev_err(phydev, "MACTYPE configuration invalid\n");
805 /* Enable EDPD mode - saving 600mW */
806 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
810 /* Allow downshift */
811 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
812 if (err && err != -EOPNOTSUPP)
818 static int mv3310_get_features(struct phy_device *phydev)
822 ret = genphy_c45_pma_read_abilities(phydev);
826 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
827 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
828 MDIO_PMA_NG_EXTABLE);
832 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
834 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
836 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
838 val & MDIO_PMA_NG_EXTABLE_5GBT);
844 static int mv3310_config_mdix(struct phy_device *phydev)
849 switch (phydev->mdix_ctrl) {
850 case ETH_TP_MDI_AUTO:
851 val = MV_PCS_CSCR1_MDIX_AUTO;
854 val = MV_PCS_CSCR1_MDIX_MDIX;
857 val = MV_PCS_CSCR1_MDIX_MDI;
863 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
864 MV_PCS_CSCR1_MDIX_MASK, val);
866 err = mv3310_reset(phydev, MV_PCS_BASE_T);
871 static int mv3310_config_aneg(struct phy_device *phydev)
873 bool changed = false;
877 ret = mv3310_config_mdix(phydev);
881 if (phydev->autoneg == AUTONEG_DISABLE)
882 return genphy_c45_pma_setup_forced(phydev);
884 ret = genphy_c45_an_config_aneg(phydev);
890 /* Clause 45 has no standardized support for 1000BaseT, therefore
891 * use vendor registers for this mode.
893 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
894 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
895 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
901 return genphy_c45_check_and_restart_aneg(phydev, changed);
904 static int mv3310_aneg_done(struct phy_device *phydev)
908 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
912 if (val & MDIO_STAT1_LSTATUS)
915 return genphy_c45_aneg_done(phydev);
918 static void mv3310_update_interface(struct phy_device *phydev)
920 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
925 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
926 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
927 * internal 16KB buffer.
929 * In USXGMII mode the PHY interface mode is also fixed.
931 if (priv->rate_match ||
932 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
933 phydev->interface = priv->const_interface;
937 /* The PHY automatically switches its serdes interface (and active PHYXS
938 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
939 * xaui / rxaui modes according to the speed.
940 * Florian suggests setting phydev->interface to communicate this to the
941 * MAC. Only do this if we are already in one of the above modes.
943 switch (phydev->speed) {
945 phydev->interface = priv->const_interface;
948 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
951 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
956 phydev->interface = PHY_INTERFACE_MODE_SGMII;
963 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
964 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
967 phydev->speed = SPEED_10000;
968 phydev->duplex = DUPLEX_FULL;
969 phydev->port = PORT_FIBRE;
974 static int mv3310_read_status_copper(struct phy_device *phydev)
976 int cssr1, speed, val;
978 val = genphy_c45_read_link(phydev);
982 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
986 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
990 /* If the link settings are not resolved, mark the link down */
991 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
996 /* Read the copper link settings */
997 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
998 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
999 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
1002 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
1003 phydev->speed = SPEED_10000;
1006 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
1007 phydev->speed = SPEED_5000;
1010 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
1011 phydev->speed = SPEED_2500;
1014 case MV_PCS_CSSR1_SPD1_1000:
1015 phydev->speed = SPEED_1000;
1018 case MV_PCS_CSSR1_SPD1_100:
1019 phydev->speed = SPEED_100;
1022 case MV_PCS_CSSR1_SPD1_10:
1023 phydev->speed = SPEED_10;
1027 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
1028 DUPLEX_FULL : DUPLEX_HALF;
1029 phydev->port = PORT_TP;
1030 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
1031 ETH_TP_MDI_X : ETH_TP_MDI;
1033 if (val & MDIO_AN_STAT1_COMPLETE) {
1034 val = genphy_c45_read_lpa(phydev);
1038 /* Read the link partner's 1G advertisement */
1039 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
1043 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1045 /* Update the pause status */
1046 phy_resolve_aneg_pause(phydev);
1052 static int mv3310_read_status(struct phy_device *phydev)
1056 phydev->speed = SPEED_UNKNOWN;
1057 phydev->duplex = DUPLEX_UNKNOWN;
1058 linkmode_zero(phydev->lp_advertising);
1061 phydev->asym_pause = 0;
1062 phydev->mdix = ETH_TP_MDI_INVALID;
1064 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
1068 if (val & MDIO_STAT1_LSTATUS)
1069 err = mv3310_read_status_10gbaser(phydev);
1071 err = mv3310_read_status_copper(phydev);
1076 mv3310_update_interface(phydev);
1081 static int mv3310_get_tunable(struct phy_device *phydev,
1082 struct ethtool_tunable *tuna, void *data)
1085 case ETHTOOL_PHY_DOWNSHIFT:
1086 return mv3310_get_downshift(phydev, data);
1087 case ETHTOOL_PHY_EDPD:
1088 return mv3310_get_edpd(phydev, data);
1094 static int mv3310_set_tunable(struct phy_device *phydev,
1095 struct ethtool_tunable *tuna, const void *data)
1098 case ETHTOOL_PHY_DOWNSHIFT:
1099 return mv3310_set_downshift(phydev, *(u8 *)data);
1100 case ETHTOOL_PHY_EDPD:
1101 return mv3310_set_edpd(phydev, *(u16 *)data);
1107 static bool mv3310_has_downshift(struct phy_device *phydev)
1109 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
1111 /* Fails to downshift with firmware older than v0.3.5.0 */
1112 return priv->firmware_ver >= MV_VERSION(0,3,5,0);
1115 static void mv3310_init_supported_interfaces(unsigned long *mask)
1117 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1118 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1119 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1120 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
1121 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1122 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1123 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1126 static void mv3340_init_supported_interfaces(unsigned long *mask)
1128 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1129 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1130 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1131 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1132 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1133 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1136 static void mv2110_init_supported_interfaces(unsigned long *mask)
1138 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1139 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1140 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1141 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1142 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1145 static void mv2111_init_supported_interfaces(unsigned long *mask)
1147 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1148 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1149 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1150 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1153 static const struct mv3310_chip mv3310_type = {
1154 .has_downshift = mv3310_has_downshift,
1155 .init_supported_interfaces = mv3310_init_supported_interfaces,
1156 .get_mactype = mv3310_get_mactype,
1157 .set_mactype = mv3310_set_mactype,
1158 .select_mactype = mv3310_select_mactype,
1159 .init_interface = mv3310_init_interface,
1162 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1166 static const struct mv3310_chip mv3340_type = {
1167 .has_downshift = mv3310_has_downshift,
1168 .init_supported_interfaces = mv3340_init_supported_interfaces,
1169 .get_mactype = mv3310_get_mactype,
1170 .set_mactype = mv3310_set_mactype,
1171 .select_mactype = mv3310_select_mactype,
1172 .init_interface = mv3340_init_interface,
1175 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1179 static const struct mv3310_chip mv2110_type = {
1180 .init_supported_interfaces = mv2110_init_supported_interfaces,
1181 .get_mactype = mv2110_get_mactype,
1182 .set_mactype = mv2110_set_mactype,
1183 .select_mactype = mv2110_select_mactype,
1184 .init_interface = mv2110_init_interface,
1187 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1191 static const struct mv3310_chip mv2111_type = {
1192 .init_supported_interfaces = mv2111_init_supported_interfaces,
1193 .get_mactype = mv2110_get_mactype,
1194 .set_mactype = mv2110_set_mactype,
1195 .select_mactype = mv2110_select_mactype,
1196 .init_interface = mv2110_init_interface,
1199 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1203 static int mv3310_get_number_of_ports(struct phy_device *phydev)
1207 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
1211 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
1212 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
1217 static int mv3310_match_phy_device(struct phy_device *phydev)
1219 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1220 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1223 return mv3310_get_number_of_ports(phydev) == 1;
1226 static int mv3340_match_phy_device(struct phy_device *phydev)
1228 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1229 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1232 return mv3310_get_number_of_ports(phydev) == 4;
1235 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1239 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1240 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1243 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1247 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1250 static int mv2110_match_phy_device(struct phy_device *phydev)
1252 return mv211x_match_phy_device(phydev, true);
1255 static int mv2111_match_phy_device(struct phy_device *phydev)
1257 return mv211x_match_phy_device(phydev, false);
1260 static void mv3110_get_wol(struct phy_device *phydev,
1261 struct ethtool_wolinfo *wol)
1265 wol->supported = WAKE_MAGIC;
1268 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
1272 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN)
1273 wol->wolopts |= WAKE_MAGIC;
1276 static int mv3110_set_wol(struct phy_device *phydev,
1277 struct ethtool_wolinfo *wol)
1281 if (wol->wolopts & WAKE_MAGIC) {
1282 /* Enable the WOL interrupt */
1283 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1284 MV_V2_PORT_INTR_MASK,
1285 MV_V2_PORT_INTR_STS_WOL_EN);
1289 /* Store the device address for the magic packet */
1290 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1291 MV_V2_MAGIC_PKT_WORD2,
1292 ((phydev->attached_dev->dev_addr[5] << 8) |
1293 phydev->attached_dev->dev_addr[4]));
1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1298 MV_V2_MAGIC_PKT_WORD1,
1299 ((phydev->attached_dev->dev_addr[3] << 8) |
1300 phydev->attached_dev->dev_addr[2]));
1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1305 MV_V2_MAGIC_PKT_WORD0,
1306 ((phydev->attached_dev->dev_addr[1] << 8) |
1307 phydev->attached_dev->dev_addr[0]));
1311 /* Clear WOL status and enable magic packet matching */
1312 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1314 MV_V2_WOL_CTRL_MAGIC_PKT_EN |
1315 MV_V2_WOL_CTRL_CLEAR_STS);
1319 /* Disable magic packet matching & reset WOL status bit */
1320 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1322 MV_V2_WOL_CTRL_MAGIC_PKT_EN,
1323 MV_V2_WOL_CTRL_CLEAR_STS);
1328 /* Reset the clear WOL status bit as it does not self-clear */
1329 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1331 MV_V2_WOL_CTRL_CLEAR_STS);
1334 static struct phy_driver mv3310_drivers[] = {
1336 .phy_id = MARVELL_PHY_ID_88X3310,
1337 .phy_id_mask = MARVELL_PHY_ID_MASK,
1338 .match_phy_device = mv3310_match_phy_device,
1339 .name = "mv88x3310",
1340 .driver_data = &mv3310_type,
1341 .get_features = mv3310_get_features,
1342 .config_init = mv3310_config_init,
1343 .probe = mv3310_probe,
1344 .suspend = mv3310_suspend,
1345 .resume = mv3310_resume,
1346 .config_aneg = mv3310_config_aneg,
1347 .aneg_done = mv3310_aneg_done,
1348 .read_status = mv3310_read_status,
1349 .get_tunable = mv3310_get_tunable,
1350 .set_tunable = mv3310_set_tunable,
1351 .remove = mv3310_remove,
1352 .set_loopback = genphy_c45_loopback,
1353 .get_wol = mv3110_get_wol,
1354 .set_wol = mv3110_set_wol,
1357 .phy_id = MARVELL_PHY_ID_88X3310,
1358 .phy_id_mask = MARVELL_PHY_ID_MASK,
1359 .match_phy_device = mv3340_match_phy_device,
1360 .name = "mv88x3340",
1361 .driver_data = &mv3340_type,
1362 .get_features = mv3310_get_features,
1363 .config_init = mv3310_config_init,
1364 .probe = mv3310_probe,
1365 .suspend = mv3310_suspend,
1366 .resume = mv3310_resume,
1367 .config_aneg = mv3310_config_aneg,
1368 .aneg_done = mv3310_aneg_done,
1369 .read_status = mv3310_read_status,
1370 .get_tunable = mv3310_get_tunable,
1371 .set_tunable = mv3310_set_tunable,
1372 .remove = mv3310_remove,
1373 .set_loopback = genphy_c45_loopback,
1376 .phy_id = MARVELL_PHY_ID_88E2110,
1377 .phy_id_mask = MARVELL_PHY_ID_MASK,
1378 .match_phy_device = mv2110_match_phy_device,
1379 .name = "mv88e2110",
1380 .driver_data = &mv2110_type,
1381 .probe = mv3310_probe,
1382 .suspend = mv3310_suspend,
1383 .resume = mv3310_resume,
1384 .config_init = mv3310_config_init,
1385 .config_aneg = mv3310_config_aneg,
1386 .aneg_done = mv3310_aneg_done,
1387 .read_status = mv3310_read_status,
1388 .get_tunable = mv3310_get_tunable,
1389 .set_tunable = mv3310_set_tunable,
1390 .remove = mv3310_remove,
1391 .set_loopback = genphy_c45_loopback,
1392 .get_wol = mv3110_get_wol,
1393 .set_wol = mv3110_set_wol,
1396 .phy_id = MARVELL_PHY_ID_88E2110,
1397 .phy_id_mask = MARVELL_PHY_ID_MASK,
1398 .match_phy_device = mv2111_match_phy_device,
1399 .name = "mv88e2111",
1400 .driver_data = &mv2111_type,
1401 .probe = mv3310_probe,
1402 .suspend = mv3310_suspend,
1403 .resume = mv3310_resume,
1404 .config_init = mv3310_config_init,
1405 .config_aneg = mv3310_config_aneg,
1406 .aneg_done = mv3310_aneg_done,
1407 .read_status = mv3310_read_status,
1408 .get_tunable = mv3310_get_tunable,
1409 .set_tunable = mv3310_set_tunable,
1410 .remove = mv3310_remove,
1411 .set_loopback = genphy_c45_loopback,
1415 module_phy_driver(mv3310_drivers);
1417 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1418 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1419 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1422 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1423 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1424 MODULE_LICENSE("GPL");