1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver.
6 * XAUI on the host side.
7 * 1000Base-X or 10GBase-R on the line side.
8 * SGMII over 1000Base-X.
10 #include <linux/module.h>
11 #include <linux/phy.h>
12 #include <linux/gpio.h>
13 #include <linux/delay.h>
14 #include <linux/mdio.h>
15 #include <linux/marvell_phy.h>
17 #include <linux/of_device.h>
18 #include <linux/of_gpio.h>
19 #include <linux/sfp.h>
20 #include <linux/netdevice.h>
22 /* Port PCS Configuration */
23 #define MV_PCS_CONFIG 0xF002
24 #define MV_PCS_HOST_XAUI 0x73
25 #define MV_PCS_LINE_10GBR (0x71 << 8)
26 #define MV_PCS_LINE_1GBX_AN (0x7B << 8)
27 #define MV_PCS_LINE_SGMII_AN (0x7F << 8)
29 /* Port Reset and Power Down */
30 #define MV_PORT_RST 0xF003
31 #define MV_LINE_RST_SW BIT(15)
32 #define MV_HOST_RST_SW BIT(7)
33 #define MV_PORT_RST_SW (MV_LINE_RST_SW | MV_HOST_RST_SW)
35 /* PMD Receive Signal Detect */
36 #define MV_RX_SIGNAL_DETECT 0x000A
37 #define MV_RX_SIGNAL_DETECT_GLOBAL BIT(0)
39 /* 1000Base-X/SGMII Control Register */
40 #define MV_1GBX_CTRL (0x2000 + MII_BMCR)
42 /* 1000BASE-X/SGMII Status Register */
43 #define MV_1GBX_STAT (0x2000 + MII_BMSR)
45 /* 1000Base-X Auto-Negotiation Advertisement Register */
46 #define MV_1GBX_ADVERTISE (0x2000 + MII_ADVERTISE)
48 /* 1000Base-X PHY Specific Status Register */
49 #define MV_1GBX_PHY_STAT 0xA003
50 #define MV_1GBX_PHY_STAT_AN_RESOLVED BIT(11)
51 #define MV_1GBX_PHY_STAT_DUPLEX BIT(13)
52 #define MV_1GBX_PHY_STAT_SPEED100 BIT(14)
53 #define MV_1GBX_PHY_STAT_SPEED1000 BIT(15)
55 #define AUTONEG_TIMEOUT 3
58 phy_interface_t line_interface;
59 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 /* SFI PMA transmit enable */
64 static int mv2222_tx_enable(struct phy_device *phydev)
66 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
67 MDIO_PMD_TXDIS_GLOBAL);
70 /* SFI PMA transmit disable */
71 static int mv2222_tx_disable(struct phy_device *phydev)
73 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
74 MDIO_PMD_TXDIS_GLOBAL);
77 static int mv2222_soft_reset(struct phy_device *phydev)
81 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST,
86 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST,
87 val, !(val & MV_PORT_RST_SW),
91 static int mv2222_disable_aneg(struct phy_device *phydev)
93 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
94 BMCR_ANENABLE | BMCR_ANRESTART);
98 return mv2222_soft_reset(phydev);
101 static int mv2222_enable_aneg(struct phy_device *phydev)
103 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
104 BMCR_ANENABLE | BMCR_RESET);
108 return mv2222_soft_reset(phydev);
111 static int mv2222_set_sgmii_speed(struct phy_device *phydev)
113 struct mv2222_data *priv = phydev->priv;
115 switch (phydev->speed) {
118 if ((linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
120 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
122 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
124 BMCR_SPEED1000 | BMCR_SPEED100,
129 if ((linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
131 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
133 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
135 BMCR_SPEED1000 | BMCR_SPEED100,
139 if ((linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
141 linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
143 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
145 BMCR_SPEED1000 | BMCR_SPEED100,
152 static bool mv2222_is_10g_capable(struct phy_device *phydev)
154 struct mv2222_data *priv = phydev->priv;
156 return (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
158 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
160 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
162 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
164 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
166 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
170 static bool mv2222_is_1gbx_capable(struct phy_device *phydev)
172 struct mv2222_data *priv = phydev->priv;
174 return linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
178 static bool mv2222_is_sgmii_capable(struct phy_device *phydev)
180 struct mv2222_data *priv = phydev->priv;
182 return (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
184 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
186 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
188 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
190 linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
192 linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
196 static int mv2222_config_line(struct phy_device *phydev)
198 struct mv2222_data *priv = phydev->priv;
200 switch (priv->line_interface) {
201 case PHY_INTERFACE_MODE_10GBASER:
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
203 MV_PCS_HOST_XAUI | MV_PCS_LINE_10GBR);
204 case PHY_INTERFACE_MODE_1000BASEX:
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
206 MV_PCS_HOST_XAUI | MV_PCS_LINE_1GBX_AN);
207 case PHY_INTERFACE_MODE_SGMII:
208 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
209 MV_PCS_HOST_XAUI | MV_PCS_LINE_SGMII_AN);
215 /* Switch between 1G (1000Base-X/SGMII) and 10G (10GBase-R) modes */
216 static int mv2222_swap_line_type(struct phy_device *phydev)
218 struct mv2222_data *priv = phydev->priv;
219 bool changed = false;
222 switch (priv->line_interface) {
223 case PHY_INTERFACE_MODE_10GBASER:
224 if (mv2222_is_1gbx_capable(phydev)) {
225 priv->line_interface = PHY_INTERFACE_MODE_1000BASEX;
229 if (mv2222_is_sgmii_capable(phydev)) {
230 priv->line_interface = PHY_INTERFACE_MODE_SGMII;
235 case PHY_INTERFACE_MODE_1000BASEX:
236 case PHY_INTERFACE_MODE_SGMII:
237 if (mv2222_is_10g_capable(phydev)) {
238 priv->line_interface = PHY_INTERFACE_MODE_10GBASER;
248 ret = mv2222_config_line(phydev);
256 static int mv2222_setup_forced(struct phy_device *phydev)
258 struct mv2222_data *priv = phydev->priv;
261 if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER) {
262 if (phydev->speed < SPEED_10000 &&
263 phydev->speed != SPEED_UNKNOWN) {
264 ret = mv2222_swap_line_type(phydev);
270 if (priv->line_interface == PHY_INTERFACE_MODE_SGMII) {
271 ret = mv2222_set_sgmii_speed(phydev);
276 return mv2222_disable_aneg(phydev);
279 static int mv2222_config_aneg(struct phy_device *phydev)
281 struct mv2222_data *priv = phydev->priv;
284 /* SFP is not present, do nothing */
285 if (priv->line_interface == PHY_INTERFACE_MODE_NA)
288 if (phydev->autoneg == AUTONEG_DISABLE ||
289 priv->line_interface == PHY_INTERFACE_MODE_10GBASER)
290 return mv2222_setup_forced(phydev);
292 adv = linkmode_adv_to_mii_adv_x(priv->supported,
293 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
295 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_ADVERTISE,
296 ADVERTISE_1000XFULL |
297 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
302 return mv2222_enable_aneg(phydev);
305 static int mv2222_aneg_done(struct phy_device *phydev)
309 if (mv2222_is_10g_capable(phydev)) {
310 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
314 if (ret & MDIO_STAT1_LSTATUS)
318 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT);
322 return (ret & BMSR_ANEGCOMPLETE);
325 /* Returns negative on error, 0 if link is down, 1 if link is up */
326 static int mv2222_read_status_10g(struct phy_device *phydev)
331 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
335 if (val & MDIO_STAT1_LSTATUS) {
338 /* 10GBASE-R do not support auto-negotiation */
339 phydev->autoneg = AUTONEG_DISABLE;
340 phydev->speed = SPEED_10000;
341 phydev->duplex = DUPLEX_FULL;
343 if (phydev->autoneg == AUTONEG_ENABLE) {
346 if (timeout > AUTONEG_TIMEOUT) {
349 val = mv2222_swap_line_type(phydev);
353 return mv2222_config_aneg(phydev);
361 /* Returns negative on error, 0 if link is down, 1 if link is up */
362 static int mv2222_read_status_1g(struct phy_device *phydev)
367 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT);
371 if (phydev->autoneg == AUTONEG_ENABLE &&
372 !(val & BMSR_ANEGCOMPLETE)) {
375 if (timeout > AUTONEG_TIMEOUT) {
378 val = mv2222_swap_line_type(phydev);
382 return mv2222_config_aneg(phydev);
388 if (!(val & BMSR_LSTATUS))
393 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_PHY_STAT);
397 if (val & MV_1GBX_PHY_STAT_AN_RESOLVED) {
398 if (val & MV_1GBX_PHY_STAT_DUPLEX)
399 phydev->duplex = DUPLEX_FULL;
401 phydev->duplex = DUPLEX_HALF;
403 if (val & MV_1GBX_PHY_STAT_SPEED1000)
404 phydev->speed = SPEED_1000;
405 else if (val & MV_1GBX_PHY_STAT_SPEED100)
406 phydev->speed = SPEED_100;
408 phydev->speed = SPEED_10;
414 static bool mv2222_link_is_operational(struct phy_device *phydev)
416 struct mv2222_data *priv = phydev->priv;
419 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_RX_SIGNAL_DETECT);
420 if (val < 0 || !(val & MV_RX_SIGNAL_DETECT_GLOBAL))
423 if (phydev->sfp_bus && !priv->sfp_link)
429 static int mv2222_read_status(struct phy_device *phydev)
431 struct mv2222_data *priv = phydev->priv;
435 phydev->speed = SPEED_UNKNOWN;
436 phydev->duplex = DUPLEX_UNKNOWN;
438 if (!mv2222_link_is_operational(phydev))
441 if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER)
442 link = mv2222_read_status_10g(phydev);
444 link = mv2222_read_status_1g(phydev);
454 static int mv2222_resume(struct phy_device *phydev)
456 return mv2222_tx_enable(phydev);
459 static int mv2222_suspend(struct phy_device *phydev)
461 return mv2222_tx_disable(phydev);
464 static int mv2222_get_features(struct phy_device *phydev)
466 /* All supported linkmodes are set at probe */
471 static int mv2222_config_init(struct phy_device *phydev)
473 if (phydev->interface != PHY_INTERFACE_MODE_XAUI)
479 static int mv2222_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
481 DECLARE_PHY_INTERFACE_MASK(interfaces);
482 struct phy_device *phydev = upstream;
483 phy_interface_t sfp_interface;
484 struct mv2222_data *priv;
488 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_supported) = { 0, };
490 priv = (struct mv2222_data *)phydev->priv;
491 dev = &phydev->mdio.dev;
493 sfp_parse_support(phydev->sfp_bus, id, sfp_supported, interfaces);
494 phydev->port = sfp_parse_port(phydev->sfp_bus, id, sfp_supported);
495 sfp_interface = sfp_select_interface(phydev->sfp_bus, sfp_supported);
497 dev_info(dev, "%s SFP module inserted\n", phy_modes(sfp_interface));
499 if (sfp_interface != PHY_INTERFACE_MODE_10GBASER &&
500 sfp_interface != PHY_INTERFACE_MODE_1000BASEX &&
501 sfp_interface != PHY_INTERFACE_MODE_SGMII) {
502 dev_err(dev, "Incompatible SFP module inserted\n");
507 priv->line_interface = sfp_interface;
508 linkmode_and(priv->supported, phydev->supported, sfp_supported);
510 ret = mv2222_config_line(phydev);
514 if (mutex_trylock(&phydev->lock)) {
515 ret = mv2222_config_aneg(phydev);
516 mutex_unlock(&phydev->lock);
522 static void mv2222_sfp_remove(void *upstream)
524 struct phy_device *phydev = upstream;
525 struct mv2222_data *priv;
527 priv = (struct mv2222_data *)phydev->priv;
529 priv->line_interface = PHY_INTERFACE_MODE_NA;
530 linkmode_zero(priv->supported);
531 phydev->port = PORT_NONE;
534 static void mv2222_sfp_link_up(void *upstream)
536 struct phy_device *phydev = upstream;
537 struct mv2222_data *priv;
540 priv->sfp_link = true;
543 static void mv2222_sfp_link_down(void *upstream)
545 struct phy_device *phydev = upstream;
546 struct mv2222_data *priv;
549 priv->sfp_link = false;
552 static const struct sfp_upstream_ops sfp_phy_ops = {
553 .module_insert = mv2222_sfp_insert,
554 .module_remove = mv2222_sfp_remove,
555 .link_up = mv2222_sfp_link_up,
556 .link_down = mv2222_sfp_link_down,
557 .attach = phy_sfp_attach,
558 .detach = phy_sfp_detach,
561 static int mv2222_probe(struct phy_device *phydev)
563 struct device *dev = &phydev->mdio.dev;
564 struct mv2222_data *priv = NULL;
566 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
568 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
569 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
570 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
571 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
572 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
573 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
574 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
575 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, supported);
576 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, supported);
577 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, supported);
578 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, supported);
579 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, supported);
580 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, supported);
581 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, supported);
582 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
583 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
584 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, supported);
585 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
587 linkmode_copy(phydev->supported, supported);
589 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
593 priv->line_interface = PHY_INTERFACE_MODE_NA;
596 return phy_sfp_probe(phydev, &sfp_phy_ops);
599 static struct phy_driver mv2222_drivers[] = {
601 .phy_id = MARVELL_PHY_ID_88X2222,
602 .phy_id_mask = MARVELL_PHY_ID_MASK,
603 .name = "Marvell 88X2222",
604 .get_features = mv2222_get_features,
605 .soft_reset = mv2222_soft_reset,
606 .config_init = mv2222_config_init,
607 .config_aneg = mv2222_config_aneg,
608 .aneg_done = mv2222_aneg_done,
609 .probe = mv2222_probe,
610 .suspend = mv2222_suspend,
611 .resume = mv2222_resume,
612 .read_status = mv2222_read_status,
615 module_phy_driver(mv2222_drivers);
617 static struct mdio_device_id __maybe_unused mv2222_tbl[] = {
618 { MARVELL_PHY_ID_88X2222, MARVELL_PHY_ID_MASK },
621 MODULE_DEVICE_TABLE(mdio, mv2222_tbl);
623 MODULE_DESCRIPTION("Marvell 88x2222 ethernet transceiver driver");
624 MODULE_LICENSE("GPL");