1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver.
6 * XAUI on the host side.
7 * 1000Base-X or 10GBase-R on the line side.
8 * SGMII over 1000Base-X.
10 #include <linux/module.h>
11 #include <linux/phy.h>
12 #include <linux/gpio.h>
13 #include <linux/delay.h>
14 #include <linux/mdio.h>
15 #include <linux/marvell_phy.h>
17 #include <linux/of_gpio.h>
18 #include <linux/sfp.h>
19 #include <linux/netdevice.h>
21 /* Port PCS Configuration */
22 #define MV_PCS_CONFIG 0xF002
23 #define MV_PCS_HOST_XAUI 0x73
24 #define MV_PCS_LINE_10GBR (0x71 << 8)
25 #define MV_PCS_LINE_1GBX_AN (0x7B << 8)
26 #define MV_PCS_LINE_SGMII_AN (0x7F << 8)
28 /* Port Reset and Power Down */
29 #define MV_PORT_RST 0xF003
30 #define MV_LINE_RST_SW BIT(15)
31 #define MV_HOST_RST_SW BIT(7)
32 #define MV_PORT_RST_SW (MV_LINE_RST_SW | MV_HOST_RST_SW)
34 /* PMD Receive Signal Detect */
35 #define MV_RX_SIGNAL_DETECT 0x000A
36 #define MV_RX_SIGNAL_DETECT_GLOBAL BIT(0)
38 /* 1000Base-X/SGMII Control Register */
39 #define MV_1GBX_CTRL (0x2000 + MII_BMCR)
41 /* 1000BASE-X/SGMII Status Register */
42 #define MV_1GBX_STAT (0x2000 + MII_BMSR)
44 /* 1000Base-X Auto-Negotiation Advertisement Register */
45 #define MV_1GBX_ADVERTISE (0x2000 + MII_ADVERTISE)
47 /* 1000Base-X PHY Specific Status Register */
48 #define MV_1GBX_PHY_STAT 0xA003
49 #define MV_1GBX_PHY_STAT_AN_RESOLVED BIT(11)
50 #define MV_1GBX_PHY_STAT_DUPLEX BIT(13)
51 #define MV_1GBX_PHY_STAT_SPEED100 BIT(14)
52 #define MV_1GBX_PHY_STAT_SPEED1000 BIT(15)
54 #define AUTONEG_TIMEOUT 3
57 phy_interface_t line_interface;
58 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
62 /* SFI PMA transmit enable */
63 static int mv2222_tx_enable(struct phy_device *phydev)
65 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
66 MDIO_PMD_TXDIS_GLOBAL);
69 /* SFI PMA transmit disable */
70 static int mv2222_tx_disable(struct phy_device *phydev)
72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
73 MDIO_PMD_TXDIS_GLOBAL);
76 static int mv2222_soft_reset(struct phy_device *phydev)
80 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST,
85 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST,
86 val, !(val & MV_PORT_RST_SW),
90 static int mv2222_disable_aneg(struct phy_device *phydev)
92 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
93 BMCR_ANENABLE | BMCR_ANRESTART);
97 return mv2222_soft_reset(phydev);
100 static int mv2222_enable_aneg(struct phy_device *phydev)
102 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
103 BMCR_ANENABLE | BMCR_RESET);
107 return mv2222_soft_reset(phydev);
110 static int mv2222_set_sgmii_speed(struct phy_device *phydev)
112 struct mv2222_data *priv = phydev->priv;
114 switch (phydev->speed) {
117 if ((linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
119 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
121 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
123 BMCR_SPEED1000 | BMCR_SPEED100,
128 if ((linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
130 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
132 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
134 BMCR_SPEED1000 | BMCR_SPEED100,
138 if ((linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
140 linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
142 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
144 BMCR_SPEED1000 | BMCR_SPEED100,
151 static bool mv2222_is_10g_capable(struct phy_device *phydev)
153 struct mv2222_data *priv = phydev->priv;
155 return (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
157 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
159 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
161 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
163 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
165 linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
169 static bool mv2222_is_1gbx_capable(struct phy_device *phydev)
171 struct mv2222_data *priv = phydev->priv;
173 return linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
177 static bool mv2222_is_sgmii_capable(struct phy_device *phydev)
179 struct mv2222_data *priv = phydev->priv;
181 return (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
183 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
185 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
187 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
189 linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
191 linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
195 static int mv2222_config_line(struct phy_device *phydev)
197 struct mv2222_data *priv = phydev->priv;
199 switch (priv->line_interface) {
200 case PHY_INTERFACE_MODE_10GBASER:
201 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
202 MV_PCS_HOST_XAUI | MV_PCS_LINE_10GBR);
203 case PHY_INTERFACE_MODE_1000BASEX:
204 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
205 MV_PCS_HOST_XAUI | MV_PCS_LINE_1GBX_AN);
206 case PHY_INTERFACE_MODE_SGMII:
207 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
208 MV_PCS_HOST_XAUI | MV_PCS_LINE_SGMII_AN);
214 /* Switch between 1G (1000Base-X/SGMII) and 10G (10GBase-R) modes */
215 static int mv2222_swap_line_type(struct phy_device *phydev)
217 struct mv2222_data *priv = phydev->priv;
218 bool changed = false;
221 switch (priv->line_interface) {
222 case PHY_INTERFACE_MODE_10GBASER:
223 if (mv2222_is_1gbx_capable(phydev)) {
224 priv->line_interface = PHY_INTERFACE_MODE_1000BASEX;
228 if (mv2222_is_sgmii_capable(phydev)) {
229 priv->line_interface = PHY_INTERFACE_MODE_SGMII;
234 case PHY_INTERFACE_MODE_1000BASEX:
235 case PHY_INTERFACE_MODE_SGMII:
236 if (mv2222_is_10g_capable(phydev)) {
237 priv->line_interface = PHY_INTERFACE_MODE_10GBASER;
247 ret = mv2222_config_line(phydev);
255 static int mv2222_setup_forced(struct phy_device *phydev)
257 struct mv2222_data *priv = phydev->priv;
260 if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER) {
261 if (phydev->speed < SPEED_10000 &&
262 phydev->speed != SPEED_UNKNOWN) {
263 ret = mv2222_swap_line_type(phydev);
269 if (priv->line_interface == PHY_INTERFACE_MODE_SGMII) {
270 ret = mv2222_set_sgmii_speed(phydev);
275 return mv2222_disable_aneg(phydev);
278 static int mv2222_config_aneg(struct phy_device *phydev)
280 struct mv2222_data *priv = phydev->priv;
283 /* SFP is not present, do nothing */
284 if (priv->line_interface == PHY_INTERFACE_MODE_NA)
287 if (phydev->autoneg == AUTONEG_DISABLE ||
288 priv->line_interface == PHY_INTERFACE_MODE_10GBASER)
289 return mv2222_setup_forced(phydev);
291 adv = linkmode_adv_to_mii_adv_x(priv->supported,
292 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
294 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_ADVERTISE,
295 ADVERTISE_1000XFULL |
296 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
301 return mv2222_enable_aneg(phydev);
304 static int mv2222_aneg_done(struct phy_device *phydev)
308 if (mv2222_is_10g_capable(phydev)) {
309 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
313 if (ret & MDIO_STAT1_LSTATUS)
317 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT);
321 return (ret & BMSR_ANEGCOMPLETE);
324 /* Returns negative on error, 0 if link is down, 1 if link is up */
325 static int mv2222_read_status_10g(struct phy_device *phydev)
330 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
334 if (val & MDIO_STAT1_LSTATUS) {
337 /* 10GBASE-R do not support auto-negotiation */
338 phydev->autoneg = AUTONEG_DISABLE;
339 phydev->speed = SPEED_10000;
340 phydev->duplex = DUPLEX_FULL;
342 if (phydev->autoneg == AUTONEG_ENABLE) {
345 if (timeout > AUTONEG_TIMEOUT) {
348 val = mv2222_swap_line_type(phydev);
352 return mv2222_config_aneg(phydev);
360 /* Returns negative on error, 0 if link is down, 1 if link is up */
361 static int mv2222_read_status_1g(struct phy_device *phydev)
366 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT);
370 if (phydev->autoneg == AUTONEG_ENABLE &&
371 !(val & BMSR_ANEGCOMPLETE)) {
374 if (timeout > AUTONEG_TIMEOUT) {
377 val = mv2222_swap_line_type(phydev);
381 return mv2222_config_aneg(phydev);
387 if (!(val & BMSR_LSTATUS))
392 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_PHY_STAT);
396 if (val & MV_1GBX_PHY_STAT_AN_RESOLVED) {
397 if (val & MV_1GBX_PHY_STAT_DUPLEX)
398 phydev->duplex = DUPLEX_FULL;
400 phydev->duplex = DUPLEX_HALF;
402 if (val & MV_1GBX_PHY_STAT_SPEED1000)
403 phydev->speed = SPEED_1000;
404 else if (val & MV_1GBX_PHY_STAT_SPEED100)
405 phydev->speed = SPEED_100;
407 phydev->speed = SPEED_10;
413 static bool mv2222_link_is_operational(struct phy_device *phydev)
415 struct mv2222_data *priv = phydev->priv;
418 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_RX_SIGNAL_DETECT);
419 if (val < 0 || !(val & MV_RX_SIGNAL_DETECT_GLOBAL))
422 if (phydev->sfp_bus && !priv->sfp_link)
428 static int mv2222_read_status(struct phy_device *phydev)
430 struct mv2222_data *priv = phydev->priv;
434 phydev->speed = SPEED_UNKNOWN;
435 phydev->duplex = DUPLEX_UNKNOWN;
437 if (!mv2222_link_is_operational(phydev))
440 if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER)
441 link = mv2222_read_status_10g(phydev);
443 link = mv2222_read_status_1g(phydev);
453 static int mv2222_resume(struct phy_device *phydev)
455 return mv2222_tx_enable(phydev);
458 static int mv2222_suspend(struct phy_device *phydev)
460 return mv2222_tx_disable(phydev);
463 static int mv2222_get_features(struct phy_device *phydev)
465 /* All supported linkmodes are set at probe */
470 static int mv2222_config_init(struct phy_device *phydev)
472 if (phydev->interface != PHY_INTERFACE_MODE_XAUI)
478 static int mv2222_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
480 DECLARE_PHY_INTERFACE_MASK(interfaces);
481 struct phy_device *phydev = upstream;
482 phy_interface_t sfp_interface;
483 struct mv2222_data *priv;
487 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_supported) = { 0, };
490 dev = &phydev->mdio.dev;
492 sfp_parse_support(phydev->sfp_bus, id, sfp_supported, interfaces);
493 phydev->port = sfp_parse_port(phydev->sfp_bus, id, sfp_supported);
494 sfp_interface = sfp_select_interface(phydev->sfp_bus, sfp_supported);
496 dev_info(dev, "%s SFP module inserted\n", phy_modes(sfp_interface));
498 if (sfp_interface != PHY_INTERFACE_MODE_10GBASER &&
499 sfp_interface != PHY_INTERFACE_MODE_1000BASEX &&
500 sfp_interface != PHY_INTERFACE_MODE_SGMII) {
501 dev_err(dev, "Incompatible SFP module inserted\n");
506 priv->line_interface = sfp_interface;
507 linkmode_and(priv->supported, phydev->supported, sfp_supported);
509 ret = mv2222_config_line(phydev);
513 if (mutex_trylock(&phydev->lock)) {
514 ret = mv2222_config_aneg(phydev);
515 mutex_unlock(&phydev->lock);
521 static void mv2222_sfp_remove(void *upstream)
523 struct phy_device *phydev = upstream;
524 struct mv2222_data *priv;
528 priv->line_interface = PHY_INTERFACE_MODE_NA;
529 linkmode_zero(priv->supported);
530 phydev->port = PORT_NONE;
533 static void mv2222_sfp_link_up(void *upstream)
535 struct phy_device *phydev = upstream;
536 struct mv2222_data *priv;
539 priv->sfp_link = true;
542 static void mv2222_sfp_link_down(void *upstream)
544 struct phy_device *phydev = upstream;
545 struct mv2222_data *priv;
548 priv->sfp_link = false;
551 static const struct sfp_upstream_ops sfp_phy_ops = {
552 .module_insert = mv2222_sfp_insert,
553 .module_remove = mv2222_sfp_remove,
554 .link_up = mv2222_sfp_link_up,
555 .link_down = mv2222_sfp_link_down,
556 .attach = phy_sfp_attach,
557 .detach = phy_sfp_detach,
560 static int mv2222_probe(struct phy_device *phydev)
562 struct device *dev = &phydev->mdio.dev;
563 struct mv2222_data *priv = NULL;
565 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
567 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
568 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
569 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
570 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
571 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
572 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
573 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
574 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, supported);
575 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, supported);
576 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, supported);
577 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, supported);
578 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, supported);
579 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, supported);
580 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, supported);
581 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
582 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
583 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, supported);
584 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
586 linkmode_copy(phydev->supported, supported);
588 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
592 priv->line_interface = PHY_INTERFACE_MODE_NA;
595 return phy_sfp_probe(phydev, &sfp_phy_ops);
598 static struct phy_driver mv2222_drivers[] = {
600 .phy_id = MARVELL_PHY_ID_88X2222,
601 .phy_id_mask = MARVELL_PHY_ID_MASK,
602 .name = "Marvell 88X2222",
603 .get_features = mv2222_get_features,
604 .soft_reset = mv2222_soft_reset,
605 .config_init = mv2222_config_init,
606 .config_aneg = mv2222_config_aneg,
607 .aneg_done = mv2222_aneg_done,
608 .probe = mv2222_probe,
609 .suspend = mv2222_suspend,
610 .resume = mv2222_resume,
611 .read_status = mv2222_read_status,
614 module_phy_driver(mv2222_drivers);
616 static struct mdio_device_id __maybe_unused mv2222_tbl[] = {
617 { MARVELL_PHY_ID_88X2222, MARVELL_PHY_ID_MASK },
620 MODULE_DEVICE_TABLE(mdio, mv2222_tbl);
622 MODULE_DESCRIPTION("Marvell 88x2222 ethernet transceiver driver");
623 MODULE_LICENSE("GPL");