1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
7 #include <linux/ethtool.h>
8 #include <linux/kernel.h>
10 #include <linux/module.h>
12 #include <linux/phy.h>
13 #include <linux/delay.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/bitfield.h>
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
21 #define DP83867_PHY_ID 0x2000a231
22 #define DP83867_DEVADDR 0x1f
24 #define MII_DP83867_PHYCTRL 0x10
25 #define MII_DP83867_PHYSTS 0x11
26 #define MII_DP83867_MICR 0x12
27 #define MII_DP83867_ISR 0x13
28 #define DP83867_CFG2 0x14
29 #define DP83867_CFG3 0x1e
30 #define DP83867_CTRL 0x1f
32 /* Extended Registers */
33 #define DP83867_FLD_THR_CFG 0x002e
34 #define DP83867_CFG4 0x0031
35 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
36 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
37 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
38 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
39 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
41 #define DP83867_RGMIICTL 0x0032
42 #define DP83867_STRAP_STS1 0x006E
43 #define DP83867_STRAP_STS2 0x006f
44 #define DP83867_RGMIIDCTL 0x0086
45 #define DP83867_RXFCFG 0x0134
46 #define DP83867_RXFPMD1 0x0136
47 #define DP83867_RXFPMD2 0x0137
48 #define DP83867_RXFPMD3 0x0138
49 #define DP83867_RXFSOP1 0x0139
50 #define DP83867_RXFSOP2 0x013A
51 #define DP83867_RXFSOP3 0x013B
52 #define DP83867_IO_MUX_CFG 0x0170
53 #define DP83867_SGMIICTL 0x00D3
54 #define DP83867_10M_SGMII_CFG 0x016F
55 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
57 #define DP83867_SW_RESET BIT(15)
58 #define DP83867_SW_RESTART BIT(14)
60 /* MICR Interrupt bits */
61 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
62 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
63 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
64 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
65 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
66 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
67 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
68 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
69 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
70 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
71 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
72 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
75 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
76 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
79 #define DP83867_SGMII_TYPE BIT(14)
82 #define DP83867_WOL_MAGIC_EN BIT(0)
83 #define DP83867_WOL_BCAST_EN BIT(2)
84 #define DP83867_WOL_UCAST_EN BIT(4)
85 #define DP83867_WOL_SEC_EN BIT(5)
86 #define DP83867_WOL_ENH_MAC BIT(7)
89 #define DP83867_STRAP_STS1_RESERVED BIT(11)
92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
93 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
95 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
96 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
97 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
100 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
101 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
102 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
103 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
104 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
105 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
106 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
109 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
110 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
111 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
112 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
113 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
114 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
116 /* IO_MUX_CFG bits */
117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
119 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
120 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
122 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
125 #define DP83867_PHYSTS_1000 BIT(15)
126 #define DP83867_PHYSTS_100 BIT(14)
127 #define DP83867_PHYSTS_DUPLEX BIT(13)
128 #define DP83867_PHYSTS_LINK BIT(10)
131 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
132 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
133 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0
134 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1
135 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2
136 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3
137 #define DP83867_DOWNSHIFT_1_COUNT 1
138 #define DP83867_DOWNSHIFT_2_COUNT 2
139 #define DP83867_DOWNSHIFT_4_COUNT 4
140 #define DP83867_DOWNSHIFT_8_COUNT 8
141 #define DP83867_SGMII_AUTONEG_EN BIT(7)
144 #define DP83867_CFG3_INT_OE BIT(7)
145 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
148 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
151 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
154 DP83867_PORT_MIRROING_KEEP,
155 DP83867_PORT_MIRROING_EN,
156 DP83867_PORT_MIRROING_DIS,
159 struct dp83867_private {
166 bool rxctrl_strap_quirk;
169 bool sgmii_ref_clk_en;
172 static int dp83867_ack_interrupt(struct phy_device *phydev)
174 int err = phy_read(phydev, MII_DP83867_ISR);
182 static int dp83867_set_wol(struct phy_device *phydev,
183 struct ethtool_wolinfo *wol)
185 struct net_device *ndev = phydev->attached_dev;
186 u16 val_rxcfg, val_micr;
189 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
190 val_micr = phy_read(phydev, MII_DP83867_MICR);
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
194 val_rxcfg |= DP83867_WOL_ENH_MAC;
195 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
197 if (wol->wolopts & WAKE_MAGIC) {
198 mac = (const u8 *)ndev->dev_addr;
200 if (!is_valid_ether_addr(mac))
203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
204 (mac[1] << 8 | mac[0]));
205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
206 (mac[3] << 8 | mac[2]));
207 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
208 (mac[5] << 8 | mac[4]));
210 val_rxcfg |= DP83867_WOL_MAGIC_EN;
212 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
215 if (wol->wolopts & WAKE_MAGICSECURE) {
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
217 (wol->sopass[1] << 8) | wol->sopass[0]);
218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
219 (wol->sopass[3] << 8) | wol->sopass[2]);
220 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
221 (wol->sopass[5] << 8) | wol->sopass[4]);
223 val_rxcfg |= DP83867_WOL_SEC_EN;
225 val_rxcfg &= ~DP83867_WOL_SEC_EN;
228 if (wol->wolopts & WAKE_UCAST)
229 val_rxcfg |= DP83867_WOL_UCAST_EN;
231 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
233 if (wol->wolopts & WAKE_BCAST)
234 val_rxcfg |= DP83867_WOL_BCAST_EN;
236 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
238 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
239 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
243 phy_write(phydev, MII_DP83867_MICR, val_micr);
248 static void dp83867_get_wol(struct phy_device *phydev,
249 struct ethtool_wolinfo *wol)
251 u16 value, sopass_val;
253 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
257 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
259 if (value & DP83867_WOL_UCAST_EN)
260 wol->wolopts |= WAKE_UCAST;
262 if (value & DP83867_WOL_BCAST_EN)
263 wol->wolopts |= WAKE_BCAST;
265 if (value & DP83867_WOL_MAGIC_EN)
266 wol->wolopts |= WAKE_MAGIC;
268 if (value & DP83867_WOL_SEC_EN) {
269 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
271 wol->sopass[0] = (sopass_val & 0xff);
272 wol->sopass[1] = (sopass_val >> 8);
274 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
276 wol->sopass[2] = (sopass_val & 0xff);
277 wol->sopass[3] = (sopass_val >> 8);
279 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
281 wol->sopass[4] = (sopass_val & 0xff);
282 wol->sopass[5] = (sopass_val >> 8);
284 wol->wolopts |= WAKE_MAGICSECURE;
287 if (!(value & DP83867_WOL_ENH_MAC))
291 static int dp83867_config_intr(struct phy_device *phydev)
293 int micr_status, err;
295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
296 err = dp83867_ack_interrupt(phydev);
300 micr_status = phy_read(phydev, MII_DP83867_MICR);
305 (MII_DP83867_MICR_AN_ERR_INT_EN |
306 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
307 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
308 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
309 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
310 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
312 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
315 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
319 err = dp83867_ack_interrupt(phydev);
325 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
327 int irq_status, irq_enabled;
329 irq_status = phy_read(phydev, MII_DP83867_ISR);
330 if (irq_status < 0) {
335 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
336 if (irq_enabled < 0) {
341 if (!(irq_status & irq_enabled))
344 phy_trigger_machine(phydev);
349 static int dp83867_read_status(struct phy_device *phydev)
351 int status = phy_read(phydev, MII_DP83867_PHYSTS);
354 ret = genphy_read_status(phydev);
361 if (status & DP83867_PHYSTS_DUPLEX)
362 phydev->duplex = DUPLEX_FULL;
364 phydev->duplex = DUPLEX_HALF;
366 if (status & DP83867_PHYSTS_1000)
367 phydev->speed = SPEED_1000;
368 else if (status & DP83867_PHYSTS_100)
369 phydev->speed = SPEED_100;
371 phydev->speed = SPEED_10;
376 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
378 int val, cnt, enable, count;
380 val = phy_read(phydev, DP83867_CFG2);
384 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
385 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
388 case DP83867_DOWNSHIFT_1_COUNT_VAL:
389 count = DP83867_DOWNSHIFT_1_COUNT;
391 case DP83867_DOWNSHIFT_2_COUNT_VAL:
392 count = DP83867_DOWNSHIFT_2_COUNT;
394 case DP83867_DOWNSHIFT_4_COUNT_VAL:
395 count = DP83867_DOWNSHIFT_4_COUNT;
397 case DP83867_DOWNSHIFT_8_COUNT_VAL:
398 count = DP83867_DOWNSHIFT_8_COUNT;
404 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
409 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
413 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
417 return phy_clear_bits(phydev, DP83867_CFG2,
418 DP83867_DOWNSHIFT_EN);
421 case DP83867_DOWNSHIFT_1_COUNT:
422 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
424 case DP83867_DOWNSHIFT_2_COUNT:
425 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
427 case DP83867_DOWNSHIFT_4_COUNT:
428 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
430 case DP83867_DOWNSHIFT_8_COUNT:
431 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
435 "Downshift count must be 1, 2, 4 or 8\n");
439 val = DP83867_DOWNSHIFT_EN;
440 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
442 return phy_modify(phydev, DP83867_CFG2,
443 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
447 static int dp83867_get_tunable(struct phy_device *phydev,
448 struct ethtool_tunable *tuna, void *data)
451 case ETHTOOL_PHY_DOWNSHIFT:
452 return dp83867_get_downshift(phydev, data);
458 static int dp83867_set_tunable(struct phy_device *phydev,
459 struct ethtool_tunable *tuna, const void *data)
462 case ETHTOOL_PHY_DOWNSHIFT:
463 return dp83867_set_downshift(phydev, *(const u8 *)data);
469 static int dp83867_config_port_mirroring(struct phy_device *phydev)
471 struct dp83867_private *dp83867 =
472 (struct dp83867_private *)phydev->priv;
474 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
475 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
476 DP83867_CFG4_PORT_MIRROR_EN);
478 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
479 DP83867_CFG4_PORT_MIRROR_EN);
483 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
485 struct dp83867_private *dp83867 = phydev->priv;
487 /* Existing behavior was to use default pin strapping delay in rgmii
488 * mode, but rgmii should have meant no delay. Warn existing users.
490 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
491 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
493 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
494 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
495 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
496 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
498 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
499 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
501 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
502 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
506 /* RX delay *must* be specified if internal delay of RX is used. */
507 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
508 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
509 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
510 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
514 /* TX delay *must* be specified if internal delay of TX is used. */
515 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
516 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
517 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
518 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
525 #if IS_ENABLED(CONFIG_OF_MDIO)
526 static int dp83867_of_init_io_impedance(struct phy_device *phydev)
528 struct dp83867_private *dp83867 = phydev->priv;
529 struct device *dev = &phydev->mdio.dev;
530 struct device_node *of_node = dev->of_node;
531 struct nvmem_cell *cell;
535 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
538 if (ret != -ENOENT && ret != -EOPNOTSUPP)
539 return phydev_err_probe(phydev, ret,
540 "failed to get nvmem cell io_impedance_ctrl\n");
542 /* If no nvmem cell, check for the boolean properties. */
543 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
544 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
545 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
546 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
548 dp83867->io_impedance = -1; /* leave at default */
553 buf = nvmem_cell_read(cell, NULL);
554 nvmem_cell_put(cell);
562 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
563 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
566 dp83867->io_impedance = val;
571 static int dp83867_of_init(struct phy_device *phydev)
573 struct dp83867_private *dp83867 = phydev->priv;
574 struct device *dev = &phydev->mdio.dev;
575 struct device_node *of_node = dev->of_node;
581 /* Optional configuration */
582 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
583 &dp83867->clk_output_sel);
584 /* If not set, keep default */
586 dp83867->set_clk_output = true;
587 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
588 * DP83867_CLK_O_SEL_OFF.
590 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
591 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
592 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
593 dp83867->clk_output_sel);
598 ret = dp83867_of_init_io_impedance(phydev);
602 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
603 "ti,dp83867-rxctrl-strap-quirk");
605 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
606 "ti,sgmii-ref-clock-output-enable");
608 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
609 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
610 &dp83867->rx_id_delay);
611 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
613 "ti,rx-internal-delay value of %u out of range\n",
614 dp83867->rx_id_delay);
618 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
619 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
620 &dp83867->tx_id_delay);
621 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
623 "ti,tx-internal-delay value of %u out of range\n",
624 dp83867->tx_id_delay);
628 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
629 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
631 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
632 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
634 ret = of_property_read_u32(of_node, "ti,fifo-depth",
635 &dp83867->tx_fifo_depth);
637 ret = of_property_read_u32(of_node, "tx-fifo-depth",
638 &dp83867->tx_fifo_depth);
640 dp83867->tx_fifo_depth =
641 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
644 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
645 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
646 dp83867->tx_fifo_depth);
650 ret = of_property_read_u32(of_node, "rx-fifo-depth",
651 &dp83867->rx_fifo_depth);
653 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
655 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
656 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
657 dp83867->rx_fifo_depth);
664 static int dp83867_of_init(struct phy_device *phydev)
666 struct dp83867_private *dp83867 = phydev->priv;
669 /* For non-OF device, the RX and TX ID values are either strapped
670 * or take from default value. So, we init RX & TX ID values here
671 * so that the RGMIIDCTL is configured correctly later in
672 * dp83867_config_init();
674 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
675 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
676 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
677 DP83867_RGMII_TX_CLK_DELAY_MAX;
679 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
680 * same here or else the default '0' means highest IO impedance
683 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
685 /* For non-OF device, the RX and TX FIFO depths are taken from
686 * default value. So, we init RX & TX FIFO depths here
687 * so that it is configured correctly later in dp83867_config_init();
689 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
690 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
694 #endif /* CONFIG_OF_MDIO */
696 static int dp83867_probe(struct phy_device *phydev)
698 struct dp83867_private *dp83867;
700 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
705 phydev->priv = dp83867;
707 return dp83867_of_init(phydev);
710 static int dp83867_config_init(struct phy_device *phydev)
712 struct dp83867_private *dp83867 = phydev->priv;
716 /* Force speed optimization for the PHY even if it strapped */
717 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
718 DP83867_DOWNSHIFT_EN);
722 ret = dp83867_verify_rgmii_cfg(phydev);
726 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
727 if (dp83867->rxctrl_strap_quirk)
728 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
731 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
732 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
733 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
734 * be set to 0x2. This may causes the PHY link to be unstable -
735 * the default value 0x1 need to be restored.
737 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
739 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
745 if (phy_interface_is_rgmii(phydev) ||
746 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
747 val = phy_read(phydev, MII_DP83867_PHYCTRL);
751 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
752 val |= (dp83867->tx_fifo_depth <<
753 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
755 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
756 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
757 val |= (dp83867->rx_fifo_depth <<
758 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
761 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
766 if (phy_interface_is_rgmii(phydev)) {
767 val = phy_read(phydev, MII_DP83867_PHYCTRL);
771 /* The code below checks if "port mirroring" N/A MODE4 has been
772 * enabled during power on bootstrap.
774 * Such N/A mode enabled by mistake can put PHY IC in some
775 * internal testing mode and disable RGMII transmission.
777 * In this particular case one needs to check STRAP_STS1
778 * register's bit 11 (marked as RESERVED).
781 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
782 if (bs & DP83867_STRAP_STS1_RESERVED)
783 val &= ~DP83867_PHYCR_RESERVED_MASK;
785 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
789 /* If rgmii mode with no internal delay is selected, we do NOT use
790 * aligned mode as one might expect. Instead we use the PHY's default
791 * based on pin strapping. And the "mode 0" default is to *use*
792 * internal delay with a value of 7 (2.00 ns).
794 * Set up RGMII delays
796 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
798 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
799 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
800 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
802 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
803 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
805 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
806 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
808 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
811 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
812 delay |= dp83867->rx_id_delay;
813 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
814 delay |= dp83867->tx_id_delay <<
815 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
817 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
821 /* If specified, set io impedance */
822 if (dp83867->io_impedance >= 0)
823 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
824 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
825 dp83867->io_impedance);
827 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
828 /* For support SPEED_10 in SGMII mode
829 * DP83867_10M_SGMII_RATE_ADAPT bit
830 * has to be cleared by software. That
831 * does not affect SPEED_100 and
834 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
835 DP83867_10M_SGMII_CFG,
836 DP83867_10M_SGMII_RATE_ADAPT_MASK,
841 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
842 * are 01). That is not enough to finalize autoneg on some
843 * devices. Increase this timer duration to maximum 16ms.
845 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
847 DP83867_CFG4_SGMII_ANEG_MASK,
848 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
853 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
854 /* SGMII type is set to 4-wire mode by default.
855 * If we place appropriate property in dts (see above)
856 * switch on 6-wire mode.
858 if (dp83867->sgmii_ref_clk_en)
859 val |= DP83867_SGMII_TYPE;
861 val &= ~DP83867_SGMII_TYPE;
862 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
864 /* This is a SW workaround for link instability if RX_CTRL is
865 * not strapped to mode 3 or 4 in HW. This is required for SGMII
866 * in addition to clearing bit 7, handled above.
868 if (dp83867->rxctrl_strap_quirk)
869 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
873 val = phy_read(phydev, DP83867_CFG3);
874 /* Enable Interrupt output INT_OE in CFG3 register */
875 if (phy_interrupt_is_valid(phydev))
876 val |= DP83867_CFG3_INT_OE;
878 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
879 phy_write(phydev, DP83867_CFG3, val);
881 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
882 dp83867_config_port_mirroring(phydev);
884 /* Clock output selection if muxing property is set */
885 if (dp83867->set_clk_output) {
886 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
888 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
889 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
891 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
892 val = dp83867->clk_output_sel <<
893 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
896 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
903 static int dp83867_phy_reset(struct phy_device *phydev)
907 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
911 usleep_range(10, 20);
913 return phy_modify(phydev, MII_DP83867_PHYCTRL,
914 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
917 static void dp83867_link_change_notify(struct phy_device *phydev)
919 /* There is a limitation in DP83867 PHY device where SGMII AN is
920 * only triggered once after the device is booted up. Even after the
921 * PHY TPI is down and up again, SGMII AN is not triggered and
922 * hence no new in-band message from PHY to MAC side SGMII.
923 * This could cause an issue during power up, when PHY is up prior
924 * to MAC. At this condition, once MAC side SGMII is up, MAC side
925 * SGMII wouldn`t receive new in-band message from TI PHY with
926 * correct link status, speed and duplex info.
927 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
928 * whenever there is a link change.
930 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
933 val = phy_clear_bits(phydev, DP83867_CFG2,
934 DP83867_SGMII_AUTONEG_EN);
938 phy_set_bits(phydev, DP83867_CFG2,
939 DP83867_SGMII_AUTONEG_EN);
943 static int dp83867_loopback(struct phy_device *phydev, bool enable)
945 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
946 enable ? BMCR_LOOPBACK : 0);
949 static struct phy_driver dp83867_driver[] = {
951 .phy_id = DP83867_PHY_ID,
952 .phy_id_mask = 0xfffffff0,
953 .name = "TI DP83867",
954 /* PHY_GBIT_FEATURES */
956 .probe = dp83867_probe,
957 .config_init = dp83867_config_init,
958 .soft_reset = dp83867_phy_reset,
960 .read_status = dp83867_read_status,
961 .get_tunable = dp83867_get_tunable,
962 .set_tunable = dp83867_set_tunable,
964 .get_wol = dp83867_get_wol,
965 .set_wol = dp83867_set_wol,
968 .config_intr = dp83867_config_intr,
969 .handle_interrupt = dp83867_handle_interrupt,
971 .suspend = genphy_suspend,
972 .resume = genphy_resume,
974 .link_change_notify = dp83867_link_change_notify,
975 .set_loopback = dp83867_loopback,
978 module_phy_driver(dp83867_driver);
980 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
981 { DP83867_PHY_ID, 0xfffffff0 },
985 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
987 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
988 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
989 MODULE_LICENSE("GPL v2");