2 * Broadcom BCM7xxx internal transceivers support.
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/brcmphy.h>
17 #include <linux/mdio.h>
19 /* Broadcom BCM7xxx internal PHY registers */
20 #define MII_BCM7XXX_CHANNEL_WIDTH 0x2000
22 /* 40nm only register definitions */
23 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
24 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
25 #define MII_BCM7XXX_100TX_DISC 0x14
26 #define MII_BCM7XXX_AUX_MODE 0x1d
27 #define MII_BCM7XX_64CLK_MDIO BIT(12)
28 #define MII_BCM7XXX_CORE_BASE1E 0x1e
29 #define MII_BCM7XXX_TEST 0x1f
30 #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
32 /* 28nm only register definitions */
33 #define MISC_ADDR(base, channel) base, channel
35 #define DSP_TAP10 MISC_ADDR(0x0a, 0)
36 #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
37 #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
38 #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
40 #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
41 #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
42 #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
43 #define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
44 #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
46 #define CORE_EXPB0 0xb0
48 static int bcm7445_config_init(struct phy_device *phydev)
51 const struct bcm7445_regs {
54 } bcm7445_regs_cfg[] = {
55 /* increases ADC latency by 24ns */
56 { MII_BCM54XX_EXP_SEL, 0x0038 },
57 { MII_BCM54XX_EXP_DATA, 0xAB95 },
58 /* increases internal 1V LDO voltage by 5% */
59 { MII_BCM54XX_EXP_SEL, 0x2038 },
60 { MII_BCM54XX_EXP_DATA, 0xBB22 },
61 /* reduce RX low pass filter corner frequency */
62 { MII_BCM54XX_EXP_SEL, 0x6038 },
63 { MII_BCM54XX_EXP_DATA, 0xFFC5 },
64 /* reduce RX high pass filter corner frequency */
65 { MII_BCM54XX_EXP_SEL, 0x003a },
66 { MII_BCM54XX_EXP_DATA, 0x2002 },
70 for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
71 ret = phy_write(phydev,
72 bcm7445_regs_cfg[i].reg,
73 bcm7445_regs_cfg[i].value);
81 static void phy_write_exp(struct phy_device *phydev,
84 phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);
85 phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
88 static void phy_write_misc(struct phy_device *phydev,
89 u16 reg, u16 chl, u16 value)
93 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
95 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
96 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
97 phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
99 tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) | reg;
100 phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);
102 phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
105 static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
107 /* Increase VCO range to prevent unlocking problem of PLL at low
110 phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
112 /* Change Ki to 011 */
113 phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
115 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
118 phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
120 /* Adjust bias current trim by -3 */
121 phy_write_misc(phydev, DSP_TAP10, 0x690b);
123 /* Switch to CORE_BASE1E */
124 phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
126 /* Reset R_CAL/RC_CAL Engine */
127 phy_write_exp(phydev, CORE_EXPB0, 0x0010);
129 /* Disable Reset R_CAL/RC_CAL Engine */
130 phy_write_exp(phydev, CORE_EXPB0, 0x0000);
132 /* write AFE_RXCONFIG_0 */
133 phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
135 /* write AFE_RXCONFIG_1 */
136 phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
138 /* write AFE_RX_LP_COUNTER */
139 phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
141 /* write AFE_HPF_TRIM_OTHERS */
142 phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
144 /* write AFTE_TX_CONFIG */
145 phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
150 static int bcm7xxx_apd_enable(struct phy_device *phydev)
154 /* Enable powering down of the DLL during auto-power down */
155 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
159 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
160 bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
162 /* Enable auto-power down */
163 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
167 val |= BCM54XX_SHD_APD_EN;
168 return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
171 static int bcm7xxx_eee_enable(struct phy_device *phydev)
175 val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
176 MDIO_MMD_AN, phydev->addr);
180 /* Enable general EEE feature at the PHY level */
181 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
183 phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
184 MDIO_MMD_AN, phydev->addr, val);
186 /* Advertise supported modes */
187 val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
188 MDIO_MMD_AN, phydev->addr);
190 val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
191 phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
192 MDIO_MMD_AN, phydev->addr, val);
197 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
199 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
200 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
203 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
204 dev_name(&phydev->dev), phydev->drv->name, rev, patch);
209 ret = bcm7445_config_init(phydev);
212 ret = bcm7xxx_28nm_afe_config_init(phydev);
219 ret = bcm7xxx_eee_enable(phydev);
223 return bcm7xxx_apd_enable(phydev);
226 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
230 /* Re-apply workarounds coming out suspend/resume */
231 ret = bcm7xxx_28nm_config_init(phydev);
235 /* 28nm Gigabit PHYs come out of reset without any half-duplex
236 * or "hub" compliant advertised mode, fix that. This does not
237 * cause any problems with the PHY library since genphy_config_aneg()
238 * gracefully handles auto-negotiated and forced modes.
240 return genphy_config_aneg(phydev);
243 static int phy_set_clr_bits(struct phy_device *dev, int location,
244 int set_mask, int clr_mask)
248 v = phy_read(dev, location);
255 ret = phy_write(dev, location, v);
262 static int bcm7xxx_config_init(struct phy_device *phydev)
266 /* Enable 64 clock MDIO */
267 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
268 phy_read(phydev, MII_BCM7XXX_AUX_MODE);
270 /* Workaround only required for 100Mbits/sec capable PHYs */
271 if (phydev->supported & PHY_GBIT_FEATURES)
274 /* set shadow mode 2 */
275 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
276 MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
280 /* set iddq_clkbias */
281 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
284 /* reset iddq_clkbias */
285 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
287 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
289 /* reset shadow mode 2 */
290 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
297 /* Workaround for putting the PHY in IDDQ mode, required
298 * for all BCM7XXX 40nm and 65nm PHYs
300 static int bcm7xxx_suspend(struct phy_device *phydev)
303 const struct bcm7xxx_regs {
306 } bcm7xxx_suspend_cfg[] = {
307 { MII_BCM7XXX_TEST, 0x008b },
308 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
309 { MII_BCM7XXX_100TX_DISC, 0x7000 },
310 { MII_BCM7XXX_TEST, 0x000f },
311 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
312 { MII_BCM7XXX_TEST, 0x000b },
316 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
317 ret = phy_write(phydev,
318 bcm7xxx_suspend_cfg[i].reg,
319 bcm7xxx_suspend_cfg[i].value);
327 static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
332 #define BCM7XXX_28NM_GPHY(_oui, _name) \
335 .phy_id_mask = 0xfffffff0, \
337 .features = PHY_GBIT_FEATURES | \
338 SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
339 .flags = PHY_IS_INTERNAL, \
340 .config_init = bcm7xxx_28nm_afe_config_init, \
341 .config_aneg = genphy_config_aneg, \
342 .read_status = genphy_read_status, \
343 .resume = bcm7xxx_28nm_resume, \
344 .driver = { .owner = THIS_MODULE }, \
347 static struct phy_driver bcm7xxx_driver[] = {
348 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
349 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
350 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
351 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
352 BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
354 .phy_id = PHY_ID_BCM7425,
355 .phy_id_mask = 0xfffffff0,
356 .name = "Broadcom BCM7425",
357 .features = PHY_GBIT_FEATURES |
358 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
360 .config_init = bcm7xxx_config_init,
361 .config_aneg = genphy_config_aneg,
362 .read_status = genphy_read_status,
363 .suspend = bcm7xxx_suspend,
364 .resume = bcm7xxx_config_init,
365 .driver = { .owner = THIS_MODULE },
367 .phy_id = PHY_ID_BCM7429,
368 .phy_id_mask = 0xfffffff0,
369 .name = "Broadcom BCM7429",
370 .features = PHY_GBIT_FEATURES |
371 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
372 .flags = PHY_IS_INTERNAL,
373 .config_init = bcm7xxx_config_init,
374 .config_aneg = genphy_config_aneg,
375 .read_status = genphy_read_status,
376 .suspend = bcm7xxx_suspend,
377 .resume = bcm7xxx_config_init,
378 .driver = { .owner = THIS_MODULE },
380 .phy_id = PHY_BCM_OUI_4,
381 .phy_id_mask = 0xffff0000,
382 .name = "Broadcom BCM7XXX 40nm",
383 .features = PHY_GBIT_FEATURES |
384 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
385 .flags = PHY_IS_INTERNAL,
386 .config_init = bcm7xxx_config_init,
387 .config_aneg = genphy_config_aneg,
388 .read_status = genphy_read_status,
389 .suspend = bcm7xxx_suspend,
390 .resume = bcm7xxx_config_init,
391 .driver = { .owner = THIS_MODULE },
393 .phy_id = PHY_BCM_OUI_5,
394 .phy_id_mask = 0xffffff00,
395 .name = "Broadcom BCM7XXX 65nm",
396 .features = PHY_BASIC_FEATURES |
397 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
398 .flags = PHY_IS_INTERNAL,
399 .config_init = bcm7xxx_dummy_config_init,
400 .config_aneg = genphy_config_aneg,
401 .read_status = genphy_read_status,
402 .suspend = bcm7xxx_suspend,
403 .resume = bcm7xxx_config_init,
404 .driver = { .owner = THIS_MODULE },
407 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
408 { PHY_ID_BCM7250, 0xfffffff0, },
409 { PHY_ID_BCM7364, 0xfffffff0, },
410 { PHY_ID_BCM7366, 0xfffffff0, },
411 { PHY_ID_BCM7425, 0xfffffff0, },
412 { PHY_ID_BCM7429, 0xfffffff0, },
413 { PHY_ID_BCM7439, 0xfffffff0, },
414 { PHY_ID_BCM7445, 0xfffffff0, },
415 { PHY_BCM_OUI_4, 0xffff0000 },
416 { PHY_BCM_OUI_5, 0xffffff00 },
420 module_phy_driver(bcm7xxx_driver);
422 MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
424 MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
425 MODULE_LICENSE("GPL");
426 MODULE_AUTHOR("Broadcom Corporation");