2 * drivers/net/phy/at803x.c
4 * Driver for Atheros 803x PHY
6 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/phy.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/of_gpio.h>
20 #include <linux/gpio/consumer.h>
22 #define AT803X_INTR_ENABLE 0x12
23 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
24 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
25 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
26 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
27 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
28 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
29 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
30 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
31 #define AT803X_INTR_ENABLE_WOL BIT(0)
33 #define AT803X_INTR_STATUS 0x13
35 #define AT803X_SMART_SPEED 0x14
36 #define AT803X_LED_CONTROL 0x18
38 #define AT803X_DEVICE_ADDR 0x03
39 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
40 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
41 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
42 #define AT803X_MMD_ACCESS_CONTROL 0x0D
43 #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
44 #define AT803X_FUNC_DATA 0x4003
45 #define AT803X_REG_CHIP_CONFIG 0x1f
46 #define AT803X_BT_BX_REG_SEL 0x8000
48 #define AT803X_DEBUG_ADDR 0x1D
49 #define AT803X_DEBUG_DATA 0x1E
51 #define AT803X_MODE_CFG_MASK 0x0F
52 #define AT803X_MODE_CFG_SGMII 0x01
54 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
55 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
57 #define AT803X_DEBUG_REG_0 0x00
58 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
60 #define AT803X_DEBUG_REG_5 0x05
61 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
63 #define ATH8030_PHY_ID 0x004dd076
64 #define ATH8031_PHY_ID 0x004dd074
65 #define ATH8035_PHY_ID 0x004dd072
66 #define AT803X_PHY_ID_MASK 0xffffffef
68 MODULE_DESCRIPTION("Atheros 803x PHY driver");
69 MODULE_AUTHOR("Matus Ujhelyi");
70 MODULE_LICENSE("GPL");
76 struct at803x_context {
85 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
89 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
93 return phy_read(phydev, AT803X_DEBUG_DATA);
96 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
102 ret = at803x_debug_reg_read(phydev, reg);
110 return phy_write(phydev, AT803X_DEBUG_DATA, val);
113 static inline int at803x_disable_rx_delay(struct phy_device *phydev)
115 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
116 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
119 static inline int at803x_disable_tx_delay(struct phy_device *phydev)
121 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
122 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
125 /* save relevant PHY registers to private copy */
126 static void at803x_context_save(struct phy_device *phydev,
127 struct at803x_context *context)
129 context->bmcr = phy_read(phydev, MII_BMCR);
130 context->advertise = phy_read(phydev, MII_ADVERTISE);
131 context->control1000 = phy_read(phydev, MII_CTRL1000);
132 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
133 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
134 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
137 /* restore relevant PHY registers from private copy */
138 static void at803x_context_restore(struct phy_device *phydev,
139 const struct at803x_context *context)
141 phy_write(phydev, MII_BMCR, context->bmcr);
142 phy_write(phydev, MII_ADVERTISE, context->advertise);
143 phy_write(phydev, MII_CTRL1000, context->control1000);
144 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
145 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
146 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
149 static int at803x_set_wol(struct phy_device *phydev,
150 struct ethtool_wolinfo *wol)
152 struct net_device *ndev = phydev->attached_dev;
156 unsigned int i, offsets[] = {
157 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
158 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
159 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
165 if (wol->wolopts & WAKE_MAGIC) {
166 mac = (const u8 *) ndev->dev_addr;
168 if (!is_valid_ether_addr(mac))
171 for (i = 0; i < 3; i++) {
172 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
174 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
176 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
178 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
179 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
182 value = phy_read(phydev, AT803X_INTR_ENABLE);
183 value |= AT803X_INTR_ENABLE_WOL;
184 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
187 value = phy_read(phydev, AT803X_INTR_STATUS);
189 value = phy_read(phydev, AT803X_INTR_ENABLE);
190 value &= (~AT803X_INTR_ENABLE_WOL);
191 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
194 value = phy_read(phydev, AT803X_INTR_STATUS);
200 static void at803x_get_wol(struct phy_device *phydev,
201 struct ethtool_wolinfo *wol)
205 wol->supported = WAKE_MAGIC;
208 value = phy_read(phydev, AT803X_INTR_ENABLE);
209 if (value & AT803X_INTR_ENABLE_WOL)
210 wol->wolopts |= WAKE_MAGIC;
213 static int at803x_suspend(struct phy_device *phydev)
218 value = phy_read(phydev, AT803X_INTR_ENABLE);
219 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
222 value = BMCR_ISOLATE;
226 phy_modify(phydev, MII_BMCR, 0, value);
231 static int at803x_resume(struct phy_device *phydev)
233 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
236 static int at803x_probe(struct phy_device *phydev)
238 struct device *dev = &phydev->mdio.dev;
239 struct at803x_priv *priv;
241 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
250 static int at803x_config_init(struct phy_device *phydev)
254 ret = genphy_config_init(phydev);
258 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
259 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
260 phydev->interface == PHY_INTERFACE_MODE_RGMII) {
261 ret = at803x_disable_rx_delay(phydev);
266 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
267 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
268 phydev->interface == PHY_INTERFACE_MODE_RGMII) {
269 ret = at803x_disable_tx_delay(phydev);
277 static int at803x_ack_interrupt(struct phy_device *phydev)
281 err = phy_read(phydev, AT803X_INTR_STATUS);
283 return (err < 0) ? err : 0;
286 static int at803x_config_intr(struct phy_device *phydev)
291 value = phy_read(phydev, AT803X_INTR_ENABLE);
293 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
294 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
295 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
296 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
297 value |= AT803X_INTR_ENABLE_LINK_FAIL;
298 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
300 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
303 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
308 static void at803x_link_change_notify(struct phy_device *phydev)
310 struct at803x_priv *priv = phydev->priv;
313 * Conduct a hardware reset for AT8030 every time a link loss is
314 * signalled. This is necessary to circumvent a hardware bug that
315 * occurs when the cable is unplugged while TX packets are pending
316 * in the FIFO. In such cases, the FIFO enters an error mode it
317 * cannot recover from by software.
319 if (phydev->state == PHY_NOLINK) {
320 if (phydev->mdio.reset && !priv->phy_reset) {
321 struct at803x_context context;
323 at803x_context_save(phydev, &context);
325 phy_device_reset(phydev, 1);
327 phy_device_reset(phydev, 0);
330 at803x_context_restore(phydev, &context);
332 phydev_dbg(phydev, "%s(): phy was reset\n",
334 priv->phy_reset = true;
337 priv->phy_reset = false;
341 static int at803x_aneg_done(struct phy_device *phydev)
345 int aneg_done = genphy_aneg_done(phydev);
346 if (aneg_done != BMSR_ANEGCOMPLETE)
350 * in SGMII mode, if copper side autoneg is successful,
351 * also check SGMII side autoneg result
353 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
354 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
357 /* switch to SGMII/fiber page */
358 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
360 /* check if the SGMII link is OK. */
361 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
362 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
365 /* switch back to copper page */
366 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
371 static struct phy_driver at803x_driver[] = {
374 .phy_id = ATH8035_PHY_ID,
375 .name = "Atheros 8035 ethernet",
376 .phy_id_mask = AT803X_PHY_ID_MASK,
377 .probe = at803x_probe,
378 .config_init = at803x_config_init,
379 .set_wol = at803x_set_wol,
380 .get_wol = at803x_get_wol,
381 .suspend = at803x_suspend,
382 .resume = at803x_resume,
383 .features = PHY_GBIT_FEATURES,
384 .ack_interrupt = at803x_ack_interrupt,
385 .config_intr = at803x_config_intr,
388 .phy_id = ATH8030_PHY_ID,
389 .name = "Atheros 8030 ethernet",
390 .phy_id_mask = AT803X_PHY_ID_MASK,
391 .probe = at803x_probe,
392 .config_init = at803x_config_init,
393 .link_change_notify = at803x_link_change_notify,
394 .set_wol = at803x_set_wol,
395 .get_wol = at803x_get_wol,
396 .suspend = at803x_suspend,
397 .resume = at803x_resume,
398 .features = PHY_BASIC_FEATURES,
399 .ack_interrupt = at803x_ack_interrupt,
400 .config_intr = at803x_config_intr,
403 .phy_id = ATH8031_PHY_ID,
404 .name = "Atheros 8031 ethernet",
405 .phy_id_mask = AT803X_PHY_ID_MASK,
406 .probe = at803x_probe,
407 .config_init = at803x_config_init,
408 .set_wol = at803x_set_wol,
409 .get_wol = at803x_get_wol,
410 .suspend = at803x_suspend,
411 .resume = at803x_resume,
412 .features = PHY_GBIT_FEATURES,
413 .aneg_done = at803x_aneg_done,
414 .ack_interrupt = &at803x_ack_interrupt,
415 .config_intr = &at803x_config_intr,
418 module_phy_driver(at803x_driver);
420 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
421 { ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
422 { ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
423 { ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
427 MODULE_DEVICE_TABLE(mdio, atheros_tbl);