2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
36 #define MASK(n) ((1ULL<<(n))-1)
37 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
38 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
39 #define MS_WIN(addr) (addr & 0x0ffc0000)
41 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
43 #define CRB_BLK(off) ((off >> 20) & 0x3f)
44 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
45 #define CRB_WINDOW_2M (0x130060)
46 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
47 #define CRB_INDIRECT_2M (0x1e0000UL)
50 static inline u64 readq(void __iomem *addr)
52 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
57 static inline void writeq(u64 val, void __iomem *addr)
59 writel(((u32) (val)), (addr));
60 writel(((u32) (val >> 32)), (addr + 4));
64 #define ADDR_IN_RANGE(addr, low, high) \
65 (((addr) < (high)) && ((addr) >= (low)))
67 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base0 + (off))
69 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
71 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
77 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
78 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
81 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
84 return PCI_OFFSET_THIRD_RANGE(adapter, off);
89 static crb_128M_2M_block_map_t
90 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
91 {{{0, 0, 0, 0} } }, /* 0: PCI */
92 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
93 {1, 0x0110000, 0x0120000, 0x130000},
94 {1, 0x0120000, 0x0122000, 0x124000},
95 {1, 0x0130000, 0x0132000, 0x126000},
96 {1, 0x0140000, 0x0142000, 0x128000},
97 {1, 0x0150000, 0x0152000, 0x12a000},
98 {1, 0x0160000, 0x0170000, 0x110000},
99 {1, 0x0170000, 0x0172000, 0x12e000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x01e0000, 0x01e0800, 0x122000},
107 {0, 0x0000000, 0x0000000, 0x000000} } },
108 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
109 {{{0, 0, 0, 0} } }, /* 3: */
110 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
111 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
112 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
113 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
114 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x08f0000, 0x08f2000, 0x172000} } },
130 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x09f0000, 0x09f2000, 0x176000} } },
146 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
162 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
178 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
179 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
180 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
181 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
182 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
183 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
184 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
185 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
186 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
187 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
188 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
189 {{{0, 0, 0, 0} } }, /* 23: */
190 {{{0, 0, 0, 0} } }, /* 24: */
191 {{{0, 0, 0, 0} } }, /* 25: */
192 {{{0, 0, 0, 0} } }, /* 26: */
193 {{{0, 0, 0, 0} } }, /* 27: */
194 {{{0, 0, 0, 0} } }, /* 28: */
195 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
196 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
197 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
198 {{{0} } }, /* 32: PCI */
199 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
200 {1, 0x2110000, 0x2120000, 0x130000},
201 {1, 0x2120000, 0x2122000, 0x124000},
202 {1, 0x2130000, 0x2132000, 0x126000},
203 {1, 0x2140000, 0x2142000, 0x128000},
204 {1, 0x2150000, 0x2152000, 0x12a000},
205 {1, 0x2160000, 0x2170000, 0x110000},
206 {1, 0x2170000, 0x2172000, 0x12e000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000} } },
215 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
221 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
222 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
223 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
224 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
225 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
226 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
227 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
228 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
229 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
230 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
231 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
232 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
234 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
235 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
236 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
237 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
238 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
239 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
240 {{{0} } }, /* 59: I2C0 */
241 {{{0} } }, /* 60: I2C1 */
242 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
243 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
244 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
248 * top 12 bits of crb internal address (hub, agent)
250 static unsigned crb_hub_agt[64] =
253 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
254 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
258 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
259 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
266 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
268 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
281 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
283 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
285 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
286 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
292 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
301 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
302 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
303 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
308 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
311 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
314 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
318 /* PCI Windowing for DDR regions. */
320 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
322 #define NETXEN_PCIE_SEM_TIMEOUT 10000
325 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
327 int done = 0, timeout = 0;
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
339 NXWR32(adapter, id_reg, adapter->portnum);
345 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
348 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
351 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
361 /* Disable an XG interface */
362 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
365 u32 port = adapter->physical_port;
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
380 #define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382 #define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384 #define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386 #define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
389 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
392 u32 port = adapter->physical_port;
394 if (port > NETXEN_NIU_MAX_XG_PORTS)
397 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
398 if (mode == NETXEN_NIU_PROMISC_MODE)
399 reg = (reg | 0x2000UL);
401 reg = (reg & ~0x2000UL);
403 if (mode == NETXEN_NIU_ALLMULTI_MODE)
404 reg = (reg | 0x1000UL);
406 reg = (reg & ~0x1000UL);
408 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
413 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
418 u8 phy = adapter->physical_port;
420 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
423 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
424 mac_hi = addr[2] | ((u32)addr[3] << 8) |
425 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
427 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
428 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
430 /* write twice to flush */
431 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
433 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
440 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
443 u16 port = adapter->physical_port;
444 u8 *addr = adapter->netdev->dev_addr;
446 if (adapter->mc_enabled)
449 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
450 val |= (1UL << (28+port));
451 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
453 /* add broadcast addr to filter */
455 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
456 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
458 /* add station addr to filter */
460 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
462 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
464 adapter->mc_enabled = 1;
469 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
472 u16 port = adapter->physical_port;
473 u8 *addr = adapter->netdev->dev_addr;
475 if (!adapter->mc_enabled)
478 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
479 val &= ~(1UL << (28+port));
480 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
490 adapter->mc_enabled = 0;
495 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
499 u16 port = adapter->physical_port;
504 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
505 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
510 void netxen_p2_nic_set_multi(struct net_device *netdev)
512 struct netxen_adapter *adapter = netdev_priv(netdev);
513 struct dev_mc_list *mc_ptr;
517 memset(null_addr, 0, 6);
519 if (netdev->flags & IFF_PROMISC) {
521 adapter->set_promisc(adapter,
522 NETXEN_NIU_PROMISC_MODE);
524 /* Full promiscuous mode */
525 netxen_nic_disable_mcast_filter(adapter);
530 if (netdev->mc_count == 0) {
531 adapter->set_promisc(adapter,
532 NETXEN_NIU_NON_PROMISC_MODE);
533 netxen_nic_disable_mcast_filter(adapter);
537 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
538 if (netdev->flags & IFF_ALLMULTI ||
539 netdev->mc_count > adapter->max_mc_count) {
540 netxen_nic_disable_mcast_filter(adapter);
544 netxen_nic_enable_mcast_filter(adapter);
546 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
547 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
549 if (index != netdev->mc_count)
550 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
551 netxen_nic_driver_name, netdev->name);
553 /* Clear out remaining addresses */
554 for (; index < adapter->max_mc_count; index++)
555 netxen_nic_set_mcast_addr(adapter, index, null_addr);
559 netxen_send_cmd_descs(struct netxen_adapter *adapter,
560 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
562 u32 i, producer, consumer;
563 struct netxen_cmd_buffer *pbuf;
564 struct cmd_desc_type0 *cmd_desc;
565 struct nx_host_tx_ring *tx_ring;
569 tx_ring = adapter->tx_ring;
570 __netif_tx_lock_bh(tx_ring->txq);
572 producer = tx_ring->producer;
573 consumer = tx_ring->sw_consumer;
575 if (nr_desc >= netxen_tx_avail(tx_ring)) {
576 netif_tx_stop_queue(tx_ring->txq);
577 __netif_tx_unlock_bh(tx_ring->txq);
582 cmd_desc = &cmd_desc_arr[i];
584 pbuf = &tx_ring->cmd_buf_arr[producer];
586 pbuf->frag_count = 0;
588 memcpy(&tx_ring->desc_head[producer],
589 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
591 producer = get_next_index(producer, tx_ring->num_desc);
594 } while (i != nr_desc);
596 tx_ring->producer = producer;
598 netxen_nic_update_cmd_producer(adapter, tx_ring);
600 __netif_tx_unlock_bh(tx_ring->txq);
606 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
609 nx_mac_req_t *mac_req;
612 memset(&req, 0, sizeof(nx_nic_req_t));
613 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
615 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
616 req.req_hdr = cpu_to_le64(word);
618 mac_req = (nx_mac_req_t *)&req.words[0];
620 memcpy(mac_req->mac_addr, addr, 6);
622 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
625 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
626 u8 *addr, struct list_head *del_list)
628 struct list_head *head;
631 /* look up if already exists */
632 list_for_each(head, del_list) {
633 cur = list_entry(head, nx_mac_list_t, list);
635 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
636 list_move_tail(head, &adapter->mac_list);
641 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
643 printk(KERN_ERR "%s: failed to add mac address filter\n",
644 adapter->netdev->name);
647 memcpy(cur->mac_addr, addr, ETH_ALEN);
648 list_add_tail(&cur->list, &adapter->mac_list);
649 return nx_p3_sre_macaddr_change(adapter,
650 cur->mac_addr, NETXEN_MAC_ADD);
653 void netxen_p3_nic_set_multi(struct net_device *netdev)
655 struct netxen_adapter *adapter = netdev_priv(netdev);
656 struct dev_mc_list *mc_ptr;
657 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
658 u32 mode = VPORT_MISS_MODE_DROP;
660 struct list_head *head;
663 list_splice_tail_init(&adapter->mac_list, &del_list);
665 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
666 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
668 if (netdev->flags & IFF_PROMISC) {
669 mode = VPORT_MISS_MODE_ACCEPT_ALL;
673 if ((netdev->flags & IFF_ALLMULTI) ||
674 (netdev->mc_count > adapter->max_mc_count)) {
675 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
679 if (netdev->mc_count > 0) {
680 for (mc_ptr = netdev->mc_list; mc_ptr;
681 mc_ptr = mc_ptr->next) {
682 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
687 adapter->set_promisc(adapter, mode);
689 while (!list_empty(head)) {
690 cur = list_entry(head->next, nx_mac_list_t, list);
692 nx_p3_sre_macaddr_change(adapter,
693 cur->mac_addr, NETXEN_MAC_DEL);
694 list_del(&cur->list);
699 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
704 memset(&req, 0, sizeof(nx_nic_req_t));
706 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
708 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
709 ((u64)adapter->portnum << 16);
710 req.req_hdr = cpu_to_le64(word);
712 req.words[0] = cpu_to_le64(mode);
714 return netxen_send_cmd_descs(adapter,
715 (struct cmd_desc_type0 *)&req, 1);
718 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
721 struct list_head *head = &adapter->mac_list;
723 while (!list_empty(head)) {
724 cur = list_entry(head->next, nx_mac_list_t, list);
725 nx_p3_sre_macaddr_change(adapter,
726 cur->mac_addr, NETXEN_MAC_DEL);
727 list_del(&cur->list);
732 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
734 /* assuming caller has already copied new addr to netdev */
735 netxen_p3_nic_set_multi(adapter->netdev);
739 #define NETXEN_CONFIG_INTR_COALESCE 3
742 * Send the interrupt coalescing parameter set by ethtool to the card.
744 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
750 memset(&req, 0, sizeof(nx_nic_req_t));
752 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
754 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
755 req.req_hdr = cpu_to_le64(word);
757 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
759 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
761 printk(KERN_ERR "ERROR. Could not send "
762 "interrupt coalescing parameters\n");
768 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
774 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
777 memset(&req, 0, sizeof(nx_nic_req_t));
779 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
781 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
782 req.req_hdr = cpu_to_le64(word);
784 req.words[0] = cpu_to_le64(enable);
786 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
788 printk(KERN_ERR "ERROR. Could not send "
789 "configure hw lro request\n");
792 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
797 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
803 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
806 memset(&req, 0, sizeof(nx_nic_req_t));
808 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
810 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
811 ((u64)adapter->portnum << 16);
812 req.req_hdr = cpu_to_le64(word);
814 req.words[0] = cpu_to_le64(enable);
816 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
818 printk(KERN_ERR "ERROR. Could not send "
819 "configure bridge mode request\n");
822 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
828 #define RSS_HASHTYPE_IP_TCP 0x3
830 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
836 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
837 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
838 0x255b0ec26d5a56daULL };
841 memset(&req, 0, sizeof(nx_nic_req_t));
842 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
844 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
849 * bits 3-0: hash_method
850 * 5-4: hash_type_ipv4
851 * 7-6: hash_type_ipv6
853 * 9: use indirection table
855 * 63-48: indirection table mask
857 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
858 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
859 ((u64)(enable & 0x1) << 8) |
861 req.words[0] = cpu_to_le64(word);
862 for (i = 0; i < 5; i++)
863 req.words[i+1] = cpu_to_le64(key[i]);
866 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
868 printk(KERN_ERR "%s: could not configure RSS\n",
869 adapter->netdev->name);
875 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
881 memset(&req, 0, sizeof(nx_nic_req_t));
882 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
884 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
885 req.req_hdr = cpu_to_le64(word);
887 req.words[0] = cpu_to_le64(cmd);
888 req.words[1] = cpu_to_le64(ip);
890 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
892 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
893 adapter->netdev->name,
894 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
899 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
905 memset(&req, 0, sizeof(nx_nic_req_t));
906 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
908 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
909 req.req_hdr = cpu_to_le64(word);
910 req.words[0] = cpu_to_le64(enable | (enable << 8));
912 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
914 printk(KERN_ERR "%s: could not configure link notification\n",
915 adapter->netdev->name);
921 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
927 memset(&req, 0, sizeof(nx_nic_req_t));
928 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
930 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
931 ((u64)adapter->portnum << 16) |
932 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
934 req.req_hdr = cpu_to_le64(word);
936 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
938 printk(KERN_ERR "%s: could not cleanup lro flows\n",
939 adapter->netdev->name);
945 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
946 * @returns 0 on success, negative on failure
949 #define MTU_FUDGE_FACTOR 100
951 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
953 struct netxen_adapter *adapter = netdev_priv(netdev);
957 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
958 max_mtu = P3_MAX_MTU;
960 max_mtu = P2_MAX_MTU;
963 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
964 netdev->name, max_mtu);
968 if (adapter->set_mtu)
969 rc = adapter->set_mtu(adapter, mtu);
977 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
978 int size, __le32 * buf)
985 for (i = 0; i < size / sizeof(u32); i++) {
986 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
988 *ptr32 = cpu_to_le32(v);
992 if ((char *)buf + size > (char *)ptr32) {
994 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
996 local = cpu_to_le32(v);
997 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1003 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1005 __le32 *pmac = (__le32 *) mac;
1008 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1010 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1013 if (*mac == cpu_to_le64(~0ULL)) {
1015 offset = NX_OLD_MAC_ADDR_OFFSET +
1016 (adapter->portnum * sizeof(u64));
1018 if (netxen_get_flash_block(adapter,
1019 offset, sizeof(u64), pmac) == -1)
1022 if (*mac == cpu_to_le64(~0ULL))
1028 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1030 uint32_t crbaddr, mac_hi, mac_lo;
1031 int pci_func = adapter->ahw.pci_func;
1033 crbaddr = CRB_MAC_BLOCK_START +
1034 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1036 mac_lo = NXRD32(adapter, crbaddr);
1037 mac_hi = NXRD32(adapter, crbaddr+4);
1040 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1042 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1048 * Changes the CRB window to the specified window.
1051 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
1053 void __iomem *offset;
1056 uint8_t func = adapter->ahw.pci_func;
1058 if (adapter->curr_window == wndw)
1061 * Move the CRB window.
1062 * We need to write to the "direct access" region of PCI
1063 * to avoid a race condition where the window register has
1064 * not been successfully written across CRB before the target
1065 * register address is received by PCI. The direct region bypasses
1068 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1069 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1072 wndw = NETXEN_WINDOW_ONE;
1074 writel(wndw, offset);
1076 /* MUST make sure window is set before we forge on... */
1077 while ((tmp = readl(offset)) != wndw) {
1078 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1079 "registered properly: 0x%08x.\n",
1080 netxen_nic_driver_name, __func__, tmp);
1087 if (wndw == NETXEN_WINDOW_ONE)
1088 adapter->curr_window = 1;
1090 adapter->curr_window = 0;
1094 * Return -1 if off is not valid,
1095 * 1 if window access is needed. 'off' is set to offset from
1096 * CRB space in 128M pci map
1097 * 0 if no window access is needed. 'off' is set to 2M addr
1098 * In: 'off' is offset from base in 128M pci map
1101 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1103 crb_128M_2M_sub_block_map_t *m;
1106 if (*off >= NETXEN_CRB_MAX)
1109 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1110 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1111 (ulong)adapter->ahw.pci_base0;
1115 if (*off < NETXEN_PCI_CRBSPACE)
1118 *off -= NETXEN_PCI_CRBSPACE;
1123 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1125 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1126 *off = *off + m->start_2M - m->start_128M +
1127 (ulong)adapter->ahw.pci_base0;
1132 * Not in direct map, use crb window
1138 * In: 'off' is offset from CRB space in 128M pci map
1139 * Out: 'off' is 2M pci map addr
1140 * side effect: lock crb window
1143 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1147 adapter->crb_win = CRB_HI(*off);
1148 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1150 * Read back value to make sure write has gone through before trying
1153 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1154 if (win_read != adapter->crb_win) {
1155 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1156 "Read crbwin (0x%x), off=0x%lx\n",
1157 __func__, adapter->crb_win, win_read, *off);
1159 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1160 (ulong)adapter->ahw.pci_base0;
1164 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1168 if (ADDR_IN_WINDOW1(off)) {
1169 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1170 } else { /* Window 0 */
1171 addr = pci_base_offset(adapter, off);
1172 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1176 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1182 if (!ADDR_IN_WINDOW1(off))
1183 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1189 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1194 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1195 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1196 } else { /* Window 0 */
1197 addr = pci_base_offset(adapter, off);
1198 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1202 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1208 if (!ADDR_IN_WINDOW1(off))
1209 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1215 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1217 unsigned long flags = 0;
1220 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1223 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1230 write_lock_irqsave(&adapter->adapter_lock, flags);
1231 crb_win_lock(adapter);
1232 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1233 writel(data, (void __iomem *)off);
1234 crb_win_unlock(adapter);
1235 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1237 writel(data, (void __iomem *)off);
1244 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1246 unsigned long flags = 0;
1250 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1253 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1260 write_lock_irqsave(&adapter->adapter_lock, flags);
1261 crb_win_lock(adapter);
1262 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1263 data = readl((void __iomem *)off);
1264 crb_win_unlock(adapter);
1265 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1267 data = readl((void __iomem *)off);
1273 * check memory access boundary.
1274 * used by test agent. support ddr access only for now
1276 static unsigned long
1277 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1278 unsigned long long addr, int size)
1280 if (!ADDR_IN_RANGE(addr,
1281 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1282 !ADDR_IN_RANGE(addr+size-1,
1283 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1284 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1291 static int netxen_pci_set_window_warning_count;
1294 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1295 unsigned long long addr)
1297 void __iomem *offset;
1299 unsigned long long qdr_max;
1300 uint8_t func = adapter->ahw.pci_func;
1302 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1303 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1305 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1308 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1309 /* DDR network side */
1310 addr -= NETXEN_ADDR_DDR_NET;
1311 window = (addr >> 25) & 0x3ff;
1312 if (adapter->ahw.ddr_mn_window != window) {
1313 adapter->ahw.ddr_mn_window = window;
1314 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1315 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1316 writel(window, offset);
1317 /* MUST make sure window is set before we forge on... */
1320 addr -= (window * NETXEN_WINDOW_ONE);
1321 addr += NETXEN_PCI_DDR_NET;
1322 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1323 addr -= NETXEN_ADDR_OCM0;
1324 addr += NETXEN_PCI_OCM0;
1325 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1326 addr -= NETXEN_ADDR_OCM1;
1327 addr += NETXEN_PCI_OCM1;
1328 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1329 /* QDR network side */
1330 addr -= NETXEN_ADDR_QDR_NET;
1331 window = (addr >> 22) & 0x3f;
1332 if (adapter->ahw.qdr_sn_window != window) {
1333 adapter->ahw.qdr_sn_window = window;
1334 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1335 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1336 writel((window << 22), offset);
1337 /* MUST make sure window is set before we forge on... */
1340 addr -= (window * 0x400000);
1341 addr += NETXEN_PCI_QDR_NET;
1344 * peg gdb frequently accesses memory that doesn't exist,
1345 * this limits the chit chat so debugging isn't slowed down.
1347 if ((netxen_pci_set_window_warning_count++ < 8)
1348 || (netxen_pci_set_window_warning_count % 64 == 0))
1349 printk("%s: Warning:netxen_nic_pci_set_window()"
1350 " Unknown address range!\n",
1351 netxen_nic_driver_name);
1358 * Note : only 32-bit writes!
1360 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1363 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1367 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1369 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1373 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1374 unsigned long long addr)
1379 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1380 /* DDR network side */
1381 window = MN_WIN(addr);
1382 adapter->ahw.ddr_mn_window = window;
1383 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1385 win_read = NXRD32(adapter,
1386 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1387 if ((win_read << 17) != window) {
1388 printk(KERN_INFO "Written MNwin (0x%x) != "
1389 "Read MNwin (0x%x)\n", window, win_read);
1391 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1392 } else if (ADDR_IN_RANGE(addr,
1393 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1394 if ((addr & 0x00ff800) == 0xff800) {
1395 printk("%s: QM access not handled.\n", __func__);
1399 window = OCM_WIN(addr);
1400 adapter->ahw.ddr_mn_window = window;
1401 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1403 win_read = NXRD32(adapter,
1404 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1405 if ((win_read >> 7) != window) {
1406 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1407 "Read OCMwin (0x%x)\n",
1408 __func__, window, win_read);
1410 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1412 } else if (ADDR_IN_RANGE(addr,
1413 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1414 /* QDR network side */
1415 window = MS_WIN(addr);
1416 adapter->ahw.qdr_sn_window = window;
1417 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1419 win_read = NXRD32(adapter,
1420 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1421 if (win_read != window) {
1422 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1423 "Read MSwin (0x%x)\n",
1424 __func__, window, win_read);
1426 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1430 * peg gdb frequently accesses memory that doesn't exist,
1431 * this limits the chit chat so debugging isn't slowed down.
1433 if ((netxen_pci_set_window_warning_count++ < 8)
1434 || (netxen_pci_set_window_warning_count%64 == 0)) {
1435 printk("%s: Warning:%s Unknown address range!\n",
1436 __func__, netxen_nic_driver_name);
1443 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1444 unsigned long long addr)
1447 unsigned long long qdr_max;
1449 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1450 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1452 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1454 if (ADDR_IN_RANGE(addr,
1455 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1456 /* DDR network side */
1457 BUG(); /* MN access can not come here */
1458 } else if (ADDR_IN_RANGE(addr,
1459 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1461 } else if (ADDR_IN_RANGE(addr,
1462 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1464 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1465 /* QDR network side */
1466 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1467 if (adapter->ahw.qdr_sn_window == window)
1474 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1475 u64 off, void *data, int size)
1477 unsigned long flags;
1478 void __iomem *addr, *mem_ptr = NULL;
1481 unsigned long mem_base;
1482 unsigned long mem_page;
1484 write_lock_irqsave(&adapter->adapter_lock, flags);
1487 * If attempting to access unknown address or straddle hw windows,
1490 start = adapter->pci_set_window(adapter, off);
1491 if ((start == -1UL) ||
1492 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1493 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1494 printk(KERN_ERR "%s out of bound pci memory access. "
1495 "offset is 0x%llx\n", netxen_nic_driver_name,
1496 (unsigned long long)off);
1500 addr = pci_base_offset(adapter, start);
1502 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1503 mem_base = pci_resource_start(adapter->pdev, 0);
1504 mem_page = start & PAGE_MASK;
1505 /* Map two pages whenever user tries to access addresses in two
1508 if (mem_page != ((start + size - 1) & PAGE_MASK))
1509 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1511 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1512 if (mem_ptr == NULL) {
1513 *(uint8_t *)data = 0;
1517 addr += start & (PAGE_SIZE - 1);
1518 write_lock_irqsave(&adapter->adapter_lock, flags);
1523 *(uint8_t *)data = readb(addr);
1526 *(uint16_t *)data = readw(addr);
1529 *(uint32_t *)data = readl(addr);
1532 *(uint64_t *)data = readq(addr);
1538 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1546 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1547 void *data, int size)
1549 unsigned long flags;
1550 void __iomem *addr, *mem_ptr = NULL;
1553 unsigned long mem_base;
1554 unsigned long mem_page;
1556 write_lock_irqsave(&adapter->adapter_lock, flags);
1559 * If attempting to access unknown address or straddle hw windows,
1562 start = adapter->pci_set_window(adapter, off);
1563 if ((start == -1UL) ||
1564 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1565 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1566 printk(KERN_ERR "%s out of bound pci memory access. "
1567 "offset is 0x%llx\n", netxen_nic_driver_name,
1568 (unsigned long long)off);
1572 addr = pci_base_offset(adapter, start);
1574 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1575 mem_base = pci_resource_start(adapter->pdev, 0);
1576 mem_page = start & PAGE_MASK;
1577 /* Map two pages whenever user tries to access addresses in two
1578 * consecutive pages.
1580 if (mem_page != ((start + size - 1) & PAGE_MASK))
1581 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1583 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1584 if (mem_ptr == NULL)
1587 addr += start & (PAGE_SIZE - 1);
1588 write_lock_irqsave(&adapter->adapter_lock, flags);
1593 writeb(*(uint8_t *)data, addr);
1596 writew(*(uint16_t *)data, addr);
1599 writel(*(uint32_t *)data, addr);
1602 writeq(*(uint64_t *)data, addr);
1608 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1614 #define MAX_CTL_CHECK 1000
1617 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1618 u64 off, void *data, int size)
1620 unsigned long flags;
1621 int i, j, ret = 0, loop, sz[2], off0;
1623 uint64_t off8, tmpw, word[2] = {0, 0};
1624 void __iomem *mem_crb;
1627 * If not MN, go check for MS or invalid.
1629 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1630 return netxen_nic_pci_mem_write_direct(adapter,
1633 off8 = off & 0xfffffff8;
1635 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1636 sz[1] = size - sz[0];
1637 loop = ((off0 + size - 1) >> 3) + 1;
1638 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1640 if ((size != 8) || (off0 != 0)) {
1641 for (i = 0; i < loop; i++) {
1642 if (adapter->pci_mem_read(adapter,
1643 off8 + (i << 3), &word[i], 8))
1650 tmpw = *((uint8_t *)data);
1653 tmpw = *((uint16_t *)data);
1656 tmpw = *((uint32_t *)data);
1660 tmpw = *((uint64_t *)data);
1663 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1664 word[0] |= tmpw << (off0 * 8);
1667 word[1] &= ~(~0ULL << (sz[1] * 8));
1668 word[1] |= tmpw >> (sz[0] * 8);
1671 write_lock_irqsave(&adapter->adapter_lock, flags);
1672 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1674 for (i = 0; i < loop; i++) {
1675 writel((uint32_t)(off8 + (i << 3)),
1676 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1678 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1679 writel(word[i] & 0xffffffff,
1680 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1681 writel((word[i] >> 32) & 0xffffffff,
1682 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1683 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1684 (mem_crb+MIU_TEST_AGT_CTRL));
1685 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1686 (mem_crb+MIU_TEST_AGT_CTRL));
1688 for (j = 0; j < MAX_CTL_CHECK; j++) {
1690 (mem_crb+MIU_TEST_AGT_CTRL));
1691 if ((temp & MIU_TA_CTL_BUSY) == 0)
1695 if (j >= MAX_CTL_CHECK) {
1696 if (printk_ratelimit())
1697 dev_err(&adapter->pdev->dev,
1698 "failed to write through agent\n");
1704 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1705 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1710 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1711 u64 off, void *data, int size)
1713 unsigned long flags;
1714 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1716 uint64_t off8, val, word[2] = {0, 0};
1717 void __iomem *mem_crb;
1721 * If not MN, go check for MS or invalid.
1723 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1724 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1726 off8 = off & 0xfffffff8;
1727 off0[0] = off & 0x7;
1729 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1730 sz[1] = size - sz[0];
1731 loop = ((off0[0] + size - 1) >> 3) + 1;
1732 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1734 write_lock_irqsave(&adapter->adapter_lock, flags);
1735 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1737 for (i = 0; i < loop; i++) {
1738 writel((uint32_t)(off8 + (i << 3)),
1739 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1741 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1742 writel(MIU_TA_CTL_ENABLE,
1743 (mem_crb+MIU_TEST_AGT_CTRL));
1744 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1745 (mem_crb+MIU_TEST_AGT_CTRL));
1747 for (j = 0; j < MAX_CTL_CHECK; j++) {
1749 (mem_crb+MIU_TEST_AGT_CTRL));
1750 if ((temp & MIU_TA_CTL_BUSY) == 0)
1754 if (j >= MAX_CTL_CHECK) {
1755 if (printk_ratelimit())
1756 dev_err(&adapter->pdev->dev,
1757 "failed to read through agent\n");
1761 start = off0[i] >> 2;
1762 end = (off0[i] + sz[i] - 1) >> 2;
1763 for (k = start; k <= end; k++) {
1764 word[i] |= ((uint64_t) readl(
1766 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1770 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1771 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1773 if (j >= MAX_CTL_CHECK)
1779 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1780 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1785 *(uint8_t *)data = val;
1788 *(uint16_t *)data = val;
1791 *(uint32_t *)data = val;
1794 *(uint64_t *)data = val;
1801 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1802 u64 off, void *data, int size)
1804 int i, j, ret = 0, loop, sz[2], off0;
1806 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1809 * If not MN, go check for MS or invalid.
1811 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1812 mem_crb = NETXEN_CRB_QDR_NET;
1814 mem_crb = NETXEN_CRB_DDR_NET;
1815 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1816 return netxen_nic_pci_mem_write_direct(adapter,
1820 off8 = off & 0xfffffff8;
1822 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1823 sz[1] = size - sz[0];
1824 loop = ((off0 + size - 1) >> 3) + 1;
1826 if ((size != 8) || (off0 != 0)) {
1827 for (i = 0; i < loop; i++) {
1828 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1836 tmpw = *((uint8_t *)data);
1839 tmpw = *((uint16_t *)data);
1842 tmpw = *((uint32_t *)data);
1846 tmpw = *((uint64_t *)data);
1850 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1851 word[0] |= tmpw << (off0 * 8);
1854 word[1] &= ~(~0ULL << (sz[1] * 8));
1855 word[1] |= tmpw >> (sz[0] * 8);
1859 * don't lock here - write_wx gets the lock if each time
1860 * write_lock_irqsave(&adapter->adapter_lock, flags);
1861 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1864 for (i = 0; i < loop; i++) {
1865 temp = off8 + (i << 3);
1866 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1868 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1869 temp = word[i] & 0xffffffff;
1870 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1871 temp = (word[i] >> 32) & 0xffffffff;
1872 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1873 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1874 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1875 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1876 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1878 for (j = 0; j < MAX_CTL_CHECK; j++) {
1879 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1880 if ((temp & MIU_TA_CTL_BUSY) == 0)
1884 if (j >= MAX_CTL_CHECK) {
1885 if (printk_ratelimit())
1886 dev_err(&adapter->pdev->dev,
1887 "failed to write through agent\n");
1894 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1895 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1901 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1902 u64 off, void *data, int size)
1904 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1906 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1909 * If not MN, go check for MS or invalid.
1912 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1913 mem_crb = NETXEN_CRB_QDR_NET;
1915 mem_crb = NETXEN_CRB_DDR_NET;
1916 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1917 return netxen_nic_pci_mem_read_direct(adapter,
1921 off8 = off & 0xfffffff8;
1922 off0[0] = off & 0x7;
1924 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1925 sz[1] = size - sz[0];
1926 loop = ((off0[0] + size - 1) >> 3) + 1;
1929 * don't lock here - write_wx gets the lock if each time
1930 * write_lock_irqsave(&adapter->adapter_lock, flags);
1931 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1934 for (i = 0; i < loop; i++) {
1935 temp = off8 + (i << 3);
1936 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1938 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1939 temp = MIU_TA_CTL_ENABLE;
1940 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1941 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1942 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1944 for (j = 0; j < MAX_CTL_CHECK; j++) {
1945 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1946 if ((temp & MIU_TA_CTL_BUSY) == 0)
1950 if (j >= MAX_CTL_CHECK) {
1951 if (printk_ratelimit())
1952 dev_err(&adapter->pdev->dev,
1953 "failed to read through agent\n");
1957 start = off0[i] >> 2;
1958 end = (off0[i] + sz[i] - 1) >> 2;
1959 for (k = start; k <= end; k++) {
1960 temp = NXRD32(adapter,
1961 mem_crb + MIU_TEST_AGT_RDDATA(k));
1962 word[i] |= ((uint64_t)temp << (32 * k));
1967 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1968 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1971 if (j >= MAX_CTL_CHECK)
1977 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1978 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1983 *(uint8_t *)data = val;
1986 *(uint16_t *)data = val;
1989 *(uint32_t *)data = val;
1992 *(uint64_t *)data = val;
1999 * Note : only 32-bit writes!
2001 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2004 NXWR32(adapter, off, data);
2009 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2011 return NXRD32(adapter, off);
2014 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2016 int offset, board_type, magic, header_version;
2017 struct pci_dev *pdev = adapter->pdev;
2019 offset = NX_FW_MAGIC_OFFSET;
2020 if (netxen_rom_fast_read(adapter, offset, &magic))
2023 offset = NX_HDR_VERSION_OFFSET;
2024 if (netxen_rom_fast_read(adapter, offset, &header_version))
2027 if (magic != NETXEN_BDINFO_MAGIC ||
2028 header_version != NETXEN_BDINFO_VERSION) {
2030 "invalid board config, magic=%08x, version=%08x\n",
2031 magic, header_version);
2035 offset = NX_BRDTYPE_OFFSET;
2036 if (netxen_rom_fast_read(adapter, offset, &board_type))
2039 adapter->ahw.board_type = board_type;
2041 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2042 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2043 if ((gpio & 0x8000) == 0)
2044 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2047 switch (board_type) {
2048 case NETXEN_BRDTYPE_P2_SB35_4G:
2049 adapter->ahw.port_type = NETXEN_NIC_GBE;
2051 case NETXEN_BRDTYPE_P2_SB31_10G:
2052 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2053 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2054 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2055 case NETXEN_BRDTYPE_P3_HMEZ:
2056 case NETXEN_BRDTYPE_P3_XG_LOM:
2057 case NETXEN_BRDTYPE_P3_10G_CX4:
2058 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2059 case NETXEN_BRDTYPE_P3_IMEZ:
2060 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2061 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2062 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2063 case NETXEN_BRDTYPE_P3_10G_XFP:
2064 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2065 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2067 case NETXEN_BRDTYPE_P1_BD:
2068 case NETXEN_BRDTYPE_P1_SB:
2069 case NETXEN_BRDTYPE_P1_SMAX:
2070 case NETXEN_BRDTYPE_P1_SOCK:
2071 case NETXEN_BRDTYPE_P3_REF_QG:
2072 case NETXEN_BRDTYPE_P3_4_GB:
2073 case NETXEN_BRDTYPE_P3_4_GB_MM:
2074 adapter->ahw.port_type = NETXEN_NIC_GBE;
2076 case NETXEN_BRDTYPE_P3_10G_TP:
2077 adapter->ahw.port_type = (adapter->portnum < 2) ?
2078 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2081 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2082 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2089 /* NIU access sections */
2091 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2093 new_mtu += MTU_FUDGE_FACTOR;
2094 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2099 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2101 new_mtu += MTU_FUDGE_FACTOR;
2102 if (adapter->physical_port == 0)
2103 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2105 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2109 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2115 if (!netif_carrier_ok(adapter->netdev)) {
2116 adapter->link_speed = 0;
2117 adapter->link_duplex = -1;
2118 adapter->link_autoneg = AUTONEG_ENABLE;
2122 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2123 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2124 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2125 adapter->link_speed = SPEED_1000;
2126 adapter->link_duplex = DUPLEX_FULL;
2127 adapter->link_autoneg = AUTONEG_DISABLE;
2131 if (adapter->phy_read
2132 && adapter->phy_read(adapter,
2133 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2135 if (netxen_get_phy_link(status)) {
2136 switch (netxen_get_phy_speed(status)) {
2138 adapter->link_speed = SPEED_10;
2141 adapter->link_speed = SPEED_100;
2144 adapter->link_speed = SPEED_1000;
2147 adapter->link_speed = 0;
2150 switch (netxen_get_phy_duplex(status)) {
2152 adapter->link_duplex = DUPLEX_HALF;
2155 adapter->link_duplex = DUPLEX_FULL;
2158 adapter->link_duplex = -1;
2161 if (adapter->phy_read
2162 && adapter->phy_read(adapter,
2163 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2165 adapter->link_autoneg = autoneg;
2170 adapter->link_speed = 0;
2171 adapter->link_duplex = -1;
2176 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2178 u32 fw_major, fw_minor, fw_build;
2179 char brd_name[NETXEN_MAX_SHORT_NAME];
2180 char serial_num[32];
2183 struct pci_dev *pdev = adapter->pdev;
2185 adapter->driver_mismatch = 0;
2187 ptr32 = (int *)&serial_num;
2188 offset = NX_FW_SERIAL_NUM_OFFSET;
2189 for (i = 0; i < 8; i++) {
2190 if (netxen_rom_fast_read(adapter, offset, &val) == -1) {
2191 dev_err(&pdev->dev, "error reading board info\n");
2192 adapter->driver_mismatch = 1;
2195 ptr32[i] = cpu_to_le32(val);
2196 offset += sizeof(u32);
2199 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2200 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2201 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2203 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2205 if (adapter->portnum == 0) {
2206 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2208 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2209 brd_name, serial_num, adapter->ahw.revision_id);
2212 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2213 adapter->driver_mismatch = 1;
2214 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2215 fw_major, fw_minor, fw_build);
2219 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2220 fw_major, fw_minor, fw_build);
2222 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2223 i = NXRD32(adapter, NETXEN_SRE_MISC);
2224 adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0;
2225 dev_info(&pdev->dev, "firmware running in %s mode\n",
2226 adapter->ahw.cut_through ? "cut-through" : "legacy");
2229 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
2230 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
2232 adapter->flags &= ~NETXEN_NIC_LRO_ENABLED;
2236 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2240 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2243 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2244 if (wol_cfg & (1UL << adapter->portnum)) {
2245 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2246 if (wol_cfg & (1 << adapter->portnum))