2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
44 #include <linux/mlx4/device.h>
45 #include <linux/mlx4/doorbell.h>
51 MODULE_AUTHOR("Roland Dreier");
52 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
53 MODULE_LICENSE("Dual BSD/GPL");
54 MODULE_VERSION(DRV_VERSION);
56 struct workqueue_struct *mlx4_wq;
58 #ifdef CONFIG_MLX4_DEBUG
60 int mlx4_debug_level = 0;
61 module_param_named(debug_level, mlx4_debug_level, int, 0644);
62 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
64 #endif /* CONFIG_MLX4_DEBUG */
69 module_param(msi_x, int, 0444);
70 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
72 #else /* CONFIG_PCI_MSI */
76 #endif /* CONFIG_PCI_MSI */
78 static char mlx4_version[] __devinitdata =
79 DRV_NAME ": Mellanox ConnectX core driver v"
80 DRV_VERSION " (" DRV_RELDATE ")\n";
82 static struct mlx4_profile default_profile = {
85 .rdmarc_per_qp = 1 << 4,
92 static int log_num_mac = 2;
93 module_param_named(log_num_mac, log_num_mac, int, 0444);
94 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
96 static int log_num_vlan;
97 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
98 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
101 module_param_named(use_prio, use_prio, bool, 0444);
102 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
105 static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
106 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
107 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
109 int mlx4_check_port_params(struct mlx4_dev *dev,
110 enum mlx4_port_type *port_type)
114 for (i = 0; i < dev->caps.num_ports - 1; i++) {
115 if (port_type[i] != port_type[i + 1]) {
116 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
117 mlx4_err(dev, "Only same port types supported "
118 "on this HCA, aborting.\n");
121 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
122 port_type[i + 1] == MLX4_PORT_TYPE_IB)
127 for (i = 0; i < dev->caps.num_ports; i++) {
128 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
129 mlx4_err(dev, "Requested port type for port %d is not "
130 "supported on this HCA\n", i + 1);
137 static void mlx4_set_port_mask(struct mlx4_dev *dev)
141 dev->caps.port_mask = 0;
142 for (i = 1; i <= dev->caps.num_ports; ++i)
143 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
144 dev->caps.port_mask |= 1 << (i - 1);
146 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
151 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
153 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
157 if (dev_cap->min_page_sz > PAGE_SIZE) {
158 mlx4_err(dev, "HCA minimum page size of %d bigger than "
159 "kernel PAGE_SIZE of %ld, aborting.\n",
160 dev_cap->min_page_sz, PAGE_SIZE);
163 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
164 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
166 dev_cap->num_ports, MLX4_MAX_PORTS);
170 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
171 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
172 "PCI resource 2 size of 0x%llx, aborting.\n",
174 (unsigned long long) pci_resource_len(dev->pdev, 2));
178 dev->caps.num_ports = dev_cap->num_ports;
179 for (i = 1; i <= dev->caps.num_ports; ++i) {
180 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
181 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
182 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
183 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
184 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
185 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
186 dev->caps.def_mac[i] = dev_cap->def_mac[i];
187 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
188 dev->caps.trans_type[i] = dev_cap->trans_type[i];
189 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
190 dev->caps.wavelength[i] = dev_cap->wavelength[i];
191 dev->caps.trans_code[i] = dev_cap->trans_code[i];
194 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
195 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
196 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
197 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
198 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
199 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
200 dev->caps.max_wqes = dev_cap->max_qp_sz;
201 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
202 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
203 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
204 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
205 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
206 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
207 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
209 * Subtract 1 from the limit because we need to allocate a
210 * spare CQE so the HCA HW can tell the difference between an
211 * empty CQ and a full CQ.
213 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
214 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
215 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
216 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
217 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
218 dev->caps.mtts_per_seg);
219 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
220 dev->caps.reserved_uars = dev_cap->reserved_uars;
221 dev->caps.reserved_pds = dev_cap->reserved_pds;
222 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
223 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
224 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
225 dev->caps.flags = dev_cap->flags;
226 dev->caps.bmme_flags = dev_cap->bmme_flags;
227 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
228 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
229 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
231 dev->caps.log_num_macs = log_num_mac;
232 dev->caps.log_num_vlans = log_num_vlan;
233 dev->caps.log_num_prios = use_prio ? 3 : 0;
235 for (i = 1; i <= dev->caps.num_ports; ++i) {
236 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
237 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
239 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
240 dev->caps.possible_type[i] = dev->caps.port_type[i];
241 mlx4_priv(dev)->sense.sense_allowed[i] =
242 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
244 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
245 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
246 mlx4_warn(dev, "Requested number of MACs is too much "
247 "for port %d, reducing to %d.\n",
248 i, 1 << dev->caps.log_num_macs);
250 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
251 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
252 mlx4_warn(dev, "Requested number of VLANs is too much "
253 "for port %d, reducing to %d.\n",
254 i, 1 << dev->caps.log_num_vlans);
258 mlx4_set_port_mask(dev);
260 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
262 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
263 (1 << dev->caps.log_num_macs) *
264 (1 << dev->caps.log_num_vlans) *
265 (1 << dev->caps.log_num_prios) *
267 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
269 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
270 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
271 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
272 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
278 * Change the port configuration of the device.
279 * Every user of this function must hold the port mutex.
281 int mlx4_change_port_types(struct mlx4_dev *dev,
282 enum mlx4_port_type *port_types)
288 for (port = 0; port < dev->caps.num_ports; port++) {
289 /* Change the port type only if the new type is different
290 * from the current, and not set to Auto */
291 if (port_types[port] != dev->caps.port_type[port + 1]) {
293 dev->caps.port_type[port + 1] = port_types[port];
297 mlx4_unregister_device(dev);
298 for (port = 1; port <= dev->caps.num_ports; port++) {
299 mlx4_CLOSE_PORT(dev, port);
300 err = mlx4_SET_PORT(dev, port);
302 mlx4_err(dev, "Failed to set port %d, "
307 mlx4_set_port_mask(dev);
308 err = mlx4_register_device(dev);
315 static ssize_t show_port_type(struct device *dev,
316 struct device_attribute *attr,
319 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
321 struct mlx4_dev *mdev = info->dev;
325 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
327 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
328 sprintf(buf, "auto (%s)\n", type);
330 sprintf(buf, "%s\n", type);
335 static ssize_t set_port_type(struct device *dev,
336 struct device_attribute *attr,
337 const char *buf, size_t count)
339 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
341 struct mlx4_dev *mdev = info->dev;
342 struct mlx4_priv *priv = mlx4_priv(mdev);
343 enum mlx4_port_type types[MLX4_MAX_PORTS];
344 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
348 if (!strcmp(buf, "ib\n"))
349 info->tmp_type = MLX4_PORT_TYPE_IB;
350 else if (!strcmp(buf, "eth\n"))
351 info->tmp_type = MLX4_PORT_TYPE_ETH;
352 else if (!strcmp(buf, "auto\n"))
353 info->tmp_type = MLX4_PORT_TYPE_AUTO;
355 mlx4_err(mdev, "%s is not supported port type\n", buf);
359 mlx4_stop_sense(mdev);
360 mutex_lock(&priv->port_mutex);
361 /* Possible type is always the one that was delivered */
362 mdev->caps.possible_type[info->port] = info->tmp_type;
364 for (i = 0; i < mdev->caps.num_ports; i++) {
365 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
366 mdev->caps.possible_type[i+1];
367 if (types[i] == MLX4_PORT_TYPE_AUTO)
368 types[i] = mdev->caps.port_type[i+1];
371 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
372 for (i = 1; i <= mdev->caps.num_ports; i++) {
373 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
374 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
380 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
381 "Set only 'eth' or 'ib' for both ports "
382 "(should be the same)\n");
386 mlx4_do_sense_ports(mdev, new_types, types);
388 err = mlx4_check_port_params(mdev, new_types);
392 /* We are about to apply the changes after the configuration
393 * was verified, no need to remember the temporary types
395 for (i = 0; i < mdev->caps.num_ports; i++)
396 priv->port[i + 1].tmp_type = 0;
398 err = mlx4_change_port_types(mdev, new_types);
401 mlx4_start_sense(mdev);
402 mutex_unlock(&priv->port_mutex);
403 return err ? err : count;
406 static int mlx4_load_fw(struct mlx4_dev *dev)
408 struct mlx4_priv *priv = mlx4_priv(dev);
411 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
412 GFP_HIGHUSER | __GFP_NOWARN, 0);
413 if (!priv->fw.fw_icm) {
414 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
418 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
420 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
424 err = mlx4_RUN_FW(dev);
426 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
436 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
440 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
443 struct mlx4_priv *priv = mlx4_priv(dev);
446 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
448 ((u64) (MLX4_CMPT_TYPE_QP *
449 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
450 cmpt_entry_sz, dev->caps.num_qps,
451 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
456 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
458 ((u64) (MLX4_CMPT_TYPE_SRQ *
459 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
460 cmpt_entry_sz, dev->caps.num_srqs,
461 dev->caps.reserved_srqs, 0, 0);
465 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
467 ((u64) (MLX4_CMPT_TYPE_CQ *
468 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
469 cmpt_entry_sz, dev->caps.num_cqs,
470 dev->caps.reserved_cqs, 0, 0);
474 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
476 ((u64) (MLX4_CMPT_TYPE_EQ *
477 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
479 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
486 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
489 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
492 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
498 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
499 struct mlx4_init_hca_param *init_hca, u64 icm_size)
501 struct mlx4_priv *priv = mlx4_priv(dev);
505 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
507 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
511 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
512 (unsigned long long) icm_size >> 10,
513 (unsigned long long) aux_pages << 2);
515 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
516 GFP_HIGHUSER | __GFP_NOWARN, 0);
517 if (!priv->fw.aux_icm) {
518 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
522 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
524 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
528 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
530 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
534 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
535 init_hca->eqc_base, dev_cap->eqc_entry_sz,
536 dev->caps.num_eqs, dev->caps.num_eqs,
539 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
544 * Reserved MTT entries must be aligned up to a cacheline
545 * boundary, since the FW will write to them, while the driver
546 * writes to all other MTT entries. (The variable
547 * dev->caps.mtt_entry_sz below is really the MTT segment
548 * size, not the raw entry size)
550 dev->caps.reserved_mtts =
551 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
552 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
554 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
556 dev->caps.mtt_entry_sz,
557 dev->caps.num_mtt_segs,
558 dev->caps.reserved_mtts, 1, 0);
560 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
564 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
566 dev_cap->dmpt_entry_sz,
568 dev->caps.reserved_mrws, 1, 1);
570 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
574 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
576 dev_cap->qpc_entry_sz,
578 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
581 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
585 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
587 dev_cap->aux_entry_sz,
589 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
592 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
596 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
598 dev_cap->altc_entry_sz,
600 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
603 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
607 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
608 init_hca->rdmarc_base,
609 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
611 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
614 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
618 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
620 dev_cap->cqc_entry_sz,
622 dev->caps.reserved_cqs, 0, 0);
624 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
625 goto err_unmap_rdmarc;
628 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
630 dev_cap->srq_entry_sz,
632 dev->caps.reserved_srqs, 0, 0);
634 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
639 * It's not strictly required, but for simplicity just map the
640 * whole multicast group table now. The table isn't very big
641 * and it's a lot easier than trying to track ref counts.
643 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
644 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
645 dev->caps.num_mgms + dev->caps.num_amgms,
646 dev->caps.num_mgms + dev->caps.num_amgms,
649 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
656 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
659 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
662 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
665 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
668 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
671 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
674 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
677 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
680 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
683 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
684 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
685 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
686 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
689 mlx4_UNMAP_ICM_AUX(dev);
692 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
697 static void mlx4_free_icms(struct mlx4_dev *dev)
699 struct mlx4_priv *priv = mlx4_priv(dev);
701 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
702 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
703 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
704 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
705 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
706 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
707 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
708 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
709 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
710 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
711 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
712 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
713 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
714 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
716 mlx4_UNMAP_ICM_AUX(dev);
717 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
720 static int map_bf_area(struct mlx4_dev *dev)
722 struct mlx4_priv *priv = mlx4_priv(dev);
723 resource_size_t bf_start;
724 resource_size_t bf_len;
727 bf_start = pci_resource_start(dev->pdev, 2) + (dev->caps.num_uars << PAGE_SHIFT);
728 bf_len = pci_resource_len(dev->pdev, 2) - (dev->caps.num_uars << PAGE_SHIFT);
729 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
730 if (!priv->bf_mapping)
736 static void unmap_bf_area(struct mlx4_dev *dev)
738 if (mlx4_priv(dev)->bf_mapping)
739 io_mapping_free(mlx4_priv(dev)->bf_mapping);
742 static void mlx4_close_hca(struct mlx4_dev *dev)
745 mlx4_CLOSE_HCA(dev, 0);
748 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
751 static int mlx4_init_hca(struct mlx4_dev *dev)
753 struct mlx4_priv *priv = mlx4_priv(dev);
754 struct mlx4_adapter adapter;
755 struct mlx4_dev_cap dev_cap;
756 struct mlx4_mod_stat_cfg mlx4_cfg;
757 struct mlx4_profile profile;
758 struct mlx4_init_hca_param init_hca;
762 err = mlx4_QUERY_FW(dev);
765 mlx4_info(dev, "non-primary physical function, skipping.\n");
767 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
771 err = mlx4_load_fw(dev);
773 mlx4_err(dev, "Failed to start FW, aborting.\n");
777 mlx4_cfg.log_pg_sz_m = 1;
778 mlx4_cfg.log_pg_sz = 0;
779 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
781 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
783 err = mlx4_dev_cap(dev, &dev_cap);
785 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
789 profile = default_profile;
791 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
792 if ((long long) icm_size < 0) {
797 if (map_bf_area(dev))
798 mlx4_dbg(dev, "Failed to map blue flame area\n");
800 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
802 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
806 err = mlx4_INIT_HCA(dev, &init_hca);
808 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
812 err = mlx4_QUERY_ADAPTER(dev, &adapter);
814 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
818 priv->eq_table.inta_pin = adapter.inta_pin;
819 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
824 mlx4_CLOSE_HCA(dev, 0);
832 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
837 static int mlx4_setup_hca(struct mlx4_dev *dev)
839 struct mlx4_priv *priv = mlx4_priv(dev);
842 __be32 ib_port_default_caps;
844 err = mlx4_init_uar_table(dev);
846 mlx4_err(dev, "Failed to initialize "
847 "user access region table, aborting.\n");
851 err = mlx4_uar_alloc(dev, &priv->driver_uar);
853 mlx4_err(dev, "Failed to allocate driver access region, "
855 goto err_uar_table_free;
858 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
860 mlx4_err(dev, "Couldn't map kernel access region, "
866 err = mlx4_init_pd_table(dev);
868 mlx4_err(dev, "Failed to initialize "
869 "protection domain table, aborting.\n");
873 err = mlx4_init_mr_table(dev);
875 mlx4_err(dev, "Failed to initialize "
876 "memory region table, aborting.\n");
877 goto err_pd_table_free;
880 err = mlx4_init_eq_table(dev);
882 mlx4_err(dev, "Failed to initialize "
883 "event queue table, aborting.\n");
884 goto err_mr_table_free;
887 err = mlx4_cmd_use_events(dev);
889 mlx4_err(dev, "Failed to switch to event-driven "
890 "firmware commands, aborting.\n");
891 goto err_eq_table_free;
896 if (dev->flags & MLX4_FLAG_MSI_X) {
897 mlx4_warn(dev, "NOP command failed to generate MSI-X "
898 "interrupt IRQ %d).\n",
899 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
900 mlx4_warn(dev, "Trying again without MSI-X.\n");
902 mlx4_err(dev, "NOP command failed to generate interrupt "
903 "(IRQ %d), aborting.\n",
904 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
905 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
911 mlx4_dbg(dev, "NOP command IRQ test passed\n");
913 err = mlx4_init_cq_table(dev);
915 mlx4_err(dev, "Failed to initialize "
916 "completion queue table, aborting.\n");
920 err = mlx4_init_srq_table(dev);
922 mlx4_err(dev, "Failed to initialize "
923 "shared receive queue table, aborting.\n");
924 goto err_cq_table_free;
927 err = mlx4_init_qp_table(dev);
929 mlx4_err(dev, "Failed to initialize "
930 "queue pair table, aborting.\n");
931 goto err_srq_table_free;
934 err = mlx4_init_mcg_table(dev);
936 mlx4_err(dev, "Failed to initialize "
937 "multicast group table, aborting.\n");
938 goto err_qp_table_free;
941 for (port = 1; port <= dev->caps.num_ports; port++) {
942 enum mlx4_port_type port_type = 0;
943 mlx4_SENSE_PORT(dev, port, &port_type);
945 dev->caps.port_type[port] = port_type;
946 ib_port_default_caps = 0;
947 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
949 mlx4_warn(dev, "failed to get port %d default "
950 "ib capabilities (%d). Continuing with "
951 "caps = 0\n", port, err);
952 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
953 err = mlx4_SET_PORT(dev, port);
955 mlx4_err(dev, "Failed to set port %d, aborting\n",
957 goto err_mcg_table_free;
960 mlx4_set_port_mask(dev);
965 mlx4_cleanup_mcg_table(dev);
968 mlx4_cleanup_qp_table(dev);
971 mlx4_cleanup_srq_table(dev);
974 mlx4_cleanup_cq_table(dev);
977 mlx4_cmd_use_polling(dev);
980 mlx4_cleanup_eq_table(dev);
983 mlx4_cleanup_mr_table(dev);
986 mlx4_cleanup_pd_table(dev);
992 mlx4_uar_free(dev, &priv->driver_uar);
995 mlx4_cleanup_uar_table(dev);
999 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1001 struct mlx4_priv *priv = mlx4_priv(dev);
1002 struct msix_entry *entries;
1003 int nreq = min_t(int, dev->caps.num_ports *
1004 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1005 + MSIX_LEGACY_SZ, MAX_MSIX);
1010 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1012 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1016 for (i = 0; i < nreq; ++i)
1017 entries[i].entry = i;
1020 err = pci_enable_msix(dev->pdev, entries, nreq);
1022 /* Try again if at least 2 vectors are available */
1024 mlx4_info(dev, "Requested %d vectors, "
1025 "but only %d MSI-X vectors available, "
1026 "trying again\n", nreq, err);
1035 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1036 /*Working in legacy mode , all EQ's shared*/
1037 dev->caps.comp_pool = 0;
1038 dev->caps.num_comp_vectors = nreq - 1;
1040 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1041 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1043 for (i = 0; i < nreq; ++i)
1044 priv->eq_table.eq[i].irq = entries[i].vector;
1046 dev->flags |= MLX4_FLAG_MSI_X;
1053 dev->caps.num_comp_vectors = 1;
1054 dev->caps.comp_pool = 0;
1056 for (i = 0; i < 2; ++i)
1057 priv->eq_table.eq[i].irq = dev->pdev->irq;
1060 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1062 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1067 mlx4_init_mac_table(dev, &info->mac_table);
1068 mlx4_init_vlan_table(dev, &info->vlan_table);
1070 sprintf(info->dev_name, "mlx4_port%d", port);
1071 info->port_attr.attr.name = info->dev_name;
1072 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1073 info->port_attr.show = show_port_type;
1074 info->port_attr.store = set_port_type;
1075 sysfs_attr_init(&info->port_attr.attr);
1077 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1079 mlx4_err(dev, "Failed to create file for port %d\n", port);
1086 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1091 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1094 static int mlx4_init_steering(struct mlx4_dev *dev)
1096 struct mlx4_priv *priv = mlx4_priv(dev);
1097 int num_entries = dev->caps.num_ports;
1100 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1104 for (i = 0; i < num_entries; i++) {
1105 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1106 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1107 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1109 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1114 static void mlx4_clear_steering(struct mlx4_dev *dev)
1116 struct mlx4_priv *priv = mlx4_priv(dev);
1117 struct mlx4_steer_index *entry, *tmp_entry;
1118 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1119 int num_entries = dev->caps.num_ports;
1122 for (i = 0; i < num_entries; i++) {
1123 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1124 list_for_each_entry_safe(pqp, tmp_pqp,
1125 &priv->steer[i].promisc_qps[j],
1127 list_del(&pqp->list);
1130 list_for_each_entry_safe(entry, tmp_entry,
1131 &priv->steer[i].steer_entries[j],
1133 list_del(&entry->list);
1134 list_for_each_entry_safe(pqp, tmp_pqp,
1137 list_del(&pqp->list);
1147 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1149 struct mlx4_priv *priv;
1150 struct mlx4_dev *dev;
1154 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1156 err = pci_enable_device(pdev);
1158 dev_err(&pdev->dev, "Cannot enable PCI device, "
1164 * Check for BARs. We expect 0: 1MB
1166 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1167 pci_resource_len(pdev, 0) != 1 << 20) {
1168 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1170 goto err_disable_pdev;
1172 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1173 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1175 goto err_disable_pdev;
1178 err = pci_request_regions(pdev, DRV_NAME);
1180 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1181 goto err_disable_pdev;
1184 pci_set_master(pdev);
1186 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1188 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1189 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1191 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1192 goto err_release_regions;
1195 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1197 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1198 "consistent PCI DMA mask.\n");
1199 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1201 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1203 goto err_release_regions;
1207 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1208 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1210 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1212 dev_err(&pdev->dev, "Device struct alloc failed, "
1215 goto err_release_regions;
1220 INIT_LIST_HEAD(&priv->ctx_list);
1221 spin_lock_init(&priv->ctx_lock);
1223 mutex_init(&priv->port_mutex);
1225 INIT_LIST_HEAD(&priv->pgdir_list);
1226 mutex_init(&priv->pgdir_mutex);
1228 pci_read_config_byte(pdev, PCI_REVISION_ID, &dev->rev_id);
1230 INIT_LIST_HEAD(&priv->bf_list);
1231 mutex_init(&priv->bf_mutex);
1234 * Now reset the HCA before we touch the PCI capabilities or
1235 * attempt a firmware command, since a boot ROM may have left
1236 * the HCA in an undefined state.
1238 err = mlx4_reset(dev);
1240 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1244 if (mlx4_cmd_init(dev)) {
1245 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1249 err = mlx4_init_hca(dev);
1253 err = mlx4_alloc_eq_table(dev);
1257 priv->msix_ctl.pool_bm = 0;
1258 spin_lock_init(&priv->msix_ctl.pool_lock);
1260 mlx4_enable_msi_x(dev);
1262 err = mlx4_init_steering(dev);
1266 err = mlx4_setup_hca(dev);
1267 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1268 dev->flags &= ~MLX4_FLAG_MSI_X;
1269 pci_disable_msix(pdev);
1270 err = mlx4_setup_hca(dev);
1276 for (port = 1; port <= dev->caps.num_ports; port++) {
1277 err = mlx4_init_port_info(dev, port);
1282 err = mlx4_register_device(dev);
1286 mlx4_sense_init(dev);
1287 mlx4_start_sense(dev);
1289 pci_set_drvdata(pdev, dev);
1294 for (--port; port >= 1; --port)
1295 mlx4_cleanup_port_info(&priv->port[port]);
1297 mlx4_cleanup_mcg_table(dev);
1298 mlx4_cleanup_qp_table(dev);
1299 mlx4_cleanup_srq_table(dev);
1300 mlx4_cleanup_cq_table(dev);
1301 mlx4_cmd_use_polling(dev);
1302 mlx4_cleanup_eq_table(dev);
1303 mlx4_cleanup_mr_table(dev);
1304 mlx4_cleanup_pd_table(dev);
1305 mlx4_cleanup_uar_table(dev);
1308 mlx4_clear_steering(dev);
1311 mlx4_free_eq_table(dev);
1314 if (dev->flags & MLX4_FLAG_MSI_X)
1315 pci_disable_msix(pdev);
1317 mlx4_close_hca(dev);
1320 mlx4_cmd_cleanup(dev);
1325 err_release_regions:
1326 pci_release_regions(pdev);
1329 pci_disable_device(pdev);
1330 pci_set_drvdata(pdev, NULL);
1334 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1335 const struct pci_device_id *id)
1337 printk_once(KERN_INFO "%s", mlx4_version);
1339 return __mlx4_init_one(pdev, id);
1342 static void mlx4_remove_one(struct pci_dev *pdev)
1344 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1345 struct mlx4_priv *priv = mlx4_priv(dev);
1349 mlx4_stop_sense(dev);
1350 mlx4_unregister_device(dev);
1352 for (p = 1; p <= dev->caps.num_ports; p++) {
1353 mlx4_cleanup_port_info(&priv->port[p]);
1354 mlx4_CLOSE_PORT(dev, p);
1357 mlx4_cleanup_mcg_table(dev);
1358 mlx4_cleanup_qp_table(dev);
1359 mlx4_cleanup_srq_table(dev);
1360 mlx4_cleanup_cq_table(dev);
1361 mlx4_cmd_use_polling(dev);
1362 mlx4_cleanup_eq_table(dev);
1363 mlx4_cleanup_mr_table(dev);
1364 mlx4_cleanup_pd_table(dev);
1367 mlx4_uar_free(dev, &priv->driver_uar);
1368 mlx4_cleanup_uar_table(dev);
1369 mlx4_clear_steering(dev);
1370 mlx4_free_eq_table(dev);
1371 mlx4_close_hca(dev);
1372 mlx4_cmd_cleanup(dev);
1374 if (dev->flags & MLX4_FLAG_MSI_X)
1375 pci_disable_msix(pdev);
1378 pci_release_regions(pdev);
1379 pci_disable_device(pdev);
1380 pci_set_drvdata(pdev, NULL);
1384 int mlx4_restart_one(struct pci_dev *pdev)
1386 mlx4_remove_one(pdev);
1387 return __mlx4_init_one(pdev, NULL);
1390 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1391 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1392 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1393 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1394 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1395 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1396 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1397 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1398 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1399 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1400 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1401 { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1402 { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1403 { PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
1404 { PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
1405 { PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
1406 { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
1407 { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
1408 { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
1409 { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
1410 { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
1411 { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
1412 { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
1413 { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
1414 { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
1415 { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
1416 { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
1417 { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
1421 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1423 static struct pci_driver mlx4_driver = {
1425 .id_table = mlx4_pci_table,
1426 .probe = mlx4_init_one,
1427 .remove = __devexit_p(mlx4_remove_one)
1430 static int __init mlx4_verify_params(void)
1432 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1433 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1437 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1438 pr_warning("mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1442 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1443 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1450 static int __init mlx4_init(void)
1454 if (mlx4_verify_params())
1459 mlx4_wq = create_singlethread_workqueue("mlx4");
1463 ret = pci_register_driver(&mlx4_driver);
1464 return ret < 0 ? ret : 0;
1467 static void __exit mlx4_cleanup(void)
1469 pci_unregister_driver(&mlx4_driver);
1470 destroy_workqueue(mlx4_wq);
1473 module_init(mlx4_init);
1474 module_exit(mlx4_cleanup);