1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "3.0.12-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 [board_X540] = &ixgbe_X540_info,
65 /* ixgbe_pci_tbl - PCI Device ID Table
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
123 /* required last entry */
126 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
128 #ifdef CONFIG_IXGBE_DCA
129 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
131 static struct notifier_block dca_notifier = {
132 .notifier_call = ixgbe_notify_dca,
138 #ifdef CONFIG_PCI_IOV
139 static unsigned int max_vfs;
140 module_param(max_vfs, uint, 0);
141 MODULE_PARM_DESC(max_vfs,
142 "Maximum number of virtual functions to allocate per physical function");
143 #endif /* CONFIG_PCI_IOV */
145 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
146 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
147 MODULE_LICENSE("GPL");
148 MODULE_VERSION(DRV_VERSION);
150 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
152 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
154 struct ixgbe_hw *hw = &adapter->hw;
159 #ifdef CONFIG_PCI_IOV
160 /* disable iov and allow time for transactions to clear */
161 pci_disable_sriov(adapter->pdev);
164 /* turn off device IOV mode */
165 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
166 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
167 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
168 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
169 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
172 /* set default pool back to 0 */
173 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
174 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
175 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
177 /* take a breather then clean up driver data */
180 kfree(adapter->vfinfo);
181 adapter->vfinfo = NULL;
183 adapter->num_vfs = 0;
184 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
187 struct ixgbe_reg_info {
192 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
194 /* General Registers */
195 {IXGBE_CTRL, "CTRL"},
196 {IXGBE_STATUS, "STATUS"},
197 {IXGBE_CTRL_EXT, "CTRL_EXT"},
199 /* Interrupt Registers */
200 {IXGBE_EICR, "EICR"},
203 {IXGBE_SRRCTL(0), "SRRCTL"},
204 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
205 {IXGBE_RDLEN(0), "RDLEN"},
206 {IXGBE_RDH(0), "RDH"},
207 {IXGBE_RDT(0), "RDT"},
208 {IXGBE_RXDCTL(0), "RXDCTL"},
209 {IXGBE_RDBAL(0), "RDBAL"},
210 {IXGBE_RDBAH(0), "RDBAH"},
213 {IXGBE_TDBAL(0), "TDBAL"},
214 {IXGBE_TDBAH(0), "TDBAH"},
215 {IXGBE_TDLEN(0), "TDLEN"},
216 {IXGBE_TDH(0), "TDH"},
217 {IXGBE_TDT(0), "TDT"},
218 {IXGBE_TXDCTL(0), "TXDCTL"},
220 /* List Terminator */
226 * ixgbe_regdump - register printout routine
228 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
234 switch (reginfo->ofs) {
235 case IXGBE_SRRCTL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
239 case IXGBE_DCA_RXCTRL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
255 case IXGBE_RXDCTL(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
276 for (i = 0; i < 64; i++)
277 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
280 for (i = 0; i < 64; i++)
281 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
284 for (i = 0; i < 64; i++)
285 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
287 case IXGBE_TXDCTL(0):
288 for (i = 0; i < 64; i++)
289 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
292 pr_info("%-15s %08x\n", reginfo->name,
293 IXGBE_READ_REG(hw, reginfo->ofs));
297 for (i = 0; i < 8; i++) {
298 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
299 pr_err("%-15s", rname);
300 for (j = 0; j < 8; j++)
301 pr_cont(" %08x", regs[i*8+j]);
308 * ixgbe_dump - Print registers, tx-rings and rx-rings
310 static void ixgbe_dump(struct ixgbe_adapter *adapter)
312 struct net_device *netdev = adapter->netdev;
313 struct ixgbe_hw *hw = &adapter->hw;
314 struct ixgbe_reg_info *reginfo;
316 struct ixgbe_ring *tx_ring;
317 struct ixgbe_tx_buffer *tx_buffer_info;
318 union ixgbe_adv_tx_desc *tx_desc;
319 struct my_u0 { u64 a; u64 b; } *u0;
320 struct ixgbe_ring *rx_ring;
321 union ixgbe_adv_rx_desc *rx_desc;
322 struct ixgbe_rx_buffer *rx_buffer_info;
326 if (!netif_msg_hw(adapter))
329 /* Print netdevice Info */
331 dev_info(&adapter->pdev->dev, "Net device Info\n");
332 pr_info("Device Name state "
333 "trans_start last_rx\n");
334 pr_info("%-15s %016lX %016lX %016lX\n",
341 /* Print Registers */
342 dev_info(&adapter->pdev->dev, "Register Dump\n");
343 pr_info(" Register Name Value\n");
344 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
345 reginfo->name; reginfo++) {
346 ixgbe_regdump(hw, reginfo);
349 /* Print TX Ring Summary */
350 if (!netdev || !netif_running(netdev))
353 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
354 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
355 for (n = 0; n < adapter->num_tx_queues; n++) {
356 tx_ring = adapter->tx_ring[n];
358 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
359 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
360 n, tx_ring->next_to_use, tx_ring->next_to_clean,
361 (u64)tx_buffer_info->dma,
362 tx_buffer_info->length,
363 tx_buffer_info->next_to_watch,
364 (u64)tx_buffer_info->time_stamp);
368 if (!netif_msg_tx_done(adapter))
369 goto rx_ring_summary;
371 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
373 /* Transmit Descriptor Formats
375 * Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 pr_info("------------------------------------\n");
387 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
388 pr_info("------------------------------------\n");
389 pr_info("T [desc] [address 63:0 ] "
390 "[PlPOIdStDDt Ln] [bi->dma ] "
391 "leng ntw timestamp bi->skb\n");
393 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
394 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
395 tx_buffer_info = &tx_ring->tx_buffer_info[i];
396 u0 = (struct my_u0 *)tx_desc;
397 pr_info("T [0x%03X] %016llX %016llX %016llX"
398 " %04X %3X %016llX %p", i,
401 (u64)tx_buffer_info->dma,
402 tx_buffer_info->length,
403 tx_buffer_info->next_to_watch,
404 (u64)tx_buffer_info->time_stamp,
405 tx_buffer_info->skb);
406 if (i == tx_ring->next_to_use &&
407 i == tx_ring->next_to_clean)
409 else if (i == tx_ring->next_to_use)
411 else if (i == tx_ring->next_to_clean)
416 if (netif_msg_pktdata(adapter) &&
417 tx_buffer_info->dma != 0)
418 print_hex_dump(KERN_INFO, "",
419 DUMP_PREFIX_ADDRESS, 16, 1,
420 phys_to_virt(tx_buffer_info->dma),
421 tx_buffer_info->length, true);
425 /* Print RX Rings Summary */
427 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
428 pr_info("Queue [NTU] [NTC]\n");
429 for (n = 0; n < adapter->num_rx_queues; n++) {
430 rx_ring = adapter->rx_ring[n];
431 pr_info("%5d %5X %5X\n",
432 n, rx_ring->next_to_use, rx_ring->next_to_clean);
436 if (!netif_msg_rx_status(adapter))
439 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
441 /* Advanced Receive Descriptor (Read) Format
443 * +-----------------------------------------------------+
444 * 0 | Packet Buffer Address [63:1] |A0/NSE|
445 * +----------------------------------------------+------+
446 * 8 | Header Buffer Address [63:1] | DD |
447 * +-----------------------------------------------------+
450 * Advanced Receive Descriptor (Write-Back) Format
452 * 63 48 47 32 31 30 21 20 16 15 4 3 0
453 * +------------------------------------------------------+
454 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
455 * | Checksum Ident | | | | Type | Type |
456 * +------------------------------------------------------+
457 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
458 * +------------------------------------------------------+
459 * 63 48 47 32 31 20 19 0
461 for (n = 0; n < adapter->num_rx_queues; n++) {
462 rx_ring = adapter->rx_ring[n];
463 pr_info("------------------------------------\n");
464 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
465 pr_info("------------------------------------\n");
466 pr_info("R [desc] [ PktBuf A0] "
467 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
468 "<-- Adv Rx Read format\n");
469 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
470 "[vl er S cks ln] ---------------- [bi->skb] "
471 "<-- Adv Rx Write-Back format\n");
473 for (i = 0; i < rx_ring->count; i++) {
474 rx_buffer_info = &rx_ring->rx_buffer_info[i];
475 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
476 u0 = (struct my_u0 *)rx_desc;
477 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
478 if (staterr & IXGBE_RXD_STAT_DD) {
479 /* Descriptor Done */
480 pr_info("RWB[0x%03X] %016llX "
481 "%016llX ---------------- %p", i,
484 rx_buffer_info->skb);
486 pr_info("R [0x%03X] %016llX "
487 "%016llX %016llX %p", i,
490 (u64)rx_buffer_info->dma,
491 rx_buffer_info->skb);
493 if (netif_msg_pktdata(adapter)) {
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(rx_buffer_info->dma),
497 rx_ring->rx_buf_len, true);
499 if (rx_ring->rx_buf_len
500 < IXGBE_RXBUFFER_2048)
501 print_hex_dump(KERN_INFO, "",
502 DUMP_PREFIX_ADDRESS, 16, 1,
504 rx_buffer_info->page_dma +
505 rx_buffer_info->page_offset
511 if (i == rx_ring->next_to_use)
513 else if (i == rx_ring->next_to_clean)
525 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
529 /* Let firmware take over control of h/w */
530 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
532 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
535 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
539 /* Let firmware know the driver has taken over */
540 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
542 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
546 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
547 * @adapter: pointer to adapter struct
548 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
549 * @queue: queue to map the corresponding interrupt to
550 * @msix_vector: the vector to map to the corresponding queue
553 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
554 u8 queue, u8 msix_vector)
557 struct ixgbe_hw *hw = &adapter->hw;
558 switch (hw->mac.type) {
559 case ixgbe_mac_82598EB:
560 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
563 index = (((direction * 64) + queue) >> 2) & 0x1F;
564 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
565 ivar &= ~(0xFF << (8 * (queue & 0x3)));
566 ivar |= (msix_vector << (8 * (queue & 0x3)));
567 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
569 case ixgbe_mac_82599EB:
571 if (direction == -1) {
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((queue & 1) * 8);
575 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
581 /* tx or rx causes */
582 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
583 index = ((16 * (queue & 1)) + (8 * direction));
584 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
585 ivar &= ~(0xFF << index);
586 ivar |= (msix_vector << index);
587 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
595 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
600 switch (adapter->hw.mac.type) {
601 case ixgbe_mac_82598EB:
602 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
605 case ixgbe_mac_82599EB:
607 mask = (qmask & 0xFFFFFFFF);
608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
609 mask = (qmask >> 32);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
617 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
618 struct ixgbe_tx_buffer *tx_buffer_info)
620 if (tx_buffer_info->dma) {
621 if (tx_buffer_info->mapped_as_page)
622 dma_unmap_page(tx_ring->dev,
624 tx_buffer_info->length,
627 dma_unmap_single(tx_ring->dev,
629 tx_buffer_info->length,
631 tx_buffer_info->dma = 0;
633 if (tx_buffer_info->skb) {
634 dev_kfree_skb_any(tx_buffer_info->skb);
635 tx_buffer_info->skb = NULL;
637 tx_buffer_info->time_stamp = 0;
638 /* tx_buffer_info must be completely set up in the transmit path */
642 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
643 * @adapter: driver private struct
644 * @index: reg idx of queue to query (0-127)
646 * Helper function to determine the traffic index for a paticular
649 * Returns : a tc index for use in range 0-7, or 0-3
651 u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
656 /* if DCB is not enabled the queues have no TC */
657 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
660 /* check valid range */
661 if (reg_idx >= adapter->hw.mac.max_tx_queues)
664 switch (adapter->hw.mac.type) {
665 case ixgbe_mac_82598EB:
669 if (dcb_i != 4 && dcb_i != 8)
672 /* if VMDq is enabled the lowest order bits determine TC */
673 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
674 IXGBE_FLAG_VMDQ_ENABLED)) {
675 tc = reg_idx & (dcb_i - 1);
680 * Convert the reg_idx into the correct TC. This bitmask
681 * targets the last full 32 ring traffic class and assigns
682 * it a value of 1. From there the rest of the rings are
683 * based on shifting the mask further up to include the
684 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
685 * will only ever be 8 or 4 and that reg_idx will never
686 * be greater then 128. The code without the power of 2
687 * optimizations would be:
688 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
690 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
691 tc >>= 9 - (reg_idx >> 5);
697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
705 if ((hw->fc.current_mode == ixgbe_fc_full) ||
706 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
707 switch (hw->mac.type) {
708 case ixgbe_mac_82598EB:
709 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
712 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
714 hwstats->lxoffrxc += data;
716 /* refill credits (no tx hang) if we received xoff */
720 for (i = 0; i < adapter->num_tx_queues; i++)
721 clear_bit(__IXGBE_HANG_CHECK_ARMED,
722 &adapter->tx_ring[i]->state);
724 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
727 /* update stats for each tc, only valid with PFC enabled */
728 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
729 switch (hw->mac.type) {
730 case ixgbe_mac_82598EB:
731 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
734 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
736 hwstats->pxoffrxc[i] += xoff[i];
739 /* disarm tx queues that have received xoff frames */
740 for (i = 0; i < adapter->num_tx_queues; i++) {
741 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
742 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
745 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
749 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
751 return ring->tx_stats.completed;
754 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
756 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
757 struct ixgbe_hw *hw = &adapter->hw;
759 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
760 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
763 return (head < tail) ?
764 tail - head : (tail + ring->count - head);
769 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
771 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
772 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
773 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
776 clear_check_for_tx_hang(tx_ring);
779 * Check for a hung queue, but be thorough. This verifies
780 * that a transmit has been completed since the previous
781 * check AND there is at least one packet pending. The
782 * ARMED bit is set to indicate a potential hang. The
783 * bit is cleared if a pause frame is received to remove
784 * false hang detection due to PFC or 802.3x frames. By
785 * requiring this to fail twice we avoid races with
786 * pfc clearing the ARMED bit and conditions where we
787 * run the check_tx_hang logic with a transmit completion
788 * pending but without time to complete it yet.
790 if ((tx_done_old == tx_done) && tx_pending) {
791 /* make sure it is true for two checks in a row */
792 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
795 /* update completed stats and continue */
796 tx_ring->tx_stats.tx_done_old = tx_done;
797 /* reset the countdown */
798 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
804 #define IXGBE_MAX_TXD_PWR 14
805 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
807 /* Tx Descriptors needed, worst case */
808 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
809 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
810 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
811 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
813 static void ixgbe_tx_timeout(struct net_device *netdev);
816 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
817 * @q_vector: structure containing interrupt and ring information
818 * @tx_ring: tx ring to clean
820 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
821 struct ixgbe_ring *tx_ring)
823 struct ixgbe_adapter *adapter = q_vector->adapter;
824 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
825 struct ixgbe_tx_buffer *tx_buffer_info;
826 unsigned int total_bytes = 0, total_packets = 0;
827 u16 i, eop, count = 0;
829 i = tx_ring->next_to_clean;
830 eop = tx_ring->tx_buffer_info[i].next_to_watch;
831 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
833 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
834 (count < tx_ring->work_limit)) {
835 bool cleaned = false;
836 rmb(); /* read buffer_info after eop_desc */
837 for ( ; !cleaned; count++) {
838 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
839 tx_buffer_info = &tx_ring->tx_buffer_info[i];
841 tx_desc->wb.status = 0;
842 cleaned = (i == eop);
845 if (i == tx_ring->count)
848 if (cleaned && tx_buffer_info->skb) {
849 total_bytes += tx_buffer_info->bytecount;
850 total_packets += tx_buffer_info->gso_segs;
853 ixgbe_unmap_and_free_tx_resource(tx_ring,
857 tx_ring->tx_stats.completed++;
858 eop = tx_ring->tx_buffer_info[i].next_to_watch;
859 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
862 tx_ring->next_to_clean = i;
863 tx_ring->total_bytes += total_bytes;
864 tx_ring->total_packets += total_packets;
865 u64_stats_update_begin(&tx_ring->syncp);
866 tx_ring->stats.packets += total_packets;
867 tx_ring->stats.bytes += total_bytes;
868 u64_stats_update_end(&tx_ring->syncp);
870 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
871 /* schedule immediate reset if we believe we hung */
872 struct ixgbe_hw *hw = &adapter->hw;
873 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
874 e_err(drv, "Detected Tx Unit Hang\n"
876 " TDH, TDT <%x>, <%x>\n"
877 " next_to_use <%x>\n"
878 " next_to_clean <%x>\n"
879 "tx_buffer_info[next_to_clean]\n"
880 " time_stamp <%lx>\n"
882 tx_ring->queue_index,
883 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
884 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
885 tx_ring->next_to_use, eop,
886 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
888 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
891 "tx hang %d detected on queue %d, resetting adapter\n",
892 adapter->tx_timeout_count + 1, tx_ring->queue_index);
894 /* schedule immediate reset if we believe we hung */
895 ixgbe_tx_timeout(adapter->netdev);
897 /* the adapter is about to reset, no point in enabling stuff */
901 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
902 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
903 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
904 /* Make sure that anybody stopping the queue after this
905 * sees the new next_to_clean.
908 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
909 !test_bit(__IXGBE_DOWN, &adapter->state)) {
910 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
911 ++tx_ring->tx_stats.restart_queue;
915 return count < tx_ring->work_limit;
918 #ifdef CONFIG_IXGBE_DCA
919 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
920 struct ixgbe_ring *rx_ring,
923 struct ixgbe_hw *hw = &adapter->hw;
925 u8 reg_idx = rx_ring->reg_idx;
927 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
928 switch (hw->mac.type) {
929 case ixgbe_mac_82598EB:
930 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
931 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
933 case ixgbe_mac_82599EB:
935 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
936 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
937 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
942 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
943 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
944 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
946 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
947 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
950 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
951 struct ixgbe_ring *tx_ring,
954 struct ixgbe_hw *hw = &adapter->hw;
956 u8 reg_idx = tx_ring->reg_idx;
958 switch (hw->mac.type) {
959 case ixgbe_mac_82598EB:
960 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
961 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
962 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
963 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
964 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
965 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
967 case ixgbe_mac_82599EB:
969 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
970 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
971 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
972 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
973 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
974 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
975 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
982 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
984 struct ixgbe_adapter *adapter = q_vector->adapter;
989 if (q_vector->cpu == cpu)
992 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
993 for (i = 0; i < q_vector->txr_count; i++) {
994 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
995 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
999 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000 for (i = 0; i < q_vector->rxr_count; i++) {
1001 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1006 q_vector->cpu = cpu;
1011 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1016 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1019 /* always use CB2 mode, difference is masked in the CB driver */
1020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1027 for (i = 0; i < num_q_vectors; i++) {
1028 adapter->q_vector[i]->cpu = -1;
1029 ixgbe_update_dca(adapter->q_vector[i]);
1033 static int __ixgbe_notify_dca(struct device *dev, void *data)
1035 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1036 unsigned long event = *(unsigned long *)data;
1038 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1042 case DCA_PROVIDER_ADD:
1043 /* if we're already enabled, don't do it again */
1044 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1046 if (dca_add_requester(dev) == 0) {
1047 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1048 ixgbe_setup_dca(adapter);
1051 /* Fall Through since DCA is disabled. */
1052 case DCA_PROVIDER_REMOVE:
1053 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054 dca_remove_requester(dev);
1055 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1064 #endif /* CONFIG_IXGBE_DCA */
1066 * ixgbe_receive_skb - Send a completed packet up the stack
1067 * @adapter: board private structure
1068 * @skb: packet to send up
1069 * @status: hardware indication of status of receive
1070 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071 * @rx_desc: rx descriptor
1073 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1074 struct sk_buff *skb, u8 status,
1075 struct ixgbe_ring *ring,
1076 union ixgbe_adv_rx_desc *rx_desc)
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct napi_struct *napi = &q_vector->napi;
1080 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1083 if (is_vlan && (tag & VLAN_VID_MASK))
1084 __vlan_hwaccel_put_tag(skb, tag);
1086 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087 napi_gro_receive(napi, skb);
1093 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094 * @adapter: address of board private structure
1095 * @status_err: hardware indication of status of receive
1096 * @skb: skb currently being received and modified
1098 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1102 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1104 skb_checksum_none_assert(skb);
1106 /* Rx csum disabled */
1107 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1110 /* if IP and error */
1111 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1113 adapter->hw_csum_rx_error++;
1117 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1120 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1121 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 * 82599 errata, UDP frames with a 0 checksum can be marked as
1127 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1131 adapter->hw_csum_rx_error++;
1135 /* It must be a TCP or UDP packet with a valid checksum */
1136 skb->ip_summed = CHECKSUM_UNNECESSARY;
1139 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1142 * Force memory writes to complete before letting h/w
1143 * know there are new descriptors to fetch. (Only
1144 * applicable for weak-ordered memory model archs,
1148 writel(val, rx_ring->tail);
1152 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1153 * @rx_ring: ring to place buffers on
1154 * @cleaned_count: number of buffers to replace
1156 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1158 union ixgbe_adv_rx_desc *rx_desc;
1159 struct ixgbe_rx_buffer *bi;
1160 struct sk_buff *skb;
1161 u16 i = rx_ring->next_to_use;
1163 /* do nothing if no valid netdev defined */
1164 if (!rx_ring->netdev)
1167 while (cleaned_count--) {
1168 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169 bi = &rx_ring->rx_buffer_info[i];
1173 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1174 rx_ring->rx_buf_len);
1176 rx_ring->rx_stats.alloc_rx_buff_failed++;
1179 /* initialize queue mapping */
1180 skb_record_rx_queue(skb, rx_ring->queue_index);
1185 bi->dma = dma_map_single(rx_ring->dev,
1187 rx_ring->rx_buf_len,
1189 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1190 rx_ring->rx_stats.alloc_rx_buff_failed++;
1196 if (ring_is_ps_enabled(rx_ring)) {
1198 bi->page = netdev_alloc_page(rx_ring->netdev);
1200 rx_ring->rx_stats.alloc_rx_page_failed++;
1205 if (!bi->page_dma) {
1206 /* use a half page if we're re-using */
1207 bi->page_offset ^= PAGE_SIZE / 2;
1208 bi->page_dma = dma_map_page(rx_ring->dev,
1213 if (dma_mapping_error(rx_ring->dev,
1215 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 /* Refresh the desc even if buffer_addrs didn't change
1222 * because each write-back erases this info. */
1223 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1226 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1227 rx_desc->read.hdr_addr = 0;
1231 if (i == rx_ring->count)
1236 if (rx_ring->next_to_use != i) {
1237 rx_ring->next_to_use = i;
1238 ixgbe_release_rx_desc(rx_ring, i);
1242 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1244 /* HW will not DMA in data larger than the given buffer, even if it
1245 * parses the (NFS, of course) header to be larger. In that case, it
1246 * fills the header buffer and spills the rest into the page.
1248 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251 if (hlen > IXGBE_RX_HDR_SIZE)
1252 hlen = IXGBE_RX_HDR_SIZE;
1257 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258 * @skb: pointer to the last skb in the rsc queue
1260 * This function changes a queue full of hw rsc buffers into a completed
1261 * packet. It uses the ->prev pointers to find the first packet and then
1262 * turns it into the frag list owner.
1264 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1266 unsigned int frag_list_size = 0;
1267 unsigned int skb_cnt = 1;
1270 struct sk_buff *prev = skb->prev;
1271 frag_list_size += skb->len;
1277 skb_shinfo(skb)->frag_list = skb->next;
1279 skb->len += frag_list_size;
1280 skb->data_len += frag_list_size;
1281 skb->truesize += frag_list_size;
1282 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1287 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1289 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290 IXGBE_RXDADV_RSCCNT_MASK);
1293 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1294 struct ixgbe_ring *rx_ring,
1295 int *work_done, int work_to_do)
1297 struct ixgbe_adapter *adapter = q_vector->adapter;
1298 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300 struct sk_buff *skb;
1301 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1302 const int current_node = numa_node_id();
1305 #endif /* IXGBE_FCOE */
1308 u16 cleaned_count = 0;
1309 bool pkt_is_rsc = false;
1311 i = rx_ring->next_to_clean;
1312 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1313 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1315 while (staterr & IXGBE_RXD_STAT_DD) {
1318 rmb(); /* read descriptor and rx_buffer_info after status DD */
1320 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1322 skb = rx_buffer_info->skb;
1323 rx_buffer_info->skb = NULL;
1324 prefetch(skb->data);
1326 if (ring_is_rsc_enabled(rx_ring))
1327 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1329 /* if this is a skb from previous receive DMA will be 0 */
1330 if (rx_buffer_info->dma) {
1333 !(staterr & IXGBE_RXD_STAT_EOP) &&
1336 * When HWRSC is enabled, delay unmapping
1337 * of the first packet. It carries the
1338 * header information, HW may still
1339 * access the header after the writeback.
1340 * Only unmap it when EOP is reached
1342 IXGBE_RSC_CB(skb)->delay_unmap = true;
1343 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1345 dma_unmap_single(rx_ring->dev,
1346 rx_buffer_info->dma,
1347 rx_ring->rx_buf_len,
1350 rx_buffer_info->dma = 0;
1352 if (ring_is_ps_enabled(rx_ring)) {
1353 hlen = ixgbe_get_hlen(rx_desc);
1354 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1356 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1361 /* assume packet split since header is unmapped */
1362 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1366 dma_unmap_page(rx_ring->dev,
1367 rx_buffer_info->page_dma,
1370 rx_buffer_info->page_dma = 0;
1371 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1372 rx_buffer_info->page,
1373 rx_buffer_info->page_offset,
1376 if ((page_count(rx_buffer_info->page) == 1) &&
1377 (page_to_nid(rx_buffer_info->page) == current_node))
1378 get_page(rx_buffer_info->page);
1380 rx_buffer_info->page = NULL;
1382 skb->len += upper_len;
1383 skb->data_len += upper_len;
1384 skb->truesize += upper_len;
1388 if (i == rx_ring->count)
1391 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1396 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397 IXGBE_RXDADV_NEXTP_SHIFT;
1398 next_buffer = &rx_ring->rx_buffer_info[nextp];
1400 next_buffer = &rx_ring->rx_buffer_info[i];
1403 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1404 if (ring_is_ps_enabled(rx_ring)) {
1405 rx_buffer_info->skb = next_buffer->skb;
1406 rx_buffer_info->dma = next_buffer->dma;
1407 next_buffer->skb = skb;
1408 next_buffer->dma = 0;
1410 skb->next = next_buffer->skb;
1411 skb->next->prev = skb;
1413 rx_ring->rx_stats.non_eop_descs++;
1418 skb = ixgbe_transform_rsc_queue(skb);
1419 /* if we got here without RSC the packet is invalid */
1421 __pskb_trim(skb, 0);
1422 rx_buffer_info->skb = skb;
1427 if (ring_is_rsc_enabled(rx_ring)) {
1428 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429 dma_unmap_single(rx_ring->dev,
1430 IXGBE_RSC_CB(skb)->dma,
1431 rx_ring->rx_buf_len,
1433 IXGBE_RSC_CB(skb)->dma = 0;
1434 IXGBE_RSC_CB(skb)->delay_unmap = false;
1438 if (ring_is_ps_enabled(rx_ring))
1439 rx_ring->rx_stats.rsc_count +=
1440 skb_shinfo(skb)->nr_frags;
1442 rx_ring->rx_stats.rsc_count +=
1443 IXGBE_RSC_CB(skb)->skb_cnt;
1444 rx_ring->rx_stats.rsc_flush++;
1447 /* ERR_MASK will only have valid bits if EOP set */
1448 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1449 /* trim packet back to size 0 and recycle it */
1450 __pskb_trim(skb, 0);
1451 rx_buffer_info->skb = skb;
1455 ixgbe_rx_checksum(adapter, rx_desc, skb);
1457 /* probably a little skewed due to removing CRC */
1458 total_rx_bytes += skb->len;
1461 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1463 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1469 #endif /* IXGBE_FCOE */
1470 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1473 rx_desc->wb.upper.status_error = 0;
1476 if (*work_done >= work_to_do)
1479 /* return some buffers to hardware, one at a time is too slow */
1480 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1481 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1485 /* use prefetched values */
1487 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1490 rx_ring->next_to_clean = i;
1491 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1494 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1497 /* include DDPed FCoE data */
1498 if (ddp_bytes > 0) {
1501 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1502 sizeof(struct fc_frame_header) -
1503 sizeof(struct fcoe_crc_eof);
1506 total_rx_bytes += ddp_bytes;
1507 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1509 #endif /* IXGBE_FCOE */
1511 rx_ring->total_packets += total_rx_packets;
1512 rx_ring->total_bytes += total_rx_bytes;
1513 u64_stats_update_begin(&rx_ring->syncp);
1514 rx_ring->stats.packets += total_rx_packets;
1515 rx_ring->stats.bytes += total_rx_bytes;
1516 u64_stats_update_end(&rx_ring->syncp);
1519 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1521 * ixgbe_configure_msix - Configure MSI-X hardware
1522 * @adapter: board private structure
1524 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1527 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1529 struct ixgbe_q_vector *q_vector;
1530 int i, q_vectors, v_idx, r_idx;
1533 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1536 * Populate the IVAR table and set the ITR values to the
1537 * corresponding register.
1539 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1540 q_vector = adapter->q_vector[v_idx];
1541 /* XXX for_each_set_bit(...) */
1542 r_idx = find_first_bit(q_vector->rxr_idx,
1543 adapter->num_rx_queues);
1545 for (i = 0; i < q_vector->rxr_count; i++) {
1546 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1548 r_idx = find_next_bit(q_vector->rxr_idx,
1549 adapter->num_rx_queues,
1552 r_idx = find_first_bit(q_vector->txr_idx,
1553 adapter->num_tx_queues);
1555 for (i = 0; i < q_vector->txr_count; i++) {
1556 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1558 r_idx = find_next_bit(q_vector->txr_idx,
1559 adapter->num_tx_queues,
1563 if (q_vector->txr_count && !q_vector->rxr_count)
1565 q_vector->eitr = adapter->tx_eitr_param;
1566 else if (q_vector->rxr_count)
1568 q_vector->eitr = adapter->rx_eitr_param;
1570 ixgbe_write_eitr(q_vector);
1571 /* If Flow Director is enabled, set interrupt affinity */
1572 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1575 * Allocate the affinity_hint cpumask, assign the mask
1576 * for this vector, and set our affinity_hint for
1579 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1582 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584 q_vector->affinity_mask);
1588 switch (adapter->hw.mac.type) {
1589 case ixgbe_mac_82598EB:
1590 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1593 case ixgbe_mac_82599EB:
1594 case ixgbe_mac_X540:
1595 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1603 /* set up to autoclear timer, and the vectors */
1604 mask = IXGBE_EIMS_ENABLE_MASK;
1605 if (adapter->num_vfs)
1606 mask &= ~(IXGBE_EIMS_OTHER |
1607 IXGBE_EIMS_MAILBOX |
1610 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1614 enum latency_range {
1618 latency_invalid = 255
1622 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623 * @adapter: pointer to adapter
1624 * @eitr: eitr setting (ints per sec) to give last timeslice
1625 * @itr_setting: current throttle rate in ints/second
1626 * @packets: the number of packets during this measurement interval
1627 * @bytes: the number of bytes during this measurement interval
1629 * Stores a new ITR value based on packets and byte
1630 * counts during the last interrupt. The advantage of per interrupt
1631 * computation is faster updates and more accurate ITR for the current
1632 * traffic pattern. Constants in this function were computed
1633 * based on theoretical maximum wire speed and thresholds were set based
1634 * on testing data as well as attempting to minimize response time
1635 * while increasing bulk throughput.
1636 * this functionality is controlled by the InterruptThrottleRate module
1637 * parameter (see ixgbe_param.c)
1639 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1640 u32 eitr, u8 itr_setting,
1641 int packets, int bytes)
1643 unsigned int retval = itr_setting;
1648 goto update_itr_done;
1651 /* simple throttlerate management
1652 * 0-20MB/s lowest (100000 ints/s)
1653 * 20-100MB/s low (20000 ints/s)
1654 * 100-1249MB/s bulk (8000 ints/s)
1656 /* what was last interrupt timeslice? */
1657 timepassed_us = 1000000/eitr;
1658 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1660 switch (itr_setting) {
1661 case lowest_latency:
1662 if (bytes_perint > adapter->eitr_low)
1663 retval = low_latency;
1666 if (bytes_perint > adapter->eitr_high)
1667 retval = bulk_latency;
1668 else if (bytes_perint <= adapter->eitr_low)
1669 retval = lowest_latency;
1672 if (bytes_perint <= adapter->eitr_high)
1673 retval = low_latency;
1682 * ixgbe_write_eitr - write EITR register in hardware specific way
1683 * @q_vector: structure containing interrupt and ring information
1685 * This function is made to be called by ethtool and by the driver
1686 * when it needs to update EITR registers at runtime. Hardware
1687 * specific quirks/differences are taken care of here.
1689 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1691 struct ixgbe_adapter *adapter = q_vector->adapter;
1692 struct ixgbe_hw *hw = &adapter->hw;
1693 int v_idx = q_vector->v_idx;
1694 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1696 switch (adapter->hw.mac.type) {
1697 case ixgbe_mac_82598EB:
1698 /* must write high and low 16 bits to reset counter */
1699 itr_reg |= (itr_reg << 16);
1701 case ixgbe_mac_82599EB:
1702 case ixgbe_mac_X540:
1704 * 82599 and X540 can support a value of zero, so allow it for
1705 * max interrupt rate, but there is an errata where it can
1706 * not be zero with RSC
1709 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1713 * set the WDIS bit to not clear the timer bits and cause an
1714 * immediate assertion of the interrupt
1716 itr_reg |= IXGBE_EITR_CNT_WDIS;
1721 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1724 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1726 struct ixgbe_adapter *adapter = q_vector->adapter;
1729 u8 current_itr, ret_itr;
1731 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732 for (i = 0; i < q_vector->txr_count; i++) {
1733 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1734 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1736 tx_ring->total_packets,
1737 tx_ring->total_bytes);
1738 /* if the result for this queue would decrease interrupt
1739 * rate for this vector then use that result */
1740 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1741 q_vector->tx_itr - 1 : ret_itr);
1742 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1746 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747 for (i = 0; i < q_vector->rxr_count; i++) {
1748 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1749 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1751 rx_ring->total_packets,
1752 rx_ring->total_bytes);
1753 /* if the result for this queue would decrease interrupt
1754 * rate for this vector then use that result */
1755 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1756 q_vector->rx_itr - 1 : ret_itr);
1757 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1761 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1763 switch (current_itr) {
1764 /* counts and packets in update_itr are dependent on these numbers */
1765 case lowest_latency:
1769 new_itr = 20000; /* aka hwitr = ~200 */
1777 if (new_itr != q_vector->eitr) {
1778 /* do an exponential smoothing */
1779 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1781 /* save the algorithm value here, not the smoothed one */
1782 q_vector->eitr = new_itr;
1784 ixgbe_write_eitr(q_vector);
1789 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790 * @work: pointer to work_struct containing our data
1792 static void ixgbe_check_overtemp_task(struct work_struct *work)
1794 struct ixgbe_adapter *adapter = container_of(work,
1795 struct ixgbe_adapter,
1796 check_overtemp_task);
1797 struct ixgbe_hw *hw = &adapter->hw;
1798 u32 eicr = adapter->interrupt_event;
1800 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1803 switch (hw->device_id) {
1804 case IXGBE_DEV_ID_82599_T3_LOM: {
1806 bool link_up = false;
1808 if (hw->mac.ops.check_link)
1809 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1811 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812 (eicr & IXGBE_EICR_LSC))
1813 /* Check if this is due to overtemp */
1814 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1819 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1824 "Network adapter has been stopped because it has over heated. "
1825 "Restart the computer. If the problem persists, "
1826 "power off the system and replace the adapter\n");
1827 /* write to clear the interrupt */
1828 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1831 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1833 struct ixgbe_hw *hw = &adapter->hw;
1835 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836 (eicr & IXGBE_EICR_GPI_SDP1)) {
1837 e_crit(probe, "Fan has stopped, replace the adapter\n");
1838 /* write to clear the interrupt */
1839 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1843 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1845 struct ixgbe_hw *hw = &adapter->hw;
1847 if (eicr & IXGBE_EICR_GPI_SDP2) {
1848 /* Clear the interrupt */
1849 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851 schedule_work(&adapter->sfp_config_module_task);
1854 if (eicr & IXGBE_EICR_GPI_SDP1) {
1855 /* Clear the interrupt */
1856 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858 schedule_work(&adapter->multispeed_fiber_task);
1862 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1864 struct ixgbe_hw *hw = &adapter->hw;
1867 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868 adapter->link_check_timeout = jiffies;
1869 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1871 IXGBE_WRITE_FLUSH(hw);
1872 schedule_work(&adapter->watchdog_task);
1876 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1878 struct net_device *netdev = data;
1879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880 struct ixgbe_hw *hw = &adapter->hw;
1884 * Workaround for Silicon errata. Use clear-by-write instead
1885 * of clear-by-read. Reading with EICS will return the
1886 * interrupt causes without clearing, which later be done
1887 * with the write to EICR.
1889 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1892 if (eicr & IXGBE_EICR_LSC)
1893 ixgbe_check_lsc(adapter);
1895 if (eicr & IXGBE_EICR_MAILBOX)
1896 ixgbe_msg_task(adapter);
1898 switch (hw->mac.type) {
1899 case ixgbe_mac_82599EB:
1900 ixgbe_check_sfp_event(adapter, eicr);
1901 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1903 adapter->interrupt_event = eicr;
1904 schedule_work(&adapter->check_overtemp_task);
1906 /* now fallthrough to handle Flow Director */
1907 case ixgbe_mac_X540:
1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr & IXGBE_EICR_FLOW_DIR) {
1911 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1912 /* Disable transmits before FDIR Re-initialization */
1913 netif_tx_stop_all_queues(netdev);
1914 for (i = 0; i < adapter->num_tx_queues; i++) {
1915 struct ixgbe_ring *tx_ring =
1916 adapter->tx_ring[i];
1917 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1919 schedule_work(&adapter->fdir_reinit_task);
1927 ixgbe_check_fan_failure(adapter, eicr);
1929 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1935 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1939 struct ixgbe_hw *hw = &adapter->hw;
1941 switch (hw->mac.type) {
1942 case ixgbe_mac_82598EB:
1943 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1944 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1946 case ixgbe_mac_82599EB:
1947 case ixgbe_mac_X540:
1948 mask = (qmask & 0xFFFFFFFF);
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1951 mask = (qmask >> 32);
1953 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1958 /* skip the flush */
1961 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1965 struct ixgbe_hw *hw = &adapter->hw;
1967 switch (hw->mac.type) {
1968 case ixgbe_mac_82598EB:
1969 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1970 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1972 case ixgbe_mac_82599EB:
1973 case ixgbe_mac_X540:
1974 mask = (qmask & 0xFFFFFFFF);
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1977 mask = (qmask >> 32);
1979 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1984 /* skip the flush */
1987 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1989 struct ixgbe_q_vector *q_vector = data;
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
1991 struct ixgbe_ring *tx_ring;
1994 if (!q_vector->txr_count)
1997 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1998 for (i = 0; i < q_vector->txr_count; i++) {
1999 tx_ring = adapter->tx_ring[r_idx];
2000 tx_ring->total_bytes = 0;
2001 tx_ring->total_packets = 0;
2002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2006 /* EIAM disabled interrupts (on this vector) for us */
2007 napi_schedule(&q_vector->napi);
2013 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2015 * @data: pointer to our q_vector struct for this interrupt vector
2017 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2019 struct ixgbe_q_vector *q_vector = data;
2020 struct ixgbe_adapter *adapter = q_vector->adapter;
2021 struct ixgbe_ring *rx_ring;
2025 #ifdef CONFIG_IXGBE_DCA
2026 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2027 ixgbe_update_dca(q_vector);
2030 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2031 for (i = 0; i < q_vector->rxr_count; i++) {
2032 rx_ring = adapter->rx_ring[r_idx];
2033 rx_ring->total_bytes = 0;
2034 rx_ring->total_packets = 0;
2035 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2039 if (!q_vector->rxr_count)
2042 /* EIAM disabled interrupts (on this vector) for us */
2043 napi_schedule(&q_vector->napi);
2048 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2050 struct ixgbe_q_vector *q_vector = data;
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 struct ixgbe_ring *ring;
2056 if (!q_vector->txr_count && !q_vector->rxr_count)
2059 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2060 for (i = 0; i < q_vector->txr_count; i++) {
2061 ring = adapter->tx_ring[r_idx];
2062 ring->total_bytes = 0;
2063 ring->total_packets = 0;
2064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2069 for (i = 0; i < q_vector->rxr_count; i++) {
2070 ring = adapter->rx_ring[r_idx];
2071 ring->total_bytes = 0;
2072 ring->total_packets = 0;
2073 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2077 /* EIAM disabled interrupts (on this vector) for us */
2078 napi_schedule(&q_vector->napi);
2084 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2085 * @napi: napi struct with our devices info in it
2086 * @budget: amount of work driver is allowed to do this pass, in packets
2088 * This function is optimized for cleaning one queue only on a single
2091 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2093 struct ixgbe_q_vector *q_vector =
2094 container_of(napi, struct ixgbe_q_vector, napi);
2095 struct ixgbe_adapter *adapter = q_vector->adapter;
2096 struct ixgbe_ring *rx_ring = NULL;
2100 #ifdef CONFIG_IXGBE_DCA
2101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2102 ixgbe_update_dca(q_vector);
2105 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2106 rx_ring = adapter->rx_ring[r_idx];
2108 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2110 /* If all Rx work done, exit the polling mode */
2111 if (work_done < budget) {
2112 napi_complete(napi);
2113 if (adapter->rx_itr_setting & 1)
2114 ixgbe_set_itr_msix(q_vector);
2115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2116 ixgbe_irq_enable_queues(adapter,
2117 ((u64)1 << q_vector->v_idx));
2124 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2125 * @napi: napi struct with our devices info in it
2126 * @budget: amount of work driver is allowed to do this pass, in packets
2128 * This function will clean more than one rx queue associated with a
2131 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2133 struct ixgbe_q_vector *q_vector =
2134 container_of(napi, struct ixgbe_q_vector, napi);
2135 struct ixgbe_adapter *adapter = q_vector->adapter;
2136 struct ixgbe_ring *ring = NULL;
2137 int work_done = 0, i;
2139 bool tx_clean_complete = true;
2141 #ifdef CONFIG_IXGBE_DCA
2142 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2143 ixgbe_update_dca(q_vector);
2146 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2147 for (i = 0; i < q_vector->txr_count; i++) {
2148 ring = adapter->tx_ring[r_idx];
2149 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2150 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2154 /* attempt to distribute budget to each queue fairly, but don't allow
2155 * the budget to go below 1 because we'll exit polling */
2156 budget /= (q_vector->rxr_count ?: 1);
2157 budget = max(budget, 1);
2158 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2159 for (i = 0; i < q_vector->rxr_count; i++) {
2160 ring = adapter->rx_ring[r_idx];
2161 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2162 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2166 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2167 ring = adapter->rx_ring[r_idx];
2168 /* If all Rx work done, exit the polling mode */
2169 if (work_done < budget) {
2170 napi_complete(napi);
2171 if (adapter->rx_itr_setting & 1)
2172 ixgbe_set_itr_msix(q_vector);
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable_queues(adapter,
2175 ((u64)1 << q_vector->v_idx));
2183 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2184 * @napi: napi struct with our devices info in it
2185 * @budget: amount of work driver is allowed to do this pass, in packets
2187 * This function is optimized for cleaning one queue only on a single
2190 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2192 struct ixgbe_q_vector *q_vector =
2193 container_of(napi, struct ixgbe_q_vector, napi);
2194 struct ixgbe_adapter *adapter = q_vector->adapter;
2195 struct ixgbe_ring *tx_ring = NULL;
2199 #ifdef CONFIG_IXGBE_DCA
2200 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2201 ixgbe_update_dca(q_vector);
2204 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2205 tx_ring = adapter->tx_ring[r_idx];
2207 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2210 /* If all Tx work done, exit the polling mode */
2211 if (work_done < budget) {
2212 napi_complete(napi);
2213 if (adapter->tx_itr_setting & 1)
2214 ixgbe_set_itr_msix(q_vector);
2215 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2216 ixgbe_irq_enable_queues(adapter,
2217 ((u64)1 << q_vector->v_idx));
2223 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2226 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2229 set_bit(r_idx, q_vector->rxr_idx);
2230 q_vector->rxr_count++;
2231 rx_ring->q_vector = q_vector;
2234 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2240 set_bit(t_idx, q_vector->txr_idx);
2241 q_vector->txr_count++;
2242 tx_ring->q_vector = q_vector;
2246 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2247 * @adapter: board private structure to initialize
2249 * This function maps descriptor rings to the queue-specific vectors
2250 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2251 * one vector per ring/queue, but on a constrained vector budget, we
2252 * group the rings as "efficiently" as possible. You would add new
2253 * mapping configurations in here.
2255 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2259 int rxr_idx = 0, txr_idx = 0;
2260 int rxr_remaining = adapter->num_rx_queues;
2261 int txr_remaining = adapter->num_tx_queues;
2266 /* No mapping required if MSI-X is disabled. */
2267 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2270 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2273 * The ideal configuration...
2274 * We have enough vectors to map one per queue.
2276 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2277 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2278 map_vector_to_rxq(adapter, v_start, rxr_idx);
2280 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2281 map_vector_to_txq(adapter, v_start, txr_idx);
2287 * If we don't have enough vectors for a 1-to-1
2288 * mapping, we'll have to group them so there are
2289 * multiple queues per vector.
2291 /* Re-adjusting *qpv takes care of the remainder. */
2292 for (i = v_start; i < q_vectors; i++) {
2293 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2294 for (j = 0; j < rqpv; j++) {
2295 map_vector_to_rxq(adapter, i, rxr_idx);
2299 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2300 for (j = 0; j < tqpv; j++) {
2301 map_vector_to_txq(adapter, i, txr_idx);
2311 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2312 * @adapter: board private structure
2314 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2315 * interrupts from the kernel.
2317 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2319 struct net_device *netdev = adapter->netdev;
2320 irqreturn_t (*handler)(int, void *);
2321 int i, vector, q_vectors, err;
2324 /* Decrement for Other and TCP Timer vectors */
2325 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2327 err = ixgbe_map_rings_to_vectors(adapter);
2331 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2332 ? &ixgbe_msix_clean_many : \
2333 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2334 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2336 for (vector = 0; vector < q_vectors; vector++) {
2337 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2338 handler = SET_HANDLER(q_vector);
2340 if (handler == &ixgbe_msix_clean_rx) {
2341 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2342 "%s-%s-%d", netdev->name, "rx", ri++);
2343 } else if (handler == &ixgbe_msix_clean_tx) {
2344 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2345 "%s-%s-%d", netdev->name, "tx", ti++);
2346 } else if (handler == &ixgbe_msix_clean_many) {
2347 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2348 "%s-%s-%d", netdev->name, "TxRx", ri++);
2351 /* skip this unused q_vector */
2354 err = request_irq(adapter->msix_entries[vector].vector,
2355 handler, 0, q_vector->name,
2358 e_err(probe, "request_irq failed for MSIX interrupt "
2359 "Error: %d\n", err);
2360 goto free_queue_irqs;
2364 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2365 err = request_irq(adapter->msix_entries[vector].vector,
2366 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2368 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2369 goto free_queue_irqs;
2375 for (i = vector - 1; i >= 0; i--)
2376 free_irq(adapter->msix_entries[--vector].vector,
2377 adapter->q_vector[i]);
2378 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2379 pci_disable_msix(adapter->pdev);
2380 kfree(adapter->msix_entries);
2381 adapter->msix_entries = NULL;
2385 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2387 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2388 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2389 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2390 u32 new_itr = q_vector->eitr;
2393 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2395 tx_ring->total_packets,
2396 tx_ring->total_bytes);
2397 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2399 rx_ring->total_packets,
2400 rx_ring->total_bytes);
2402 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2404 switch (current_itr) {
2405 /* counts and packets in update_itr are dependent on these numbers */
2406 case lowest_latency:
2410 new_itr = 20000; /* aka hwitr = ~200 */
2419 if (new_itr != q_vector->eitr) {
2420 /* do an exponential smoothing */
2421 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2423 /* save the algorithm value here */
2424 q_vector->eitr = new_itr;
2426 ixgbe_write_eitr(q_vector);
2431 * ixgbe_irq_enable - Enable default interrupt generation settings
2432 * @adapter: board private structure
2434 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2439 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2440 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2441 mask |= IXGBE_EIMS_GPI_SDP0;
2442 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2443 mask |= IXGBE_EIMS_GPI_SDP1;
2444 switch (adapter->hw.mac.type) {
2445 case ixgbe_mac_82599EB:
2446 case ixgbe_mac_X540:
2447 mask |= IXGBE_EIMS_ECC;
2448 mask |= IXGBE_EIMS_GPI_SDP1;
2449 mask |= IXGBE_EIMS_GPI_SDP2;
2450 if (adapter->num_vfs)
2451 mask |= IXGBE_EIMS_MAILBOX;
2456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2457 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2458 mask |= IXGBE_EIMS_FLOW_DIR;
2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2462 ixgbe_irq_enable_queues(adapter, ~0);
2464 IXGBE_WRITE_FLUSH(&adapter->hw);
2466 if (adapter->num_vfs > 32) {
2467 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2473 * ixgbe_intr - legacy mode Interrupt Handler
2474 * @irq: interrupt number
2475 * @data: pointer to a network interface device structure
2477 static irqreturn_t ixgbe_intr(int irq, void *data)
2479 struct net_device *netdev = data;
2480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
2482 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2486 * Workaround for silicon errata on 82598. Mask the interrupts
2487 * before the read of EICR.
2489 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2491 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2492 * therefore no explict interrupt disable is necessary */
2493 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2496 * shared interrupt alert!
2497 * make sure interrupts are enabled because the read will
2498 * have disabled interrupts due to EIAM
2499 * finish the workaround of silicon errata on 82598. Unmask
2500 * the interrupt that we masked before the EICR read.
2502 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2503 ixgbe_irq_enable(adapter, true, true);
2504 return IRQ_NONE; /* Not our interrupt */
2507 if (eicr & IXGBE_EICR_LSC)
2508 ixgbe_check_lsc(adapter);
2510 switch (hw->mac.type) {
2511 case ixgbe_mac_82599EB:
2512 ixgbe_check_sfp_event(adapter, eicr);
2513 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515 adapter->interrupt_event = eicr;
2516 schedule_work(&adapter->check_overtemp_task);
2523 ixgbe_check_fan_failure(adapter, eicr);
2525 if (napi_schedule_prep(&(q_vector->napi))) {
2526 adapter->tx_ring[0]->total_packets = 0;
2527 adapter->tx_ring[0]->total_bytes = 0;
2528 adapter->rx_ring[0]->total_packets = 0;
2529 adapter->rx_ring[0]->total_bytes = 0;
2530 /* would disable interrupts here but EIAM disabled it */
2531 __napi_schedule(&(q_vector->napi));
2535 * re-enable link(maybe) and non-queue interrupts, no flush.
2536 * ixgbe_poll will re-enable the queue interrupts
2539 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540 ixgbe_irq_enable(adapter, false, false);
2545 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2547 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2549 for (i = 0; i < q_vectors; i++) {
2550 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2551 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553 q_vector->rxr_count = 0;
2554 q_vector->txr_count = 0;
2559 * ixgbe_request_irq - initialize interrupts
2560 * @adapter: board private structure
2562 * Attempts to configure interrupts using the best available
2563 * capabilities of the hardware and kernel.
2565 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2567 struct net_device *netdev = adapter->netdev;
2570 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571 err = ixgbe_request_msix_irqs(adapter);
2572 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2573 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2574 netdev->name, netdev);
2576 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2577 netdev->name, netdev);
2581 e_err(probe, "request_irq failed, Error %d\n", err);
2586 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2588 struct net_device *netdev = adapter->netdev;
2590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2593 q_vectors = adapter->num_msix_vectors;
2596 free_irq(adapter->msix_entries[i].vector, netdev);
2599 for (; i >= 0; i--) {
2600 free_irq(adapter->msix_entries[i].vector,
2601 adapter->q_vector[i]);
2604 ixgbe_reset_q_vectors(adapter);
2606 free_irq(adapter->pdev->irq, netdev);
2611 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2612 * @adapter: board private structure
2614 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2616 switch (adapter->hw.mac.type) {
2617 case ixgbe_mac_82598EB:
2618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2620 case ixgbe_mac_82599EB:
2621 case ixgbe_mac_X540:
2622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2625 if (adapter->num_vfs > 32)
2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2631 IXGBE_WRITE_FLUSH(&adapter->hw);
2632 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2634 for (i = 0; i < adapter->num_msix_vectors; i++)
2635 synchronize_irq(adapter->msix_entries[i].vector);
2637 synchronize_irq(adapter->pdev->irq);
2642 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2645 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2647 struct ixgbe_hw *hw = &adapter->hw;
2649 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2650 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2652 ixgbe_set_ivar(adapter, 0, 0, 0);
2653 ixgbe_set_ivar(adapter, 1, 0, 0);
2655 map_vector_to_rxq(adapter, 0, 0);
2656 map_vector_to_txq(adapter, 0, 0);
2658 e_info(hw, "Legacy interrupt IVAR setup done\n");
2662 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2663 * @adapter: board private structure
2664 * @ring: structure containing ring specific data
2666 * Configure the Tx descriptor ring after a reset.
2668 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2669 struct ixgbe_ring *ring)
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u64 tdba = ring->dma;
2675 u8 reg_idx = ring->reg_idx;
2677 /* disable queue to avoid issues while updating state */
2678 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2679 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2680 txdctl & ~IXGBE_TXDCTL_ENABLE);
2681 IXGBE_WRITE_FLUSH(hw);
2683 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2684 (tdba & DMA_BIT_MASK(32)));
2685 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2686 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2687 ring->count * sizeof(union ixgbe_adv_tx_desc));
2688 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2689 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2690 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2692 /* configure fetching thresholds */
2693 if (adapter->rx_itr_setting == 0) {
2694 /* cannot set wthresh when itr==0 */
2695 txdctl &= ~0x007F0000;
2697 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2698 txdctl |= (8 << 16);
2700 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2701 /* PThresh workaround for Tx hang with DFP enabled. */
2705 /* reinitialize flowdirector state */
2706 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2707 adapter->atr_sample_rate) {
2708 ring->atr_sample_rate = adapter->atr_sample_rate;
2709 ring->atr_count = 0;
2710 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2712 ring->atr_sample_rate = 0;
2715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2718 txdctl |= IXGBE_TXDCTL_ENABLE;
2719 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2721 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2726 /* poll to verify queue is enabled */
2729 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2730 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2732 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2735 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2737 struct ixgbe_hw *hw = &adapter->hw;
2741 if (hw->mac.type == ixgbe_mac_82598EB)
2744 /* disable the arbiter while setting MTQC */
2745 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2746 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2747 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2749 /* set transmit pool layout */
2750 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2751 switch (adapter->flags & mask) {
2753 case (IXGBE_FLAG_SRIOV_ENABLED):
2754 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2755 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2758 case (IXGBE_FLAG_DCB_ENABLED):
2759 /* We enable 8 traffic classes, DCB only */
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2765 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2769 /* re-enable the arbiter */
2770 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2775 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2776 * @adapter: board private structure
2778 * Configure the Tx unit of the MAC after a reset.
2780 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2782 struct ixgbe_hw *hw = &adapter->hw;
2786 ixgbe_setup_mtqc(adapter);
2788 if (hw->mac.type != ixgbe_mac_82598EB) {
2789 /* DMATXCTL.EN must be before Tx queues are enabled */
2790 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2791 dmatxctl |= IXGBE_DMATXCTL_TE;
2792 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2795 /* Setup the HW Tx Head and Tail descriptor pointers */
2796 for (i = 0; i < adapter->num_tx_queues; i++)
2797 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2800 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2802 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *rx_ring)
2806 u8 reg_idx = rx_ring->reg_idx;
2808 switch (adapter->hw.mac.type) {
2809 case ixgbe_mac_82598EB: {
2810 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2811 const int mask = feature[RING_F_RSS].mask;
2812 reg_idx = reg_idx & mask;
2815 case ixgbe_mac_82599EB:
2816 case ixgbe_mac_X540:
2821 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2823 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2824 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2825 if (adapter->num_vfs)
2826 srrctl |= IXGBE_SRRCTL_DROP_EN;
2828 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2829 IXGBE_SRRCTL_BSIZEHDR_MASK;
2831 if (ring_is_ps_enabled(rx_ring)) {
2832 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2833 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2835 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2837 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2839 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2840 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2847 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2849 struct ixgbe_hw *hw = &adapter->hw;
2850 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2851 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2852 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2853 u32 mrqc = 0, reta = 0;
2858 /* Fill out hash function seeds */
2859 for (i = 0; i < 10; i++)
2860 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2862 /* Fill out redirection table */
2863 for (i = 0, j = 0; i < 128; i++, j++) {
2864 if (j == adapter->ring_feature[RING_F_RSS].indices)
2866 /* reta = 4-byte sliding window of
2867 * 0x00..(indices-1)(indices-1)00..etc. */
2868 reta = (reta << 8) | (j * 0x11);
2870 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2873 /* Disable indicating checksum in descriptor, enables RSS hash */
2874 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2875 rxcsum |= IXGBE_RXCSUM_PCSD;
2876 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2878 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2879 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2881 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2882 #ifdef CONFIG_IXGBE_DCB
2883 | IXGBE_FLAG_DCB_ENABLED
2885 | IXGBE_FLAG_SRIOV_ENABLED
2889 case (IXGBE_FLAG_RSS_ENABLED):
2890 mrqc = IXGBE_MRQC_RSSEN;
2892 case (IXGBE_FLAG_SRIOV_ENABLED):
2893 mrqc = IXGBE_MRQC_VMDQEN;
2895 #ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED):
2897 mrqc = IXGBE_MRQC_RT8TCEN;
2899 #endif /* CONFIG_IXGBE_DCB */
2904 /* Perform hash on these packet types */
2905 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2906 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2907 | IXGBE_MRQC_RSS_FIELD_IPV6
2908 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2910 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2914 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2915 * @adapter: address of board private structure
2916 * @ring: structure containing ring specific data
2918 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2919 struct ixgbe_ring *ring)
2921 struct ixgbe_hw *hw = &adapter->hw;
2923 u8 reg_idx = ring->reg_idx;
2925 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2926 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2931 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2932 * @adapter: address of board private structure
2933 * @index: index of ring to set
2935 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2936 struct ixgbe_ring *ring)
2938 struct ixgbe_hw *hw = &adapter->hw;
2941 u8 reg_idx = ring->reg_idx;
2943 if (!ring_is_rsc_enabled(ring))
2946 rx_buf_len = ring->rx_buf_len;
2947 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2948 rscctrl |= IXGBE_RSCCTL_RSCEN;
2950 * we must limit the number of descriptors so that the
2951 * total size of max desc * buf_len is not greater
2954 if (ring_is_ps_enabled(ring)) {
2955 #if (MAX_SKB_FRAGS > 16)
2956 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2957 #elif (MAX_SKB_FRAGS > 8)
2958 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2959 #elif (MAX_SKB_FRAGS > 4)
2960 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2965 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2967 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2970 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2972 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2976 * ixgbe_set_uta - Set unicast filter table address
2977 * @adapter: board private structure
2979 * The unicast table address is a register array of 32-bit registers.
2980 * The table is meant to be used in a way similar to how the MTA is used
2981 * however due to certain limitations in the hardware it is necessary to
2982 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2983 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2985 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2987 struct ixgbe_hw *hw = &adapter->hw;
2990 /* The UTA table only exists on 82599 hardware and newer */
2991 if (hw->mac.type < ixgbe_mac_82599EB)
2994 /* we only need to do this if VMDq is enabled */
2995 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2998 for (i = 0; i < 128; i++)
2999 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3002 #define IXGBE_MAX_RX_DESC_POLL 10
3003 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004 struct ixgbe_ring *ring)
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3009 u8 reg_idx = ring->reg_idx;
3011 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012 if (hw->mac.type == ixgbe_mac_82598EB &&
3013 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3018 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3022 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023 "the polling period\n", reg_idx);
3027 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 u64 rdba = ring->dma;
3033 u8 reg_idx = ring->reg_idx;
3035 /* disable queue to avoid issues while updating state */
3036 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3037 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
3038 rxdctl & ~IXGBE_RXDCTL_ENABLE);
3039 IXGBE_WRITE_FLUSH(hw);
3041 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3042 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3043 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3044 ring->count * sizeof(union ixgbe_adv_rx_desc));
3045 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3046 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3047 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3049 ixgbe_configure_srrctl(adapter, ring);
3050 ixgbe_configure_rscctl(adapter, ring);
3052 if (hw->mac.type == ixgbe_mac_82598EB) {
3054 * enable cache line friendly hardware writes:
3055 * PTHRESH=32 descriptors (half the internal cache),
3056 * this also removes ugly rx_no_buffer_count increment
3057 * HTHRESH=4 descriptors (to minimize latency on fetch)
3058 * WTHRESH=8 burst writeback up to two cache lines
3060 rxdctl &= ~0x3FFFFF;
3064 /* enable receive descriptor ring */
3065 rxdctl |= IXGBE_RXDCTL_ENABLE;
3066 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3068 ixgbe_rx_desc_queue_enable(adapter, ring);
3069 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3072 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3074 struct ixgbe_hw *hw = &adapter->hw;
3077 /* PSRTYPE must be initialized in non 82598 adapters */
3078 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3079 IXGBE_PSRTYPE_UDPHDR |
3080 IXGBE_PSRTYPE_IPV4HDR |
3081 IXGBE_PSRTYPE_L2HDR |
3082 IXGBE_PSRTYPE_IPV6HDR;
3084 if (hw->mac.type == ixgbe_mac_82598EB)
3087 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3088 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3090 for (p = 0; p < adapter->num_rx_pools; p++)
3091 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3095 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3097 struct ixgbe_hw *hw = &adapter->hw;
3100 u32 reg_offset, vf_shift;
3103 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3106 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3107 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3108 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3109 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3111 vf_shift = adapter->num_vfs % 32;
3112 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3114 /* Enable only the PF's pool for Tx/Rx */
3115 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3116 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3117 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3118 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3119 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3121 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3122 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3125 * Set up VF register offsets for selected VT Mode,
3126 * i.e. 32 or 64 VFs for SR-IOV
3128 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3129 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3130 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3131 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3133 /* enable Tx loopback for VF/PF communication */
3134 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3137 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3139 struct ixgbe_hw *hw = &adapter->hw;
3140 struct net_device *netdev = adapter->netdev;
3141 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3143 struct ixgbe_ring *rx_ring;
3147 /* Decide whether to use packet split mode or not */
3148 /* Do not use packet split if we're in SR-IOV Mode */
3149 if (!adapter->num_vfs)
3150 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3152 /* Set the RX buffer length according to the mode */
3153 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3154 rx_buf_len = IXGBE_RX_HDR_SIZE;
3156 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3157 (netdev->mtu <= ETH_DATA_LEN))
3158 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3160 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3164 /* adjust max frame to be able to do baby jumbo for FCoE */
3165 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3166 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3167 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3169 #endif /* IXGBE_FCOE */
3170 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3171 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3172 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3173 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3175 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3178 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3179 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3180 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3181 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3184 * Setup the HW Rx Head and Tail Descriptor Pointers and
3185 * the Base and Length of the Rx Descriptor Ring
3187 for (i = 0; i < adapter->num_rx_queues; i++) {
3188 rx_ring = adapter->rx_ring[i];
3189 rx_ring->rx_buf_len = rx_buf_len;
3191 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3192 set_ring_ps_enabled(rx_ring);
3194 clear_ring_ps_enabled(rx_ring);
3196 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3197 set_ring_rsc_enabled(rx_ring);
3199 clear_ring_rsc_enabled(rx_ring);
3202 if (netdev->features & NETIF_F_FCOE_MTU) {
3203 struct ixgbe_ring_feature *f;
3204 f = &adapter->ring_feature[RING_F_FCOE];
3205 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3206 clear_ring_ps_enabled(rx_ring);
3207 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3208 rx_ring->rx_buf_len =
3209 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3210 } else if (!ring_is_rsc_enabled(rx_ring) &&
3211 !ring_is_ps_enabled(rx_ring)) {
3212 rx_ring->rx_buf_len =
3213 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3216 #endif /* IXGBE_FCOE */
3220 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3222 struct ixgbe_hw *hw = &adapter->hw;
3223 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3225 switch (hw->mac.type) {
3226 case ixgbe_mac_82598EB:
3228 * For VMDq support of different descriptor types or
3229 * buffer sizes through the use of multiple SRRCTL
3230 * registers, RDRXCTL.MVMEN must be set to 1
3232 * also, the manual doesn't mention it clearly but DCA hints
3233 * will only use queue 0's tags unless this bit is set. Side
3234 * effects of setting this bit are only that SRRCTL must be
3235 * fully programmed [0..15]
3237 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3239 case ixgbe_mac_82599EB:
3240 case ixgbe_mac_X540:
3241 /* Disable RSC for ACK packets */
3242 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3243 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3244 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3245 /* hardware requires some bits to be set by default */
3246 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3247 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3250 /* We should do nothing since we don't know this hardware */
3254 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3258 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3259 * @adapter: board private structure
3261 * Configure the Rx unit of the MAC after a reset.
3263 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3265 struct ixgbe_hw *hw = &adapter->hw;
3269 /* disable receives while setting up the descriptors */
3270 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3271 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3273 ixgbe_setup_psrtype(adapter);
3274 ixgbe_setup_rdrxctl(adapter);
3276 /* Program registers for the distribution of queues */
3277 ixgbe_setup_mrqc(adapter);
3279 ixgbe_set_uta(adapter);
3281 /* set_rx_buffer_len must be called before ring initialization */
3282 ixgbe_set_rx_buffer_len(adapter);
3285 * Setup the HW Rx Head and Tail Descriptor Pointers and
3286 * the Base and Length of the Rx Descriptor Ring
3288 for (i = 0; i < adapter->num_rx_queues; i++)
3289 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3291 /* disable drop enable for 82598 parts */
3292 if (hw->mac.type == ixgbe_mac_82598EB)
3293 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3295 /* enable all receives */
3296 rxctrl |= IXGBE_RXCTRL_RXEN;
3297 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3300 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3302 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3303 struct ixgbe_hw *hw = &adapter->hw;
3304 int pool_ndx = adapter->num_vfs;
3306 /* add VID to filter table */
3307 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3308 set_bit(vid, adapter->active_vlans);
3311 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3313 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3314 struct ixgbe_hw *hw = &adapter->hw;
3315 int pool_ndx = adapter->num_vfs;
3317 /* remove VID from filter table */
3318 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3319 clear_bit(vid, adapter->active_vlans);
3323 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3324 * @adapter: driver data
3326 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3328 struct ixgbe_hw *hw = &adapter->hw;
3331 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3332 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3333 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3337 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3338 * @adapter: driver data
3340 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3342 struct ixgbe_hw *hw = &adapter->hw;
3345 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3346 vlnctrl |= IXGBE_VLNCTRL_VFE;
3347 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3348 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3352 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3353 * @adapter: driver data
3355 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3357 struct ixgbe_hw *hw = &adapter->hw;
3361 switch (hw->mac.type) {
3362 case ixgbe_mac_82598EB:
3363 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3364 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3365 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3367 case ixgbe_mac_82599EB:
3368 case ixgbe_mac_X540:
3369 for (i = 0; i < adapter->num_rx_queues; i++) {
3370 j = adapter->rx_ring[i]->reg_idx;
3371 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3372 vlnctrl &= ~IXGBE_RXDCTL_VME;
3373 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3382 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3383 * @adapter: driver data
3385 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3387 struct ixgbe_hw *hw = &adapter->hw;
3391 switch (hw->mac.type) {
3392 case ixgbe_mac_82598EB:
3393 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3394 vlnctrl |= IXGBE_VLNCTRL_VME;
3395 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3397 case ixgbe_mac_82599EB:
3398 case ixgbe_mac_X540:
3399 for (i = 0; i < adapter->num_rx_queues; i++) {
3400 j = adapter->rx_ring[i]->reg_idx;
3401 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3402 vlnctrl |= IXGBE_RXDCTL_VME;
3403 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3411 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3415 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3417 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3418 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3422 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3423 * @netdev: network interface device structure
3425 * Writes unicast address list to the RAR table.
3426 * Returns: -ENOMEM on failure/insufficient address space
3427 * 0 on no addresses written
3428 * X on writing X addresses to the RAR table
3430 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3432 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3433 struct ixgbe_hw *hw = &adapter->hw;
3434 unsigned int vfn = adapter->num_vfs;
3435 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3438 /* return ENOMEM indicating insufficient memory for addresses */
3439 if (netdev_uc_count(netdev) > rar_entries)
3442 if (!netdev_uc_empty(netdev) && rar_entries) {
3443 struct netdev_hw_addr *ha;
3444 /* return error if we do not support writing to RAR table */
3445 if (!hw->mac.ops.set_rar)
3448 netdev_for_each_uc_addr(ha, netdev) {
3451 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3456 /* write the addresses in reverse order to avoid write combining */
3457 for (; rar_entries > 0 ; rar_entries--)
3458 hw->mac.ops.clear_rar(hw, rar_entries);
3464 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3465 * @netdev: network interface device structure
3467 * The set_rx_method entry point is called whenever the unicast/multicast
3468 * address list or the network interface flags are updated. This routine is
3469 * responsible for configuring the hardware for proper unicast, multicast and
3472 void ixgbe_set_rx_mode(struct net_device *netdev)
3474 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3475 struct ixgbe_hw *hw = &adapter->hw;
3476 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3479 /* Check for Promiscuous and All Multicast modes */
3481 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3483 /* set all bits that we expect to always be set */
3484 fctrl |= IXGBE_FCTRL_BAM;
3485 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3486 fctrl |= IXGBE_FCTRL_PMCF;
3488 /* clear the bits we are changing the status of */
3489 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3491 if (netdev->flags & IFF_PROMISC) {
3492 hw->addr_ctrl.user_set_promisc = true;
3493 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3494 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3495 /* don't hardware filter vlans in promisc mode */
3496 ixgbe_vlan_filter_disable(adapter);
3498 if (netdev->flags & IFF_ALLMULTI) {
3499 fctrl |= IXGBE_FCTRL_MPE;
3500 vmolr |= IXGBE_VMOLR_MPE;
3503 * Write addresses to the MTA, if the attempt fails
3504 * then we should just turn on promiscous mode so
3505 * that we can at least receive multicast traffic
3507 hw->mac.ops.update_mc_addr_list(hw, netdev);
3508 vmolr |= IXGBE_VMOLR_ROMPE;
3510 ixgbe_vlan_filter_enable(adapter);
3511 hw->addr_ctrl.user_set_promisc = false;
3513 * Write addresses to available RAR registers, if there is not
3514 * sufficient space to store all the addresses then enable
3515 * unicast promiscous mode
3517 count = ixgbe_write_uc_addr_list(netdev);
3519 fctrl |= IXGBE_FCTRL_UPE;
3520 vmolr |= IXGBE_VMOLR_ROPE;
3524 if (adapter->num_vfs) {
3525 ixgbe_restore_vf_multicasts(adapter);
3526 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3527 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3529 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3532 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3534 if (netdev->features & NETIF_F_HW_VLAN_RX)
3535 ixgbe_vlan_strip_enable(adapter);
3537 ixgbe_vlan_strip_disable(adapter);
3540 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3543 struct ixgbe_q_vector *q_vector;
3544 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3546 /* legacy and MSI only use one vector */
3547 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3550 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3551 struct napi_struct *napi;
3552 q_vector = adapter->q_vector[q_idx];
3553 napi = &q_vector->napi;
3554 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3555 if (!q_vector->rxr_count || !q_vector->txr_count) {
3556 if (q_vector->txr_count == 1)
3557 napi->poll = &ixgbe_clean_txonly;
3558 else if (q_vector->rxr_count == 1)
3559 napi->poll = &ixgbe_clean_rxonly;
3567 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3570 struct ixgbe_q_vector *q_vector;
3571 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3573 /* legacy and MSI only use one vector */
3574 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3577 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3578 q_vector = adapter->q_vector[q_idx];
3579 napi_disable(&q_vector->napi);
3583 #ifdef CONFIG_IXGBE_DCB
3585 * ixgbe_configure_dcb - Configure DCB hardware
3586 * @adapter: ixgbe adapter struct
3588 * This is called by the driver on open to configure the DCB hardware.
3589 * This is also called by the gennetlink interface when reconfiguring
3592 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3594 struct ixgbe_hw *hw = &adapter->hw;
3595 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3597 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3598 if (hw->mac.type == ixgbe_mac_82598EB)
3599 netif_set_gso_max_size(adapter->netdev, 65536);
3603 if (hw->mac.type == ixgbe_mac_82598EB)
3604 netif_set_gso_max_size(adapter->netdev, 32768);
3607 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3608 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3611 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3613 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3616 /* Enable VLAN tag insert/strip */
3617 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3619 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3621 /* reconfigure the hardware */
3622 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3626 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3628 struct net_device *netdev = adapter->netdev;
3629 struct ixgbe_hw *hw = &adapter->hw;
3632 #ifdef CONFIG_IXGBE_DCB
3633 ixgbe_configure_dcb(adapter);
3636 ixgbe_set_rx_mode(netdev);
3637 ixgbe_restore_vlan(adapter);
3640 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3641 ixgbe_configure_fcoe(adapter);
3643 #endif /* IXGBE_FCOE */
3644 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3645 for (i = 0; i < adapter->num_tx_queues; i++)
3646 adapter->tx_ring[i]->atr_sample_rate =
3647 adapter->atr_sample_rate;
3648 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3649 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3650 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3652 ixgbe_configure_virtualization(adapter);
3654 ixgbe_configure_tx(adapter);
3655 ixgbe_configure_rx(adapter);
3658 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3660 switch (hw->phy.type) {
3661 case ixgbe_phy_sfp_avago:
3662 case ixgbe_phy_sfp_ftl:
3663 case ixgbe_phy_sfp_intel:
3664 case ixgbe_phy_sfp_unknown:
3665 case ixgbe_phy_sfp_passive_tyco:
3666 case ixgbe_phy_sfp_passive_unknown:
3667 case ixgbe_phy_sfp_active_unknown:
3668 case ixgbe_phy_sfp_ftl_active:
3676 * ixgbe_sfp_link_config - set up SFP+ link
3677 * @adapter: pointer to private adapter struct
3679 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3681 struct ixgbe_hw *hw = &adapter->hw;
3683 if (hw->phy.multispeed_fiber) {
3685 * In multispeed fiber setups, the device may not have
3686 * had a physical connection when the driver loaded.
3687 * If that's the case, the initial link configuration
3688 * couldn't get the MAC into 10G or 1G mode, so we'll
3689 * never have a link status change interrupt fire.
3690 * We need to try and force an autonegotiation
3691 * session, then bring up link.
3693 hw->mac.ops.setup_sfp(hw);
3694 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3695 schedule_work(&adapter->multispeed_fiber_task);
3698 * Direct Attach Cu and non-multispeed fiber modules
3699 * still need to be configured properly prior to
3702 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3703 schedule_work(&adapter->sfp_config_module_task);
3708 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3709 * @hw: pointer to private hardware struct
3711 * Returns 0 on success, negative on failure
3713 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3716 bool negotiation, link_up = false;
3717 u32 ret = IXGBE_ERR_LINK_SETUP;
3719 if (hw->mac.ops.check_link)
3720 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3725 if (hw->mac.ops.get_link_capabilities)
3726 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3731 if (hw->mac.ops.setup_link)
3732 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3737 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3739 struct ixgbe_hw *hw = &adapter->hw;
3742 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3743 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3745 gpie |= IXGBE_GPIE_EIAME;
3747 * use EIAM to auto-mask when MSI-X interrupt is asserted
3748 * this saves a register write for every interrupt
3750 switch (hw->mac.type) {
3751 case ixgbe_mac_82598EB:
3752 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3754 case ixgbe_mac_82599EB:
3755 case ixgbe_mac_X540:
3757 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3758 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3762 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3763 * specifically only auto mask tx and rx interrupts */
3764 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3767 /* XXX: to interrupt immediately for EICS writes, enable this */
3768 /* gpie |= IXGBE_GPIE_EIMEN; */
3770 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3771 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3772 gpie |= IXGBE_GPIE_VTMODE_64;
3775 /* Enable fan failure interrupt */
3776 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3777 gpie |= IXGBE_SDP1_GPIEN;
3779 if (hw->mac.type == ixgbe_mac_82599EB)
3780 gpie |= IXGBE_SDP1_GPIEN;
3781 gpie |= IXGBE_SDP2_GPIEN;
3783 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3786 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3788 struct ixgbe_hw *hw = &adapter->hw;
3792 ixgbe_get_hw_control(adapter);
3793 ixgbe_setup_gpie(adapter);
3795 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3796 ixgbe_configure_msix(adapter);
3798 ixgbe_configure_msi_and_legacy(adapter);
3800 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3801 if (hw->mac.ops.enable_tx_laser &&
3802 ((hw->phy.multispeed_fiber) ||
3803 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3804 (hw->mac.type == ixgbe_mac_82599EB))))
3805 hw->mac.ops.enable_tx_laser(hw);
3807 clear_bit(__IXGBE_DOWN, &adapter->state);
3808 ixgbe_napi_enable_all(adapter);
3810 if (ixgbe_is_sfp(hw)) {
3811 ixgbe_sfp_link_config(adapter);
3813 err = ixgbe_non_sfp_link_config(hw);
3815 e_err(probe, "link_config FAILED %d\n", err);
3818 /* clear any pending interrupts, may auto mask */
3819 IXGBE_READ_REG(hw, IXGBE_EICR);
3820 ixgbe_irq_enable(adapter, true, true);
3823 * If this adapter has a fan, check to see if we had a failure
3824 * before we enabled the interrupt.
3826 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3827 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3828 if (esdp & IXGBE_ESDP_SDP1)
3829 e_crit(drv, "Fan has stopped, replace the adapter\n");
3833 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3834 * arrived before interrupts were enabled but after probe. Such
3835 * devices wouldn't have their type identified yet. We need to
3836 * kick off the SFP+ module setup first, then try to bring up link.
3837 * If we're not hot-pluggable SFP+, we just need to configure link
3840 if (hw->phy.type == ixgbe_phy_unknown)
3841 schedule_work(&adapter->sfp_config_module_task);
3843 /* enable transmits */
3844 netif_tx_start_all_queues(adapter->netdev);
3846 /* bring the link up in the watchdog, this could race with our first
3847 * link up interrupt but shouldn't be a problem */
3848 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3849 adapter->link_check_timeout = jiffies;
3850 mod_timer(&adapter->watchdog_timer, jiffies);
3852 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3853 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3854 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3855 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3860 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3862 WARN_ON(in_interrupt());
3863 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3865 ixgbe_down(adapter);
3867 * If SR-IOV enabled then wait a bit before bringing the adapter
3868 * back up to give the VFs time to respond to the reset. The
3869 * two second wait is based upon the watchdog timer cycle in
3872 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3875 clear_bit(__IXGBE_RESETTING, &adapter->state);
3878 int ixgbe_up(struct ixgbe_adapter *adapter)
3880 /* hardware has been reset, we need to reload some things */
3881 ixgbe_configure(adapter);
3883 return ixgbe_up_complete(adapter);
3886 void ixgbe_reset(struct ixgbe_adapter *adapter)
3888 struct ixgbe_hw *hw = &adapter->hw;
3891 err = hw->mac.ops.init_hw(hw);
3894 case IXGBE_ERR_SFP_NOT_PRESENT:
3896 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3897 e_dev_err("master disable timed out\n");
3899 case IXGBE_ERR_EEPROM_VERSION:
3900 /* We are running on a pre-production device, log a warning */
3901 e_dev_warn("This device is a pre-production adapter/LOM. "
3902 "Please be aware there may be issuesassociated with "
3903 "your hardware. If you are experiencing problems "
3904 "please contact your Intel or hardware "
3905 "representative who provided you with this "
3909 e_dev_err("Hardware Error: %d\n", err);
3912 /* reprogram the RAR[0] in case user changed it. */
3913 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3918 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3919 * @rx_ring: ring to free buffers from
3921 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3923 struct device *dev = rx_ring->dev;
3927 /* ring already cleared, nothing to do */
3928 if (!rx_ring->rx_buffer_info)
3931 /* Free all the Rx ring sk_buffs */
3932 for (i = 0; i < rx_ring->count; i++) {
3933 struct ixgbe_rx_buffer *rx_buffer_info;
3935 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3936 if (rx_buffer_info->dma) {
3937 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3938 rx_ring->rx_buf_len,
3940 rx_buffer_info->dma = 0;
3942 if (rx_buffer_info->skb) {
3943 struct sk_buff *skb = rx_buffer_info->skb;
3944 rx_buffer_info->skb = NULL;
3946 struct sk_buff *this = skb;
3947 if (IXGBE_RSC_CB(this)->delay_unmap) {
3948 dma_unmap_single(dev,
3949 IXGBE_RSC_CB(this)->dma,
3950 rx_ring->rx_buf_len,
3952 IXGBE_RSC_CB(this)->dma = 0;
3953 IXGBE_RSC_CB(skb)->delay_unmap = false;
3956 dev_kfree_skb(this);
3959 if (!rx_buffer_info->page)
3961 if (rx_buffer_info->page_dma) {
3962 dma_unmap_page(dev, rx_buffer_info->page_dma,
3963 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3964 rx_buffer_info->page_dma = 0;
3966 put_page(rx_buffer_info->page);
3967 rx_buffer_info->page = NULL;
3968 rx_buffer_info->page_offset = 0;
3971 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3972 memset(rx_ring->rx_buffer_info, 0, size);
3974 /* Zero out the descriptor ring */
3975 memset(rx_ring->desc, 0, rx_ring->size);
3977 rx_ring->next_to_clean = 0;
3978 rx_ring->next_to_use = 0;
3982 * ixgbe_clean_tx_ring - Free Tx Buffers
3983 * @tx_ring: ring to be cleaned
3985 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3987 struct ixgbe_tx_buffer *tx_buffer_info;
3991 /* ring already cleared, nothing to do */
3992 if (!tx_ring->tx_buffer_info)
3995 /* Free all the Tx ring sk_buffs */
3996 for (i = 0; i < tx_ring->count; i++) {
3997 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3998 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4001 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4002 memset(tx_ring->tx_buffer_info, 0, size);
4004 /* Zero out the descriptor ring */
4005 memset(tx_ring->desc, 0, tx_ring->size);
4007 tx_ring->next_to_use = 0;
4008 tx_ring->next_to_clean = 0;
4012 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4013 * @adapter: board private structure
4015 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4019 for (i = 0; i < adapter->num_rx_queues; i++)
4020 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4024 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4025 * @adapter: board private structure
4027 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4031 for (i = 0; i < adapter->num_tx_queues; i++)
4032 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4035 void ixgbe_down(struct ixgbe_adapter *adapter)
4037 struct net_device *netdev = adapter->netdev;
4038 struct ixgbe_hw *hw = &adapter->hw;
4042 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4044 /* signal that we are down to the interrupt handler */
4045 set_bit(__IXGBE_DOWN, &adapter->state);
4047 /* disable receive for all VFs and wait one second */
4048 if (adapter->num_vfs) {
4049 /* ping all the active vfs to let them know we are going down */
4050 ixgbe_ping_all_vfs(adapter);
4052 /* Disable all VFTE/VFRE TX/RX */
4053 ixgbe_disable_tx_rx(adapter);
4055 /* Mark all the VFs as inactive */
4056 for (i = 0 ; i < adapter->num_vfs; i++)
4057 adapter->vfinfo[i].clear_to_send = 0;
4060 /* disable receives */
4061 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4062 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4064 IXGBE_WRITE_FLUSH(hw);
4067 netif_tx_stop_all_queues(netdev);
4069 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4070 del_timer_sync(&adapter->sfp_timer);
4071 del_timer_sync(&adapter->watchdog_timer);
4072 cancel_work_sync(&adapter->watchdog_task);
4074 netif_carrier_off(netdev);
4075 netif_tx_disable(netdev);
4077 ixgbe_irq_disable(adapter);
4079 ixgbe_napi_disable_all(adapter);
4081 /* Cleanup the affinity_hint CPU mask memory and callback */
4082 for (i = 0; i < num_q_vectors; i++) {
4083 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4084 /* clear the affinity_mask in the IRQ descriptor */
4085 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4086 /* release the CPU mask memory */
4087 free_cpumask_var(q_vector->affinity_mask);
4090 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4091 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4092 cancel_work_sync(&adapter->fdir_reinit_task);
4094 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4095 cancel_work_sync(&adapter->check_overtemp_task);
4097 /* disable transmits in the hardware now that interrupts are off */
4098 for (i = 0; i < adapter->num_tx_queues; i++) {
4099 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4100 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4101 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4102 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4104 /* Disable the Tx DMA engine on 82599 */
4105 switch (hw->mac.type) {
4106 case ixgbe_mac_82599EB:
4107 case ixgbe_mac_X540:
4108 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4109 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4110 ~IXGBE_DMATXCTL_TE));
4116 /* clear n-tuple filters that are cached */
4117 ethtool_ntuple_flush(netdev);
4119 if (!pci_channel_offline(adapter->pdev))
4120 ixgbe_reset(adapter);
4122 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4123 if (hw->mac.ops.disable_tx_laser &&
4124 ((hw->phy.multispeed_fiber) ||
4125 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4126 (hw->mac.type == ixgbe_mac_82599EB))))
4127 hw->mac.ops.disable_tx_laser(hw);
4129 ixgbe_clean_all_tx_rings(adapter);
4130 ixgbe_clean_all_rx_rings(adapter);
4132 #ifdef CONFIG_IXGBE_DCA
4133 /* since we reset the hardware DCA settings were cleared */
4134 ixgbe_setup_dca(adapter);
4139 * ixgbe_poll - NAPI Rx polling callback
4140 * @napi: structure for representing this polling device
4141 * @budget: how many packets driver is allowed to clean
4143 * This function is used for legacy and MSI, NAPI mode
4145 static int ixgbe_poll(struct napi_struct *napi, int budget)
4147 struct ixgbe_q_vector *q_vector =
4148 container_of(napi, struct ixgbe_q_vector, napi);
4149 struct ixgbe_adapter *adapter = q_vector->adapter;
4150 int tx_clean_complete, work_done = 0;
4152 #ifdef CONFIG_IXGBE_DCA
4153 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4154 ixgbe_update_dca(q_vector);
4157 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4158 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4160 if (!tx_clean_complete)
4163 /* If budget not fully consumed, exit the polling mode */
4164 if (work_done < budget) {
4165 napi_complete(napi);
4166 if (adapter->rx_itr_setting & 1)
4167 ixgbe_set_itr(adapter);
4168 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4169 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4175 * ixgbe_tx_timeout - Respond to a Tx Hang
4176 * @netdev: network interface device structure
4178 static void ixgbe_tx_timeout(struct net_device *netdev)
4180 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4182 adapter->tx_timeout_count++;
4184 /* Do the reset outside of interrupt context */
4185 schedule_work(&adapter->reset_task);
4188 static void ixgbe_reset_task(struct work_struct *work)
4190 struct ixgbe_adapter *adapter;
4191 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4193 /* If we're already down or resetting, just bail */
4194 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4195 test_bit(__IXGBE_RESETTING, &adapter->state))
4198 ixgbe_dump(adapter);
4199 netdev_err(adapter->netdev, "Reset adapter\n");
4200 ixgbe_reinit_locked(adapter);
4203 #ifdef CONFIG_IXGBE_DCB
4204 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4207 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4209 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4213 adapter->num_rx_queues = f->indices;
4214 adapter->num_tx_queues = f->indices;
4222 * ixgbe_set_rss_queues: Allocate queues for RSS
4223 * @adapter: board private structure to initialize
4225 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4226 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4229 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4232 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4234 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4236 adapter->num_rx_queues = f->indices;
4237 adapter->num_tx_queues = f->indices;
4247 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4248 * @adapter: board private structure to initialize
4250 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4251 * to the original CPU that initiated the Tx session. This runs in addition
4252 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4253 * Rx load across CPUs using RSS.
4256 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4259 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4261 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4264 /* Flow Director must have RSS enabled */
4265 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4266 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4267 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4268 adapter->num_tx_queues = f_fdir->indices;
4269 adapter->num_rx_queues = f_fdir->indices;
4272 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4273 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4280 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4281 * @adapter: board private structure to initialize
4283 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4284 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4285 * rx queues out of the max number of rx queues, instead, it is used as the
4286 * index of the first rx queue used by FCoE.
4289 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4292 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4294 f->indices = min((int)num_online_cpus(), f->indices);
4295 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4296 adapter->num_rx_queues = 1;
4297 adapter->num_tx_queues = 1;
4298 #ifdef CONFIG_IXGBE_DCB
4299 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4300 e_info(probe, "FCoE enabled with DCB\n");
4301 ixgbe_set_dcb_queues(adapter);
4304 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4305 e_info(probe, "FCoE enabled with RSS\n");
4306 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4307 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4308 ixgbe_set_fdir_queues(adapter);
4310 ixgbe_set_rss_queues(adapter);
4312 /* adding FCoE rx rings to the end */
4313 f->mask = adapter->num_rx_queues;
4314 adapter->num_rx_queues += f->indices;
4315 adapter->num_tx_queues += f->indices;
4323 #endif /* IXGBE_FCOE */
4325 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4326 * @adapter: board private structure to initialize
4328 * IOV doesn't actually use anything, so just NAK the
4329 * request for now and let the other queue routines
4330 * figure out what to do.
4332 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4338 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4339 * @adapter: board private structure to initialize
4341 * This is the top level queue allocation routine. The order here is very
4342 * important, starting with the "most" number of features turned on at once,
4343 * and ending with the smallest set of features. This way large combinations
4344 * can be allocated if they're turned on, and smaller combinations are the
4345 * fallthrough conditions.
4348 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4350 /* Start with base case */
4351 adapter->num_rx_queues = 1;
4352 adapter->num_tx_queues = 1;
4353 adapter->num_rx_pools = adapter->num_rx_queues;
4354 adapter->num_rx_queues_per_pool = 1;
4356 if (ixgbe_set_sriov_queues(adapter))
4360 if (ixgbe_set_fcoe_queues(adapter))
4363 #endif /* IXGBE_FCOE */
4364 #ifdef CONFIG_IXGBE_DCB
4365 if (ixgbe_set_dcb_queues(adapter))
4369 if (ixgbe_set_fdir_queues(adapter))
4372 if (ixgbe_set_rss_queues(adapter))
4375 /* fallback to base case */
4376 adapter->num_rx_queues = 1;
4377 adapter->num_tx_queues = 1;
4380 /* Notify the stack of the (possibly) reduced queue counts. */
4381 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4382 return netif_set_real_num_rx_queues(adapter->netdev,
4383 adapter->num_rx_queues);
4386 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4389 int err, vector_threshold;
4391 /* We'll want at least 3 (vector_threshold):
4394 * 3) Other (Link Status Change, etc.)
4395 * 4) TCP Timer (optional)
4397 vector_threshold = MIN_MSIX_COUNT;
4399 /* The more we get, the more we will assign to Tx/Rx Cleanup
4400 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4401 * Right now, we simply care about how many we'll get; we'll
4402 * set them up later while requesting irq's.
4404 while (vectors >= vector_threshold) {
4405 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4407 if (!err) /* Success in acquiring all requested vectors. */
4410 vectors = 0; /* Nasty failure, quit now */
4411 else /* err == number of vectors we should try again with */
4415 if (vectors < vector_threshold) {
4416 /* Can't allocate enough MSI-X interrupts? Oh well.
4417 * This just means we'll go with either a single MSI
4418 * vector or fall back to legacy interrupts.
4420 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4421 "Unable to allocate MSI-X interrupts\n");
4422 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4423 kfree(adapter->msix_entries);
4424 adapter->msix_entries = NULL;
4426 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4428 * Adjust for only the vectors we'll use, which is minimum
4429 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4430 * vectors we were allocated.
4432 adapter->num_msix_vectors = min(vectors,
4433 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4438 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4439 * @adapter: board private structure to initialize
4441 * Cache the descriptor ring offsets for RSS to the assigned rings.
4444 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4448 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4451 for (i = 0; i < adapter->num_rx_queues; i++)
4452 adapter->rx_ring[i]->reg_idx = i;
4453 for (i = 0; i < adapter->num_tx_queues; i++)
4454 adapter->tx_ring[i]->reg_idx = i;
4459 #ifdef CONFIG_IXGBE_DCB
4461 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4462 * @adapter: board private structure to initialize
4464 * Cache the descriptor ring offsets for DCB to the assigned rings.
4467 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4471 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4473 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4476 /* the number of queues is assumed to be symmetric */
4477 switch (adapter->hw.mac.type) {
4478 case ixgbe_mac_82598EB:
4479 for (i = 0; i < dcb_i; i++) {
4480 adapter->rx_ring[i]->reg_idx = i << 3;
4481 adapter->tx_ring[i]->reg_idx = i << 2;
4485 case ixgbe_mac_82599EB:
4486 case ixgbe_mac_X540:
4489 * Tx TC0 starts at: descriptor queue 0
4490 * Tx TC1 starts at: descriptor queue 32
4491 * Tx TC2 starts at: descriptor queue 64
4492 * Tx TC3 starts at: descriptor queue 80
4493 * Tx TC4 starts at: descriptor queue 96
4494 * Tx TC5 starts at: descriptor queue 104
4495 * Tx TC6 starts at: descriptor queue 112
4496 * Tx TC7 starts at: descriptor queue 120
4498 * Rx TC0-TC7 are offset by 16 queues each
4500 for (i = 0; i < 3; i++) {
4501 adapter->tx_ring[i]->reg_idx = i << 5;
4502 adapter->rx_ring[i]->reg_idx = i << 4;
4504 for ( ; i < 5; i++) {
4505 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4506 adapter->rx_ring[i]->reg_idx = i << 4;
4508 for ( ; i < dcb_i; i++) {
4509 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4510 adapter->rx_ring[i]->reg_idx = i << 4;
4513 } else if (dcb_i == 4) {
4515 * Tx TC0 starts at: descriptor queue 0
4516 * Tx TC1 starts at: descriptor queue 64
4517 * Tx TC2 starts at: descriptor queue 96
4518 * Tx TC3 starts at: descriptor queue 112
4520 * Rx TC0-TC3 are offset by 32 queues each
4522 adapter->tx_ring[0]->reg_idx = 0;
4523 adapter->tx_ring[1]->reg_idx = 64;
4524 adapter->tx_ring[2]->reg_idx = 96;
4525 adapter->tx_ring[3]->reg_idx = 112;
4526 for (i = 0 ; i < dcb_i; i++)
4527 adapter->rx_ring[i]->reg_idx = i << 5;
4539 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4540 * @adapter: board private structure to initialize
4542 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4545 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4550 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4551 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4552 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4553 for (i = 0; i < adapter->num_rx_queues; i++)
4554 adapter->rx_ring[i]->reg_idx = i;
4555 for (i = 0; i < adapter->num_tx_queues; i++)
4556 adapter->tx_ring[i]->reg_idx = i;
4565 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4566 * @adapter: board private structure to initialize
4568 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4571 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4573 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4575 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4577 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4580 #ifdef CONFIG_IXGBE_DCB
4581 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4582 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4584 ixgbe_cache_ring_dcb(adapter);
4585 /* find out queues in TC for FCoE */
4586 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4587 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4589 * In 82599, the number of Tx queues for each traffic
4590 * class for both 8-TC and 4-TC modes are:
4591 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4592 * 8 TCs: 32 32 16 16 8 8 8 8
4593 * 4 TCs: 64 64 32 32
4594 * We have max 8 queues for FCoE, where 8 the is
4595 * FCoE redirection table size. If TC for FCoE is
4596 * less than or equal to TC3, we have enough queues
4597 * to add max of 8 queues for FCoE, so we start FCoE
4598 * Tx queue from the next one, i.e., reg_idx + 1.
4599 * If TC for FCoE is above TC3, implying 8 TC mode,
4600 * and we need 8 for FCoE, we have to take all queues
4601 * in that traffic class for FCoE.
4603 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4606 #endif /* CONFIG_IXGBE_DCB */
4607 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4608 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4609 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4610 ixgbe_cache_ring_fdir(adapter);
4612 ixgbe_cache_ring_rss(adapter);
4614 fcoe_rx_i = f->mask;
4615 fcoe_tx_i = f->mask;
4617 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4618 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4619 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4624 #endif /* IXGBE_FCOE */
4626 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4627 * @adapter: board private structure to initialize
4629 * SR-IOV doesn't use any descriptor rings but changes the default if
4630 * no other mapping is used.
4633 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4635 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4636 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4637 if (adapter->num_vfs)
4644 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4645 * @adapter: board private structure to initialize
4647 * Once we know the feature-set enabled for the device, we'll cache
4648 * the register offset the descriptor ring is assigned to.
4650 * Note, the order the various feature calls is important. It must start with
4651 * the "most" features enabled at the same time, then trickle down to the
4652 * least amount of features turned on at once.
4654 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4656 /* start with default case */
4657 adapter->rx_ring[0]->reg_idx = 0;
4658 adapter->tx_ring[0]->reg_idx = 0;
4660 if (ixgbe_cache_ring_sriov(adapter))
4664 if (ixgbe_cache_ring_fcoe(adapter))
4667 #endif /* IXGBE_FCOE */
4668 #ifdef CONFIG_IXGBE_DCB
4669 if (ixgbe_cache_ring_dcb(adapter))
4673 if (ixgbe_cache_ring_fdir(adapter))
4676 if (ixgbe_cache_ring_rss(adapter))
4681 * ixgbe_alloc_queues - Allocate memory for all rings
4682 * @adapter: board private structure to initialize
4684 * We allocate one ring per queue at run-time since we don't know the
4685 * number of queues at compile-time. The polling_netdev array is
4686 * intended for Multiqueue, but should work fine with a single queue.
4688 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4690 int rx = 0, tx = 0, nid = adapter->node;
4692 if (nid < 0 || !node_online(nid))
4693 nid = first_online_node;
4695 for (; tx < adapter->num_tx_queues; tx++) {
4696 struct ixgbe_ring *ring;
4698 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4700 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4702 goto err_allocation;
4703 ring->count = adapter->tx_ring_count;
4704 ring->queue_index = tx;
4705 ring->numa_node = nid;
4706 ring->dev = &adapter->pdev->dev;
4707 ring->netdev = adapter->netdev;
4709 adapter->tx_ring[tx] = ring;
4712 for (; rx < adapter->num_rx_queues; rx++) {
4713 struct ixgbe_ring *ring;
4715 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4717 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4719 goto err_allocation;
4720 ring->count = adapter->rx_ring_count;
4721 ring->queue_index = rx;
4722 ring->numa_node = nid;
4723 ring->dev = &adapter->pdev->dev;
4724 ring->netdev = adapter->netdev;
4726 adapter->rx_ring[rx] = ring;
4729 ixgbe_cache_ring_register(adapter);
4735 kfree(adapter->tx_ring[--tx]);
4738 kfree(adapter->rx_ring[--rx]);
4743 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4744 * @adapter: board private structure to initialize
4746 * Attempt to configure the interrupts using the best available
4747 * capabilities of the hardware and the kernel.
4749 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4751 struct ixgbe_hw *hw = &adapter->hw;
4753 int vector, v_budget;
4756 * It's easy to be greedy for MSI-X vectors, but it really
4757 * doesn't do us much good if we have a lot more vectors
4758 * than CPU's. So let's be conservative and only ask for
4759 * (roughly) the same number of vectors as there are CPU's.
4761 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4762 (int)num_online_cpus()) + NON_Q_VECTORS;
4765 * At the same time, hardware can only support a maximum of
4766 * hw.mac->max_msix_vectors vectors. With features
4767 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4768 * descriptor queues supported by our device. Thus, we cap it off in
4769 * those rare cases where the cpu count also exceeds our vector limit.
4771 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4773 /* A failure in MSI-X entry allocation isn't fatal, but it does
4774 * mean we disable MSI-X capabilities of the adapter. */
4775 adapter->msix_entries = kcalloc(v_budget,
4776 sizeof(struct msix_entry), GFP_KERNEL);
4777 if (adapter->msix_entries) {
4778 for (vector = 0; vector < v_budget; vector++)
4779 adapter->msix_entries[vector].entry = vector;
4781 ixgbe_acquire_msix_vectors(adapter, v_budget);
4783 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4787 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4788 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4789 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4790 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4791 adapter->atr_sample_rate = 0;
4792 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4793 ixgbe_disable_sriov(adapter);
4795 err = ixgbe_set_num_queues(adapter);
4799 err = pci_enable_msi(adapter->pdev);
4801 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4803 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4804 "Unable to allocate MSI interrupt, "
4805 "falling back to legacy. Error: %d\n", err);
4815 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4816 * @adapter: board private structure to initialize
4818 * We allocate one q_vector per queue interrupt. If allocation fails we
4821 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4823 int q_idx, num_q_vectors;
4824 struct ixgbe_q_vector *q_vector;
4826 int (*poll)(struct napi_struct *, int);
4828 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4829 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4830 napi_vectors = adapter->num_rx_queues;
4831 poll = &ixgbe_clean_rxtx_many;
4838 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4839 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4840 GFP_KERNEL, adapter->node);
4842 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4846 q_vector->adapter = adapter;
4847 if (q_vector->txr_count && !q_vector->rxr_count)
4848 q_vector->eitr = adapter->tx_eitr_param;
4850 q_vector->eitr = adapter->rx_eitr_param;
4851 q_vector->v_idx = q_idx;
4852 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4853 adapter->q_vector[q_idx] = q_vector;
4861 q_vector = adapter->q_vector[q_idx];
4862 netif_napi_del(&q_vector->napi);
4864 adapter->q_vector[q_idx] = NULL;
4870 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4871 * @adapter: board private structure to initialize
4873 * This function frees the memory allocated to the q_vectors. In addition if
4874 * NAPI is enabled it will delete any references to the NAPI struct prior
4875 * to freeing the q_vector.
4877 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4879 int q_idx, num_q_vectors;
4881 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4882 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4886 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4887 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4888 adapter->q_vector[q_idx] = NULL;
4889 netif_napi_del(&q_vector->napi);
4894 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4896 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4897 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4898 pci_disable_msix(adapter->pdev);
4899 kfree(adapter->msix_entries);
4900 adapter->msix_entries = NULL;
4901 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4902 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4903 pci_disable_msi(adapter->pdev);
4908 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4909 * @adapter: board private structure to initialize
4911 * We determine which interrupt scheme to use based on...
4912 * - Kernel support (MSI, MSI-X)
4913 * - which can be user-defined (via MODULE_PARAM)
4914 * - Hardware queue count (num_*_queues)
4915 * - defined by miscellaneous hardware support/features (RSS, etc.)
4917 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4921 /* Number of supported queues */
4922 err = ixgbe_set_num_queues(adapter);
4926 err = ixgbe_set_interrupt_capability(adapter);
4928 e_dev_err("Unable to setup interrupt capabilities\n");
4929 goto err_set_interrupt;
4932 err = ixgbe_alloc_q_vectors(adapter);
4934 e_dev_err("Unable to allocate memory for queue vectors\n");
4935 goto err_alloc_q_vectors;
4938 err = ixgbe_alloc_queues(adapter);
4940 e_dev_err("Unable to allocate memory for queues\n");
4941 goto err_alloc_queues;
4944 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4945 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4946 adapter->num_rx_queues, adapter->num_tx_queues);
4948 set_bit(__IXGBE_DOWN, &adapter->state);
4953 ixgbe_free_q_vectors(adapter);
4954 err_alloc_q_vectors:
4955 ixgbe_reset_interrupt_capability(adapter);
4960 static void ring_free_rcu(struct rcu_head *head)
4962 kfree(container_of(head, struct ixgbe_ring, rcu));
4966 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4967 * @adapter: board private structure to clear interrupt scheme on
4969 * We go through and clear interrupt specific resources and reset the structure
4970 * to pre-load conditions
4972 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4976 for (i = 0; i < adapter->num_tx_queues; i++) {
4977 kfree(adapter->tx_ring[i]);
4978 adapter->tx_ring[i] = NULL;
4980 for (i = 0; i < adapter->num_rx_queues; i++) {
4981 struct ixgbe_ring *ring = adapter->rx_ring[i];
4983 /* ixgbe_get_stats64() might access this ring, we must wait
4984 * a grace period before freeing it.
4986 call_rcu(&ring->rcu, ring_free_rcu);
4987 adapter->rx_ring[i] = NULL;
4990 adapter->num_tx_queues = 0;
4991 adapter->num_rx_queues = 0;
4993 ixgbe_free_q_vectors(adapter);
4994 ixgbe_reset_interrupt_capability(adapter);
4998 * ixgbe_sfp_timer - worker thread to find a missing module
4999 * @data: pointer to our adapter struct
5001 static void ixgbe_sfp_timer(unsigned long data)
5003 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5006 * Do the sfp_timer outside of interrupt context due to the
5007 * delays that sfp+ detection requires
5009 schedule_work(&adapter->sfp_task);
5013 * ixgbe_sfp_task - worker thread to find a missing module
5014 * @work: pointer to work_struct containing our data
5016 static void ixgbe_sfp_task(struct work_struct *work)
5018 struct ixgbe_adapter *adapter = container_of(work,
5019 struct ixgbe_adapter,
5021 struct ixgbe_hw *hw = &adapter->hw;
5023 if ((hw->phy.type == ixgbe_phy_nl) &&
5024 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5025 s32 ret = hw->phy.ops.identify_sfp(hw);
5026 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5028 ret = hw->phy.ops.reset(hw);
5029 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5030 e_dev_err("failed to initialize because an unsupported "
5031 "SFP+ module type was detected.\n");
5032 e_dev_err("Reload the driver after installing a "
5033 "supported module.\n");
5034 unregister_netdev(adapter->netdev);
5036 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5038 /* don't need this routine any more */
5039 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5043 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5044 mod_timer(&adapter->sfp_timer,
5045 round_jiffies(jiffies + (2 * HZ)));
5049 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5050 * @adapter: board private structure to initialize
5052 * ixgbe_sw_init initializes the Adapter private data structure.
5053 * Fields are initialized based on PCI device information and
5054 * OS network device settings (MTU size).
5056 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5058 struct ixgbe_hw *hw = &adapter->hw;
5059 struct pci_dev *pdev = adapter->pdev;
5060 struct net_device *dev = adapter->netdev;
5062 #ifdef CONFIG_IXGBE_DCB
5064 struct tc_configuration *tc;
5066 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5068 /* PCI config space info */
5070 hw->vendor_id = pdev->vendor;
5071 hw->device_id = pdev->device;
5072 hw->revision_id = pdev->revision;
5073 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5074 hw->subsystem_device_id = pdev->subsystem_device;
5076 /* Set capability flags */
5077 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5078 adapter->ring_feature[RING_F_RSS].indices = rss;
5079 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5080 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5081 switch (hw->mac.type) {
5082 case ixgbe_mac_82598EB:
5083 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5084 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5085 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5087 case ixgbe_mac_82599EB:
5088 case ixgbe_mac_X540:
5089 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5090 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5091 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5092 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5093 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5094 if (dev->features & NETIF_F_NTUPLE) {
5095 /* Flow Director perfect filter enabled */
5096 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5097 adapter->atr_sample_rate = 0;
5098 spin_lock_init(&adapter->fdir_perfect_lock);
5100 /* Flow Director hash filters enabled */
5101 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5102 adapter->atr_sample_rate = 20;
5104 adapter->ring_feature[RING_F_FDIR].indices =
5105 IXGBE_MAX_FDIR_INDICES;
5106 adapter->fdir_pballoc = 0;
5108 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5109 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5110 adapter->ring_feature[RING_F_FCOE].indices = 0;
5111 #ifdef CONFIG_IXGBE_DCB
5112 /* Default traffic class to use for FCoE */
5113 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5114 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5116 #endif /* IXGBE_FCOE */
5122 #ifdef CONFIG_IXGBE_DCB
5123 /* Configure DCB traffic classes */
5124 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5125 tc = &adapter->dcb_cfg.tc_config[j];
5126 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5127 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5128 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5129 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5130 tc->dcb_pfc = pfc_disabled;
5132 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5133 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5134 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5135 adapter->dcb_cfg.pfc_mode_enable = false;
5136 adapter->dcb_cfg.round_robin_enable = false;
5137 adapter->dcb_set_bitmap = 0x00;
5138 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5139 adapter->ring_feature[RING_F_DCB].indices);
5143 /* default flow control settings */
5144 hw->fc.requested_mode = ixgbe_fc_full;
5145 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5147 adapter->last_lfc_mode = hw->fc.current_mode;
5149 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5150 hw->fc.low_water = FC_LOW_WATER(max_frame);
5151 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5152 hw->fc.send_xon = true;
5153 hw->fc.disable_fc_autoneg = false;
5155 /* enable itr by default in dynamic mode */
5156 adapter->rx_itr_setting = 1;
5157 adapter->rx_eitr_param = 20000;
5158 adapter->tx_itr_setting = 1;
5159 adapter->tx_eitr_param = 10000;
5161 /* set defaults for eitr in MegaBytes */
5162 adapter->eitr_low = 10;
5163 adapter->eitr_high = 20;
5165 /* set default ring sizes */
5166 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5167 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5169 /* initialize eeprom parameters */
5170 if (ixgbe_init_eeprom_params_generic(hw)) {
5171 e_dev_err("EEPROM initialization failed\n");
5175 /* enable rx csum by default */
5176 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5178 /* get assigned NUMA node */
5179 adapter->node = dev_to_node(&pdev->dev);
5181 set_bit(__IXGBE_DOWN, &adapter->state);
5187 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5188 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5190 * Return 0 on success, negative on failure
5192 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5194 struct device *dev = tx_ring->dev;
5197 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5198 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5199 if (!tx_ring->tx_buffer_info)
5200 tx_ring->tx_buffer_info = vzalloc(size);
5201 if (!tx_ring->tx_buffer_info)
5204 /* round up to nearest 4K */
5205 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5206 tx_ring->size = ALIGN(tx_ring->size, 4096);
5208 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5209 &tx_ring->dma, GFP_KERNEL);
5213 tx_ring->next_to_use = 0;
5214 tx_ring->next_to_clean = 0;
5215 tx_ring->work_limit = tx_ring->count;
5219 vfree(tx_ring->tx_buffer_info);
5220 tx_ring->tx_buffer_info = NULL;
5221 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5226 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5227 * @adapter: board private structure
5229 * If this function returns with an error, then it's possible one or
5230 * more of the rings is populated (while the rest are not). It is the
5231 * callers duty to clean those orphaned rings.
5233 * Return 0 on success, negative on failure
5235 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5239 for (i = 0; i < adapter->num_tx_queues; i++) {
5240 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5243 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5251 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5252 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5254 * Returns 0 on success, negative on failure
5256 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5258 struct device *dev = rx_ring->dev;
5261 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5262 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5263 if (!rx_ring->rx_buffer_info)
5264 rx_ring->rx_buffer_info = vzalloc(size);
5265 if (!rx_ring->rx_buffer_info)
5268 /* Round up to nearest 4K */
5269 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5270 rx_ring->size = ALIGN(rx_ring->size, 4096);
5272 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5273 &rx_ring->dma, GFP_KERNEL);
5278 rx_ring->next_to_clean = 0;
5279 rx_ring->next_to_use = 0;
5283 vfree(rx_ring->rx_buffer_info);
5284 rx_ring->rx_buffer_info = NULL;
5285 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5290 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5291 * @adapter: board private structure
5293 * If this function returns with an error, then it's possible one or
5294 * more of the rings is populated (while the rest are not). It is the
5295 * callers duty to clean those orphaned rings.
5297 * Return 0 on success, negative on failure
5299 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5303 for (i = 0; i < adapter->num_rx_queues; i++) {
5304 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5307 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5315 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5316 * @tx_ring: Tx descriptor ring for a specific queue
5318 * Free all transmit software resources
5320 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5322 ixgbe_clean_tx_ring(tx_ring);
5324 vfree(tx_ring->tx_buffer_info);
5325 tx_ring->tx_buffer_info = NULL;
5327 /* if not set, then don't free */
5331 dma_free_coherent(tx_ring->dev, tx_ring->size,
5332 tx_ring->desc, tx_ring->dma);
5334 tx_ring->desc = NULL;
5338 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5339 * @adapter: board private structure
5341 * Free all transmit software resources
5343 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5347 for (i = 0; i < adapter->num_tx_queues; i++)
5348 if (adapter->tx_ring[i]->desc)
5349 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5353 * ixgbe_free_rx_resources - Free Rx Resources
5354 * @rx_ring: ring to clean the resources from
5356 * Free all receive software resources
5358 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5360 ixgbe_clean_rx_ring(rx_ring);
5362 vfree(rx_ring->rx_buffer_info);
5363 rx_ring->rx_buffer_info = NULL;
5365 /* if not set, then don't free */
5369 dma_free_coherent(rx_ring->dev, rx_ring->size,
5370 rx_ring->desc, rx_ring->dma);
5372 rx_ring->desc = NULL;
5376 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5377 * @adapter: board private structure
5379 * Free all receive software resources
5381 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5385 for (i = 0; i < adapter->num_rx_queues; i++)
5386 if (adapter->rx_ring[i]->desc)
5387 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5391 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5392 * @netdev: network interface device structure
5393 * @new_mtu: new value for maximum frame size
5395 * Returns 0 on success, negative on failure
5397 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5399 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5400 struct ixgbe_hw *hw = &adapter->hw;
5401 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5403 /* MTU < 68 is an error and causes problems on some kernels */
5404 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5407 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5408 /* must set new MTU before calling down or up */
5409 netdev->mtu = new_mtu;
5411 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5412 hw->fc.low_water = FC_LOW_WATER(max_frame);
5414 if (netif_running(netdev))
5415 ixgbe_reinit_locked(adapter);
5421 * ixgbe_open - Called when a network interface is made active
5422 * @netdev: network interface device structure
5424 * Returns 0 on success, negative value on failure
5426 * The open entry point is called when a network interface is made
5427 * active by the system (IFF_UP). At this point all resources needed
5428 * for transmit and receive operations are allocated, the interrupt
5429 * handler is registered with the OS, the watchdog timer is started,
5430 * and the stack is notified that the interface is ready.
5432 static int ixgbe_open(struct net_device *netdev)
5434 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5437 /* disallow open during test */
5438 if (test_bit(__IXGBE_TESTING, &adapter->state))
5441 netif_carrier_off(netdev);
5443 /* allocate transmit descriptors */
5444 err = ixgbe_setup_all_tx_resources(adapter);
5448 /* allocate receive descriptors */
5449 err = ixgbe_setup_all_rx_resources(adapter);
5453 ixgbe_configure(adapter);
5455 err = ixgbe_request_irq(adapter);
5459 err = ixgbe_up_complete(adapter);
5463 netif_tx_start_all_queues(netdev);
5468 ixgbe_release_hw_control(adapter);
5469 ixgbe_free_irq(adapter);
5472 ixgbe_free_all_rx_resources(adapter);
5474 ixgbe_free_all_tx_resources(adapter);
5475 ixgbe_reset(adapter);
5481 * ixgbe_close - Disables a network interface
5482 * @netdev: network interface device structure
5484 * Returns 0, this is not allowed to fail
5486 * The close entry point is called when an interface is de-activated
5487 * by the OS. The hardware is still under the drivers control, but
5488 * needs to be disabled. A global MAC reset is issued to stop the
5489 * hardware, and all transmit and receive resources are freed.
5491 static int ixgbe_close(struct net_device *netdev)
5493 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5495 ixgbe_down(adapter);
5496 ixgbe_free_irq(adapter);
5498 ixgbe_free_all_tx_resources(adapter);
5499 ixgbe_free_all_rx_resources(adapter);
5501 ixgbe_release_hw_control(adapter);
5507 static int ixgbe_resume(struct pci_dev *pdev)
5509 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5510 struct net_device *netdev = adapter->netdev;
5513 pci_set_power_state(pdev, PCI_D0);
5514 pci_restore_state(pdev);
5516 * pci_restore_state clears dev->state_saved so call
5517 * pci_save_state to restore it.
5519 pci_save_state(pdev);
5521 err = pci_enable_device_mem(pdev);
5523 e_dev_err("Cannot enable PCI device from suspend\n");
5526 pci_set_master(pdev);
5528 pci_wake_from_d3(pdev, false);
5530 err = ixgbe_init_interrupt_scheme(adapter);
5532 e_dev_err("Cannot initialize interrupts for device\n");
5536 ixgbe_reset(adapter);
5538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5540 if (netif_running(netdev)) {
5541 err = ixgbe_open(netdev);
5546 netif_device_attach(netdev);
5550 #endif /* CONFIG_PM */
5552 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5554 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5555 struct net_device *netdev = adapter->netdev;
5556 struct ixgbe_hw *hw = &adapter->hw;
5558 u32 wufc = adapter->wol;
5563 netif_device_detach(netdev);
5565 if (netif_running(netdev)) {
5566 ixgbe_down(adapter);
5567 ixgbe_free_irq(adapter);
5568 ixgbe_free_all_tx_resources(adapter);
5569 ixgbe_free_all_rx_resources(adapter);
5572 ixgbe_clear_interrupt_scheme(adapter);
5575 retval = pci_save_state(pdev);
5581 ixgbe_set_rx_mode(netdev);
5583 /* turn on all-multi mode if wake on multicast is enabled */
5584 if (wufc & IXGBE_WUFC_MC) {
5585 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5586 fctrl |= IXGBE_FCTRL_MPE;
5587 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5590 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5591 ctrl |= IXGBE_CTRL_GIO_DIS;
5592 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5594 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5596 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5597 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5600 switch (hw->mac.type) {
5601 case ixgbe_mac_82598EB:
5602 pci_wake_from_d3(pdev, false);
5604 case ixgbe_mac_82599EB:
5605 case ixgbe_mac_X540:
5606 pci_wake_from_d3(pdev, !!wufc);
5612 *enable_wake = !!wufc;
5614 ixgbe_release_hw_control(adapter);
5616 pci_disable_device(pdev);
5622 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5627 retval = __ixgbe_shutdown(pdev, &wake);
5632 pci_prepare_to_sleep(pdev);
5634 pci_wake_from_d3(pdev, false);
5635 pci_set_power_state(pdev, PCI_D3hot);
5640 #endif /* CONFIG_PM */
5642 static void ixgbe_shutdown(struct pci_dev *pdev)
5646 __ixgbe_shutdown(pdev, &wake);
5648 if (system_state == SYSTEM_POWER_OFF) {
5649 pci_wake_from_d3(pdev, wake);
5650 pci_set_power_state(pdev, PCI_D3hot);
5655 * ixgbe_update_stats - Update the board statistics counters.
5656 * @adapter: board private structure
5658 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5660 struct net_device *netdev = adapter->netdev;
5661 struct ixgbe_hw *hw = &adapter->hw;
5662 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5664 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5665 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5666 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5667 u64 bytes = 0, packets = 0;
5669 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5670 test_bit(__IXGBE_RESETTING, &adapter->state))
5673 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5676 for (i = 0; i < 16; i++)
5677 adapter->hw_rx_no_dma_resources +=
5678 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5679 for (i = 0; i < adapter->num_rx_queues; i++) {
5680 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5681 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5683 adapter->rsc_total_count = rsc_count;
5684 adapter->rsc_total_flush = rsc_flush;
5687 for (i = 0; i < adapter->num_rx_queues; i++) {
5688 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5689 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5690 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5691 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5692 bytes += rx_ring->stats.bytes;
5693 packets += rx_ring->stats.packets;
5695 adapter->non_eop_descs = non_eop_descs;
5696 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5697 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5698 netdev->stats.rx_bytes = bytes;
5699 netdev->stats.rx_packets = packets;
5703 /* gather some stats to the adapter struct that are per queue */
5704 for (i = 0; i < adapter->num_tx_queues; i++) {
5705 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5706 restart_queue += tx_ring->tx_stats.restart_queue;
5707 tx_busy += tx_ring->tx_stats.tx_busy;
5708 bytes += tx_ring->stats.bytes;
5709 packets += tx_ring->stats.packets;
5711 adapter->restart_queue = restart_queue;
5712 adapter->tx_busy = tx_busy;
5713 netdev->stats.tx_bytes = bytes;
5714 netdev->stats.tx_packets = packets;
5716 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5717 for (i = 0; i < 8; i++) {
5718 /* for packet buffers not used, the register should read 0 */
5719 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5721 hwstats->mpc[i] += mpc;
5722 total_mpc += hwstats->mpc[i];
5723 if (hw->mac.type == ixgbe_mac_82598EB)
5724 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5725 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5726 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5727 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5728 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5729 switch (hw->mac.type) {
5730 case ixgbe_mac_82598EB:
5731 hwstats->pxonrxc[i] +=
5732 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5734 case ixgbe_mac_82599EB:
5735 case ixgbe_mac_X540:
5736 hwstats->pxonrxc[i] +=
5737 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5742 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5743 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5745 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5746 /* work around hardware counting issue */
5747 hwstats->gprc -= missed_rx;
5749 ixgbe_update_xoff_received(adapter);
5751 /* 82598 hardware only has a 32 bit counter in the high register */
5752 switch (hw->mac.type) {
5753 case ixgbe_mac_82598EB:
5754 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5755 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5756 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5757 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5759 case ixgbe_mac_82599EB:
5760 case ixgbe_mac_X540:
5761 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5762 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5763 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5764 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5765 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5766 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5767 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5768 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5769 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5771 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5772 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5773 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5774 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5775 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5776 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5777 #endif /* IXGBE_FCOE */
5782 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5783 hwstats->bprc += bprc;
5784 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5785 if (hw->mac.type == ixgbe_mac_82598EB)
5786 hwstats->mprc -= bprc;
5787 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5788 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5789 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5790 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5791 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5792 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5793 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5794 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5795 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5796 hwstats->lxontxc += lxon;
5797 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5798 hwstats->lxofftxc += lxoff;
5799 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5800 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5801 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5803 * 82598 errata - tx of flow control packets is included in tx counters
5805 xon_off_tot = lxon + lxoff;
5806 hwstats->gptc -= xon_off_tot;
5807 hwstats->mptc -= xon_off_tot;
5808 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5809 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5810 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5811 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5812 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5813 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5814 hwstats->ptc64 -= xon_off_tot;
5815 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5816 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5817 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5818 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5819 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5820 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5822 /* Fill out the OS statistics structure */
5823 netdev->stats.multicast = hwstats->mprc;
5826 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5827 netdev->stats.rx_dropped = 0;
5828 netdev->stats.rx_length_errors = hwstats->rlec;
5829 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5830 netdev->stats.rx_missed_errors = total_mpc;
5834 * ixgbe_watchdog - Timer Call-back
5835 * @data: pointer to adapter cast into an unsigned long
5837 static void ixgbe_watchdog(unsigned long data)
5839 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5840 struct ixgbe_hw *hw = &adapter->hw;
5845 * Do the watchdog outside of interrupt context due to the lovely
5846 * delays that some of the newer hardware requires
5849 if (test_bit(__IXGBE_DOWN, &adapter->state))
5850 goto watchdog_short_circuit;
5852 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5854 * for legacy and MSI interrupts don't set any bits
5855 * that are enabled for EIAM, because this operation
5856 * would set *both* EIMS and EICS for any bit in EIAM
5858 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5859 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5860 goto watchdog_reschedule;
5863 /* get one bit for every active tx/rx interrupt vector */
5864 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5865 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5866 if (qv->rxr_count || qv->txr_count)
5867 eics |= ((u64)1 << i);
5870 /* Cause software interrupt to ensure rx rings are cleaned */
5871 ixgbe_irq_rearm_queues(adapter, eics);
5873 watchdog_reschedule:
5874 /* Reset the timer */
5875 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5877 watchdog_short_circuit:
5878 schedule_work(&adapter->watchdog_task);
5882 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5883 * @work: pointer to work_struct containing our data
5885 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5887 struct ixgbe_adapter *adapter = container_of(work,
5888 struct ixgbe_adapter,
5889 multispeed_fiber_task);
5890 struct ixgbe_hw *hw = &adapter->hw;
5894 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5895 autoneg = hw->phy.autoneg_advertised;
5896 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5897 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5898 hw->mac.autotry_restart = false;
5899 if (hw->mac.ops.setup_link)
5900 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5901 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5902 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5906 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5907 * @work: pointer to work_struct containing our data
5909 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5911 struct ixgbe_adapter *adapter = container_of(work,
5912 struct ixgbe_adapter,
5913 sfp_config_module_task);
5914 struct ixgbe_hw *hw = &adapter->hw;
5917 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5919 /* Time for electrical oscillations to settle down */
5921 err = hw->phy.ops.identify_sfp(hw);
5923 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5924 e_dev_err("failed to initialize because an unsupported SFP+ "
5925 "module type was detected.\n");
5926 e_dev_err("Reload the driver after installing a supported "
5928 unregister_netdev(adapter->netdev);
5931 hw->mac.ops.setup_sfp(hw);
5933 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5934 /* This will also work for DA Twinax connections */
5935 schedule_work(&adapter->multispeed_fiber_task);
5936 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5940 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5941 * @work: pointer to work_struct containing our data
5943 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5945 struct ixgbe_adapter *adapter = container_of(work,
5946 struct ixgbe_adapter,
5948 struct ixgbe_hw *hw = &adapter->hw;
5951 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5952 for (i = 0; i < adapter->num_tx_queues; i++)
5953 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5954 &(adapter->tx_ring[i]->state));
5956 e_err(probe, "failed to finish FDIR re-initialization, "
5957 "ignored adding FDIR ATR filters\n");
5959 /* Done FDIR Re-initialization, enable transmits */
5960 netif_tx_start_all_queues(adapter->netdev);
5963 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5966 * ixgbe_watchdog_task - worker thread to bring link up
5967 * @work: pointer to work_struct containing our data
5969 static void ixgbe_watchdog_task(struct work_struct *work)
5971 struct ixgbe_adapter *adapter = container_of(work,
5972 struct ixgbe_adapter,
5974 struct net_device *netdev = adapter->netdev;
5975 struct ixgbe_hw *hw = &adapter->hw;
5979 struct ixgbe_ring *tx_ring;
5980 int some_tx_pending = 0;
5982 mutex_lock(&ixgbe_watchdog_lock);
5984 link_up = adapter->link_up;
5985 link_speed = adapter->link_speed;
5987 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5988 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5991 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5992 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5993 hw->mac.ops.fc_enable(hw, i);
5995 hw->mac.ops.fc_enable(hw, 0);
5998 hw->mac.ops.fc_enable(hw, 0);
6003 time_after(jiffies, (adapter->link_check_timeout +
6004 IXGBE_TRY_LINK_TIMEOUT))) {
6005 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6006 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6008 adapter->link_up = link_up;
6009 adapter->link_speed = link_speed;
6013 if (!netif_carrier_ok(netdev)) {
6014 bool flow_rx, flow_tx;
6016 switch (hw->mac.type) {
6017 case ixgbe_mac_82598EB: {
6018 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6019 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6020 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6021 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6024 case ixgbe_mac_82599EB:
6025 case ixgbe_mac_X540: {
6026 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6027 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6028 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6029 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6038 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6039 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6041 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6042 "1 Gbps" : "unknown speed")),
6043 ((flow_rx && flow_tx) ? "RX/TX" :
6045 (flow_tx ? "TX" : "None"))));
6047 netif_carrier_on(netdev);
6049 /* Force detection of hung controller */
6050 for (i = 0; i < adapter->num_tx_queues; i++) {
6051 tx_ring = adapter->tx_ring[i];
6052 set_check_for_tx_hang(tx_ring);
6056 adapter->link_up = false;
6057 adapter->link_speed = 0;
6058 if (netif_carrier_ok(netdev)) {
6059 e_info(drv, "NIC Link is Down\n");
6060 netif_carrier_off(netdev);
6064 if (!netif_carrier_ok(netdev)) {
6065 for (i = 0; i < adapter->num_tx_queues; i++) {
6066 tx_ring = adapter->tx_ring[i];
6067 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6068 some_tx_pending = 1;
6073 if (some_tx_pending) {
6074 /* We've lost link, so the controller stops DMA,
6075 * but we've got queued Tx work that's never going
6076 * to get done, so reset controller to flush Tx.
6077 * (Do the reset outside of interrupt context).
6079 schedule_work(&adapter->reset_task);
6083 ixgbe_update_stats(adapter);
6084 mutex_unlock(&ixgbe_watchdog_lock);
6087 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6088 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6089 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6091 struct ixgbe_adv_tx_context_desc *context_desc;
6094 struct ixgbe_tx_buffer *tx_buffer_info;
6095 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6096 u32 mss_l4len_idx, l4len;
6098 if (skb_is_gso(skb)) {
6099 if (skb_header_cloned(skb)) {
6100 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6104 l4len = tcp_hdrlen(skb);
6107 if (protocol == htons(ETH_P_IP)) {
6108 struct iphdr *iph = ip_hdr(skb);
6111 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6115 } else if (skb_is_gso_v6(skb)) {
6116 ipv6_hdr(skb)->payload_len = 0;
6117 tcp_hdr(skb)->check =
6118 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6119 &ipv6_hdr(skb)->daddr,
6123 i = tx_ring->next_to_use;
6125 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6126 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6128 /* VLAN MACLEN IPLEN */
6129 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6131 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6132 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6133 IXGBE_ADVTXD_MACLEN_SHIFT);
6134 *hdr_len += skb_network_offset(skb);
6136 (skb_transport_header(skb) - skb_network_header(skb));
6138 (skb_transport_header(skb) - skb_network_header(skb));
6139 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6140 context_desc->seqnum_seed = 0;
6142 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6143 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6144 IXGBE_ADVTXD_DTYP_CTXT);
6146 if (protocol == htons(ETH_P_IP))
6147 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6148 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6149 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6153 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6154 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6155 /* use index 1 for TSO */
6156 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6157 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6159 tx_buffer_info->time_stamp = jiffies;
6160 tx_buffer_info->next_to_watch = i;
6163 if (i == tx_ring->count)
6165 tx_ring->next_to_use = i;
6172 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6178 case cpu_to_be16(ETH_P_IP):
6179 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6180 switch (ip_hdr(skb)->protocol) {
6182 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6185 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6189 case cpu_to_be16(ETH_P_IPV6):
6190 /* XXX what about other V6 headers?? */
6191 switch (ipv6_hdr(skb)->nexthdr) {
6193 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6196 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6201 if (unlikely(net_ratelimit()))
6202 e_warn(probe, "partial checksum but proto=%x!\n",
6210 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6211 struct ixgbe_ring *tx_ring,
6212 struct sk_buff *skb, u32 tx_flags,
6215 struct ixgbe_adv_tx_context_desc *context_desc;
6217 struct ixgbe_tx_buffer *tx_buffer_info;
6218 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6220 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6221 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6222 i = tx_ring->next_to_use;
6223 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6224 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6226 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6228 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6229 vlan_macip_lens |= (skb_network_offset(skb) <<
6230 IXGBE_ADVTXD_MACLEN_SHIFT);
6231 if (skb->ip_summed == CHECKSUM_PARTIAL)
6232 vlan_macip_lens |= (skb_transport_header(skb) -
6233 skb_network_header(skb));
6235 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6236 context_desc->seqnum_seed = 0;
6238 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6239 IXGBE_ADVTXD_DTYP_CTXT);
6241 if (skb->ip_summed == CHECKSUM_PARTIAL)
6242 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6244 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6245 /* use index zero for tx checksum offload */
6246 context_desc->mss_l4len_idx = 0;
6248 tx_buffer_info->time_stamp = jiffies;
6249 tx_buffer_info->next_to_watch = i;
6252 if (i == tx_ring->count)
6254 tx_ring->next_to_use = i;
6262 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6263 struct ixgbe_ring *tx_ring,
6264 struct sk_buff *skb, u32 tx_flags,
6265 unsigned int first, const u8 hdr_len)
6267 struct device *dev = tx_ring->dev;
6268 struct ixgbe_tx_buffer *tx_buffer_info;
6270 unsigned int total = skb->len;
6271 unsigned int offset = 0, size, count = 0, i;
6272 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6274 unsigned int bytecount = skb->len;
6277 i = tx_ring->next_to_use;
6279 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6280 /* excluding fcoe_crc_eof for FCoE */
6281 total -= sizeof(struct fcoe_crc_eof);
6283 len = min(skb_headlen(skb), total);
6285 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6286 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6288 tx_buffer_info->length = size;
6289 tx_buffer_info->mapped_as_page = false;
6290 tx_buffer_info->dma = dma_map_single(dev,
6292 size, DMA_TO_DEVICE);
6293 if (dma_mapping_error(dev, tx_buffer_info->dma))
6295 tx_buffer_info->time_stamp = jiffies;
6296 tx_buffer_info->next_to_watch = i;
6305 if (i == tx_ring->count)
6310 for (f = 0; f < nr_frags; f++) {
6311 struct skb_frag_struct *frag;
6313 frag = &skb_shinfo(skb)->frags[f];
6314 len = min((unsigned int)frag->size, total);
6315 offset = frag->page_offset;
6319 if (i == tx_ring->count)
6322 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6323 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6325 tx_buffer_info->length = size;
6326 tx_buffer_info->dma = dma_map_page(dev,
6330 tx_buffer_info->mapped_as_page = true;
6331 if (dma_mapping_error(dev, tx_buffer_info->dma))
6333 tx_buffer_info->time_stamp = jiffies;
6334 tx_buffer_info->next_to_watch = i;
6345 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6346 gso_segs = skb_shinfo(skb)->gso_segs;
6348 /* adjust for FCoE Sequence Offload */
6349 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6350 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6351 skb_shinfo(skb)->gso_size);
6352 #endif /* IXGBE_FCOE */
6353 bytecount += (gso_segs - 1) * hdr_len;
6355 /* multiply data chunks by size of headers */
6356 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6357 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6358 tx_ring->tx_buffer_info[i].skb = skb;
6359 tx_ring->tx_buffer_info[first].next_to_watch = i;
6364 e_dev_err("TX DMA map failed\n");
6366 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6367 tx_buffer_info->dma = 0;
6368 tx_buffer_info->time_stamp = 0;
6369 tx_buffer_info->next_to_watch = 0;
6373 /* clear timestamp and dma mappings for remaining portion of packet */
6376 i += tx_ring->count;
6378 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6379 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6385 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6386 int tx_flags, int count, u32 paylen, u8 hdr_len)
6388 union ixgbe_adv_tx_desc *tx_desc = NULL;
6389 struct ixgbe_tx_buffer *tx_buffer_info;
6390 u32 olinfo_status = 0, cmd_type_len = 0;
6392 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6394 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6396 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6398 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6399 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6401 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6402 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6404 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6405 IXGBE_ADVTXD_POPTS_SHIFT;
6407 /* use index 1 context for tso */
6408 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6409 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6410 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6411 IXGBE_ADVTXD_POPTS_SHIFT;
6413 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6414 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6415 IXGBE_ADVTXD_POPTS_SHIFT;
6417 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6418 olinfo_status |= IXGBE_ADVTXD_CC;
6419 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6420 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6421 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6424 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6426 i = tx_ring->next_to_use;
6428 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6429 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6430 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6431 tx_desc->read.cmd_type_len =
6432 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6433 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6435 if (i == tx_ring->count)
6439 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6442 * Force memory writes to complete before letting h/w
6443 * know there are new descriptors to fetch. (Only
6444 * applicable for weak-ordered memory model archs,
6449 tx_ring->next_to_use = i;
6450 writel(i, tx_ring->tail);
6453 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6454 u8 queue, u32 tx_flags, __be16 protocol)
6456 struct ixgbe_atr_input atr_input;
6457 struct iphdr *iph = ip_hdr(skb);
6458 struct ethhdr *eth = (struct ethhdr *)skb->data;
6462 /* Right now, we support IPv4 w/ TCP only */
6463 if (protocol != htons(ETH_P_IP) ||
6464 iph->protocol != IPPROTO_TCP)
6467 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6469 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6470 IXGBE_TX_FLAGS_VLAN_SHIFT;
6474 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6475 ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6476 ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6477 ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6478 ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6479 /* src and dst are inverted, think how the receiver sees them */
6480 ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6481 ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6483 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6484 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6487 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6489 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6490 /* Herbert's original patch had:
6491 * smp_mb__after_netif_stop_queue();
6492 * but since that doesn't exist yet, just open code it. */
6495 /* We need to check again in a case another CPU has just
6496 * made room available. */
6497 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6500 /* A reprieve! - use start_queue because it doesn't call schedule */
6501 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6502 ++tx_ring->tx_stats.restart_queue;
6506 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6508 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6510 return __ixgbe_maybe_stop_tx(tx_ring, size);
6513 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6515 struct ixgbe_adapter *adapter = netdev_priv(dev);
6516 int txq = smp_processor_id();
6520 protocol = vlan_get_protocol(skb);
6522 if ((protocol == htons(ETH_P_FCOE)) ||
6523 (protocol == htons(ETH_P_FIP))) {
6524 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6525 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6526 txq += adapter->ring_feature[RING_F_FCOE].mask;
6528 #ifdef CONFIG_IXGBE_DCB
6529 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6530 txq = adapter->fcoe.up;
6537 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6538 while (unlikely(txq >= dev->real_num_tx_queues))
6539 txq -= dev->real_num_tx_queues;
6543 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6544 if (skb->priority == TC_PRIO_CONTROL)
6545 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6547 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6552 return skb_tx_hash(dev, skb);
6555 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6556 struct ixgbe_adapter *adapter,
6557 struct ixgbe_ring *tx_ring)
6559 struct net_device *netdev = tx_ring->netdev;
6560 struct netdev_queue *txq;
6562 unsigned int tx_flags = 0;
6569 protocol = vlan_get_protocol(skb);
6571 if (vlan_tx_tag_present(skb)) {
6572 tx_flags |= vlan_tx_tag_get(skb);
6573 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6574 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6575 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6577 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6578 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6579 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6580 skb->priority != TC_PRIO_CONTROL) {
6581 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6582 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6583 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6587 /* for FCoE with DCB, we force the priority to what
6588 * was specified by the switch */
6589 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6590 (protocol == htons(ETH_P_FCOE) ||
6591 protocol == htons(ETH_P_FIP))) {
6592 #ifdef CONFIG_IXGBE_DCB
6593 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6594 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6595 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6596 tx_flags |= ((adapter->fcoe.up << 13)
6597 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6600 /* flag for FCoE offloads */
6601 if (protocol == htons(ETH_P_FCOE))
6602 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6606 /* four things can cause us to need a context descriptor */
6607 if (skb_is_gso(skb) ||
6608 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6609 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6610 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6613 count += TXD_USE_COUNT(skb_headlen(skb));
6614 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6615 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6617 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6618 tx_ring->tx_stats.tx_busy++;
6619 return NETDEV_TX_BUSY;
6622 first = tx_ring->next_to_use;
6623 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6625 /* setup tx offload for FCoE */
6626 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6628 dev_kfree_skb_any(skb);
6629 return NETDEV_TX_OK;
6632 tx_flags |= IXGBE_TX_FLAGS_FSO;
6633 #endif /* IXGBE_FCOE */
6635 if (protocol == htons(ETH_P_IP))
6636 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6637 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6640 dev_kfree_skb_any(skb);
6641 return NETDEV_TX_OK;
6645 tx_flags |= IXGBE_TX_FLAGS_TSO;
6646 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6648 (skb->ip_summed == CHECKSUM_PARTIAL))
6649 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6652 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6654 /* add the ATR filter if ATR is on */
6655 if (tx_ring->atr_sample_rate) {
6656 ++tx_ring->atr_count;
6657 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6658 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6660 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6661 tx_flags, protocol);
6662 tx_ring->atr_count = 0;
6665 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6666 txq->tx_bytes += skb->len;
6668 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6669 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6672 dev_kfree_skb_any(skb);
6673 tx_ring->tx_buffer_info[first].time_stamp = 0;
6674 tx_ring->next_to_use = first;
6677 return NETDEV_TX_OK;
6680 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6683 struct ixgbe_ring *tx_ring;
6685 tx_ring = adapter->tx_ring[skb->queue_mapping];
6686 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6690 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6691 * @netdev: network interface device structure
6692 * @p: pointer to an address structure
6694 * Returns 0 on success, negative on failure
6696 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6699 struct ixgbe_hw *hw = &adapter->hw;
6700 struct sockaddr *addr = p;
6702 if (!is_valid_ether_addr(addr->sa_data))
6703 return -EADDRNOTAVAIL;
6705 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6706 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6708 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6715 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6717 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6718 struct ixgbe_hw *hw = &adapter->hw;
6722 if (prtad != hw->phy.mdio.prtad)
6724 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6730 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6731 u16 addr, u16 value)
6733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6734 struct ixgbe_hw *hw = &adapter->hw;
6736 if (prtad != hw->phy.mdio.prtad)
6738 return hw->phy.ops.write_reg(hw, addr, devad, value);
6741 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6743 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6745 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6749 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6751 * @netdev: network interface device structure
6753 * Returns non-zero on failure
6755 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6758 struct ixgbe_adapter *adapter = netdev_priv(dev);
6759 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6761 if (is_valid_ether_addr(mac->san_addr)) {
6763 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6770 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6772 * @netdev: network interface device structure
6774 * Returns non-zero on failure
6776 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6779 struct ixgbe_adapter *adapter = netdev_priv(dev);
6780 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6782 if (is_valid_ether_addr(mac->san_addr)) {
6784 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6790 #ifdef CONFIG_NET_POLL_CONTROLLER
6792 * Polling 'interrupt' - used by things like netconsole to send skbs
6793 * without having to re-enable interrupts. It's not called while
6794 * the interrupt routine is executing.
6796 static void ixgbe_netpoll(struct net_device *netdev)
6798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6801 /* if interface is down do nothing */
6802 if (test_bit(__IXGBE_DOWN, &adapter->state))
6805 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6806 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6807 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6808 for (i = 0; i < num_q_vectors; i++) {
6809 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6810 ixgbe_msix_clean_many(0, q_vector);
6813 ixgbe_intr(adapter->pdev->irq, netdev);
6815 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6819 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6820 struct rtnl_link_stats64 *stats)
6822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6825 /* accurate rx/tx bytes/packets stats */
6826 dev_txq_stats_fold(netdev, stats);
6828 for (i = 0; i < adapter->num_rx_queues; i++) {
6829 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6835 start = u64_stats_fetch_begin_bh(&ring->syncp);
6836 packets = ring->stats.packets;
6837 bytes = ring->stats.bytes;
6838 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6839 stats->rx_packets += packets;
6840 stats->rx_bytes += bytes;
6844 /* following stats updated by ixgbe_watchdog_task() */
6845 stats->multicast = netdev->stats.multicast;
6846 stats->rx_errors = netdev->stats.rx_errors;
6847 stats->rx_length_errors = netdev->stats.rx_length_errors;
6848 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6849 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6854 static const struct net_device_ops ixgbe_netdev_ops = {
6855 .ndo_open = ixgbe_open,
6856 .ndo_stop = ixgbe_close,
6857 .ndo_start_xmit = ixgbe_xmit_frame,
6858 .ndo_select_queue = ixgbe_select_queue,
6859 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6860 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6861 .ndo_validate_addr = eth_validate_addr,
6862 .ndo_set_mac_address = ixgbe_set_mac,
6863 .ndo_change_mtu = ixgbe_change_mtu,
6864 .ndo_tx_timeout = ixgbe_tx_timeout,
6865 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6866 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6867 .ndo_do_ioctl = ixgbe_ioctl,
6868 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6869 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6870 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6871 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6872 .ndo_get_stats64 = ixgbe_get_stats64,
6873 #ifdef CONFIG_NET_POLL_CONTROLLER
6874 .ndo_poll_controller = ixgbe_netpoll,
6877 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6878 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6879 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6880 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6881 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6882 #endif /* IXGBE_FCOE */
6885 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6886 const struct ixgbe_info *ii)
6888 #ifdef CONFIG_PCI_IOV
6889 struct ixgbe_hw *hw = &adapter->hw;
6892 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6895 /* The 82599 supports up to 64 VFs per physical function
6896 * but this implementation limits allocation to 63 so that
6897 * basic networking resources are still available to the
6900 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6901 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6902 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6904 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6907 /* If call to enable VFs succeeded then allocate memory
6908 * for per VF control structures.
6911 kcalloc(adapter->num_vfs,
6912 sizeof(struct vf_data_storage), GFP_KERNEL);
6913 if (adapter->vfinfo) {
6914 /* Now that we're sure SR-IOV is enabled
6915 * and memory allocated set up the mailbox parameters
6917 ixgbe_init_mbx_params_pf(hw);
6918 memcpy(&hw->mbx.ops, ii->mbx_ops,
6919 sizeof(hw->mbx.ops));
6921 /* Disable RSC when in SR-IOV mode */
6922 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6923 IXGBE_FLAG2_RSC_ENABLED);
6928 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6929 "SRIOV disabled\n");
6930 pci_disable_sriov(adapter->pdev);
6933 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6934 adapter->num_vfs = 0;
6935 #endif /* CONFIG_PCI_IOV */
6939 * ixgbe_probe - Device Initialization Routine
6940 * @pdev: PCI device information struct
6941 * @ent: entry in ixgbe_pci_tbl
6943 * Returns 0 on success, negative on failure
6945 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6946 * The OS initialization, configuring of the adapter private structure,
6947 * and a hardware reset occur.
6949 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6950 const struct pci_device_id *ent)
6952 struct net_device *netdev;
6953 struct ixgbe_adapter *adapter = NULL;
6954 struct ixgbe_hw *hw;
6955 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6956 static int cards_found;
6957 int i, err, pci_using_dac;
6958 u8 part_str[IXGBE_PBANUM_LENGTH];
6959 unsigned int indices = num_possible_cpus();
6965 /* Catch broken hardware that put the wrong VF device ID in
6966 * the PCIe SR-IOV capability.
6968 if (pdev->is_virtfn) {
6969 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6970 pci_name(pdev), pdev->vendor, pdev->device);
6974 err = pci_enable_device_mem(pdev);
6978 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6979 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6982 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6984 err = dma_set_coherent_mask(&pdev->dev,
6988 "No usable DMA configuration, aborting\n");
6995 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6996 IORESOURCE_MEM), ixgbe_driver_name);
6999 "pci_request_selected_regions failed 0x%x\n", err);
7003 pci_enable_pcie_error_reporting(pdev);
7005 pci_set_master(pdev);
7006 pci_save_state(pdev);
7008 if (ii->mac == ixgbe_mac_82598EB)
7009 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7011 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7013 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7015 indices += min_t(unsigned int, num_possible_cpus(),
7016 IXGBE_MAX_FCOE_INDICES);
7018 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7021 goto err_alloc_etherdev;
7024 SET_NETDEV_DEV(netdev, &pdev->dev);
7026 adapter = netdev_priv(netdev);
7027 pci_set_drvdata(pdev, adapter);
7029 adapter->netdev = netdev;
7030 adapter->pdev = pdev;
7033 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7035 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7036 pci_resource_len(pdev, 0));
7042 for (i = 1; i <= 5; i++) {
7043 if (pci_resource_len(pdev, i) == 0)
7047 netdev->netdev_ops = &ixgbe_netdev_ops;
7048 ixgbe_set_ethtool_ops(netdev);
7049 netdev->watchdog_timeo = 5 * HZ;
7050 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7052 adapter->bd_number = cards_found;
7055 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7056 hw->mac.type = ii->mac;
7059 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7060 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7061 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7062 if (!(eec & (1 << 8)))
7063 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7066 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7067 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7068 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7069 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7070 hw->phy.mdio.mmds = 0;
7071 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7072 hw->phy.mdio.dev = netdev;
7073 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7074 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7076 /* set up this timer and work struct before calling get_invariants
7077 * which might start the timer
7079 init_timer(&adapter->sfp_timer);
7080 adapter->sfp_timer.function = ixgbe_sfp_timer;
7081 adapter->sfp_timer.data = (unsigned long) adapter;
7083 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7085 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7086 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7088 /* a new SFP+ module arrival, called from GPI SDP2 context */
7089 INIT_WORK(&adapter->sfp_config_module_task,
7090 ixgbe_sfp_config_module_task);
7092 ii->get_invariants(hw);
7094 /* setup the private structure */
7095 err = ixgbe_sw_init(adapter);
7099 /* Make it possible the adapter to be woken up via WOL */
7100 switch (adapter->hw.mac.type) {
7101 case ixgbe_mac_82599EB:
7102 case ixgbe_mac_X540:
7103 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7110 * If there is a fan on this device and it has failed log the
7113 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7114 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7115 if (esdp & IXGBE_ESDP_SDP1)
7116 e_crit(probe, "Fan has stopped, replace the adapter\n");
7119 /* reset_hw fills in the perm_addr as well */
7120 hw->phy.reset_if_overtemp = true;
7121 err = hw->mac.ops.reset_hw(hw);
7122 hw->phy.reset_if_overtemp = false;
7123 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7124 hw->mac.type == ixgbe_mac_82598EB) {
7126 * Start a kernel thread to watch for a module to arrive.
7127 * Only do this for 82598, since 82599 will generate
7128 * interrupts on module arrival.
7130 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7131 mod_timer(&adapter->sfp_timer,
7132 round_jiffies(jiffies + (2 * HZ)));
7134 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7135 e_dev_err("failed to initialize because an unsupported SFP+ "
7136 "module type was detected.\n");
7137 e_dev_err("Reload the driver after installing a supported "
7141 e_dev_err("HW Init failed: %d\n", err);
7145 ixgbe_probe_vf(adapter, ii);
7147 netdev->features = NETIF_F_SG |
7149 NETIF_F_HW_VLAN_TX |
7150 NETIF_F_HW_VLAN_RX |
7151 NETIF_F_HW_VLAN_FILTER;
7153 netdev->features |= NETIF_F_IPV6_CSUM;
7154 netdev->features |= NETIF_F_TSO;
7155 netdev->features |= NETIF_F_TSO6;
7156 netdev->features |= NETIF_F_GRO;
7158 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7159 netdev->features |= NETIF_F_SCTP_CSUM;
7161 netdev->vlan_features |= NETIF_F_TSO;
7162 netdev->vlan_features |= NETIF_F_TSO6;
7163 netdev->vlan_features |= NETIF_F_IP_CSUM;
7164 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7165 netdev->vlan_features |= NETIF_F_SG;
7167 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7168 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7169 IXGBE_FLAG_DCB_ENABLED);
7170 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7171 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7173 #ifdef CONFIG_IXGBE_DCB
7174 netdev->dcbnl_ops = &dcbnl_ops;
7178 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7179 if (hw->mac.ops.get_device_caps) {
7180 hw->mac.ops.get_device_caps(hw, &device_caps);
7181 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7182 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7185 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7186 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7187 netdev->vlan_features |= NETIF_F_FSO;
7188 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7190 #endif /* IXGBE_FCOE */
7191 if (pci_using_dac) {
7192 netdev->features |= NETIF_F_HIGHDMA;
7193 netdev->vlan_features |= NETIF_F_HIGHDMA;
7196 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7197 netdev->features |= NETIF_F_LRO;
7199 /* make sure the EEPROM is good */
7200 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7201 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7206 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7207 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7209 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7210 e_dev_err("invalid MAC address\n");
7215 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7216 if (hw->mac.ops.disable_tx_laser &&
7217 ((hw->phy.multispeed_fiber) ||
7218 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7219 (hw->mac.type == ixgbe_mac_82599EB))))
7220 hw->mac.ops.disable_tx_laser(hw);
7222 init_timer(&adapter->watchdog_timer);
7223 adapter->watchdog_timer.function = ixgbe_watchdog;
7224 adapter->watchdog_timer.data = (unsigned long)adapter;
7226 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7227 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7229 err = ixgbe_init_interrupt_scheme(adapter);
7233 switch (pdev->device) {
7234 case IXGBE_DEV_ID_82599_SFP:
7235 /* Only this subdevice supports WOL */
7236 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7237 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7238 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7240 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7241 /* All except this subdevice support WOL */
7242 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7243 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7244 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7246 case IXGBE_DEV_ID_82599_KX4:
7247 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7248 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7254 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7256 /* pick up the PCI bus settings for reporting later */
7257 hw->mac.ops.get_bus_info(hw);
7259 /* print bus type/speed/width info */
7260 e_dev_info("(PCI Express:%s:%s) %pM\n",
7261 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7262 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7264 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7265 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7266 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7270 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7272 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7273 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7274 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7275 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7278 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7279 hw->mac.type, hw->phy.type, part_str);
7281 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7282 e_dev_warn("PCI-Express bandwidth available for this card is "
7283 "not sufficient for optimal performance.\n");
7284 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7288 /* save off EEPROM version number */
7289 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7291 /* reset the hardware with the new settings */
7292 err = hw->mac.ops.start_hw(hw);
7294 if (err == IXGBE_ERR_EEPROM_VERSION) {
7295 /* We are running on a pre-production device, log a warning */
7296 e_dev_warn("This device is a pre-production adapter/LOM. "
7297 "Please be aware there may be issues associated "
7298 "with your hardware. If you are experiencing "
7299 "problems please contact your Intel or hardware "
7300 "representative who provided you with this "
7303 strcpy(netdev->name, "eth%d");
7304 err = register_netdev(netdev);
7308 /* carrier off reporting is important to ethtool even BEFORE open */
7309 netif_carrier_off(netdev);
7311 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7312 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7313 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7315 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7316 INIT_WORK(&adapter->check_overtemp_task,
7317 ixgbe_check_overtemp_task);
7318 #ifdef CONFIG_IXGBE_DCA
7319 if (dca_add_requester(&pdev->dev) == 0) {
7320 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7321 ixgbe_setup_dca(adapter);
7324 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7325 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7326 for (i = 0; i < adapter->num_vfs; i++)
7327 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7330 /* add san mac addr to netdev */
7331 ixgbe_add_sanmac_netdev(netdev);
7333 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7338 ixgbe_release_hw_control(adapter);
7339 ixgbe_clear_interrupt_scheme(adapter);
7342 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7343 ixgbe_disable_sriov(adapter);
7344 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7345 del_timer_sync(&adapter->sfp_timer);
7346 cancel_work_sync(&adapter->sfp_task);
7347 cancel_work_sync(&adapter->multispeed_fiber_task);
7348 cancel_work_sync(&adapter->sfp_config_module_task);
7349 iounmap(hw->hw_addr);
7351 free_netdev(netdev);
7353 pci_release_selected_regions(pdev,
7354 pci_select_bars(pdev, IORESOURCE_MEM));
7357 pci_disable_device(pdev);
7362 * ixgbe_remove - Device Removal Routine
7363 * @pdev: PCI device information struct
7365 * ixgbe_remove is called by the PCI subsystem to alert the driver
7366 * that it should release a PCI device. The could be caused by a
7367 * Hot-Plug event, or because the driver is going to be removed from
7370 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7372 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7373 struct net_device *netdev = adapter->netdev;
7375 set_bit(__IXGBE_DOWN, &adapter->state);
7376 /* clear the module not found bit to make sure the worker won't
7379 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7380 del_timer_sync(&adapter->watchdog_timer);
7382 del_timer_sync(&adapter->sfp_timer);
7383 cancel_work_sync(&adapter->watchdog_task);
7384 cancel_work_sync(&adapter->sfp_task);
7385 cancel_work_sync(&adapter->multispeed_fiber_task);
7386 cancel_work_sync(&adapter->sfp_config_module_task);
7387 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7388 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7389 cancel_work_sync(&adapter->fdir_reinit_task);
7390 flush_scheduled_work();
7392 #ifdef CONFIG_IXGBE_DCA
7393 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7394 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7395 dca_remove_requester(&pdev->dev);
7396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7401 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7402 ixgbe_cleanup_fcoe(adapter);
7404 #endif /* IXGBE_FCOE */
7406 /* remove the added san mac */
7407 ixgbe_del_sanmac_netdev(netdev);
7409 if (netdev->reg_state == NETREG_REGISTERED)
7410 unregister_netdev(netdev);
7412 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7413 ixgbe_disable_sriov(adapter);
7415 ixgbe_clear_interrupt_scheme(adapter);
7417 ixgbe_release_hw_control(adapter);
7419 iounmap(adapter->hw.hw_addr);
7420 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7423 e_dev_info("complete\n");
7425 free_netdev(netdev);
7427 pci_disable_pcie_error_reporting(pdev);
7429 pci_disable_device(pdev);
7433 * ixgbe_io_error_detected - called when PCI error is detected
7434 * @pdev: Pointer to PCI device
7435 * @state: The current pci connection state
7437 * This function is called after a PCI bus error affecting
7438 * this device has been detected.
7440 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7441 pci_channel_state_t state)
7443 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7444 struct net_device *netdev = adapter->netdev;
7446 netif_device_detach(netdev);
7448 if (state == pci_channel_io_perm_failure)
7449 return PCI_ERS_RESULT_DISCONNECT;
7451 if (netif_running(netdev))
7452 ixgbe_down(adapter);
7453 pci_disable_device(pdev);
7455 /* Request a slot reset. */
7456 return PCI_ERS_RESULT_NEED_RESET;
7460 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7461 * @pdev: Pointer to PCI device
7463 * Restart the card from scratch, as if from a cold-boot.
7465 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7467 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7468 pci_ers_result_t result;
7471 if (pci_enable_device_mem(pdev)) {
7472 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7473 result = PCI_ERS_RESULT_DISCONNECT;
7475 pci_set_master(pdev);
7476 pci_restore_state(pdev);
7477 pci_save_state(pdev);
7479 pci_wake_from_d3(pdev, false);
7481 ixgbe_reset(adapter);
7482 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7483 result = PCI_ERS_RESULT_RECOVERED;
7486 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7488 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7489 "failed 0x%0x\n", err);
7490 /* non-fatal, continue */
7497 * ixgbe_io_resume - called when traffic can start flowing again.
7498 * @pdev: Pointer to PCI device
7500 * This callback is called when the error recovery driver tells us that
7501 * its OK to resume normal operation.
7503 static void ixgbe_io_resume(struct pci_dev *pdev)
7505 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7506 struct net_device *netdev = adapter->netdev;
7508 if (netif_running(netdev)) {
7509 if (ixgbe_up(adapter)) {
7510 e_info(probe, "ixgbe_up failed after reset\n");
7515 netif_device_attach(netdev);
7518 static struct pci_error_handlers ixgbe_err_handler = {
7519 .error_detected = ixgbe_io_error_detected,
7520 .slot_reset = ixgbe_io_slot_reset,
7521 .resume = ixgbe_io_resume,
7524 static struct pci_driver ixgbe_driver = {
7525 .name = ixgbe_driver_name,
7526 .id_table = ixgbe_pci_tbl,
7527 .probe = ixgbe_probe,
7528 .remove = __devexit_p(ixgbe_remove),
7530 .suspend = ixgbe_suspend,
7531 .resume = ixgbe_resume,
7533 .shutdown = ixgbe_shutdown,
7534 .err_handler = &ixgbe_err_handler
7538 * ixgbe_init_module - Driver Registration Routine
7540 * ixgbe_init_module is the first routine called when the driver is
7541 * loaded. All it does is register with the PCI subsystem.
7543 static int __init ixgbe_init_module(void)
7546 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7547 pr_info("%s\n", ixgbe_copyright);
7549 #ifdef CONFIG_IXGBE_DCA
7550 dca_register_notify(&dca_notifier);
7553 ret = pci_register_driver(&ixgbe_driver);
7557 module_init(ixgbe_init_module);
7560 * ixgbe_exit_module - Driver Exit Cleanup Routine
7562 * ixgbe_exit_module is called just before the driver is removed
7565 static void __exit ixgbe_exit_module(void)
7567 #ifdef CONFIG_IXGBE_DCA
7568 dca_unregister_notify(&dca_notifier);
7570 pci_unregister_driver(&ixgbe_driver);
7571 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7574 #ifdef CONFIG_IXGBE_DCA
7575 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7580 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7581 __ixgbe_notify_dca);
7583 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7586 #endif /* CONFIG_IXGBE_DCA */
7589 * ixgbe_get_hw_dev return device
7590 * used by hardware layer to print debugging information
7592 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7594 struct ixgbe_adapter *adapter = hw->back;
7595 return adapter->netdev;
7598 module_exit(ixgbe_exit_module);